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v3d: Include the number of max temps used in the shader-db output.
[mesa.git] / src / broadcom / compiler / vir.c
1 /*
2 * Copyright © 2016-2017 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "broadcom/common/v3d_device_info.h"
25 #include "v3d_compiler.h"
26
27 int
28 vir_get_nsrc(struct qinst *inst)
29 {
30 switch (inst->qpu.type) {
31 case V3D_QPU_INSTR_TYPE_BRANCH:
32 return 0;
33 case V3D_QPU_INSTR_TYPE_ALU:
34 if (inst->qpu.alu.add.op != V3D_QPU_A_NOP)
35 return v3d_qpu_add_op_num_src(inst->qpu.alu.add.op);
36 else
37 return v3d_qpu_mul_op_num_src(inst->qpu.alu.mul.op);
38 }
39
40 return 0;
41 }
42
43 /**
44 * Returns whether the instruction has any side effects that must be
45 * preserved.
46 */
47 bool
48 vir_has_side_effects(struct v3d_compile *c, struct qinst *inst)
49 {
50 switch (inst->qpu.type) {
51 case V3D_QPU_INSTR_TYPE_BRANCH:
52 return true;
53 case V3D_QPU_INSTR_TYPE_ALU:
54 switch (inst->qpu.alu.add.op) {
55 case V3D_QPU_A_SETREVF:
56 case V3D_QPU_A_SETMSF:
57 case V3D_QPU_A_VPMSETUP:
58 case V3D_QPU_A_STVPMV:
59 case V3D_QPU_A_STVPMD:
60 case V3D_QPU_A_STVPMP:
61 case V3D_QPU_A_VPMWT:
62 case V3D_QPU_A_TMUWT:
63 return true;
64 default:
65 break;
66 }
67
68 switch (inst->qpu.alu.mul.op) {
69 case V3D_QPU_M_MULTOP:
70 return true;
71 default:
72 break;
73 }
74 }
75
76 if (inst->qpu.sig.ldtmu ||
77 inst->qpu.sig.ldvary ||
78 inst->qpu.sig.wrtmuc ||
79 inst->qpu.sig.thrsw) {
80 return true;
81 }
82
83 return false;
84 }
85
86 bool
87 vir_is_raw_mov(struct qinst *inst)
88 {
89 if (inst->qpu.type != V3D_QPU_INSTR_TYPE_ALU ||
90 (inst->qpu.alu.mul.op != V3D_QPU_M_FMOV &&
91 inst->qpu.alu.mul.op != V3D_QPU_M_MOV)) {
92 return false;
93 }
94
95 if (inst->qpu.alu.add.output_pack != V3D_QPU_PACK_NONE ||
96 inst->qpu.alu.mul.output_pack != V3D_QPU_PACK_NONE) {
97 return false;
98 }
99
100 if (inst->qpu.alu.add.a_unpack != V3D_QPU_UNPACK_NONE ||
101 inst->qpu.alu.add.b_unpack != V3D_QPU_UNPACK_NONE ||
102 inst->qpu.alu.mul.a_unpack != V3D_QPU_UNPACK_NONE ||
103 inst->qpu.alu.mul.b_unpack != V3D_QPU_UNPACK_NONE) {
104 return false;
105 }
106
107 if (inst->qpu.flags.ac != V3D_QPU_COND_NONE ||
108 inst->qpu.flags.mc != V3D_QPU_COND_NONE)
109 return false;
110
111 return true;
112 }
113
114 bool
115 vir_is_add(struct qinst *inst)
116 {
117 return (inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU &&
118 inst->qpu.alu.add.op != V3D_QPU_A_NOP);
119 }
120
121 bool
122 vir_is_mul(struct qinst *inst)
123 {
124 return (inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU &&
125 inst->qpu.alu.mul.op != V3D_QPU_M_NOP);
126 }
127
128 bool
129 vir_is_tex(struct qinst *inst)
130 {
131 if (inst->dst.file == QFILE_MAGIC)
132 return v3d_qpu_magic_waddr_is_tmu(inst->dst.index);
133
134 if (inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU &&
135 inst->qpu.alu.add.op == V3D_QPU_A_TMUWT) {
136 return true;
137 }
138
139 return false;
140 }
141
142 bool
143 vir_writes_r3(const struct v3d_device_info *devinfo, struct qinst *inst)
144 {
145 for (int i = 0; i < vir_get_nsrc(inst); i++) {
146 switch (inst->src[i].file) {
147 case QFILE_VPM:
148 return true;
149 default:
150 break;
151 }
152 }
153
154 if (devinfo->ver < 41 && (inst->qpu.sig.ldvary ||
155 inst->qpu.sig.ldtlb ||
156 inst->qpu.sig.ldtlbu ||
157 inst->qpu.sig.ldvpm)) {
158 return true;
159 }
160
161 return false;
162 }
163
164 bool
165 vir_writes_r4(const struct v3d_device_info *devinfo, struct qinst *inst)
166 {
167 switch (inst->dst.file) {
168 case QFILE_MAGIC:
169 switch (inst->dst.index) {
170 case V3D_QPU_WADDR_RECIP:
171 case V3D_QPU_WADDR_RSQRT:
172 case V3D_QPU_WADDR_EXP:
173 case V3D_QPU_WADDR_LOG:
174 case V3D_QPU_WADDR_SIN:
175 return true;
176 }
177 break;
178 default:
179 break;
180 }
181
182 if (devinfo->ver < 41 && inst->qpu.sig.ldtmu)
183 return true;
184
185 return false;
186 }
187
188 void
189 vir_set_unpack(struct qinst *inst, int src,
190 enum v3d_qpu_input_unpack unpack)
191 {
192 assert(src == 0 || src == 1);
193
194 if (vir_is_add(inst)) {
195 if (src == 0)
196 inst->qpu.alu.add.a_unpack = unpack;
197 else
198 inst->qpu.alu.add.b_unpack = unpack;
199 } else {
200 assert(vir_is_mul(inst));
201 if (src == 0)
202 inst->qpu.alu.mul.a_unpack = unpack;
203 else
204 inst->qpu.alu.mul.b_unpack = unpack;
205 }
206 }
207
208 void
209 vir_set_cond(struct qinst *inst, enum v3d_qpu_cond cond)
210 {
211 if (vir_is_add(inst)) {
212 inst->qpu.flags.ac = cond;
213 } else {
214 assert(vir_is_mul(inst));
215 inst->qpu.flags.mc = cond;
216 }
217 }
218
219 void
220 vir_set_pf(struct qinst *inst, enum v3d_qpu_pf pf)
221 {
222 if (vir_is_add(inst)) {
223 inst->qpu.flags.apf = pf;
224 } else {
225 assert(vir_is_mul(inst));
226 inst->qpu.flags.mpf = pf;
227 }
228 }
229
230 void
231 vir_set_uf(struct qinst *inst, enum v3d_qpu_uf uf)
232 {
233 if (vir_is_add(inst)) {
234 inst->qpu.flags.auf = uf;
235 } else {
236 assert(vir_is_mul(inst));
237 inst->qpu.flags.muf = uf;
238 }
239 }
240
241 #if 0
242 uint8_t
243 vir_channels_written(struct qinst *inst)
244 {
245 if (vir_is_mul(inst)) {
246 switch (inst->dst.pack) {
247 case QPU_PACK_MUL_NOP:
248 case QPU_PACK_MUL_8888:
249 return 0xf;
250 case QPU_PACK_MUL_8A:
251 return 0x1;
252 case QPU_PACK_MUL_8B:
253 return 0x2;
254 case QPU_PACK_MUL_8C:
255 return 0x4;
256 case QPU_PACK_MUL_8D:
257 return 0x8;
258 }
259 } else {
260 switch (inst->dst.pack) {
261 case QPU_PACK_A_NOP:
262 case QPU_PACK_A_8888:
263 case QPU_PACK_A_8888_SAT:
264 case QPU_PACK_A_32_SAT:
265 return 0xf;
266 case QPU_PACK_A_8A:
267 case QPU_PACK_A_8A_SAT:
268 return 0x1;
269 case QPU_PACK_A_8B:
270 case QPU_PACK_A_8B_SAT:
271 return 0x2;
272 case QPU_PACK_A_8C:
273 case QPU_PACK_A_8C_SAT:
274 return 0x4;
275 case QPU_PACK_A_8D:
276 case QPU_PACK_A_8D_SAT:
277 return 0x8;
278 case QPU_PACK_A_16A:
279 case QPU_PACK_A_16A_SAT:
280 return 0x3;
281 case QPU_PACK_A_16B:
282 case QPU_PACK_A_16B_SAT:
283 return 0xc;
284 }
285 }
286 unreachable("Bad pack field");
287 }
288 #endif
289
290 struct qreg
291 vir_get_temp(struct v3d_compile *c)
292 {
293 struct qreg reg;
294
295 reg.file = QFILE_TEMP;
296 reg.index = c->num_temps++;
297
298 if (c->num_temps > c->defs_array_size) {
299 uint32_t old_size = c->defs_array_size;
300 c->defs_array_size = MAX2(old_size * 2, 16);
301
302 c->defs = reralloc(c, c->defs, struct qinst *,
303 c->defs_array_size);
304 memset(&c->defs[old_size], 0,
305 sizeof(c->defs[0]) * (c->defs_array_size - old_size));
306
307 c->spillable = reralloc(c, c->spillable,
308 BITSET_WORD,
309 BITSET_WORDS(c->defs_array_size));
310 for (int i = old_size; i < c->defs_array_size; i++)
311 BITSET_SET(c->spillable, i);
312 }
313
314 return reg;
315 }
316
317 struct qinst *
318 vir_add_inst(enum v3d_qpu_add_op op, struct qreg dst, struct qreg src0, struct qreg src1)
319 {
320 struct qinst *inst = calloc(1, sizeof(*inst));
321
322 inst->qpu = v3d_qpu_nop();
323 inst->qpu.alu.add.op = op;
324
325 inst->dst = dst;
326 inst->src[0] = src0;
327 inst->src[1] = src1;
328 inst->uniform = ~0;
329
330 return inst;
331 }
332
333 struct qinst *
334 vir_mul_inst(enum v3d_qpu_mul_op op, struct qreg dst, struct qreg src0, struct qreg src1)
335 {
336 struct qinst *inst = calloc(1, sizeof(*inst));
337
338 inst->qpu = v3d_qpu_nop();
339 inst->qpu.alu.mul.op = op;
340
341 inst->dst = dst;
342 inst->src[0] = src0;
343 inst->src[1] = src1;
344 inst->uniform = ~0;
345
346 return inst;
347 }
348
349 struct qinst *
350 vir_branch_inst(struct v3d_compile *c, enum v3d_qpu_branch_cond cond)
351 {
352 struct qinst *inst = calloc(1, sizeof(*inst));
353
354 inst->qpu = v3d_qpu_nop();
355 inst->qpu.type = V3D_QPU_INSTR_TYPE_BRANCH;
356 inst->qpu.branch.cond = cond;
357 inst->qpu.branch.msfign = V3D_QPU_MSFIGN_NONE;
358 inst->qpu.branch.bdi = V3D_QPU_BRANCH_DEST_REL;
359 inst->qpu.branch.ub = true;
360 inst->qpu.branch.bdu = V3D_QPU_BRANCH_DEST_REL;
361
362 inst->dst = vir_nop_reg();
363 inst->uniform = vir_get_uniform_index(c, QUNIFORM_CONSTANT, 0);
364
365 return inst;
366 }
367
368 static void
369 vir_emit(struct v3d_compile *c, struct qinst *inst)
370 {
371 switch (c->cursor.mode) {
372 case vir_cursor_add:
373 list_add(&inst->link, c->cursor.link);
374 break;
375 case vir_cursor_addtail:
376 list_addtail(&inst->link, c->cursor.link);
377 break;
378 }
379
380 c->cursor = vir_after_inst(inst);
381 c->live_intervals_valid = false;
382 }
383
384 /* Updates inst to write to a new temporary, emits it, and notes the def. */
385 struct qreg
386 vir_emit_def(struct v3d_compile *c, struct qinst *inst)
387 {
388 assert(inst->dst.file == QFILE_NULL);
389
390 /* If we're emitting an instruction that's a def, it had better be
391 * writing a register.
392 */
393 if (inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU) {
394 assert(inst->qpu.alu.add.op == V3D_QPU_A_NOP ||
395 v3d_qpu_add_op_has_dst(inst->qpu.alu.add.op));
396 assert(inst->qpu.alu.mul.op == V3D_QPU_M_NOP ||
397 v3d_qpu_mul_op_has_dst(inst->qpu.alu.mul.op));
398 }
399
400 inst->dst = vir_get_temp(c);
401
402 if (inst->dst.file == QFILE_TEMP)
403 c->defs[inst->dst.index] = inst;
404
405 vir_emit(c, inst);
406
407 return inst->dst;
408 }
409
410 struct qinst *
411 vir_emit_nondef(struct v3d_compile *c, struct qinst *inst)
412 {
413 if (inst->dst.file == QFILE_TEMP)
414 c->defs[inst->dst.index] = NULL;
415
416 vir_emit(c, inst);
417
418 return inst;
419 }
420
421 struct qblock *
422 vir_new_block(struct v3d_compile *c)
423 {
424 struct qblock *block = rzalloc(c, struct qblock);
425
426 list_inithead(&block->instructions);
427
428 block->predecessors = _mesa_set_create(block,
429 _mesa_hash_pointer,
430 _mesa_key_pointer_equal);
431
432 block->index = c->next_block_index++;
433
434 return block;
435 }
436
437 void
438 vir_set_emit_block(struct v3d_compile *c, struct qblock *block)
439 {
440 c->cur_block = block;
441 c->cursor = vir_after_block(block);
442 list_addtail(&block->link, &c->blocks);
443 }
444
445 struct qblock *
446 vir_entry_block(struct v3d_compile *c)
447 {
448 return list_first_entry(&c->blocks, struct qblock, link);
449 }
450
451 struct qblock *
452 vir_exit_block(struct v3d_compile *c)
453 {
454 return list_last_entry(&c->blocks, struct qblock, link);
455 }
456
457 void
458 vir_link_blocks(struct qblock *predecessor, struct qblock *successor)
459 {
460 _mesa_set_add(successor->predecessors, predecessor);
461 if (predecessor->successors[0]) {
462 assert(!predecessor->successors[1]);
463 predecessor->successors[1] = successor;
464 } else {
465 predecessor->successors[0] = successor;
466 }
467 }
468
469 const struct v3d_compiler *
470 v3d_compiler_init(const struct v3d_device_info *devinfo)
471 {
472 struct v3d_compiler *compiler = rzalloc(NULL, struct v3d_compiler);
473 if (!compiler)
474 return NULL;
475
476 compiler->devinfo = devinfo;
477
478 if (!vir_init_reg_sets(compiler)) {
479 ralloc_free(compiler);
480 return NULL;
481 }
482
483 return compiler;
484 }
485
486 void
487 v3d_compiler_free(const struct v3d_compiler *compiler)
488 {
489 ralloc_free((void *)compiler);
490 }
491
492 static struct v3d_compile *
493 vir_compile_init(const struct v3d_compiler *compiler,
494 struct v3d_key *key,
495 nir_shader *s,
496 void (*debug_output)(const char *msg,
497 void *debug_output_data),
498 void *debug_output_data,
499 int program_id, int variant_id)
500 {
501 struct v3d_compile *c = rzalloc(NULL, struct v3d_compile);
502
503 c->compiler = compiler;
504 c->devinfo = compiler->devinfo;
505 c->key = key;
506 c->program_id = program_id;
507 c->variant_id = variant_id;
508 c->threads = 4;
509 c->debug_output = debug_output;
510 c->debug_output_data = debug_output_data;
511
512 s = nir_shader_clone(c, s);
513 c->s = s;
514
515 list_inithead(&c->blocks);
516 vir_set_emit_block(c, vir_new_block(c));
517
518 c->output_position_index = -1;
519 c->output_sample_mask_index = -1;
520
521 c->def_ht = _mesa_hash_table_create(c, _mesa_hash_pointer,
522 _mesa_key_pointer_equal);
523
524 return c;
525 }
526
527 static int
528 type_size_vec4(const struct glsl_type *type, bool bindless)
529 {
530 return glsl_count_attribute_slots(type, false);
531 }
532
533 static void
534 v3d_lower_nir(struct v3d_compile *c)
535 {
536 struct nir_lower_tex_options tex_options = {
537 .lower_txd = true,
538 .lower_tg4_broadcom_swizzle = true,
539
540 .lower_rect = false, /* XXX: Use this on V3D 3.x */
541 .lower_txp = ~0,
542 /* Apply swizzles to all samplers. */
543 .swizzle_result = ~0,
544 };
545
546 /* Lower the format swizzle and (for 32-bit returns)
547 * ARB_texture_swizzle-style swizzle.
548 */
549 for (int i = 0; i < ARRAY_SIZE(c->key->tex); i++) {
550 for (int j = 0; j < 4; j++)
551 tex_options.swizzles[i][j] = c->key->tex[i].swizzle[j];
552
553 if (c->key->tex[i].clamp_s)
554 tex_options.saturate_s |= 1 << i;
555 if (c->key->tex[i].clamp_t)
556 tex_options.saturate_t |= 1 << i;
557 if (c->key->tex[i].clamp_r)
558 tex_options.saturate_r |= 1 << i;
559 if (c->key->tex[i].return_size == 16) {
560 tex_options.lower_tex_packing[i] =
561 nir_lower_tex_packing_16;
562 }
563 }
564
565 NIR_PASS_V(c->s, nir_lower_tex, &tex_options);
566 NIR_PASS_V(c->s, nir_lower_system_values);
567 }
568
569 static void
570 v3d_set_prog_data_uniforms(struct v3d_compile *c,
571 struct v3d_prog_data *prog_data)
572 {
573 int count = c->num_uniforms;
574 struct v3d_uniform_list *ulist = &prog_data->uniforms;
575
576 ulist->count = count;
577 ulist->data = ralloc_array(prog_data, uint32_t, count);
578 memcpy(ulist->data, c->uniform_data,
579 count * sizeof(*ulist->data));
580 ulist->contents = ralloc_array(prog_data, enum quniform_contents, count);
581 memcpy(ulist->contents, c->uniform_contents,
582 count * sizeof(*ulist->contents));
583 }
584
585 static void
586 v3d_vs_set_prog_data(struct v3d_compile *c,
587 struct v3d_vs_prog_data *prog_data)
588 {
589 /* The vertex data gets format converted by the VPM so that
590 * each attribute channel takes up a VPM column. Precompute
591 * the sizes for the shader record.
592 */
593 for (int i = 0; i < ARRAY_SIZE(prog_data->vattr_sizes); i++) {
594 prog_data->vattr_sizes[i] = c->vattr_sizes[i];
595 prog_data->vpm_input_size += c->vattr_sizes[i];
596 }
597
598 prog_data->uses_vid = (c->s->info.system_values_read &
599 (1ull << SYSTEM_VALUE_VERTEX_ID));
600 prog_data->uses_iid = (c->s->info.system_values_read &
601 (1ull << SYSTEM_VALUE_INSTANCE_ID));
602
603 if (prog_data->uses_vid)
604 prog_data->vpm_input_size++;
605 if (prog_data->uses_iid)
606 prog_data->vpm_input_size++;
607
608 /* Input/output segment size are in sectors (8 rows of 32 bits per
609 * channel).
610 */
611 prog_data->vpm_input_size = align(prog_data->vpm_input_size, 8) / 8;
612 prog_data->vpm_output_size = align(c->vpm_output_size, 8) / 8;
613
614 /* Set us up for shared input/output segments. This is apparently
615 * necessary for our VCM setup to avoid varying corruption.
616 */
617 prog_data->separate_segments = false;
618 prog_data->vpm_output_size = MAX2(prog_data->vpm_output_size,
619 prog_data->vpm_input_size);
620 prog_data->vpm_input_size = 0;
621
622 /* Compute VCM cache size. We set up our program to take up less than
623 * half of the VPM, so that any set of bin and render programs won't
624 * run out of space. We need space for at least one input segment,
625 * and then allocate the rest to output segments (one for the current
626 * program, the rest to VCM). The valid range of the VCM cache size
627 * field is 1-4 16-vertex batches, but GFXH-1744 limits us to 2-4
628 * batches.
629 */
630 assert(c->devinfo->vpm_size);
631 int sector_size = V3D_CHANNELS * sizeof(uint32_t) * 8;
632 int vpm_size_in_sectors = c->devinfo->vpm_size / sector_size;
633 int half_vpm = vpm_size_in_sectors / 2;
634 int vpm_output_sectors = half_vpm - prog_data->vpm_input_size;
635 int vpm_output_batches = vpm_output_sectors / prog_data->vpm_output_size;
636 assert(vpm_output_batches >= 2);
637 prog_data->vcm_cache_size = CLAMP(vpm_output_batches - 1, 2, 4);
638 }
639
640 static void
641 v3d_set_fs_prog_data_inputs(struct v3d_compile *c,
642 struct v3d_fs_prog_data *prog_data)
643 {
644 prog_data->num_inputs = c->num_inputs;
645 memcpy(prog_data->input_slots, c->input_slots,
646 c->num_inputs * sizeof(*c->input_slots));
647
648 STATIC_ASSERT(ARRAY_SIZE(prog_data->flat_shade_flags) >
649 (V3D_MAX_FS_INPUTS - 1) / 24);
650 for (int i = 0; i < V3D_MAX_FS_INPUTS; i++) {
651 if (BITSET_TEST(c->flat_shade_flags, i))
652 prog_data->flat_shade_flags[i / 24] |= 1 << (i % 24);
653
654 if (BITSET_TEST(c->noperspective_flags, i))
655 prog_data->noperspective_flags[i / 24] |= 1 << (i % 24);
656
657 if (BITSET_TEST(c->centroid_flags, i))
658 prog_data->centroid_flags[i / 24] |= 1 << (i % 24);
659 }
660 }
661
662 static void
663 v3d_fs_set_prog_data(struct v3d_compile *c,
664 struct v3d_fs_prog_data *prog_data)
665 {
666 v3d_set_fs_prog_data_inputs(c, prog_data);
667 prog_data->writes_z = c->writes_z;
668 prog_data->disable_ez = !c->s->info.fs.early_fragment_tests;
669 prog_data->uses_center_w = c->uses_center_w;
670 }
671
672 static void
673 v3d_set_prog_data(struct v3d_compile *c,
674 struct v3d_prog_data *prog_data)
675 {
676 prog_data->threads = c->threads;
677 prog_data->single_seg = !c->last_thrsw;
678 prog_data->spill_size = c->spill_size;
679
680 v3d_set_prog_data_uniforms(c, prog_data);
681
682 if (c->s->info.stage == MESA_SHADER_VERTEX) {
683 v3d_vs_set_prog_data(c, (struct v3d_vs_prog_data *)prog_data);
684 } else {
685 assert(c->s->info.stage == MESA_SHADER_FRAGMENT);
686 v3d_fs_set_prog_data(c, (struct v3d_fs_prog_data *)prog_data);
687 }
688 }
689
690 static uint64_t *
691 v3d_return_qpu_insts(struct v3d_compile *c, uint32_t *final_assembly_size)
692 {
693 *final_assembly_size = c->qpu_inst_count * sizeof(uint64_t);
694
695 uint64_t *qpu_insts = malloc(*final_assembly_size);
696 if (!qpu_insts)
697 return NULL;
698
699 memcpy(qpu_insts, c->qpu_insts, *final_assembly_size);
700
701 vir_compile_destroy(c);
702
703 return qpu_insts;
704 }
705
706 static void
707 v3d_nir_lower_vs_early(struct v3d_compile *c)
708 {
709 /* Split our I/O vars and dead code eliminate the unused
710 * components.
711 */
712 NIR_PASS_V(c->s, nir_lower_io_to_scalar_early,
713 nir_var_shader_in | nir_var_shader_out);
714 uint64_t used_outputs[4] = {0};
715 for (int i = 0; i < c->vs_key->num_fs_inputs; i++) {
716 int slot = v3d_slot_get_slot(c->vs_key->fs_inputs[i]);
717 int comp = v3d_slot_get_component(c->vs_key->fs_inputs[i]);
718 used_outputs[comp] |= 1ull << slot;
719 }
720 NIR_PASS_V(c->s, nir_remove_unused_io_vars,
721 &c->s->outputs, used_outputs, NULL); /* demotes to globals */
722 NIR_PASS_V(c->s, nir_lower_global_vars_to_local);
723 v3d_optimize_nir(c->s);
724 NIR_PASS_V(c->s, nir_remove_dead_variables, nir_var_shader_in);
725 NIR_PASS_V(c->s, nir_lower_io, nir_var_shader_in | nir_var_shader_out,
726 type_size_vec4,
727 (nir_lower_io_options)0);
728 }
729
730 static void
731 v3d_fixup_fs_output_types(struct v3d_compile *c)
732 {
733 nir_foreach_variable(var, &c->s->outputs) {
734 uint32_t mask = 0;
735
736 switch (var->data.location) {
737 case FRAG_RESULT_COLOR:
738 mask = ~0;
739 break;
740 case FRAG_RESULT_DATA0:
741 case FRAG_RESULT_DATA1:
742 case FRAG_RESULT_DATA2:
743 case FRAG_RESULT_DATA3:
744 mask = 1 << (var->data.location - FRAG_RESULT_DATA0);
745 break;
746 }
747
748 if (c->fs_key->int_color_rb & mask) {
749 var->type =
750 glsl_vector_type(GLSL_TYPE_INT,
751 glsl_get_components(var->type));
752 } else if (c->fs_key->uint_color_rb & mask) {
753 var->type =
754 glsl_vector_type(GLSL_TYPE_UINT,
755 glsl_get_components(var->type));
756 }
757 }
758 }
759
760 static void
761 v3d_nir_lower_fs_early(struct v3d_compile *c)
762 {
763 if (c->fs_key->int_color_rb || c->fs_key->uint_color_rb)
764 v3d_fixup_fs_output_types(c);
765
766 /* If the shader has no non-TLB side effects, we can promote it to
767 * enabling early_fragment_tests even if the user didn't.
768 */
769 if (!(c->s->info.num_images ||
770 c->s->info.num_ssbos ||
771 c->s->info.num_abos)) {
772 c->s->info.fs.early_fragment_tests = true;
773 }
774 }
775
776 static void
777 v3d_nir_lower_vs_late(struct v3d_compile *c)
778 {
779 if (c->vs_key->clamp_color)
780 NIR_PASS_V(c->s, nir_lower_clamp_color_outputs);
781
782 if (c->key->ucp_enables) {
783 NIR_PASS_V(c->s, nir_lower_clip_vs, c->key->ucp_enables,
784 false);
785 NIR_PASS_V(c->s, nir_lower_io_to_scalar,
786 nir_var_shader_out);
787 }
788
789 /* Note: VS output scalarizing must happen after nir_lower_clip_vs. */
790 NIR_PASS_V(c->s, nir_lower_io_to_scalar, nir_var_shader_out);
791 }
792
793 static void
794 v3d_nir_lower_fs_late(struct v3d_compile *c)
795 {
796 if (c->fs_key->light_twoside)
797 NIR_PASS_V(c->s, nir_lower_two_sided_color);
798
799 if (c->fs_key->clamp_color)
800 NIR_PASS_V(c->s, nir_lower_clamp_color_outputs);
801
802 if (c->fs_key->alpha_test) {
803 NIR_PASS_V(c->s, nir_lower_alpha_test,
804 c->fs_key->alpha_test_func,
805 false);
806 }
807
808 if (c->key->ucp_enables)
809 NIR_PASS_V(c->s, nir_lower_clip_fs, c->key->ucp_enables);
810
811 /* Note: FS input scalarizing must happen after
812 * nir_lower_two_sided_color, which only handles a vec4 at a time.
813 */
814 NIR_PASS_V(c->s, nir_lower_io_to_scalar, nir_var_shader_in);
815 }
816
817 static uint32_t
818 vir_get_max_temps(struct v3d_compile *c)
819 {
820 int max_ip = 0;
821 vir_for_each_inst_inorder(inst, c)
822 max_ip++;
823
824 uint32_t *pressure = rzalloc_array(NULL, uint32_t, max_ip);
825
826 for (int t = 0; t < c->num_temps; t++) {
827 for (int i = c->temp_start[t]; (i < c->temp_end[t] &&
828 i < max_ip); i++) {
829 if (i > max_ip)
830 break;
831 pressure[i]++;
832 }
833 }
834
835 uint32_t max_temps = 0;
836 for (int i = 0; i < max_ip; i++)
837 max_temps = MAX2(max_temps, pressure[i]);
838
839 ralloc_free(pressure);
840
841 return max_temps;
842 }
843
844 uint64_t *v3d_compile(const struct v3d_compiler *compiler,
845 struct v3d_key *key,
846 struct v3d_prog_data **out_prog_data,
847 nir_shader *s,
848 void (*debug_output)(const char *msg,
849 void *debug_output_data),
850 void *debug_output_data,
851 int program_id, int variant_id,
852 uint32_t *final_assembly_size)
853 {
854 struct v3d_prog_data *prog_data;
855 struct v3d_compile *c = vir_compile_init(compiler, key, s,
856 debug_output, debug_output_data,
857 program_id, variant_id);
858
859 switch (c->s->info.stage) {
860 case MESA_SHADER_VERTEX:
861 c->vs_key = (struct v3d_vs_key *)key;
862 prog_data = rzalloc_size(NULL, sizeof(struct v3d_vs_prog_data));
863 break;
864 case MESA_SHADER_FRAGMENT:
865 c->fs_key = (struct v3d_fs_key *)key;
866 prog_data = rzalloc_size(NULL, sizeof(struct v3d_fs_prog_data));
867 break;
868 default:
869 unreachable("unsupported shader stage");
870 }
871
872 if (c->s->info.stage == MESA_SHADER_VERTEX) {
873 v3d_nir_lower_vs_early(c);
874 } else {
875 assert(c->s->info.stage == MESA_SHADER_FRAGMENT);
876 v3d_nir_lower_fs_early(c);
877 }
878
879 v3d_lower_nir(c);
880
881 if (c->s->info.stage == MESA_SHADER_VERTEX) {
882 v3d_nir_lower_vs_late(c);
883 } else {
884 assert(c->s->info.stage == MESA_SHADER_FRAGMENT);
885 v3d_nir_lower_fs_late(c);
886 }
887
888 NIR_PASS_V(c->s, v3d_nir_lower_io, c);
889 NIR_PASS_V(c->s, v3d_nir_lower_txf_ms, c);
890 NIR_PASS_V(c->s, v3d_nir_lower_image_load_store);
891 NIR_PASS_V(c->s, nir_lower_idiv);
892
893 v3d_optimize_nir(c->s);
894 NIR_PASS_V(c->s, nir_lower_bool_to_int32);
895 NIR_PASS_V(c->s, nir_convert_from_ssa, true);
896
897 v3d_nir_to_vir(c);
898
899 v3d_set_prog_data(c, prog_data);
900
901 *out_prog_data = prog_data;
902
903 char *shaderdb;
904 int ret = asprintf(&shaderdb,
905 "%s shader: %d inst, %d threads, %d loops, "
906 "%d uniforms, %d max-temps, %d:%d spills:fills",
907 vir_get_stage_name(c),
908 c->qpu_inst_count,
909 c->threads,
910 c->loops,
911 c->num_uniforms,
912 vir_get_max_temps(c),
913 c->spills,
914 c->fills);
915 if (ret >= 0) {
916 c->debug_output(shaderdb, c->debug_output_data);
917 free(shaderdb);
918 }
919
920 return v3d_return_qpu_insts(c, final_assembly_size);
921 }
922
923 void
924 vir_remove_instruction(struct v3d_compile *c, struct qinst *qinst)
925 {
926 if (qinst->dst.file == QFILE_TEMP)
927 c->defs[qinst->dst.index] = NULL;
928
929 assert(&qinst->link != c->cursor.link);
930
931 list_del(&qinst->link);
932 free(qinst);
933
934 c->live_intervals_valid = false;
935 }
936
937 struct qreg
938 vir_follow_movs(struct v3d_compile *c, struct qreg reg)
939 {
940 /* XXX
941 int pack = reg.pack;
942
943 while (reg.file == QFILE_TEMP &&
944 c->defs[reg.index] &&
945 (c->defs[reg.index]->op == QOP_MOV ||
946 c->defs[reg.index]->op == QOP_FMOV) &&
947 !c->defs[reg.index]->dst.pack &&
948 !c->defs[reg.index]->src[0].pack) {
949 reg = c->defs[reg.index]->src[0];
950 }
951
952 reg.pack = pack;
953 */
954 return reg;
955 }
956
957 void
958 vir_compile_destroy(struct v3d_compile *c)
959 {
960 /* Defuse the assert that we aren't removing the cursor's instruction.
961 */
962 c->cursor.link = NULL;
963
964 vir_for_each_block(block, c) {
965 while (!list_empty(&block->instructions)) {
966 struct qinst *qinst =
967 list_first_entry(&block->instructions,
968 struct qinst, link);
969 vir_remove_instruction(c, qinst);
970 }
971 }
972
973 ralloc_free(c);
974 }
975
976 uint32_t
977 vir_get_uniform_index(struct v3d_compile *c,
978 enum quniform_contents contents,
979 uint32_t data)
980 {
981 for (int i = 0; i < c->num_uniforms; i++) {
982 if (c->uniform_contents[i] == contents &&
983 c->uniform_data[i] == data) {
984 return i;
985 }
986 }
987
988 uint32_t uniform = c->num_uniforms++;
989
990 if (uniform >= c->uniform_array_size) {
991 c->uniform_array_size = MAX2(MAX2(16, uniform + 1),
992 c->uniform_array_size * 2);
993
994 c->uniform_data = reralloc(c, c->uniform_data,
995 uint32_t,
996 c->uniform_array_size);
997 c->uniform_contents = reralloc(c, c->uniform_contents,
998 enum quniform_contents,
999 c->uniform_array_size);
1000 }
1001
1002 c->uniform_contents[uniform] = contents;
1003 c->uniform_data[uniform] = data;
1004
1005 return uniform;
1006 }
1007
1008 struct qreg
1009 vir_uniform(struct v3d_compile *c,
1010 enum quniform_contents contents,
1011 uint32_t data)
1012 {
1013 struct qinst *inst = vir_NOP(c);
1014 inst->qpu.sig.ldunif = true;
1015 inst->uniform = vir_get_uniform_index(c, contents, data);
1016 inst->dst = vir_get_temp(c);
1017 c->defs[inst->dst.index] = inst;
1018 return inst->dst;
1019 }
1020
1021 #define OPTPASS(func) \
1022 do { \
1023 bool stage_progress = func(c); \
1024 if (stage_progress) { \
1025 progress = true; \
1026 if (print_opt_debug) { \
1027 fprintf(stderr, \
1028 "VIR opt pass %2d: %s progress\n", \
1029 pass, #func); \
1030 } \
1031 /*XXX vir_validate(c);*/ \
1032 } \
1033 } while (0)
1034
1035 void
1036 vir_optimize(struct v3d_compile *c)
1037 {
1038 bool print_opt_debug = false;
1039 int pass = 1;
1040
1041 while (true) {
1042 bool progress = false;
1043
1044 OPTPASS(vir_opt_copy_propagate);
1045 OPTPASS(vir_opt_redundant_flags);
1046 OPTPASS(vir_opt_dead_code);
1047 OPTPASS(vir_opt_small_immediates);
1048
1049 if (!progress)
1050 break;
1051
1052 pass++;
1053 }
1054 }
1055
1056 const char *
1057 vir_get_stage_name(struct v3d_compile *c)
1058 {
1059 if (c->vs_key && c->vs_key->is_coord)
1060 return "MESA_SHADER_COORD";
1061 else
1062 return gl_shader_stage_name(c->s->info.stage);
1063 }