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v3d: Use nir_remove_unused_io_vars to handle binner shader output DCE
[mesa.git] / src / broadcom / compiler / vir.c
1 /*
2 * Copyright © 2016-2017 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "broadcom/common/v3d_device_info.h"
25 #include "v3d_compiler.h"
26
27 int
28 vir_get_non_sideband_nsrc(struct qinst *inst)
29 {
30 switch (inst->qpu.type) {
31 case V3D_QPU_INSTR_TYPE_BRANCH:
32 return 0;
33 case V3D_QPU_INSTR_TYPE_ALU:
34 if (inst->qpu.alu.add.op != V3D_QPU_A_NOP)
35 return v3d_qpu_add_op_num_src(inst->qpu.alu.add.op);
36 else
37 return v3d_qpu_mul_op_num_src(inst->qpu.alu.mul.op);
38 }
39
40 return 0;
41 }
42
43 int
44 vir_get_nsrc(struct qinst *inst)
45 {
46 int nsrc = vir_get_non_sideband_nsrc(inst);
47
48 if (vir_has_implicit_uniform(inst))
49 nsrc++;
50
51 return nsrc;
52 }
53
54 bool
55 vir_has_implicit_uniform(struct qinst *inst)
56 {
57 switch (inst->qpu.type) {
58 case V3D_QPU_INSTR_TYPE_BRANCH:
59 return true;
60 case V3D_QPU_INSTR_TYPE_ALU:
61 switch (inst->dst.file) {
62 case QFILE_TLBU:
63 return true;
64 default:
65 return inst->has_implicit_uniform;
66 }
67 }
68 return false;
69 }
70
71 /* The sideband uniform for textures gets stored after the normal ALU
72 * arguments.
73 */
74 int
75 vir_get_implicit_uniform_src(struct qinst *inst)
76 {
77 if (!vir_has_implicit_uniform(inst))
78 return -1;
79 return vir_get_nsrc(inst) - 1;
80 }
81
82 /**
83 * Returns whether the instruction has any side effects that must be
84 * preserved.
85 */
86 bool
87 vir_has_side_effects(struct v3d_compile *c, struct qinst *inst)
88 {
89 switch (inst->qpu.type) {
90 case V3D_QPU_INSTR_TYPE_BRANCH:
91 return true;
92 case V3D_QPU_INSTR_TYPE_ALU:
93 switch (inst->qpu.alu.add.op) {
94 case V3D_QPU_A_SETREVF:
95 case V3D_QPU_A_SETMSF:
96 case V3D_QPU_A_VPMSETUP:
97 case V3D_QPU_A_STVPMV:
98 case V3D_QPU_A_STVPMD:
99 case V3D_QPU_A_STVPMP:
100 case V3D_QPU_A_VPMWT:
101 case V3D_QPU_A_TMUWT:
102 return true;
103 default:
104 break;
105 }
106
107 switch (inst->qpu.alu.mul.op) {
108 case V3D_QPU_M_MULTOP:
109 return true;
110 default:
111 break;
112 }
113 }
114
115 if (inst->qpu.sig.ldtmu ||
116 inst->qpu.sig.ldvary ||
117 inst->qpu.sig.wrtmuc ||
118 inst->qpu.sig.thrsw) {
119 return true;
120 }
121
122 return false;
123 }
124
125 bool
126 vir_is_float_input(struct qinst *inst)
127 {
128 /* XXX: More instrs */
129 switch (inst->qpu.type) {
130 case V3D_QPU_INSTR_TYPE_BRANCH:
131 return false;
132 case V3D_QPU_INSTR_TYPE_ALU:
133 switch (inst->qpu.alu.add.op) {
134 case V3D_QPU_A_FADD:
135 case V3D_QPU_A_FSUB:
136 case V3D_QPU_A_FMIN:
137 case V3D_QPU_A_FMAX:
138 case V3D_QPU_A_FTOIN:
139 return true;
140 default:
141 break;
142 }
143
144 switch (inst->qpu.alu.mul.op) {
145 case V3D_QPU_M_FMOV:
146 case V3D_QPU_M_VFMUL:
147 case V3D_QPU_M_FMUL:
148 return true;
149 default:
150 break;
151 }
152 }
153
154 return false;
155 }
156
157 bool
158 vir_is_raw_mov(struct qinst *inst)
159 {
160 if (inst->qpu.type != V3D_QPU_INSTR_TYPE_ALU ||
161 (inst->qpu.alu.mul.op != V3D_QPU_M_FMOV &&
162 inst->qpu.alu.mul.op != V3D_QPU_M_MOV)) {
163 return false;
164 }
165
166 if (inst->qpu.alu.add.output_pack != V3D_QPU_PACK_NONE ||
167 inst->qpu.alu.mul.output_pack != V3D_QPU_PACK_NONE) {
168 return false;
169 }
170
171 if (inst->qpu.flags.ac != V3D_QPU_COND_NONE ||
172 inst->qpu.flags.mc != V3D_QPU_COND_NONE)
173 return false;
174
175 return true;
176 }
177
178 bool
179 vir_is_add(struct qinst *inst)
180 {
181 return (inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU &&
182 inst->qpu.alu.add.op != V3D_QPU_A_NOP);
183 }
184
185 bool
186 vir_is_mul(struct qinst *inst)
187 {
188 return (inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU &&
189 inst->qpu.alu.mul.op != V3D_QPU_M_NOP);
190 }
191
192 bool
193 vir_is_tex(struct qinst *inst)
194 {
195 if (inst->dst.file == QFILE_MAGIC)
196 return v3d_qpu_magic_waddr_is_tmu(inst->dst.index);
197
198 if (inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU &&
199 inst->qpu.alu.add.op == V3D_QPU_A_TMUWT) {
200 return true;
201 }
202
203 return false;
204 }
205
206 bool
207 vir_depends_on_flags(struct qinst *inst)
208 {
209 if (inst->qpu.type == V3D_QPU_INSTR_TYPE_BRANCH) {
210 return (inst->qpu.branch.cond != V3D_QPU_BRANCH_COND_ALWAYS);
211 } else {
212 return (inst->qpu.flags.ac != V3D_QPU_COND_NONE &&
213 inst->qpu.flags.mc != V3D_QPU_COND_NONE);
214 }
215 }
216
217 bool
218 vir_writes_r3(const struct v3d_device_info *devinfo, struct qinst *inst)
219 {
220 for (int i = 0; i < vir_get_nsrc(inst); i++) {
221 switch (inst->src[i].file) {
222 case QFILE_VPM:
223 return true;
224 default:
225 break;
226 }
227 }
228
229 if (devinfo->ver < 41 && (inst->qpu.sig.ldvary ||
230 inst->qpu.sig.ldtlb ||
231 inst->qpu.sig.ldtlbu ||
232 inst->qpu.sig.ldvpm)) {
233 return true;
234 }
235
236 return false;
237 }
238
239 bool
240 vir_writes_r4(const struct v3d_device_info *devinfo, struct qinst *inst)
241 {
242 switch (inst->dst.file) {
243 case QFILE_MAGIC:
244 switch (inst->dst.index) {
245 case V3D_QPU_WADDR_RECIP:
246 case V3D_QPU_WADDR_RSQRT:
247 case V3D_QPU_WADDR_EXP:
248 case V3D_QPU_WADDR_LOG:
249 case V3D_QPU_WADDR_SIN:
250 return true;
251 }
252 break;
253 default:
254 break;
255 }
256
257 if (devinfo->ver < 41 && inst->qpu.sig.ldtmu)
258 return true;
259
260 return false;
261 }
262
263 void
264 vir_set_unpack(struct qinst *inst, int src,
265 enum v3d_qpu_input_unpack unpack)
266 {
267 assert(src == 0 || src == 1);
268
269 if (vir_is_add(inst)) {
270 if (src == 0)
271 inst->qpu.alu.add.a_unpack = unpack;
272 else
273 inst->qpu.alu.add.b_unpack = unpack;
274 } else {
275 assert(vir_is_mul(inst));
276 if (src == 0)
277 inst->qpu.alu.mul.a_unpack = unpack;
278 else
279 inst->qpu.alu.mul.b_unpack = unpack;
280 }
281 }
282
283 void
284 vir_set_cond(struct qinst *inst, enum v3d_qpu_cond cond)
285 {
286 if (vir_is_add(inst)) {
287 inst->qpu.flags.ac = cond;
288 } else {
289 assert(vir_is_mul(inst));
290 inst->qpu.flags.mc = cond;
291 }
292 }
293
294 void
295 vir_set_pf(struct qinst *inst, enum v3d_qpu_pf pf)
296 {
297 if (vir_is_add(inst)) {
298 inst->qpu.flags.apf = pf;
299 } else {
300 assert(vir_is_mul(inst));
301 inst->qpu.flags.mpf = pf;
302 }
303 }
304
305 #if 0
306 uint8_t
307 vir_channels_written(struct qinst *inst)
308 {
309 if (vir_is_mul(inst)) {
310 switch (inst->dst.pack) {
311 case QPU_PACK_MUL_NOP:
312 case QPU_PACK_MUL_8888:
313 return 0xf;
314 case QPU_PACK_MUL_8A:
315 return 0x1;
316 case QPU_PACK_MUL_8B:
317 return 0x2;
318 case QPU_PACK_MUL_8C:
319 return 0x4;
320 case QPU_PACK_MUL_8D:
321 return 0x8;
322 }
323 } else {
324 switch (inst->dst.pack) {
325 case QPU_PACK_A_NOP:
326 case QPU_PACK_A_8888:
327 case QPU_PACK_A_8888_SAT:
328 case QPU_PACK_A_32_SAT:
329 return 0xf;
330 case QPU_PACK_A_8A:
331 case QPU_PACK_A_8A_SAT:
332 return 0x1;
333 case QPU_PACK_A_8B:
334 case QPU_PACK_A_8B_SAT:
335 return 0x2;
336 case QPU_PACK_A_8C:
337 case QPU_PACK_A_8C_SAT:
338 return 0x4;
339 case QPU_PACK_A_8D:
340 case QPU_PACK_A_8D_SAT:
341 return 0x8;
342 case QPU_PACK_A_16A:
343 case QPU_PACK_A_16A_SAT:
344 return 0x3;
345 case QPU_PACK_A_16B:
346 case QPU_PACK_A_16B_SAT:
347 return 0xc;
348 }
349 }
350 unreachable("Bad pack field");
351 }
352 #endif
353
354 struct qreg
355 vir_get_temp(struct v3d_compile *c)
356 {
357 struct qreg reg;
358
359 reg.file = QFILE_TEMP;
360 reg.index = c->num_temps++;
361
362 if (c->num_temps > c->defs_array_size) {
363 uint32_t old_size = c->defs_array_size;
364 c->defs_array_size = MAX2(old_size * 2, 16);
365
366 c->defs = reralloc(c, c->defs, struct qinst *,
367 c->defs_array_size);
368 memset(&c->defs[old_size], 0,
369 sizeof(c->defs[0]) * (c->defs_array_size - old_size));
370
371 c->spillable = reralloc(c, c->spillable,
372 BITSET_WORD,
373 BITSET_WORDS(c->defs_array_size));
374 for (int i = old_size; i < c->defs_array_size; i++)
375 BITSET_SET(c->spillable, i);
376 }
377
378 return reg;
379 }
380
381 struct qinst *
382 vir_add_inst(enum v3d_qpu_add_op op, struct qreg dst, struct qreg src0, struct qreg src1)
383 {
384 struct qinst *inst = calloc(1, sizeof(*inst));
385
386 inst->qpu = v3d_qpu_nop();
387 inst->qpu.alu.add.op = op;
388
389 inst->dst = dst;
390 inst->src[0] = src0;
391 inst->src[1] = src1;
392 inst->uniform = ~0;
393
394 return inst;
395 }
396
397 struct qinst *
398 vir_mul_inst(enum v3d_qpu_mul_op op, struct qreg dst, struct qreg src0, struct qreg src1)
399 {
400 struct qinst *inst = calloc(1, sizeof(*inst));
401
402 inst->qpu = v3d_qpu_nop();
403 inst->qpu.alu.mul.op = op;
404
405 inst->dst = dst;
406 inst->src[0] = src0;
407 inst->src[1] = src1;
408 inst->uniform = ~0;
409
410 return inst;
411 }
412
413 struct qinst *
414 vir_branch_inst(enum v3d_qpu_branch_cond cond, struct qreg src)
415 {
416 struct qinst *inst = calloc(1, sizeof(*inst));
417
418 inst->qpu = v3d_qpu_nop();
419 inst->qpu.type = V3D_QPU_INSTR_TYPE_BRANCH;
420 inst->qpu.branch.cond = cond;
421 inst->qpu.branch.msfign = V3D_QPU_MSFIGN_NONE;
422 inst->qpu.branch.bdi = V3D_QPU_BRANCH_DEST_REL;
423 inst->qpu.branch.ub = true;
424 inst->qpu.branch.bdu = V3D_QPU_BRANCH_DEST_REL;
425
426 inst->dst = vir_reg(QFILE_NULL, 0);
427 inst->src[0] = src;
428 inst->uniform = ~0;
429
430 return inst;
431 }
432
433 static void
434 vir_emit(struct v3d_compile *c, struct qinst *inst)
435 {
436 switch (c->cursor.mode) {
437 case vir_cursor_add:
438 list_add(&inst->link, c->cursor.link);
439 break;
440 case vir_cursor_addtail:
441 list_addtail(&inst->link, c->cursor.link);
442 break;
443 }
444
445 c->cursor = vir_after_inst(inst);
446 c->live_intervals_valid = false;
447 }
448
449 /* Updates inst to write to a new temporary, emits it, and notes the def. */
450 struct qreg
451 vir_emit_def(struct v3d_compile *c, struct qinst *inst)
452 {
453 assert(inst->dst.file == QFILE_NULL);
454
455 /* If we're emitting an instruction that's a def, it had better be
456 * writing a register.
457 */
458 if (inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU) {
459 assert(inst->qpu.alu.add.op == V3D_QPU_A_NOP ||
460 v3d_qpu_add_op_has_dst(inst->qpu.alu.add.op));
461 assert(inst->qpu.alu.mul.op == V3D_QPU_M_NOP ||
462 v3d_qpu_mul_op_has_dst(inst->qpu.alu.mul.op));
463 }
464
465 inst->dst = vir_get_temp(c);
466
467 if (inst->dst.file == QFILE_TEMP)
468 c->defs[inst->dst.index] = inst;
469
470 vir_emit(c, inst);
471
472 return inst->dst;
473 }
474
475 struct qinst *
476 vir_emit_nondef(struct v3d_compile *c, struct qinst *inst)
477 {
478 if (inst->dst.file == QFILE_TEMP)
479 c->defs[inst->dst.index] = NULL;
480
481 vir_emit(c, inst);
482
483 return inst;
484 }
485
486 struct qblock *
487 vir_new_block(struct v3d_compile *c)
488 {
489 struct qblock *block = rzalloc(c, struct qblock);
490
491 list_inithead(&block->instructions);
492
493 block->predecessors = _mesa_set_create(block,
494 _mesa_hash_pointer,
495 _mesa_key_pointer_equal);
496
497 block->index = c->next_block_index++;
498
499 return block;
500 }
501
502 void
503 vir_set_emit_block(struct v3d_compile *c, struct qblock *block)
504 {
505 c->cur_block = block;
506 c->cursor = vir_after_block(block);
507 list_addtail(&block->link, &c->blocks);
508 }
509
510 struct qblock *
511 vir_entry_block(struct v3d_compile *c)
512 {
513 return list_first_entry(&c->blocks, struct qblock, link);
514 }
515
516 struct qblock *
517 vir_exit_block(struct v3d_compile *c)
518 {
519 return list_last_entry(&c->blocks, struct qblock, link);
520 }
521
522 void
523 vir_link_blocks(struct qblock *predecessor, struct qblock *successor)
524 {
525 _mesa_set_add(successor->predecessors, predecessor);
526 if (predecessor->successors[0]) {
527 assert(!predecessor->successors[1]);
528 predecessor->successors[1] = successor;
529 } else {
530 predecessor->successors[0] = successor;
531 }
532 }
533
534 const struct v3d_compiler *
535 v3d_compiler_init(const struct v3d_device_info *devinfo)
536 {
537 struct v3d_compiler *compiler = rzalloc(NULL, struct v3d_compiler);
538 if (!compiler)
539 return NULL;
540
541 compiler->devinfo = devinfo;
542
543 if (!vir_init_reg_sets(compiler)) {
544 ralloc_free(compiler);
545 return NULL;
546 }
547
548 return compiler;
549 }
550
551 void
552 v3d_compiler_free(const struct v3d_compiler *compiler)
553 {
554 ralloc_free((void *)compiler);
555 }
556
557 static struct v3d_compile *
558 vir_compile_init(const struct v3d_compiler *compiler,
559 struct v3d_key *key,
560 nir_shader *s,
561 int program_id, int variant_id)
562 {
563 struct v3d_compile *c = rzalloc(NULL, struct v3d_compile);
564
565 c->compiler = compiler;
566 c->devinfo = compiler->devinfo;
567 c->key = key;
568 c->program_id = program_id;
569 c->variant_id = variant_id;
570 c->threads = 4;
571
572 s = nir_shader_clone(c, s);
573 c->s = s;
574
575 list_inithead(&c->blocks);
576 vir_set_emit_block(c, vir_new_block(c));
577
578 c->output_position_index = -1;
579 c->output_point_size_index = -1;
580 c->output_sample_mask_index = -1;
581
582 c->def_ht = _mesa_hash_table_create(c, _mesa_hash_pointer,
583 _mesa_key_pointer_equal);
584
585 return c;
586 }
587
588 static int
589 type_size_vec4(const struct glsl_type *type)
590 {
591 return glsl_count_attribute_slots(type, false);
592 }
593
594 static void
595 v3d_lower_nir(struct v3d_compile *c)
596 {
597 struct nir_lower_tex_options tex_options = {
598 .lower_txd = true,
599 .lower_rect = false, /* XXX: Use this on V3D 3.x */
600 .lower_txp = ~0,
601 /* Apply swizzles to all samplers. */
602 .swizzle_result = ~0,
603 };
604
605 /* Lower the format swizzle and (for 32-bit returns)
606 * ARB_texture_swizzle-style swizzle.
607 */
608 for (int i = 0; i < ARRAY_SIZE(c->key->tex); i++) {
609 for (int j = 0; j < 4; j++)
610 tex_options.swizzles[i][j] = c->key->tex[i].swizzle[j];
611
612 if (c->key->tex[i].clamp_s)
613 tex_options.saturate_s |= 1 << i;
614 if (c->key->tex[i].clamp_t)
615 tex_options.saturate_t |= 1 << i;
616 if (c->key->tex[i].clamp_r)
617 tex_options.saturate_r |= 1 << i;
618 }
619
620 NIR_PASS_V(c->s, nir_lower_tex, &tex_options);
621 }
622
623 static void
624 v3d_lower_nir_late(struct v3d_compile *c)
625 {
626 NIR_PASS_V(c->s, v3d_nir_lower_io, c);
627 NIR_PASS_V(c->s, v3d_nir_lower_txf_ms, c);
628 NIR_PASS_V(c->s, nir_lower_idiv);
629 }
630
631 static void
632 v3d_set_prog_data_uniforms(struct v3d_compile *c,
633 struct v3d_prog_data *prog_data)
634 {
635 int count = c->num_uniforms;
636 struct v3d_uniform_list *ulist = &prog_data->uniforms;
637
638 ulist->count = count;
639 ulist->data = ralloc_array(prog_data, uint32_t, count);
640 memcpy(ulist->data, c->uniform_data,
641 count * sizeof(*ulist->data));
642 ulist->contents = ralloc_array(prog_data, enum quniform_contents, count);
643 memcpy(ulist->contents, c->uniform_contents,
644 count * sizeof(*ulist->contents));
645 }
646
647 /* Copy the compiler UBO range state to the compiled shader, dropping out
648 * arrays that were never referenced by an indirect load.
649 *
650 * (Note that QIR dead code elimination of an array access still leaves that
651 * array alive, though)
652 */
653 static void
654 v3d_set_prog_data_ubo(struct v3d_compile *c,
655 struct v3d_prog_data *prog_data)
656 {
657 if (!c->num_ubo_ranges)
658 return;
659
660 prog_data->num_ubo_ranges = 0;
661 prog_data->ubo_ranges = ralloc_array(prog_data, struct v3d_ubo_range,
662 c->num_ubo_ranges);
663 for (int i = 0; i < c->num_ubo_ranges; i++) {
664 if (!c->ubo_range_used[i])
665 continue;
666
667 struct v3d_ubo_range *range = &c->ubo_ranges[i];
668 prog_data->ubo_ranges[prog_data->num_ubo_ranges++] = *range;
669 prog_data->ubo_size += range->size;
670 }
671
672 if (prog_data->ubo_size) {
673 if (V3D_DEBUG & V3D_DEBUG_SHADERDB) {
674 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d UBO uniforms\n",
675 vir_get_stage_name(c),
676 c->program_id, c->variant_id,
677 prog_data->ubo_size / 4);
678 }
679 }
680 }
681
682 static void
683 v3d_set_prog_data(struct v3d_compile *c,
684 struct v3d_prog_data *prog_data)
685 {
686 prog_data->threads = c->threads;
687 prog_data->single_seg = !c->last_thrsw;
688 prog_data->spill_size = c->spill_size;
689
690 v3d_set_prog_data_uniforms(c, prog_data);
691 v3d_set_prog_data_ubo(c, prog_data);
692 }
693
694 static uint64_t *
695 v3d_return_qpu_insts(struct v3d_compile *c, uint32_t *final_assembly_size)
696 {
697 *final_assembly_size = c->qpu_inst_count * sizeof(uint64_t);
698
699 uint64_t *qpu_insts = malloc(*final_assembly_size);
700 if (!qpu_insts)
701 return NULL;
702
703 memcpy(qpu_insts, c->qpu_insts, *final_assembly_size);
704
705 vir_compile_destroy(c);
706
707 return qpu_insts;
708 }
709
710 uint64_t *v3d_compile_vs(const struct v3d_compiler *compiler,
711 struct v3d_vs_key *key,
712 struct v3d_vs_prog_data *prog_data,
713 nir_shader *s,
714 int program_id, int variant_id,
715 uint32_t *final_assembly_size)
716 {
717 struct v3d_compile *c = vir_compile_init(compiler, &key->base, s,
718 program_id, variant_id);
719
720 c->vs_key = key;
721
722 /* Split our I/O vars and dead code eliminate the unused
723 * components.
724 */
725 NIR_PASS_V(c->s, nir_lower_io_to_scalar_early,
726 nir_var_shader_in | nir_var_shader_out);
727 uint64_t used_outputs[4] = {0};
728 for (int i = 0; i < c->vs_key->num_fs_inputs; i++) {
729 int slot = v3d_slot_get_slot(c->vs_key->fs_inputs[i]);
730 int comp = v3d_slot_get_component(c->vs_key->fs_inputs[i]);
731 used_outputs[comp] |= 1ull << slot;
732 }
733 NIR_PASS_V(c->s, nir_remove_unused_io_vars,
734 &c->s->outputs, used_outputs, NULL); /* demotes to globals */
735 NIR_PASS_V(c->s, nir_lower_global_vars_to_local);
736 v3d_optimize_nir(c->s);
737 NIR_PASS_V(c->s, nir_remove_dead_variables, nir_var_shader_in);
738 NIR_PASS_V(c->s, nir_lower_io, nir_var_shader_in | nir_var_shader_out,
739 type_size_vec4,
740 (nir_lower_io_options)0);
741
742 v3d_lower_nir(c);
743
744 if (key->clamp_color)
745 NIR_PASS_V(c->s, nir_lower_clamp_color_outputs);
746
747 if (key->base.ucp_enables) {
748 NIR_PASS_V(c->s, nir_lower_clip_vs, key->base.ucp_enables);
749 NIR_PASS_V(c->s, nir_lower_io_to_scalar,
750 nir_var_shader_out);
751 }
752
753 /* Note: VS output scalarizing must happen after nir_lower_clip_vs. */
754 NIR_PASS_V(c->s, nir_lower_io_to_scalar, nir_var_shader_out);
755
756 v3d_lower_nir_late(c);
757 v3d_optimize_nir(c->s);
758 NIR_PASS_V(c->s, nir_convert_from_ssa, true);
759
760 v3d_nir_to_vir(c);
761
762 v3d_set_prog_data(c, &prog_data->base);
763
764 prog_data->base.num_inputs = c->num_inputs;
765
766 /* The vertex data gets format converted by the VPM so that
767 * each attribute channel takes up a VPM column. Precompute
768 * the sizes for the shader record.
769 */
770 for (int i = 0; i < ARRAY_SIZE(prog_data->vattr_sizes); i++) {
771 prog_data->vattr_sizes[i] = c->vattr_sizes[i];
772 prog_data->vpm_input_size += c->vattr_sizes[i];
773 }
774
775 prog_data->uses_vid = (s->info.system_values_read &
776 (1ull << SYSTEM_VALUE_VERTEX_ID));
777 prog_data->uses_iid = (s->info.system_values_read &
778 (1ull << SYSTEM_VALUE_INSTANCE_ID));
779
780 if (prog_data->uses_vid)
781 prog_data->vpm_input_size++;
782 if (prog_data->uses_iid)
783 prog_data->vpm_input_size++;
784
785 /* Input/output segment size are in sectors (8 rows of 32 bits per
786 * channel).
787 */
788 prog_data->vpm_input_size = align(prog_data->vpm_input_size, 8) / 8;
789 prog_data->vpm_output_size = align(c->num_vpm_writes, 8) / 8;
790
791 /* Compute VCM cache size. We set up our program to take up less than
792 * half of the VPM, so that any set of bin and render programs won't
793 * run out of space. We need space for at least one input segment,
794 * and then allocate the rest to output segments (one for the current
795 * program, the rest to VCM). The valid range of the VCM cache size
796 * field is 1-4 16-vertex batches, but GFXH-1744 limits us to 2-4
797 * batches.
798 */
799 assert(c->devinfo->vpm_size);
800 int sector_size = 16 * sizeof(uint32_t) * 8;
801 int vpm_size_in_sectors = c->devinfo->vpm_size / sector_size;
802 int half_vpm = vpm_size_in_sectors / 2;
803 int vpm_output_sectors = half_vpm - prog_data->vpm_input_size;
804 int vpm_output_batches = vpm_output_sectors / prog_data->vpm_output_size;
805 assert(vpm_output_batches >= 2);
806 prog_data->vcm_cache_size = CLAMP(vpm_output_batches - 1, 2, 4);
807
808 return v3d_return_qpu_insts(c, final_assembly_size);
809 }
810
811 static void
812 v3d_set_fs_prog_data_inputs(struct v3d_compile *c,
813 struct v3d_fs_prog_data *prog_data)
814 {
815 prog_data->base.num_inputs = c->num_inputs;
816 memcpy(prog_data->input_slots, c->input_slots,
817 c->num_inputs * sizeof(*c->input_slots));
818
819 STATIC_ASSERT(ARRAY_SIZE(prog_data->flat_shade_flags) >
820 (V3D_MAX_FS_INPUTS - 1) / 24);
821 for (int i = 0; i < V3D_MAX_FS_INPUTS; i++) {
822 if (BITSET_TEST(c->flat_shade_flags, i))
823 prog_data->flat_shade_flags[i / 24] |= 1 << (i % 24);
824
825 if (BITSET_TEST(c->noperspective_flags, i))
826 prog_data->noperspective_flags[i / 24] |= 1 << (i % 24);
827
828 if (BITSET_TEST(c->centroid_flags, i))
829 prog_data->centroid_flags[i / 24] |= 1 << (i % 24);
830 }
831 }
832
833 static void
834 v3d_fixup_fs_output_types(struct v3d_compile *c)
835 {
836 nir_foreach_variable(var, &c->s->outputs) {
837 uint32_t mask = 0;
838
839 switch (var->data.location) {
840 case FRAG_RESULT_COLOR:
841 mask = ~0;
842 break;
843 case FRAG_RESULT_DATA0:
844 case FRAG_RESULT_DATA1:
845 case FRAG_RESULT_DATA2:
846 case FRAG_RESULT_DATA3:
847 mask = 1 << (var->data.location - FRAG_RESULT_DATA0);
848 break;
849 }
850
851 if (c->fs_key->int_color_rb & mask) {
852 var->type =
853 glsl_vector_type(GLSL_TYPE_INT,
854 glsl_get_components(var->type));
855 } else if (c->fs_key->uint_color_rb & mask) {
856 var->type =
857 glsl_vector_type(GLSL_TYPE_UINT,
858 glsl_get_components(var->type));
859 }
860 }
861 }
862
863 uint64_t *v3d_compile_fs(const struct v3d_compiler *compiler,
864 struct v3d_fs_key *key,
865 struct v3d_fs_prog_data *prog_data,
866 nir_shader *s,
867 int program_id, int variant_id,
868 uint32_t *final_assembly_size)
869 {
870 struct v3d_compile *c = vir_compile_init(compiler, &key->base, s,
871 program_id, variant_id);
872
873 c->fs_key = key;
874
875 if (key->int_color_rb || key->uint_color_rb)
876 v3d_fixup_fs_output_types(c);
877
878 v3d_lower_nir(c);
879
880 if (key->light_twoside)
881 NIR_PASS_V(c->s, nir_lower_two_sided_color);
882
883 if (key->clamp_color)
884 NIR_PASS_V(c->s, nir_lower_clamp_color_outputs);
885
886 if (key->alpha_test) {
887 NIR_PASS_V(c->s, nir_lower_alpha_test, key->alpha_test_func,
888 false);
889 }
890
891 if (key->base.ucp_enables)
892 NIR_PASS_V(c->s, nir_lower_clip_fs, key->base.ucp_enables);
893
894 /* Note: FS input scalarizing must happen after
895 * nir_lower_two_sided_color, which only handles a vec4 at a time.
896 */
897 NIR_PASS_V(c->s, nir_lower_io_to_scalar, nir_var_shader_in);
898
899 v3d_lower_nir_late(c);
900 v3d_optimize_nir(c->s);
901 NIR_PASS_V(c->s, nir_convert_from_ssa, true);
902
903 v3d_nir_to_vir(c);
904
905 v3d_set_prog_data(c, &prog_data->base);
906 v3d_set_fs_prog_data_inputs(c, prog_data);
907 prog_data->writes_z = (c->s->info.outputs_written &
908 (1 << FRAG_RESULT_DEPTH));
909 prog_data->discard = (c->s->info.fs.uses_discard ||
910 c->fs_key->sample_alpha_to_coverage);
911 prog_data->uses_center_w = c->uses_center_w;
912
913 return v3d_return_qpu_insts(c, final_assembly_size);
914 }
915
916 void
917 vir_remove_instruction(struct v3d_compile *c, struct qinst *qinst)
918 {
919 if (qinst->dst.file == QFILE_TEMP)
920 c->defs[qinst->dst.index] = NULL;
921
922 assert(&qinst->link != c->cursor.link);
923
924 list_del(&qinst->link);
925 free(qinst);
926
927 c->live_intervals_valid = false;
928 }
929
930 struct qreg
931 vir_follow_movs(struct v3d_compile *c, struct qreg reg)
932 {
933 /* XXX
934 int pack = reg.pack;
935
936 while (reg.file == QFILE_TEMP &&
937 c->defs[reg.index] &&
938 (c->defs[reg.index]->op == QOP_MOV ||
939 c->defs[reg.index]->op == QOP_FMOV) &&
940 !c->defs[reg.index]->dst.pack &&
941 !c->defs[reg.index]->src[0].pack) {
942 reg = c->defs[reg.index]->src[0];
943 }
944
945 reg.pack = pack;
946 */
947 return reg;
948 }
949
950 void
951 vir_compile_destroy(struct v3d_compile *c)
952 {
953 /* Defuse the assert that we aren't removing the cursor's instruction.
954 */
955 c->cursor.link = NULL;
956
957 vir_for_each_block(block, c) {
958 while (!list_empty(&block->instructions)) {
959 struct qinst *qinst =
960 list_first_entry(&block->instructions,
961 struct qinst, link);
962 vir_remove_instruction(c, qinst);
963 }
964 }
965
966 ralloc_free(c);
967 }
968
969 struct qreg
970 vir_uniform(struct v3d_compile *c,
971 enum quniform_contents contents,
972 uint32_t data)
973 {
974 for (int i = 0; i < c->num_uniforms; i++) {
975 if (c->uniform_contents[i] == contents &&
976 c->uniform_data[i] == data) {
977 return vir_reg(QFILE_UNIF, i);
978 }
979 }
980
981 uint32_t uniform = c->num_uniforms++;
982
983 if (uniform >= c->uniform_array_size) {
984 c->uniform_array_size = MAX2(MAX2(16, uniform + 1),
985 c->uniform_array_size * 2);
986
987 c->uniform_data = reralloc(c, c->uniform_data,
988 uint32_t,
989 c->uniform_array_size);
990 c->uniform_contents = reralloc(c, c->uniform_contents,
991 enum quniform_contents,
992 c->uniform_array_size);
993 }
994
995 c->uniform_contents[uniform] = contents;
996 c->uniform_data[uniform] = data;
997
998 return vir_reg(QFILE_UNIF, uniform);
999 }
1000
1001 static bool
1002 vir_can_set_flags(struct v3d_compile *c, struct qinst *inst)
1003 {
1004 if (c->devinfo->ver >= 40 && (v3d_qpu_reads_vpm(&inst->qpu) ||
1005 v3d_qpu_uses_sfu(&inst->qpu))) {
1006 return false;
1007 }
1008
1009 return true;
1010 }
1011
1012 void
1013 vir_PF(struct v3d_compile *c, struct qreg src, enum v3d_qpu_pf pf)
1014 {
1015 struct qinst *last_inst = NULL;
1016
1017 if (!list_empty(&c->cur_block->instructions)) {
1018 last_inst = (struct qinst *)c->cur_block->instructions.prev;
1019
1020 /* Can't stuff the PF into the last last inst if our cursor
1021 * isn't pointing after it.
1022 */
1023 struct vir_cursor after_inst = vir_after_inst(last_inst);
1024 if (c->cursor.mode != after_inst.mode ||
1025 c->cursor.link != after_inst.link)
1026 last_inst = NULL;
1027 }
1028
1029 if (src.file != QFILE_TEMP ||
1030 !c->defs[src.index] ||
1031 last_inst != c->defs[src.index] ||
1032 !vir_can_set_flags(c, last_inst)) {
1033 /* XXX: Make the MOV be the appropriate type */
1034 last_inst = vir_MOV_dest(c, vir_reg(QFILE_NULL, 0), src);
1035 }
1036
1037 vir_set_pf(last_inst, pf);
1038 }
1039
1040 #define OPTPASS(func) \
1041 do { \
1042 bool stage_progress = func(c); \
1043 if (stage_progress) { \
1044 progress = true; \
1045 if (print_opt_debug) { \
1046 fprintf(stderr, \
1047 "VIR opt pass %2d: %s progress\n", \
1048 pass, #func); \
1049 } \
1050 /*XXX vir_validate(c);*/ \
1051 } \
1052 } while (0)
1053
1054 void
1055 vir_optimize(struct v3d_compile *c)
1056 {
1057 bool print_opt_debug = false;
1058 int pass = 1;
1059
1060 while (true) {
1061 bool progress = false;
1062
1063 OPTPASS(vir_opt_copy_propagate);
1064 OPTPASS(vir_opt_dead_code);
1065 OPTPASS(vir_opt_small_immediates);
1066
1067 if (!progress)
1068 break;
1069
1070 pass++;
1071 }
1072 }
1073
1074 const char *
1075 vir_get_stage_name(struct v3d_compile *c)
1076 {
1077 if (c->vs_key && c->vs_key->is_coord)
1078 return "MESA_SHADER_COORD";
1079 else
1080 return gl_shader_stage_name(c->s->info.stage);
1081 }