projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
v3d: Implement ALPHA_TO_COVERAGE.
[mesa.git] / src / broadcom / compiler / vir.c
1 /*
2 * Copyright © 2016-2017 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "broadcom/common/v3d_device_info.h"
25 #include "v3d_compiler.h"
26
27 int
28 vir_get_non_sideband_nsrc(struct qinst *inst)
29 {
30 switch (inst->qpu.type) {
31 case V3D_QPU_INSTR_TYPE_BRANCH:
32 return 0;
33 case V3D_QPU_INSTR_TYPE_ALU:
34 if (inst->qpu.alu.add.op != V3D_QPU_A_NOP)
35 return v3d_qpu_add_op_num_src(inst->qpu.alu.add.op);
36 else
37 return v3d_qpu_mul_op_num_src(inst->qpu.alu.mul.op);
38 }
39
40 return 0;
41 }
42
43 int
44 vir_get_nsrc(struct qinst *inst)
45 {
46 int nsrc = vir_get_non_sideband_nsrc(inst);
47
48 if (vir_has_implicit_uniform(inst))
49 nsrc++;
50
51 return nsrc;
52 }
53
54 bool
55 vir_has_implicit_uniform(struct qinst *inst)
56 {
57 switch (inst->qpu.type) {
58 case V3D_QPU_INSTR_TYPE_BRANCH:
59 return true;
60 case V3D_QPU_INSTR_TYPE_ALU:
61 switch (inst->dst.file) {
62 case QFILE_TLBU:
63 return true;
64 default:
65 return inst->has_implicit_uniform;
66 }
67 }
68 return false;
69 }
70
71 /* The sideband uniform for textures gets stored after the normal ALU
72 * arguments.
73 */
74 int
75 vir_get_implicit_uniform_src(struct qinst *inst)
76 {
77 return vir_get_nsrc(inst) - 1;
78 }
79
80 /**
81 * Returns whether the instruction has any side effects that must be
82 * preserved.
83 */
84 bool
85 vir_has_side_effects(struct v3d_compile *c, struct qinst *inst)
86 {
87 switch (inst->qpu.type) {
88 case V3D_QPU_INSTR_TYPE_BRANCH:
89 return true;
90 case V3D_QPU_INSTR_TYPE_ALU:
91 switch (inst->qpu.alu.add.op) {
92 case V3D_QPU_A_SETREVF:
93 case V3D_QPU_A_SETMSF:
94 case V3D_QPU_A_VPMSETUP:
95 case V3D_QPU_A_STVPMV:
96 case V3D_QPU_A_STVPMD:
97 case V3D_QPU_A_STVPMP:
98 case V3D_QPU_A_VPMWT:
99 return true;
100 default:
101 break;
102 }
103
104 switch (inst->qpu.alu.mul.op) {
105 case V3D_QPU_M_MULTOP:
106 return true;
107 default:
108 break;
109 }
110 }
111
112 if (inst->qpu.sig.ldtmu ||
113 inst->qpu.sig.ldvary ||
114 inst->qpu.sig.wrtmuc ||
115 inst->qpu.sig.thrsw) {
116 return true;
117 }
118
119 return false;
120 }
121
122 bool
123 vir_is_float_input(struct qinst *inst)
124 {
125 /* XXX: More instrs */
126 switch (inst->qpu.type) {
127 case V3D_QPU_INSTR_TYPE_BRANCH:
128 return false;
129 case V3D_QPU_INSTR_TYPE_ALU:
130 switch (inst->qpu.alu.add.op) {
131 case V3D_QPU_A_FADD:
132 case V3D_QPU_A_FSUB:
133 case V3D_QPU_A_FMIN:
134 case V3D_QPU_A_FMAX:
135 case V3D_QPU_A_FTOIN:
136 return true;
137 default:
138 break;
139 }
140
141 switch (inst->qpu.alu.mul.op) {
142 case V3D_QPU_M_FMOV:
143 case V3D_QPU_M_VFMUL:
144 case V3D_QPU_M_FMUL:
145 return true;
146 default:
147 break;
148 }
149 }
150
151 return false;
152 }
153
154 bool
155 vir_is_raw_mov(struct qinst *inst)
156 {
157 if (inst->qpu.type != V3D_QPU_INSTR_TYPE_ALU ||
158 (inst->qpu.alu.mul.op != V3D_QPU_M_FMOV &&
159 inst->qpu.alu.mul.op != V3D_QPU_M_MOV)) {
160 return false;
161 }
162
163 if (inst->qpu.alu.add.output_pack != V3D_QPU_PACK_NONE ||
164 inst->qpu.alu.mul.output_pack != V3D_QPU_PACK_NONE) {
165 return false;
166 }
167
168 if (inst->qpu.flags.ac != V3D_QPU_COND_NONE ||
169 inst->qpu.flags.mc != V3D_QPU_COND_NONE)
170 return false;
171
172 return true;
173 }
174
175 bool
176 vir_is_add(struct qinst *inst)
177 {
178 return (inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU &&
179 inst->qpu.alu.add.op != V3D_QPU_A_NOP);
180 }
181
182 bool
183 vir_is_mul(struct qinst *inst)
184 {
185 return (inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU &&
186 inst->qpu.alu.mul.op != V3D_QPU_M_NOP);
187 }
188
189 bool
190 vir_is_tex(struct qinst *inst)
191 {
192 if (inst->dst.file == QFILE_MAGIC)
193 return v3d_qpu_magic_waddr_is_tmu(inst->dst.index);
194
195 return false;
196 }
197
198 bool
199 vir_depends_on_flags(struct qinst *inst)
200 {
201 if (inst->qpu.type == V3D_QPU_INSTR_TYPE_BRANCH) {
202 return (inst->qpu.branch.cond != V3D_QPU_BRANCH_COND_ALWAYS);
203 } else {
204 return (inst->qpu.flags.ac != V3D_QPU_COND_NONE &&
205 inst->qpu.flags.mc != V3D_QPU_COND_NONE);
206 }
207 }
208
209 bool
210 vir_writes_r3(const struct v3d_device_info *devinfo, struct qinst *inst)
211 {
212 for (int i = 0; i < vir_get_nsrc(inst); i++) {
213 switch (inst->src[i].file) {
214 case QFILE_VPM:
215 return true;
216 default:
217 break;
218 }
219 }
220
221 if (devinfo->ver < 41 && (inst->qpu.sig.ldvary ||
222 inst->qpu.sig.ldtlb ||
223 inst->qpu.sig.ldtlbu ||
224 inst->qpu.sig.ldvpm)) {
225 return true;
226 }
227
228 return false;
229 }
230
231 bool
232 vir_writes_r4(const struct v3d_device_info *devinfo, struct qinst *inst)
233 {
234 switch (inst->dst.file) {
235 case QFILE_MAGIC:
236 switch (inst->dst.index) {
237 case V3D_QPU_WADDR_RECIP:
238 case V3D_QPU_WADDR_RSQRT:
239 case V3D_QPU_WADDR_EXP:
240 case V3D_QPU_WADDR_LOG:
241 case V3D_QPU_WADDR_SIN:
242 return true;
243 }
244 break;
245 default:
246 break;
247 }
248
249 if (devinfo->ver < 41 && inst->qpu.sig.ldtmu)
250 return true;
251
252 return false;
253 }
254
255 void
256 vir_set_unpack(struct qinst *inst, int src,
257 enum v3d_qpu_input_unpack unpack)
258 {
259 assert(src == 0 || src == 1);
260
261 if (vir_is_add(inst)) {
262 if (src == 0)
263 inst->qpu.alu.add.a_unpack = unpack;
264 else
265 inst->qpu.alu.add.b_unpack = unpack;
266 } else {
267 assert(vir_is_mul(inst));
268 if (src == 0)
269 inst->qpu.alu.mul.a_unpack = unpack;
270 else
271 inst->qpu.alu.mul.b_unpack = unpack;
272 }
273 }
274
275 void
276 vir_set_cond(struct qinst *inst, enum v3d_qpu_cond cond)
277 {
278 if (vir_is_add(inst)) {
279 inst->qpu.flags.ac = cond;
280 } else {
281 assert(vir_is_mul(inst));
282 inst->qpu.flags.mc = cond;
283 }
284 }
285
286 void
287 vir_set_pf(struct qinst *inst, enum v3d_qpu_pf pf)
288 {
289 if (vir_is_add(inst)) {
290 inst->qpu.flags.apf = pf;
291 } else {
292 assert(vir_is_mul(inst));
293 inst->qpu.flags.mpf = pf;
294 }
295 }
296
297 #if 0
298 uint8_t
299 vir_channels_written(struct qinst *inst)
300 {
301 if (vir_is_mul(inst)) {
302 switch (inst->dst.pack) {
303 case QPU_PACK_MUL_NOP:
304 case QPU_PACK_MUL_8888:
305 return 0xf;
306 case QPU_PACK_MUL_8A:
307 return 0x1;
308 case QPU_PACK_MUL_8B:
309 return 0x2;
310 case QPU_PACK_MUL_8C:
311 return 0x4;
312 case QPU_PACK_MUL_8D:
313 return 0x8;
314 }
315 } else {
316 switch (inst->dst.pack) {
317 case QPU_PACK_A_NOP:
318 case QPU_PACK_A_8888:
319 case QPU_PACK_A_8888_SAT:
320 case QPU_PACK_A_32_SAT:
321 return 0xf;
322 case QPU_PACK_A_8A:
323 case QPU_PACK_A_8A_SAT:
324 return 0x1;
325 case QPU_PACK_A_8B:
326 case QPU_PACK_A_8B_SAT:
327 return 0x2;
328 case QPU_PACK_A_8C:
329 case QPU_PACK_A_8C_SAT:
330 return 0x4;
331 case QPU_PACK_A_8D:
332 case QPU_PACK_A_8D_SAT:
333 return 0x8;
334 case QPU_PACK_A_16A:
335 case QPU_PACK_A_16A_SAT:
336 return 0x3;
337 case QPU_PACK_A_16B:
338 case QPU_PACK_A_16B_SAT:
339 return 0xc;
340 }
341 }
342 unreachable("Bad pack field");
343 }
344 #endif
345
346 struct qreg
347 vir_get_temp(struct v3d_compile *c)
348 {
349 struct qreg reg;
350
351 reg.file = QFILE_TEMP;
352 reg.index = c->num_temps++;
353
354 if (c->num_temps > c->defs_array_size) {
355 uint32_t old_size = c->defs_array_size;
356 c->defs_array_size = MAX2(old_size * 2, 16);
357
358 c->defs = reralloc(c, c->defs, struct qinst *,
359 c->defs_array_size);
360 memset(&c->defs[old_size], 0,
361 sizeof(c->defs[0]) * (c->defs_array_size - old_size));
362
363 c->spillable = reralloc(c, c->spillable,
364 BITSET_WORD,
365 BITSET_WORDS(c->defs_array_size));
366 for (int i = old_size; i < c->defs_array_size; i++)
367 BITSET_SET(c->spillable, i);
368 }
369
370 return reg;
371 }
372
373 struct qinst *
374 vir_add_inst(enum v3d_qpu_add_op op, struct qreg dst, struct qreg src0, struct qreg src1)
375 {
376 struct qinst *inst = calloc(1, sizeof(*inst));
377
378 inst->qpu = v3d_qpu_nop();
379 inst->qpu.alu.add.op = op;
380
381 inst->dst = dst;
382 inst->src[0] = src0;
383 inst->src[1] = src1;
384 inst->uniform = ~0;
385
386 return inst;
387 }
388
389 struct qinst *
390 vir_mul_inst(enum v3d_qpu_mul_op op, struct qreg dst, struct qreg src0, struct qreg src1)
391 {
392 struct qinst *inst = calloc(1, sizeof(*inst));
393
394 inst->qpu = v3d_qpu_nop();
395 inst->qpu.alu.mul.op = op;
396
397 inst->dst = dst;
398 inst->src[0] = src0;
399 inst->src[1] = src1;
400 inst->uniform = ~0;
401
402 return inst;
403 }
404
405 struct qinst *
406 vir_branch_inst(enum v3d_qpu_branch_cond cond, struct qreg src)
407 {
408 struct qinst *inst = calloc(1, sizeof(*inst));
409
410 inst->qpu = v3d_qpu_nop();
411 inst->qpu.type = V3D_QPU_INSTR_TYPE_BRANCH;
412 inst->qpu.branch.cond = cond;
413 inst->qpu.branch.msfign = V3D_QPU_MSFIGN_NONE;
414 inst->qpu.branch.bdi = V3D_QPU_BRANCH_DEST_REL;
415 inst->qpu.branch.ub = true;
416 inst->qpu.branch.bdu = V3D_QPU_BRANCH_DEST_REL;
417
418 inst->dst = vir_reg(QFILE_NULL, 0);
419 inst->src[0] = src;
420 inst->uniform = ~0;
421
422 return inst;
423 }
424
425 static void
426 vir_emit(struct v3d_compile *c, struct qinst *inst)
427 {
428 switch (c->cursor.mode) {
429 case vir_cursor_add:
430 list_add(&inst->link, c->cursor.link);
431 break;
432 case vir_cursor_addtail:
433 list_addtail(&inst->link, c->cursor.link);
434 break;
435 }
436
437 c->cursor = vir_after_inst(inst);
438 c->live_intervals_valid = false;
439 }
440
441 /* Updates inst to write to a new temporary, emits it, and notes the def. */
442 struct qreg
443 vir_emit_def(struct v3d_compile *c, struct qinst *inst)
444 {
445 assert(inst->dst.file == QFILE_NULL);
446
447 inst->dst = vir_get_temp(c);
448
449 if (inst->dst.file == QFILE_TEMP)
450 c->defs[inst->dst.index] = inst;
451
452 vir_emit(c, inst);
453
454 return inst->dst;
455 }
456
457 struct qinst *
458 vir_emit_nondef(struct v3d_compile *c, struct qinst *inst)
459 {
460 if (inst->dst.file == QFILE_TEMP)
461 c->defs[inst->dst.index] = NULL;
462
463 vir_emit(c, inst);
464
465 return inst;
466 }
467
468 struct qblock *
469 vir_new_block(struct v3d_compile *c)
470 {
471 struct qblock *block = rzalloc(c, struct qblock);
472
473 list_inithead(&block->instructions);
474
475 block->predecessors = _mesa_set_create(block,
476 _mesa_hash_pointer,
477 _mesa_key_pointer_equal);
478
479 block->index = c->next_block_index++;
480
481 return block;
482 }
483
484 void
485 vir_set_emit_block(struct v3d_compile *c, struct qblock *block)
486 {
487 c->cur_block = block;
488 c->cursor = vir_after_block(block);
489 list_addtail(&block->link, &c->blocks);
490 }
491
492 struct qblock *
493 vir_entry_block(struct v3d_compile *c)
494 {
495 return list_first_entry(&c->blocks, struct qblock, link);
496 }
497
498 struct qblock *
499 vir_exit_block(struct v3d_compile *c)
500 {
501 return list_last_entry(&c->blocks, struct qblock, link);
502 }
503
504 void
505 vir_link_blocks(struct qblock *predecessor, struct qblock *successor)
506 {
507 _mesa_set_add(successor->predecessors, predecessor);
508 if (predecessor->successors[0]) {
509 assert(!predecessor->successors[1]);
510 predecessor->successors[1] = successor;
511 } else {
512 predecessor->successors[0] = successor;
513 }
514 }
515
516 const struct v3d_compiler *
517 v3d_compiler_init(const struct v3d_device_info *devinfo)
518 {
519 struct v3d_compiler *compiler = rzalloc(NULL, struct v3d_compiler);
520 if (!compiler)
521 return NULL;
522
523 compiler->devinfo = devinfo;
524
525 if (!vir_init_reg_sets(compiler)) {
526 ralloc_free(compiler);
527 return NULL;
528 }
529
530 return compiler;
531 }
532
533 void
534 v3d_compiler_free(const struct v3d_compiler *compiler)
535 {
536 ralloc_free((void *)compiler);
537 }
538
539 static struct v3d_compile *
540 vir_compile_init(const struct v3d_compiler *compiler,
541 struct v3d_key *key,
542 nir_shader *s,
543 int program_id, int variant_id)
544 {
545 struct v3d_compile *c = rzalloc(NULL, struct v3d_compile);
546
547 c->compiler = compiler;
548 c->devinfo = compiler->devinfo;
549 c->key = key;
550 c->program_id = program_id;
551 c->variant_id = variant_id;
552 c->threads = 4;
553
554 s = nir_shader_clone(c, s);
555 c->s = s;
556
557 list_inithead(&c->blocks);
558 vir_set_emit_block(c, vir_new_block(c));
559
560 c->output_position_index = -1;
561 c->output_point_size_index = -1;
562 c->output_sample_mask_index = -1;
563
564 c->def_ht = _mesa_hash_table_create(c, _mesa_hash_pointer,
565 _mesa_key_pointer_equal);
566
567 return c;
568 }
569
570 static void
571 v3d_lower_nir(struct v3d_compile *c)
572 {
573 struct nir_lower_tex_options tex_options = {
574 .lower_txd = true,
575 .lower_rect = false, /* XXX */
576 .lower_txp = ~0,
577 /* Apply swizzles to all samplers. */
578 .swizzle_result = ~0,
579 };
580
581 /* Lower the format swizzle and (for 32-bit returns)
582 * ARB_texture_swizzle-style swizzle.
583 */
584 for (int i = 0; i < ARRAY_SIZE(c->key->tex); i++) {
585 for (int j = 0; j < 4; j++)
586 tex_options.swizzles[i][j] = c->key->tex[i].swizzle[j];
587
588 if (c->key->tex[i].clamp_s)
589 tex_options.saturate_s |= 1 << i;
590 if (c->key->tex[i].clamp_t)
591 tex_options.saturate_t |= 1 << i;
592 if (c->key->tex[i].clamp_r)
593 tex_options.saturate_r |= 1 << i;
594 }
595
596 NIR_PASS_V(c->s, nir_lower_tex, &tex_options);
597 }
598
599 static void
600 v3d_lower_nir_late(struct v3d_compile *c)
601 {
602 NIR_PASS_V(c->s, v3d_nir_lower_io, c);
603 NIR_PASS_V(c->s, v3d_nir_lower_txf_ms, c);
604 NIR_PASS_V(c->s, nir_lower_idiv);
605 }
606
607 static void
608 v3d_set_prog_data_uniforms(struct v3d_compile *c,
609 struct v3d_prog_data *prog_data)
610 {
611 int count = c->num_uniforms;
612 struct v3d_uniform_list *ulist = &prog_data->uniforms;
613
614 ulist->count = count;
615 ulist->data = ralloc_array(prog_data, uint32_t, count);
616 memcpy(ulist->data, c->uniform_data,
617 count * sizeof(*ulist->data));
618 ulist->contents = ralloc_array(prog_data, enum quniform_contents, count);
619 memcpy(ulist->contents, c->uniform_contents,
620 count * sizeof(*ulist->contents));
621 }
622
623 /* Copy the compiler UBO range state to the compiled shader, dropping out
624 * arrays that were never referenced by an indirect load.
625 *
626 * (Note that QIR dead code elimination of an array access still leaves that
627 * array alive, though)
628 */
629 static void
630 v3d_set_prog_data_ubo(struct v3d_compile *c,
631 struct v3d_prog_data *prog_data)
632 {
633 if (!c->num_ubo_ranges)
634 return;
635
636 prog_data->num_ubo_ranges = 0;
637 prog_data->ubo_ranges = ralloc_array(prog_data, struct v3d_ubo_range,
638 c->num_ubo_ranges);
639 for (int i = 0; i < c->num_ubo_ranges; i++) {
640 if (!c->ubo_range_used[i])
641 continue;
642
643 struct v3d_ubo_range *range = &c->ubo_ranges[i];
644 prog_data->ubo_ranges[prog_data->num_ubo_ranges++] = *range;
645 prog_data->ubo_size += range->size;
646 }
647
648 if (prog_data->ubo_size) {
649 if (V3D_DEBUG & V3D_DEBUG_SHADERDB) {
650 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d UBO uniforms\n",
651 vir_get_stage_name(c),
652 c->program_id, c->variant_id,
653 prog_data->ubo_size / 4);
654 }
655 }
656 }
657
658 static void
659 v3d_set_prog_data(struct v3d_compile *c,
660 struct v3d_prog_data *prog_data)
661 {
662 prog_data->threads = c->threads;
663 prog_data->single_seg = !c->last_thrsw;
664 prog_data->spill_size = c->spill_size;
665
666 v3d_set_prog_data_uniforms(c, prog_data);
667 v3d_set_prog_data_ubo(c, prog_data);
668 }
669
670 static uint64_t *
671 v3d_return_qpu_insts(struct v3d_compile *c, uint32_t *final_assembly_size)
672 {
673 *final_assembly_size = c->qpu_inst_count * sizeof(uint64_t);
674
675 uint64_t *qpu_insts = malloc(*final_assembly_size);
676 if (!qpu_insts)
677 return NULL;
678
679 memcpy(qpu_insts, c->qpu_insts, *final_assembly_size);
680
681 vir_compile_destroy(c);
682
683 return qpu_insts;
684 }
685
686 uint64_t *v3d_compile_vs(const struct v3d_compiler *compiler,
687 struct v3d_vs_key *key,
688 struct v3d_vs_prog_data *prog_data,
689 nir_shader *s,
690 int program_id, int variant_id,
691 uint32_t *final_assembly_size)
692 {
693 struct v3d_compile *c = vir_compile_init(compiler, &key->base, s,
694 program_id, variant_id);
695
696 c->vs_key = key;
697
698 v3d_lower_nir(c);
699
700 if (key->clamp_color)
701 NIR_PASS_V(c->s, nir_lower_clamp_color_outputs);
702
703 if (key->base.ucp_enables) {
704 NIR_PASS_V(c->s, nir_lower_clip_vs, key->base.ucp_enables);
705 NIR_PASS_V(c->s, nir_lower_io_to_scalar,
706 nir_var_shader_out);
707 }
708
709 /* Note: VS output scalarizing must happen after nir_lower_clip_vs. */
710 NIR_PASS_V(c->s, nir_lower_io_to_scalar, nir_var_shader_out);
711
712 v3d_lower_nir_late(c);
713 v3d_optimize_nir(c->s);
714 NIR_PASS_V(c->s, nir_convert_from_ssa, true);
715
716 v3d_nir_to_vir(c);
717
718 v3d_set_prog_data(c, &prog_data->base);
719
720 prog_data->base.num_inputs = c->num_inputs;
721
722 /* The vertex data gets format converted by the VPM so that
723 * each attribute channel takes up a VPM column. Precompute
724 * the sizes for the shader record.
725 */
726 for (int i = 0; i < ARRAY_SIZE(prog_data->vattr_sizes); i++) {
727 prog_data->vattr_sizes[i] = c->vattr_sizes[i];
728 prog_data->vpm_input_size += c->vattr_sizes[i];
729 }
730
731 prog_data->uses_vid = (s->info.system_values_read &
732 (1ull << SYSTEM_VALUE_VERTEX_ID));
733 prog_data->uses_iid = (s->info.system_values_read &
734 (1ull << SYSTEM_VALUE_INSTANCE_ID));
735
736 if (prog_data->uses_vid)
737 prog_data->vpm_input_size++;
738 if (prog_data->uses_iid)
739 prog_data->vpm_input_size++;
740
741 /* Input/output segment size are in 8x32-bit multiples. */
742 prog_data->vpm_input_size = align(prog_data->vpm_input_size, 8) / 8;
743 prog_data->vpm_output_size = align(c->num_vpm_writes, 8) / 8;
744
745 return v3d_return_qpu_insts(c, final_assembly_size);
746 }
747
748 static void
749 v3d_set_fs_prog_data_inputs(struct v3d_compile *c,
750 struct v3d_fs_prog_data *prog_data)
751 {
752 prog_data->base.num_inputs = c->num_inputs;
753 memcpy(prog_data->input_slots, c->input_slots,
754 c->num_inputs * sizeof(*c->input_slots));
755
756 STATIC_ASSERT(ARRAY_SIZE(prog_data->flat_shade_flags) >
757 (V3D_MAX_FS_INPUTS - 1) / 24);
758 for (int i = 0; i < V3D_MAX_FS_INPUTS; i++) {
759 if (BITSET_TEST(c->flat_shade_flags, i))
760 prog_data->flat_shade_flags[i / 24] |= 1 << (i % 24);
761
762 if (BITSET_TEST(c->centroid_flags, i))
763 prog_data->centroid_flags[i / 24] |= 1 << (i % 24);
764 }
765 }
766
767 static void
768 v3d_fixup_fs_output_types(struct v3d_compile *c)
769 {
770 nir_foreach_variable(var, &c->s->outputs) {
771 uint32_t mask = 0;
772
773 switch (var->data.location) {
774 case FRAG_RESULT_COLOR:
775 mask = ~0;
776 break;
777 case FRAG_RESULT_DATA0:
778 case FRAG_RESULT_DATA1:
779 case FRAG_RESULT_DATA2:
780 case FRAG_RESULT_DATA3:
781 mask = 1 << (var->data.location - FRAG_RESULT_DATA0);
782 break;
783 }
784
785 if (c->fs_key->int_color_rb & mask) {
786 var->type =
787 glsl_vector_type(GLSL_TYPE_INT,
788 glsl_get_components(var->type));
789 } else if (c->fs_key->uint_color_rb & mask) {
790 var->type =
791 glsl_vector_type(GLSL_TYPE_UINT,
792 glsl_get_components(var->type));
793 }
794 }
795 }
796
797 uint64_t *v3d_compile_fs(const struct v3d_compiler *compiler,
798 struct v3d_fs_key *key,
799 struct v3d_fs_prog_data *prog_data,
800 nir_shader *s,
801 int program_id, int variant_id,
802 uint32_t *final_assembly_size)
803 {
804 struct v3d_compile *c = vir_compile_init(compiler, &key->base, s,
805 program_id, variant_id);
806
807 c->fs_key = key;
808
809 if (key->int_color_rb || key->uint_color_rb)
810 v3d_fixup_fs_output_types(c);
811
812 v3d_lower_nir(c);
813
814 if (key->light_twoside)
815 NIR_PASS_V(c->s, nir_lower_two_sided_color);
816
817 if (key->clamp_color)
818 NIR_PASS_V(c->s, nir_lower_clamp_color_outputs);
819
820 if (key->alpha_test) {
821 NIR_PASS_V(c->s, nir_lower_alpha_test, key->alpha_test_func,
822 false);
823 }
824
825 if (key->base.ucp_enables)
826 NIR_PASS_V(c->s, nir_lower_clip_fs, key->base.ucp_enables);
827
828 /* Note: FS input scalarizing must happen after
829 * nir_lower_two_sided_color, which only handles a vec4 at a time.
830 */
831 NIR_PASS_V(c->s, nir_lower_io_to_scalar, nir_var_shader_in);
832
833 v3d_lower_nir_late(c);
834 v3d_optimize_nir(c->s);
835 NIR_PASS_V(c->s, nir_convert_from_ssa, true);
836
837 v3d_nir_to_vir(c);
838
839 v3d_set_prog_data(c, &prog_data->base);
840 v3d_set_fs_prog_data_inputs(c, prog_data);
841 prog_data->writes_z = (c->s->info.outputs_written &
842 (1 << FRAG_RESULT_DEPTH));
843 prog_data->discard = (c->s->info.fs.uses_discard ||
844 c->fs_key->sample_alpha_to_coverage);
845 prog_data->uses_center_w = c->uses_center_w;
846
847 return v3d_return_qpu_insts(c, final_assembly_size);
848 }
849
850 void
851 vir_remove_instruction(struct v3d_compile *c, struct qinst *qinst)
852 {
853 if (qinst->dst.file == QFILE_TEMP)
854 c->defs[qinst->dst.index] = NULL;
855
856 assert(&qinst->link != c->cursor.link);
857
858 list_del(&qinst->link);
859 free(qinst);
860
861 c->live_intervals_valid = false;
862 }
863
864 struct qreg
865 vir_follow_movs(struct v3d_compile *c, struct qreg reg)
866 {
867 /* XXX
868 int pack = reg.pack;
869
870 while (reg.file == QFILE_TEMP &&
871 c->defs[reg.index] &&
872 (c->defs[reg.index]->op == QOP_MOV ||
873 c->defs[reg.index]->op == QOP_FMOV) &&
874 !c->defs[reg.index]->dst.pack &&
875 !c->defs[reg.index]->src[0].pack) {
876 reg = c->defs[reg.index]->src[0];
877 }
878
879 reg.pack = pack;
880 */
881 return reg;
882 }
883
884 void
885 vir_compile_destroy(struct v3d_compile *c)
886 {
887 /* Defuse the assert that we aren't removing the cursor's instruction.
888 */
889 c->cursor.link = NULL;
890
891 vir_for_each_block(block, c) {
892 while (!list_empty(&block->instructions)) {
893 struct qinst *qinst =
894 list_first_entry(&block->instructions,
895 struct qinst, link);
896 vir_remove_instruction(c, qinst);
897 }
898 }
899
900 ralloc_free(c);
901 }
902
903 struct qreg
904 vir_uniform(struct v3d_compile *c,
905 enum quniform_contents contents,
906 uint32_t data)
907 {
908 for (int i = 0; i < c->num_uniforms; i++) {
909 if (c->uniform_contents[i] == contents &&
910 c->uniform_data[i] == data) {
911 return vir_reg(QFILE_UNIF, i);
912 }
913 }
914
915 uint32_t uniform = c->num_uniforms++;
916
917 if (uniform >= c->uniform_array_size) {
918 c->uniform_array_size = MAX2(MAX2(16, uniform + 1),
919 c->uniform_array_size * 2);
920
921 c->uniform_data = reralloc(c, c->uniform_data,
922 uint32_t,
923 c->uniform_array_size);
924 c->uniform_contents = reralloc(c, c->uniform_contents,
925 enum quniform_contents,
926 c->uniform_array_size);
927 }
928
929 c->uniform_contents[uniform] = contents;
930 c->uniform_data[uniform] = data;
931
932 return vir_reg(QFILE_UNIF, uniform);
933 }
934
935 void
936 vir_PF(struct v3d_compile *c, struct qreg src, enum v3d_qpu_pf pf)
937 {
938 struct qinst *last_inst = NULL;
939
940 if (!list_empty(&c->cur_block->instructions)) {
941 last_inst = (struct qinst *)c->cur_block->instructions.prev;
942
943 /* Can't stuff the PF into the last last inst if our cursor
944 * isn't pointing after it.
945 */
946 struct vir_cursor after_inst = vir_after_inst(last_inst);
947 if (c->cursor.mode != after_inst.mode ||
948 c->cursor.link != after_inst.link)
949 last_inst = NULL;
950 }
951
952 if (src.file != QFILE_TEMP ||
953 !c->defs[src.index] ||
954 last_inst != c->defs[src.index]) {
955 /* XXX: Make the MOV be the appropriate type */
956 last_inst = vir_MOV_dest(c, vir_reg(QFILE_NULL, 0), src);
957 }
958
959 vir_set_pf(last_inst, pf);
960 }
961
962 #define OPTPASS(func) \
963 do { \
964 bool stage_progress = func(c); \
965 if (stage_progress) { \
966 progress = true; \
967 if (print_opt_debug) { \
968 fprintf(stderr, \
969 "VIR opt pass %2d: %s progress\n", \
970 pass, #func); \
971 } \
972 /*XXX vir_validate(c);*/ \
973 } \
974 } while (0)
975
976 void
977 vir_optimize(struct v3d_compile *c)
978 {
979 bool print_opt_debug = false;
980 int pass = 1;
981
982 while (true) {
983 bool progress = false;
984
985 OPTPASS(vir_opt_copy_propagate);
986 OPTPASS(vir_opt_dead_code);
987
988 if (!progress)
989 break;
990
991 pass++;
992 }
993 }
994
995 const char *
996 vir_get_stage_name(struct v3d_compile *c)
997 {
998 if (c->vs_key && c->vs_key->is_coord)
999 return "MESA_SHADER_COORD";
1000 else
1001 return gl_shader_stage_name(c->s->info.stage);
1002 }