broadcom/vc5: Add support for V3Dv4 signal bits.
[mesa.git] / src / broadcom / compiler / vir_dump.c
1 /*
2 * Copyright © 2016-2017 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "broadcom/common/v3d_device_info.h"
25 #include "v3d_compiler.h"
26
27 static void
28 vir_print_reg(struct v3d_compile *c, struct qreg reg)
29 {
30 static const char *files[] = {
31 [QFILE_TEMP] = "t",
32 [QFILE_VARY] = "v",
33 [QFILE_UNIF] = "u",
34 [QFILE_TLB] = "tlb",
35 [QFILE_TLBU] = "tlbu",
36 };
37 static const char *quniform_names[] = {
38 [QUNIFORM_VIEWPORT_X_SCALE] = "vp_x_scale",
39 [QUNIFORM_VIEWPORT_Y_SCALE] = "vp_y_scale",
40 [QUNIFORM_VIEWPORT_Z_OFFSET] = "vp_z_offset",
41 [QUNIFORM_VIEWPORT_Z_SCALE] = "vp_z_scale",
42 };
43
44 switch (reg.file) {
45
46 case QFILE_NULL:
47 fprintf(stderr, "null");
48 break;
49
50 case QFILE_LOAD_IMM:
51 fprintf(stderr, "0x%08x (%f)", reg.index, uif(reg.index));
52 break;
53
54 case QFILE_REG:
55 fprintf(stderr, "rf%d", reg.index);
56 break;
57
58 case QFILE_MAGIC:
59 fprintf(stderr, "%s", v3d_qpu_magic_waddr_name(reg.index));
60 break;
61
62 case QFILE_SMALL_IMM:
63 if ((int)reg.index >= -16 && (int)reg.index <= 15)
64 fprintf(stderr, "%d", reg.index);
65 else
66 fprintf(stderr, "%f", uif(reg.index));
67 break;
68
69 case QFILE_VPM:
70 fprintf(stderr, "vpm%d.%d",
71 reg.index / 4, reg.index % 4);
72 break;
73
74 case QFILE_TLB:
75 fprintf(stderr, "%s", files[reg.file]);
76 break;
77
78 case QFILE_UNIF: {
79 enum quniform_contents contents = c->uniform_contents[reg.index];
80
81 fprintf(stderr, "%s%d", files[reg.file], reg.index);
82
83 switch (contents) {
84 case QUNIFORM_CONSTANT:
85 fprintf(stderr, " (0x%08x / %f)",
86 c->uniform_data[reg.index],
87 uif(c->uniform_data[reg.index]));
88 break;
89
90 case QUNIFORM_UNIFORM:
91 fprintf(stderr, " (push[%d])",
92 c->uniform_data[reg.index]);
93 break;
94
95 case QUNIFORM_TEXTURE_CONFIG_P1:
96 fprintf(stderr, " (tex[%d].p1)",
97 c->uniform_data[reg.index]);
98 break;
99
100 case QUNIFORM_TEXTURE_WIDTH:
101 fprintf(stderr, " (tex[%d].width)",
102 c->uniform_data[reg.index]);
103 break;
104 case QUNIFORM_TEXTURE_HEIGHT:
105 fprintf(stderr, " (tex[%d].height)",
106 c->uniform_data[reg.index]);
107 break;
108 case QUNIFORM_TEXTURE_DEPTH:
109 fprintf(stderr, " (tex[%d].depth)",
110 c->uniform_data[reg.index]);
111 break;
112 case QUNIFORM_TEXTURE_ARRAY_SIZE:
113 fprintf(stderr, " (tex[%d].array_size)",
114 c->uniform_data[reg.index]);
115 break;
116 case QUNIFORM_TEXTURE_LEVELS:
117 fprintf(stderr, " (tex[%d].levels)",
118 c->uniform_data[reg.index]);
119 break;
120
121 case QUNIFORM_UBO_ADDR:
122 fprintf(stderr, " (ubo[%d])",
123 c->uniform_data[reg.index]);
124 break;
125
126 default:
127 if (quniform_contents_is_texture_p0(contents)) {
128 fprintf(stderr, " (tex[%d].p0: 0x%08x)",
129 contents - QUNIFORM_TEXTURE_CONFIG_P0_0,
130 c->uniform_data[reg.index]);
131 } else if (contents < ARRAY_SIZE(quniform_names)) {
132 fprintf(stderr, " (%s)",
133 quniform_names[contents]);
134 } else {
135 fprintf(stderr, " (%d / 0x%08x)", contents,
136 c->uniform_data[reg.index]);
137 }
138 }
139
140 break;
141 }
142
143 default:
144 fprintf(stderr, "%s%d", files[reg.file], reg.index);
145 break;
146 }
147 }
148
149 static void
150 vir_dump_sig_addr(const struct v3d_device_info *devinfo,
151 const struct v3d_qpu_instr *instr)
152 {
153 if (devinfo->ver < 41)
154 return;
155
156 if (!instr->sig_magic)
157 fprintf(stderr, ".rf%d", instr->sig_addr);
158 else {
159 const char *name = v3d_qpu_magic_waddr_name(instr->sig_addr);
160 if (name)
161 fprintf(stderr, ".%s", name);
162 else
163 fprintf(stderr, ".UNKNOWN%d", instr->sig_addr);
164 }
165 }
166
167 static void
168 vir_dump_sig(struct v3d_compile *c, struct qinst *inst)
169 {
170 struct v3d_qpu_sig *sig = &inst->qpu.sig;
171
172 if (sig->thrsw)
173 fprintf(stderr, "; thrsw");
174 if (sig->ldvary) {
175 fprintf(stderr, "; ldvary");
176 vir_dump_sig_addr(c->devinfo, &inst->qpu);
177 }
178 if (sig->ldvpm)
179 fprintf(stderr, "; ldvpm");
180 if (sig->ldtmu) {
181 fprintf(stderr, "; ldtmu");
182 vir_dump_sig_addr(c->devinfo, &inst->qpu);
183 }
184 if (sig->ldtlb) {
185 fprintf(stderr, "; ldtlb");
186 vir_dump_sig_addr(c->devinfo, &inst->qpu);
187 }
188 if (sig->ldtlbu) {
189 fprintf(stderr, "; ldtlbu");
190 vir_dump_sig_addr(c->devinfo, &inst->qpu);
191 }
192 if (sig->ldunif)
193 fprintf(stderr, "; ldunif");
194 if (sig->ldunifrf) {
195 fprintf(stderr, "; ldunifrf");
196 vir_dump_sig_addr(c->devinfo, &inst->qpu);
197 }
198 if (sig->ldunifa)
199 fprintf(stderr, "; ldunifa");
200 if (sig->ldunifarf) {
201 fprintf(stderr, "; ldunifarf");
202 vir_dump_sig_addr(c->devinfo, &inst->qpu);
203 }
204 if (sig->wrtmuc)
205 fprintf(stderr, "; wrtmuc");
206 }
207
208 static void
209 vir_dump_alu(struct v3d_compile *c, struct qinst *inst)
210 {
211 struct v3d_qpu_instr *instr = &inst->qpu;
212 int nsrc = vir_get_non_sideband_nsrc(inst);
213 int sideband_nsrc = vir_get_nsrc(inst);
214 enum v3d_qpu_input_unpack unpack[2];
215
216 if (inst->qpu.alu.add.op != V3D_QPU_A_NOP) {
217 fprintf(stderr, "%s", v3d_qpu_add_op_name(instr->alu.add.op));
218 fprintf(stderr, "%s", v3d_qpu_cond_name(instr->flags.ac));
219 fprintf(stderr, "%s", v3d_qpu_pf_name(instr->flags.apf));
220 fprintf(stderr, "%s", v3d_qpu_uf_name(instr->flags.auf));
221 fprintf(stderr, " ");
222
223 vir_print_reg(c, inst->dst);
224 fprintf(stderr, "%s", v3d_qpu_pack_name(instr->alu.add.output_pack));
225
226 unpack[0] = instr->alu.add.a_unpack;
227 unpack[1] = instr->alu.add.b_unpack;
228 } else {
229 fprintf(stderr, "%s", v3d_qpu_mul_op_name(instr->alu.mul.op));
230 fprintf(stderr, "%s", v3d_qpu_cond_name(instr->flags.mc));
231 fprintf(stderr, "%s", v3d_qpu_pf_name(instr->flags.mpf));
232 fprintf(stderr, "%s", v3d_qpu_uf_name(instr->flags.muf));
233 fprintf(stderr, " ");
234
235 vir_print_reg(c, inst->dst);
236 fprintf(stderr, "%s", v3d_qpu_pack_name(instr->alu.mul.output_pack));
237
238 unpack[0] = instr->alu.mul.a_unpack;
239 unpack[1] = instr->alu.mul.b_unpack;
240 }
241
242 for (int i = 0; i < sideband_nsrc; i++) {
243 fprintf(stderr, ", ");
244 vir_print_reg(c, inst->src[i]);
245 if (i < nsrc)
246 fprintf(stderr, "%s", v3d_qpu_unpack_name(unpack[i]));
247 }
248
249 vir_dump_sig(c, inst);
250 }
251
252 void
253 vir_dump_inst(struct v3d_compile *c, struct qinst *inst)
254 {
255 struct v3d_qpu_instr *instr = &inst->qpu;
256
257 switch (inst->qpu.type) {
258 case V3D_QPU_INSTR_TYPE_ALU:
259 vir_dump_alu(c, inst);
260 break;
261 case V3D_QPU_INSTR_TYPE_BRANCH:
262 fprintf(stderr, "b");
263 if (instr->branch.ub)
264 fprintf(stderr, "u");
265
266 fprintf(stderr, "%s",
267 v3d_qpu_branch_cond_name(instr->branch.cond));
268 fprintf(stderr, "%s", v3d_qpu_msfign_name(instr->branch.msfign));
269
270 switch (instr->branch.bdi) {
271 case V3D_QPU_BRANCH_DEST_ABS:
272 fprintf(stderr, " zero_addr+0x%08x", instr->branch.offset);
273 break;
274
275 case V3D_QPU_BRANCH_DEST_REL:
276 fprintf(stderr, " %d", instr->branch.offset);
277 break;
278
279 case V3D_QPU_BRANCH_DEST_LINK_REG:
280 fprintf(stderr, " lri");
281 break;
282
283 case V3D_QPU_BRANCH_DEST_REGFILE:
284 fprintf(stderr, " rf%d", instr->branch.raddr_a);
285 break;
286 }
287
288 if (instr->branch.ub) {
289 switch (instr->branch.bdu) {
290 case V3D_QPU_BRANCH_DEST_ABS:
291 fprintf(stderr, ", a:unif");
292 break;
293
294 case V3D_QPU_BRANCH_DEST_REL:
295 fprintf(stderr, ", r:unif");
296 break;
297
298 case V3D_QPU_BRANCH_DEST_LINK_REG:
299 fprintf(stderr, ", lri");
300 break;
301
302 case V3D_QPU_BRANCH_DEST_REGFILE:
303 fprintf(stderr, ", rf%d", instr->branch.raddr_a);
304 break;
305 }
306 }
307
308 if (vir_has_implicit_uniform(inst)) {
309 fprintf(stderr, " ");
310 vir_print_reg(c, inst->src[vir_get_implicit_uniform_src(inst)]);
311 }
312
313 break;
314 }
315 }
316
317 void
318 vir_dump(struct v3d_compile *c)
319 {
320 int ip = 0;
321
322 vir_for_each_block(block, c) {
323 fprintf(stderr, "BLOCK %d:\n", block->index);
324 vir_for_each_inst(inst, block) {
325 if (c->temp_start) {
326 bool first = true;
327
328 for (int i = 0; i < c->num_temps; i++) {
329 if (c->temp_start[i] != ip)
330 continue;
331
332 if (first) {
333 first = false;
334 } else {
335 fprintf(stderr, ", ");
336 }
337 fprintf(stderr, "S%4d", i);
338 }
339
340 if (first)
341 fprintf(stderr, " ");
342 else
343 fprintf(stderr, " ");
344 }
345
346 if (c->temp_end) {
347 bool first = true;
348
349 for (int i = 0; i < c->num_temps; i++) {
350 if (c->temp_end[i] != ip)
351 continue;
352
353 if (first) {
354 first = false;
355 } else {
356 fprintf(stderr, ", ");
357 }
358 fprintf(stderr, "E%4d", i);
359 }
360
361 if (first)
362 fprintf(stderr, " ");
363 else
364 fprintf(stderr, " ");
365 }
366
367 vir_dump_inst(c, inst);
368 fprintf(stderr, "\n");
369 ip++;
370 }
371 if (block->successors[1]) {
372 fprintf(stderr, "-> BLOCK %d, %d\n",
373 block->successors[0]->index,
374 block->successors[1]->index);
375 } else if (block->successors[0]) {
376 fprintf(stderr, "-> BLOCK %d\n",
377 block->successors[0]->index);
378 }
379 }
380 }