2 * Copyright © 2016-2017 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "broadcom/common/v3d_device_info.h"
25 #include "v3d_compiler.h"
27 /* Prints a human-readable description of the uniform reference. */
29 vir_dump_uniform(enum quniform_contents contents
,
32 static const char *quniform_names
[] = {
33 [QUNIFORM_ALPHA_REF
] = "alpha_ref",
34 [QUNIFORM_LINE_WIDTH
] = "line_width",
35 [QUNIFORM_AA_LINE_WIDTH
] = "aa_line_width",
36 [QUNIFORM_VIEWPORT_X_SCALE
] = "vp_x_scale",
37 [QUNIFORM_VIEWPORT_Y_SCALE
] = "vp_y_scale",
38 [QUNIFORM_VIEWPORT_Z_OFFSET
] = "vp_z_offset",
39 [QUNIFORM_VIEWPORT_Z_SCALE
] = "vp_z_scale",
40 [QUNIFORM_SHARED_OFFSET
] = "shared_offset",
44 case QUNIFORM_CONSTANT
:
45 fprintf(stderr
, "0x%08x / %f", data
, uif(data
));
48 case QUNIFORM_UNIFORM
:
49 fprintf(stderr
, "push[%d]", data
);
52 case QUNIFORM_TEXTURE_CONFIG_P1
:
53 fprintf(stderr
, "tex[%d].p1", data
);
56 case QUNIFORM_TMU_CONFIG_P0
:
57 fprintf(stderr
, "tex[%d].p0 | 0x%x",
58 v3d_unit_data_get_unit(data
),
59 v3d_unit_data_get_offset(data
));
62 case QUNIFORM_TMU_CONFIG_P1
:
63 fprintf(stderr
, "tex[%d].p1 | 0x%x",
64 v3d_unit_data_get_unit(data
),
65 v3d_unit_data_get_offset(data
));
68 case QUNIFORM_IMAGE_TMU_CONFIG_P0
:
69 fprintf(stderr
, "img[%d].p0 | 0x%x",
70 v3d_unit_data_get_unit(data
),
71 v3d_unit_data_get_offset(data
));
74 case QUNIFORM_TEXTURE_WIDTH
:
75 fprintf(stderr
, "tex[%d].width", data
);
77 case QUNIFORM_TEXTURE_HEIGHT
:
78 fprintf(stderr
, "tex[%d].height", data
);
80 case QUNIFORM_TEXTURE_DEPTH
:
81 fprintf(stderr
, "tex[%d].depth", data
);
83 case QUNIFORM_TEXTURE_ARRAY_SIZE
:
84 fprintf(stderr
, "tex[%d].array_size", data
);
86 case QUNIFORM_TEXTURE_LEVELS
:
87 fprintf(stderr
, "tex[%d].levels", data
);
90 case QUNIFORM_IMAGE_WIDTH
:
91 fprintf(stderr
, "img[%d].width", data
);
93 case QUNIFORM_IMAGE_HEIGHT
:
94 fprintf(stderr
, "img[%d].height", data
);
96 case QUNIFORM_IMAGE_DEPTH
:
97 fprintf(stderr
, "img[%d].depth", data
);
99 case QUNIFORM_IMAGE_ARRAY_SIZE
:
100 fprintf(stderr
, "img[%d].array_size", data
);
103 case QUNIFORM_SPILL_OFFSET
:
104 fprintf(stderr
, "spill_offset");
107 case QUNIFORM_SPILL_SIZE_PER_THREAD
:
108 fprintf(stderr
, "spill_size_per_thread");
111 case QUNIFORM_UBO_ADDR
:
112 fprintf(stderr
, "ubo[%d]+0x%x",
113 v3d_unit_data_get_unit(data
),
114 v3d_unit_data_get_offset(data
));
117 case QUNIFORM_SSBO_OFFSET
:
118 fprintf(stderr
, "ssbo[%d]", data
);
121 case QUNIFORM_GET_BUFFER_SIZE
:
122 fprintf(stderr
, "ssbo_size[%d]", data
);
125 case QUNIFORM_NUM_WORK_GROUPS
:
126 fprintf(stderr
, "num_wg.%c", data
< 3 ? "xyz"[data
] : '?');
130 if (quniform_contents_is_texture_p0(contents
)) {
131 fprintf(stderr
, "tex[%d].p0: 0x%08x",
132 contents
- QUNIFORM_TEXTURE_CONFIG_P0_0
,
134 } else if (contents
< ARRAY_SIZE(quniform_names
) &&
135 quniform_names
[contents
]) {
136 fprintf(stderr
, "%s",
137 quniform_names
[contents
]);
139 fprintf(stderr
, "%d / 0x%08x", contents
, data
);
145 vir_print_reg(struct v3d_compile
*c
, const struct qinst
*inst
,
151 fprintf(stderr
, "null");
155 fprintf(stderr
, "0x%08x (%f)", reg
.index
, uif(reg
.index
));
159 fprintf(stderr
, "rf%d", reg
.index
);
163 fprintf(stderr
, "%s", v3d_qpu_magic_waddr_name(reg
.index
));
166 case QFILE_SMALL_IMM
: {
168 bool ok
= v3d_qpu_small_imm_unpack(c
->devinfo
,
171 assert(ok
); (void) ok
;
173 if ((int)inst
->qpu
.raddr_b
>= -16 &&
174 (int)inst
->qpu
.raddr_b
<= 15)
175 fprintf(stderr
, "%d", unpacked
);
177 fprintf(stderr
, "%f", uif(unpacked
));
182 fprintf(stderr
, "vpm%d.%d",
183 reg
.index
/ 4, reg
.index
% 4);
187 fprintf(stderr
, "t%d", reg
.index
);
193 vir_dump_sig_addr(const struct v3d_device_info
*devinfo
,
194 const struct v3d_qpu_instr
*instr
)
196 if (devinfo
->ver
< 41)
199 if (!instr
->sig_magic
)
200 fprintf(stderr
, ".rf%d", instr
->sig_addr
);
202 const char *name
= v3d_qpu_magic_waddr_name(instr
->sig_addr
);
204 fprintf(stderr
, ".%s", name
);
206 fprintf(stderr
, ".UNKNOWN%d", instr
->sig_addr
);
211 vir_dump_sig(struct v3d_compile
*c
, struct qinst
*inst
)
213 struct v3d_qpu_sig
*sig
= &inst
->qpu
.sig
;
216 fprintf(stderr
, "; thrsw");
218 fprintf(stderr
, "; ldvary");
219 vir_dump_sig_addr(c
->devinfo
, &inst
->qpu
);
222 fprintf(stderr
, "; ldvpm");
224 fprintf(stderr
, "; ldtmu");
225 vir_dump_sig_addr(c
->devinfo
, &inst
->qpu
);
228 fprintf(stderr
, "; ldtlb");
229 vir_dump_sig_addr(c
->devinfo
, &inst
->qpu
);
232 fprintf(stderr
, "; ldtlbu");
233 vir_dump_sig_addr(c
->devinfo
, &inst
->qpu
);
236 fprintf(stderr
, "; ldunif");
238 fprintf(stderr
, "; ldunifrf");
239 vir_dump_sig_addr(c
->devinfo
, &inst
->qpu
);
242 fprintf(stderr
, "; ldunifa");
243 if (sig
->ldunifarf
) {
244 fprintf(stderr
, "; ldunifarf");
245 vir_dump_sig_addr(c
->devinfo
, &inst
->qpu
);
248 fprintf(stderr
, "; wrtmuc");
252 vir_dump_alu(struct v3d_compile
*c
, struct qinst
*inst
)
254 struct v3d_qpu_instr
*instr
= &inst
->qpu
;
255 int nsrc
= vir_get_nsrc(inst
);
256 enum v3d_qpu_input_unpack unpack
[2];
258 if (inst
->qpu
.alu
.add
.op
!= V3D_QPU_A_NOP
) {
259 fprintf(stderr
, "%s", v3d_qpu_add_op_name(instr
->alu
.add
.op
));
260 fprintf(stderr
, "%s", v3d_qpu_cond_name(instr
->flags
.ac
));
261 fprintf(stderr
, "%s", v3d_qpu_pf_name(instr
->flags
.apf
));
262 fprintf(stderr
, "%s", v3d_qpu_uf_name(instr
->flags
.auf
));
263 fprintf(stderr
, " ");
265 vir_print_reg(c
, inst
, inst
->dst
);
266 fprintf(stderr
, "%s", v3d_qpu_pack_name(instr
->alu
.add
.output_pack
));
268 unpack
[0] = instr
->alu
.add
.a_unpack
;
269 unpack
[1] = instr
->alu
.add
.b_unpack
;
271 fprintf(stderr
, "%s", v3d_qpu_mul_op_name(instr
->alu
.mul
.op
));
272 fprintf(stderr
, "%s", v3d_qpu_cond_name(instr
->flags
.mc
));
273 fprintf(stderr
, "%s", v3d_qpu_pf_name(instr
->flags
.mpf
));
274 fprintf(stderr
, "%s", v3d_qpu_uf_name(instr
->flags
.muf
));
275 fprintf(stderr
, " ");
277 vir_print_reg(c
, inst
, inst
->dst
);
278 fprintf(stderr
, "%s", v3d_qpu_pack_name(instr
->alu
.mul
.output_pack
));
280 unpack
[0] = instr
->alu
.mul
.a_unpack
;
281 unpack
[1] = instr
->alu
.mul
.b_unpack
;
284 for (int i
= 0; i
< nsrc
; i
++) {
285 fprintf(stderr
, ", ");
286 vir_print_reg(c
, inst
, inst
->src
[i
]);
287 fprintf(stderr
, "%s", v3d_qpu_unpack_name(unpack
[i
]));
290 vir_dump_sig(c
, inst
);
294 vir_dump_inst(struct v3d_compile
*c
, struct qinst
*inst
)
296 struct v3d_qpu_instr
*instr
= &inst
->qpu
;
298 switch (inst
->qpu
.type
) {
299 case V3D_QPU_INSTR_TYPE_ALU
:
300 vir_dump_alu(c
, inst
);
302 case V3D_QPU_INSTR_TYPE_BRANCH
:
303 fprintf(stderr
, "b");
304 if (instr
->branch
.ub
)
305 fprintf(stderr
, "u");
307 fprintf(stderr
, "%s",
308 v3d_qpu_branch_cond_name(instr
->branch
.cond
));
309 fprintf(stderr
, "%s", v3d_qpu_msfign_name(instr
->branch
.msfign
));
311 switch (instr
->branch
.bdi
) {
312 case V3D_QPU_BRANCH_DEST_ABS
:
313 fprintf(stderr
, " zero_addr+0x%08x", instr
->branch
.offset
);
316 case V3D_QPU_BRANCH_DEST_REL
:
317 fprintf(stderr
, " %d", instr
->branch
.offset
);
320 case V3D_QPU_BRANCH_DEST_LINK_REG
:
321 fprintf(stderr
, " lri");
324 case V3D_QPU_BRANCH_DEST_REGFILE
:
325 fprintf(stderr
, " rf%d", instr
->branch
.raddr_a
);
329 if (instr
->branch
.ub
) {
330 switch (instr
->branch
.bdu
) {
331 case V3D_QPU_BRANCH_DEST_ABS
:
332 fprintf(stderr
, ", a:unif");
335 case V3D_QPU_BRANCH_DEST_REL
:
336 fprintf(stderr
, ", r:unif");
339 case V3D_QPU_BRANCH_DEST_LINK_REG
:
340 fprintf(stderr
, ", lri");
343 case V3D_QPU_BRANCH_DEST_REGFILE
:
344 fprintf(stderr
, ", rf%d", instr
->branch
.raddr_a
);
351 if (vir_has_uniform(inst
)) {
352 fprintf(stderr
, " (");
353 vir_dump_uniform(c
->uniform_contents
[inst
->uniform
],
354 c
->uniform_data
[inst
->uniform
]);
355 fprintf(stderr
, ")");
360 vir_dump(struct v3d_compile
*c
)
365 vir_for_each_block(block
, c
) {
366 fprintf(stderr
, "BLOCK %d:\n", block
->index
);
367 vir_for_each_inst(inst
, block
) {
368 if (c
->live_intervals_valid
) {
369 for (int i
= 0; i
< c
->num_temps
; i
++) {
370 if (c
->temp_start
[i
] == ip
)
374 fprintf(stderr
, "P%4d ", pressure
);
378 for (int i
= 0; i
< c
->num_temps
; i
++) {
379 if (c
->temp_start
[i
] != ip
)
385 fprintf(stderr
, ", ");
387 if (BITSET_TEST(c
->spillable
, i
))
388 fprintf(stderr
, "S%4d", i
);
390 fprintf(stderr
, "U%4d", i
);
394 fprintf(stderr
, " ");
396 fprintf(stderr
, " ");
399 if (c
->live_intervals_valid
) {
402 for (int i
= 0; i
< c
->num_temps
; i
++) {
403 if (c
->temp_end
[i
] != ip
)
409 fprintf(stderr
, ", ");
411 fprintf(stderr
, "E%4d", i
);
416 fprintf(stderr
, " ");
418 fprintf(stderr
, " ");
421 vir_dump_inst(c
, inst
);
422 fprintf(stderr
, "\n");
425 if (block
->successors
[1]) {
426 fprintf(stderr
, "-> BLOCK %d, %d\n",
427 block
->successors
[0]->index
,
428 block
->successors
[1]->index
);
429 } else if (block
->successors
[0]) {
430 fprintf(stderr
, "-> BLOCK %d\n",
431 block
->successors
[0]->index
);