2 * Copyright © 2014 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "util/ralloc.h"
25 #include "util/register_allocate.h"
26 #include "common/v3d_device_info.h"
27 #include "v3d_compiler.h"
29 #define QPU_R(i) { .magic = false, .index = i }
33 #define PHYS_INDEX (ACC_INDEX + ACC_COUNT)
37 is_last_ldtmu(struct qinst
*inst
, struct qblock
*block
)
39 list_for_each_entry_from(struct qinst
, scan_inst
, inst
,
40 &block
->instructions
, link
) {
41 if (inst
->qpu
.sig
.ldtmu
)
43 if (v3d_qpu_writes_tmu(&inst
->qpu
))
51 v3d_choose_spill_node(struct v3d_compile
*c
, struct ra_graph
*g
,
52 uint32_t *temp_to_node
)
54 float block_scale
= 1.0;
55 float spill_costs
[c
->num_temps
];
56 bool in_tmu_operation
= false;
57 bool started_last_seg
= false;
59 for (unsigned i
= 0; i
< c
->num_temps
; i
++)
62 /* XXX: Scale the cost up when inside of a loop. */
63 vir_for_each_block(block
, c
) {
64 vir_for_each_inst(inst
, block
) {
65 /* We can't insert a new TMU operation while currently
66 * in a TMU operation, and we can't insert new thread
67 * switches after starting output writes.
71 (c
->threads
> 1 && started_last_seg
));
73 for (int i
= 0; i
< vir_get_nsrc(inst
); i
++) {
74 if (inst
->src
[i
].file
!= QFILE_TEMP
)
77 int temp
= inst
->src
[i
].index
;
79 BITSET_CLEAR(c
->spillable
,
82 spill_costs
[temp
] += block_scale
;
86 if (inst
->dst
.file
== QFILE_TEMP
) {
87 int temp
= inst
->dst
.index
;
90 BITSET_CLEAR(c
->spillable
,
93 spill_costs
[temp
] += block_scale
;
97 if (inst
->is_last_thrsw
)
98 started_last_seg
= true;
100 if (v3d_qpu_writes_vpm(&inst
->qpu
) ||
101 v3d_qpu_uses_tlb(&inst
->qpu
))
102 started_last_seg
= true;
104 /* Track when we're in between a TMU setup and the
105 * final LDTMU or TMUWT from that TMU setup. We can't
106 * spill/fill any temps during that time, because that
107 * involves inserting a new TMU setup/LDTMU sequence.
109 if (inst
->qpu
.sig
.ldtmu
&&
110 is_last_ldtmu(inst
, block
))
111 in_tmu_operation
= false;
113 if (inst
->qpu
.type
== V3D_QPU_INSTR_TYPE_ALU
&&
114 inst
->qpu
.alu
.add
.op
== V3D_QPU_A_TMUWT
)
115 in_tmu_operation
= false;
117 if (v3d_qpu_writes_tmu(&inst
->qpu
))
118 in_tmu_operation
= true;
122 for (unsigned i
= 0; i
< c
->num_temps
; i
++) {
123 int node
= temp_to_node
[i
];
125 if (BITSET_TEST(c
->spillable
, i
))
126 ra_set_node_spill_cost(g
, node
, spill_costs
[i
]);
129 return ra_get_best_spill_node(g
);
132 /* The spill offset for this thread takes a bit of setup, so do it once at
136 v3d_setup_spill_base(struct v3d_compile
*c
)
138 c
->cursor
= vir_before_block(vir_entry_block(c
));
140 int start_num_temps
= c
->num_temps
;
142 /* Each thread wants to be in a separate region of the scratch space
143 * so that the QPUs aren't fighting over cache lines. We have the
144 * driver keep a single global spill BO rather than
145 * per-spilling-program BOs, so we need a uniform from the driver for
146 * what the per-thread scale is.
148 struct qreg thread_offset
=
151 vir_uniform(c
, QUNIFORM_SPILL_SIZE_PER_THREAD
, 0));
153 /* Each channel in a reg is 4 bytes, so scale them up by that. */
154 struct qreg element_offset
= vir_SHL(c
, vir_EIDX(c
),
155 vir_uniform_ui(c
, 2));
157 c
->spill_base
= vir_ADD(c
,
158 vir_ADD(c
, thread_offset
, element_offset
),
159 vir_uniform(c
, QUNIFORM_SPILL_OFFSET
, 0));
161 /* Make sure that we don't spill the spilling setup instructions. */
162 for (int i
= start_num_temps
; i
< c
->num_temps
; i
++)
163 BITSET_CLEAR(c
->spillable
, i
);
167 v3d_emit_spill_tmua(struct v3d_compile
*c
, uint32_t spill_offset
)
169 vir_ADD_dest(c
, vir_reg(QFILE_MAGIC
,
172 vir_uniform_ui(c
, spill_offset
));
176 v3d_spill_reg(struct v3d_compile
*c
, int spill_temp
)
178 uint32_t spill_offset
= c
->spill_size
;
179 c
->spill_size
+= 16 * sizeof(uint32_t);
181 if (spill_offset
== 0)
182 v3d_setup_spill_base(c
);
184 struct qinst
*last_thrsw
= c
->last_thrsw
;
185 assert(!last_thrsw
|| last_thrsw
->is_last_thrsw
);
187 int start_num_temps
= c
->num_temps
;
189 vir_for_each_inst_inorder(inst
, c
) {
190 for (int i
= 0; i
< vir_get_nsrc(inst
); i
++) {
191 if (inst
->src
[i
].file
!= QFILE_TEMP
||
192 inst
->src
[i
].index
!= spill_temp
) {
196 c
->cursor
= vir_before_inst(inst
);
198 v3d_emit_spill_tmua(c
, spill_offset
);
200 inst
->src
[i
] = vir_LDTMU(c
);
204 if (inst
->dst
.file
== QFILE_TEMP
&&
205 inst
->dst
.index
== spill_temp
) {
206 c
->cursor
= vir_after_inst(inst
);
208 inst
->dst
.index
= c
->num_temps
++;
209 vir_MOV_dest(c
, vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_TMUD
),
211 v3d_emit_spill_tmua(c
, spill_offset
);
217 /* If we didn't have a last-thrsw inserted by nir_to_vir and
218 * we've been inserting thrsws, then insert a new last_thrsw
219 * right before we start the vpm/tlb sequence for the last
222 if (!last_thrsw
&& c
->last_thrsw
&&
223 (v3d_qpu_writes_vpm(&inst
->qpu
) ||
224 v3d_qpu_uses_tlb(&inst
->qpu
))) {
225 c
->cursor
= vir_before_inst(inst
);
228 last_thrsw
= c
->last_thrsw
;
229 last_thrsw
->is_last_thrsw
= true;
233 /* Make sure c->last_thrsw is the actual last thrsw, not just one we
234 * inserted in our most recent unspill.
237 c
->last_thrsw
= last_thrsw
;
239 /* Don't allow spilling of our spilling instructions. There's no way
240 * they can help get things colored.
242 for (int i
= start_num_temps
; i
< c
->num_temps
; i
++)
243 BITSET_CLEAR(c
->spillable
, i
);
246 struct v3d_ra_select_callback_data
{
252 v3d_ra_select_callback(struct ra_graph
*g
, BITSET_WORD
*regs
, void *data
)
254 struct v3d_ra_select_callback_data
*v3d_ra
= data
;
256 /* Choose an accumulator if possible (I think it's lower power than
257 * phys regs), but round-robin through them to give post-RA
258 * instruction selection more options.
260 for (int i
= 0; i
< ACC_COUNT
; i
++) {
261 int acc_off
= (v3d_ra
->next_acc
+ i
) % ACC_COUNT
;
262 int acc
= ACC_INDEX
+ acc_off
;
264 if (BITSET_TEST(regs
, acc
)) {
265 v3d_ra
->next_acc
= acc_off
+ 1;
270 for (int i
= 0; i
< PHYS_COUNT
; i
++) {
271 int phys_off
= (v3d_ra
->next_phys
+ i
) % PHYS_COUNT
;
272 int phys
= PHYS_INDEX
+ phys_off
;
274 if (BITSET_TEST(regs
, phys
)) {
275 v3d_ra
->next_phys
= phys_off
+ 1;
280 unreachable("RA must pass us at least one possible reg.");
284 vir_init_reg_sets(struct v3d_compiler
*compiler
)
286 /* Allocate up to 3 regfile classes, for the ways the physical
287 * register file can be divided up for fragment shader threading.
289 int max_thread_index
= (compiler
->devinfo
->ver
>= 40 ? 2 : 3);
291 compiler
->regs
= ra_alloc_reg_set(compiler
, PHYS_INDEX
+ PHYS_COUNT
,
296 for (int threads
= 0; threads
< max_thread_index
; threads
++) {
297 compiler
->reg_class_phys_or_acc
[threads
] =
298 ra_alloc_reg_class(compiler
->regs
);
299 compiler
->reg_class_phys
[threads
] =
300 ra_alloc_reg_class(compiler
->regs
);
302 for (int i
= PHYS_INDEX
;
303 i
< PHYS_INDEX
+ (PHYS_COUNT
>> threads
); i
++) {
304 ra_class_add_reg(compiler
->regs
,
305 compiler
->reg_class_phys_or_acc
[threads
], i
);
306 ra_class_add_reg(compiler
->regs
,
307 compiler
->reg_class_phys
[threads
], i
);
310 for (int i
= ACC_INDEX
+ 0; i
< ACC_INDEX
+ ACC_COUNT
; i
++) {
311 ra_class_add_reg(compiler
->regs
,
312 compiler
->reg_class_phys_or_acc
[threads
], i
);
316 ra_set_finalize(compiler
->regs
, NULL
);
321 struct node_to_temp_map
{
327 node_to_temp_priority(const void *in_a
, const void *in_b
)
329 const struct node_to_temp_map
*a
= in_a
;
330 const struct node_to_temp_map
*b
= in_b
;
332 return a
->priority
- b
->priority
;
335 #define CLASS_BIT_PHYS (1 << 0)
336 #define CLASS_BIT_R0_R2 (1 << 1)
337 #define CLASS_BIT_R3 (1 << 2)
338 #define CLASS_BIT_R4 (1 << 3)
341 * Returns a mapping from QFILE_TEMP indices to struct qpu_regs.
343 * The return value should be freed by the caller.
346 v3d_register_allocate(struct v3d_compile
*c
, bool *spilled
)
348 struct node_to_temp_map map
[c
->num_temps
];
349 uint32_t temp_to_node
[c
->num_temps
];
350 uint8_t class_bits
[c
->num_temps
];
351 struct qpu_reg
*temp_registers
= calloc(c
->num_temps
,
352 sizeof(*temp_registers
));
353 int acc_nodes
[ACC_COUNT
];
354 struct v3d_ra_select_callback_data callback_data
= {
356 /* Start at RF3, to try to keep the TLB writes from using
364 vir_calculate_live_intervals(c
);
366 /* Convert 1, 2, 4 threads to 0, 1, 2 index.
368 * V3D 4.x has double the physical register space, so 64 physical regs
369 * are available at both 1x and 2x threading, and 4x has 32.
371 int thread_index
= ffs(c
->threads
) - 1;
372 if (c
->devinfo
->ver
>= 40) {
373 if (thread_index
>= 1)
377 struct ra_graph
*g
= ra_alloc_interference_graph(c
->compiler
->regs
,
379 ARRAY_SIZE(acc_nodes
));
380 ra_set_select_reg_callback(g
, v3d_ra_select_callback
, &callback_data
);
382 /* Make some fixed nodes for the accumulators, which we will need to
383 * interfere with when ops have implied r3/r4 writes or for the thread
384 * switches. We could represent these as classes for the nodes to
385 * live in, but the classes take up a lot of memory to set up, so we
386 * don't want to make too many.
388 for (int i
= 0; i
< ARRAY_SIZE(acc_nodes
); i
++) {
389 acc_nodes
[i
] = c
->num_temps
+ i
;
390 ra_set_node_reg(g
, acc_nodes
[i
], ACC_INDEX
+ i
);
393 for (uint32_t i
= 0; i
< c
->num_temps
; i
++) {
395 map
[i
].priority
= c
->temp_end
[i
] - c
->temp_start
[i
];
397 qsort(map
, c
->num_temps
, sizeof(map
[0]), node_to_temp_priority
);
398 for (uint32_t i
= 0; i
< c
->num_temps
; i
++) {
399 temp_to_node
[map
[i
].temp
] = i
;
402 /* Figure out our register classes and preallocated registers. We
403 * start with any temp being able to be in any file, then instructions
404 * incrementally remove bits that the temp definitely can't be in.
407 CLASS_BIT_PHYS
| CLASS_BIT_R0_R2
| CLASS_BIT_R3
| CLASS_BIT_R4
,
411 vir_for_each_inst_inorder(inst
, c
) {
412 /* If the instruction writes r3/r4 (and optionally moves its
413 * result to a temp), nothing else can be stored in r3/r4 across
416 if (vir_writes_r3(c
->devinfo
, inst
)) {
417 for (int i
= 0; i
< c
->num_temps
; i
++) {
418 if (c
->temp_start
[i
] < ip
&&
419 c
->temp_end
[i
] > ip
) {
420 ra_add_node_interference(g
,
426 if (vir_writes_r4(c
->devinfo
, inst
)) {
427 for (int i
= 0; i
< c
->num_temps
; i
++) {
428 if (c
->temp_start
[i
] < ip
&&
429 c
->temp_end
[i
] > ip
) {
430 ra_add_node_interference(g
,
437 if (inst
->qpu
.type
== V3D_QPU_INSTR_TYPE_ALU
) {
438 switch (inst
->qpu
.alu
.add
.op
) {
439 case V3D_QPU_A_LDVPMV_IN
:
440 case V3D_QPU_A_LDVPMV_OUT
:
441 case V3D_QPU_A_LDVPMD_IN
:
442 case V3D_QPU_A_LDVPMD_OUT
:
443 case V3D_QPU_A_LDVPMP
:
444 case V3D_QPU_A_LDVPMG_IN
:
445 case V3D_QPU_A_LDVPMG_OUT
:
446 /* LDVPMs only store to temps (the MA flag
447 * decides whether the LDVPM is in or out)
449 assert(inst
->dst
.file
== QFILE_TEMP
);
450 class_bits
[inst
->dst
.index
] &= CLASS_BIT_PHYS
;
453 case V3D_QPU_A_RECIP
:
454 case V3D_QPU_A_RSQRT
:
458 case V3D_QPU_A_RSQRT2
:
459 /* The SFU instructions write directly to the
462 assert(inst
->dst
.file
== QFILE_TEMP
);
463 class_bits
[inst
->dst
.index
] &= CLASS_BIT_PHYS
;
471 if (inst
->src
[0].file
== QFILE_REG
) {
472 switch (inst
->src
[0].index
) {
476 /* Payload setup instructions: Force allocate
477 * the dst to the given register (so the MOV
480 assert(inst
->qpu
.alu
.mul
.op
== V3D_QPU_M_MOV
);
481 assert(inst
->dst
.file
== QFILE_TEMP
);
483 temp_to_node
[inst
->dst
.index
],
490 if (inst
->qpu
.sig
.thrsw
) {
491 /* All accumulators are invalidated across a thread
494 for (int i
= 0; i
< c
->num_temps
; i
++) {
495 if (c
->temp_start
[i
] < ip
&& c
->temp_end
[i
] > ip
)
496 class_bits
[i
] &= CLASS_BIT_PHYS
;
503 for (uint32_t i
= 0; i
< c
->num_temps
; i
++) {
504 if (class_bits
[i
] == CLASS_BIT_PHYS
) {
505 ra_set_node_class(g
, temp_to_node
[i
],
506 c
->compiler
->reg_class_phys
[thread_index
]);
508 assert(class_bits
[i
] == (CLASS_BIT_PHYS
|
512 ra_set_node_class(g
, temp_to_node
[i
],
513 c
->compiler
->reg_class_phys_or_acc
[thread_index
]);
517 for (uint32_t i
= 0; i
< c
->num_temps
; i
++) {
518 for (uint32_t j
= i
+ 1; j
< c
->num_temps
; j
++) {
519 if (!(c
->temp_start
[i
] >= c
->temp_end
[j
] ||
520 c
->temp_start
[j
] >= c
->temp_end
[i
])) {
521 ra_add_node_interference(g
,
528 /* Debug code to force a bit of register spilling, for running across
529 * conformance tests to make sure that spilling works.
531 int force_register_spills
= 0;
532 if (c
->spill_size
< 16 * sizeof(uint32_t) * force_register_spills
) {
533 int node
= v3d_choose_spill_node(c
, g
, temp_to_node
);
535 v3d_spill_reg(c
, map
[node
].temp
);
542 bool ok
= ra_allocate(g
);
544 /* Try to spill, if we can't reduce threading first. */
545 if (thread_index
== 0) {
546 int node
= v3d_choose_spill_node(c
, g
, temp_to_node
);
549 v3d_spill_reg(c
, map
[node
].temp
);
552 /* Ask the outer loop to call back in. */
558 free(temp_registers
);
562 for (uint32_t i
= 0; i
< c
->num_temps
; i
++) {
563 int ra_reg
= ra_get_node_reg(g
, temp_to_node
[i
]);
564 if (ra_reg
< PHYS_INDEX
) {
565 temp_registers
[i
].magic
= true;
566 temp_registers
[i
].index
= (V3D_QPU_WADDR_R0
+
569 temp_registers
[i
].magic
= false;
570 temp_registers
[i
].index
= ra_reg
- PHYS_INDEX
;
573 /* If the value's never used, just write to the NOP register
574 * for clarity in debug output.
576 if (c
->temp_start
[i
] == c
->temp_end
[i
]) {
577 temp_registers
[i
].magic
= true;
578 temp_registers
[i
].index
= V3D_QPU_WADDR_NOP
;
584 if (V3D_DEBUG
& V3D_DEBUG_SHADERDB
) {
585 fprintf(stderr
, "SHADER-DB: %s prog %d/%d: %d spills\n",
586 vir_get_stage_name(c
),
587 c
->program_id
, c
->variant_id
,
590 fprintf(stderr
, "SHADER-DB: %s prog %d/%d: %d fills\n",
591 vir_get_stage_name(c
),
592 c
->program_id
, c
->variant_id
,
596 return temp_registers
;