src/broadcom/qpu/qpu_disasm.c

   1 /*
   2  * Copyright © 2016 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <string.h>
  25 #include <stdio.h>
  26 #include "util/ralloc.h"
  27
  28 #include "broadcom/common/v3d_device_info.h"
  29 #include "qpu_instr.h"
  30 #include "qpu_disasm.h"
  31
  32 struct disasm_state {
  33         const struct v3d_device_info *devinfo;
  34         char *string;
  35         size_t offset;
  36 };
  37
  38 static void
  39 append(struct disasm_state *disasm, const char *fmt, ...)
  40 {
  41         va_list args;
  42         va_start(args, fmt);
  43         ralloc_vasprintf_rewrite_tail(&disasm->string,
  44                                       &disasm->offset,
  45                                       fmt, args);
  46         va_end(args);
  47 }
  48
  49 static void
  50 pad_to(struct disasm_state *disasm, int n)
  51 {
  52         /* FIXME: Do a single append somehow. */
  53         while (disasm->offset < n)
  54                 append(disasm, " ");
  55 }
  56
  57
  58 static void
  59 v3d_qpu_disasm_raddr(struct disasm_state *disasm,
  60                      const struct v3d_qpu_instr *instr, uint8_t mux)
  61 {
  62         if (mux == V3D_QPU_MUX_A) {
  63                 append(disasm, "rf%d", instr->raddr_a);
  64         } else if (mux == V3D_QPU_MUX_B) {
  65                 append(disasm, "rf%d", instr->raddr_b);
  66         } else {
  67                 append(disasm, "r%d", mux);
  68         }
  69 }
  70
  71 static void
  72 v3d_qpu_disasm_waddr(struct disasm_state *disasm, uint32_t waddr, bool magic)
  73 {
  74         if (!magic) {
  75                 append(disasm, "rf%d", waddr);
  76                 return;
  77         }
  78
  79         const char *name = v3d_qpu_magic_waddr_name(waddr);
  80         if (name)
  81                 append(disasm, "%s", name);
  82         else
  83                 append(disasm, "waddr UNKNOWN %d", waddr);
  84 }
  85
  86 static void
  87 v3d_qpu_disasm_add(struct disasm_state *disasm,
  88                    const struct v3d_qpu_instr *instr)
  89 {
  90         bool has_dst = v3d_qpu_add_op_has_dst(instr->alu.add.op);
  91         int num_src = v3d_qpu_add_op_num_src(instr->alu.add.op);
  92
  93         append(disasm, "%s", v3d_qpu_add_op_name(instr->alu.add.op));
  94         append(disasm, "%s", v3d_qpu_cond_name(instr->flags.ac));
  95         append(disasm, "%s", v3d_qpu_pf_name(instr->flags.apf));
  96         append(disasm, "%s", v3d_qpu_uf_name(instr->flags.auf));
  97
  98         append(disasm, "  ");
  99
 100         if (has_dst) {
 101                 v3d_qpu_disasm_waddr(disasm, instr->alu.add.waddr,
 102                                      instr->alu.add.magic_write);
 103                 append(disasm, v3d_qpu_pack_name(instr->alu.add.output_pack));
 104         }
 105
 106         if (num_src >= 1) {
 107                 if (has_dst)
 108                         append(disasm, ", ");
 109                 v3d_qpu_disasm_raddr(disasm, instr, instr->alu.add.a);
 110                 append(disasm, "%s",
 111                        v3d_qpu_unpack_name(instr->alu.add.a_unpack));
 112         }
 113
 114         if (num_src >= 2) {
 115                 append(disasm, ", ");
 116                 v3d_qpu_disasm_raddr(disasm, instr, instr->alu.add.b);
 117                 append(disasm, "%s",
 118                        v3d_qpu_unpack_name(instr->alu.add.b_unpack));
 119         }
 120 }
 121
 122 static void
 123 v3d_qpu_disasm_mul(struct disasm_state *disasm,
 124                    const struct v3d_qpu_instr *instr)
 125 {
 126         bool has_dst = v3d_qpu_mul_op_has_dst(instr->alu.mul.op);
 127         int num_src = v3d_qpu_mul_op_num_src(instr->alu.mul.op);
 128
 129         pad_to(disasm, 21);
 130         append(disasm, "; ");
 131
 132         append(disasm, "%s", v3d_qpu_mul_op_name(instr->alu.mul.op));
 133         append(disasm, "%s", v3d_qpu_cond_name(instr->flags.mc));
 134         append(disasm, "%s", v3d_qpu_pf_name(instr->flags.mpf));
 135         append(disasm, "%s", v3d_qpu_uf_name(instr->flags.muf));
 136
 137         if (instr->alu.mul.op == V3D_QPU_M_NOP)
 138                 return;
 139
 140         append(disasm, "  ");
 141
 142         if (has_dst) {
 143                 v3d_qpu_disasm_waddr(disasm, instr->alu.mul.waddr,
 144                                      instr->alu.mul.magic_write);
 145                 append(disasm, v3d_qpu_pack_name(instr->alu.mul.output_pack));
 146         }
 147
 148         if (num_src >= 1) {
 149                 if (has_dst)
 150                         append(disasm, ", ");
 151                 v3d_qpu_disasm_raddr(disasm, instr, instr->alu.mul.a);
 152                 append(disasm, "%s",
 153                        v3d_qpu_unpack_name(instr->alu.mul.a_unpack));
 154         }
 155
 156         if (num_src >= 2) {
 157                 append(disasm, ", ");
 158                 v3d_qpu_disasm_raddr(disasm, instr, instr->alu.mul.b);
 159                 append(disasm, "%s",
 160                        v3d_qpu_unpack_name(instr->alu.mul.b_unpack));
 161         }
 162 }
 163
 164 static void
 165 v3d_qpu_disasm_sig(struct disasm_state *disasm,
 166                    const struct v3d_qpu_instr *instr)
 167 {
 168         const struct v3d_qpu_sig *sig = &instr->sig;
 169
 170         if (!sig->thrsw &&
 171             !sig->ldvary &&
 172             !sig->ldvpm &&
 173             !sig->ldtmu &&
 174             !sig->ldunif &&
 175             !sig->wrtmuc) {
 176                 return;
 177         }
 178
 179         pad_to(disasm, 41);
 180
 181         if (sig->thrsw)
 182                 append(disasm, "; thrsw");
 183         if (sig->ldvary)
 184                 append(disasm, "; ldvary");
 185         if (sig->ldvpm)
 186                 append(disasm, "; ldvpm");
 187         if (sig->ldtmu)
 188                 append(disasm, "; ldtmu");
 189         if (sig->ldunif)
 190                 append(disasm, "; ldunif");
 191         if (sig->wrtmuc)
 192                 append(disasm, "; wrtmuc");
 193 }
 194
 195 static void
 196 v3d_qpu_disasm_alu(struct disasm_state *disasm,
 197                    const struct v3d_qpu_instr *instr)
 198 {
 199         v3d_qpu_disasm_add(disasm, instr);
 200         v3d_qpu_disasm_mul(disasm, instr);
 201         v3d_qpu_disasm_sig(disasm, instr);
 202 }
 203
 204 static void
 205 v3d_qpu_disasm_branch(struct disasm_state *disasm,
 206                       const struct v3d_qpu_instr *instr)
 207 {
 208         append(disasm, "b");
 209         if (instr->branch.ub)
 210                 append(disasm, "u");
 211         append(disasm, "%s", v3d_qpu_branch_cond_name(instr->branch.cond));
 212         append(disasm, "%s", v3d_qpu_msfign_name(instr->branch.msfign));
 213
 214         switch (instr->branch.bdi) {
 215         case V3D_QPU_BRANCH_DEST_ABS:
 216                 append(disasm, "  zero_addr+0x%08x", instr->branch.offset);
 217                 break;
 218
 219         case V3D_QPU_BRANCH_DEST_REL:
 220                 append(disasm, "  %d", instr->branch.offset);
 221                 break;
 222
 223         case V3D_QPU_BRANCH_DEST_LINK_REG:
 224                 append(disasm, "  lri");
 225                 break;
 226
 227         case V3D_QPU_BRANCH_DEST_REGFILE:
 228                 append(disasm, "  rf%d", instr->branch.raddr_a);
 229                 break;
 230         }
 231
 232         if (instr->branch.ub) {
 233                 switch (instr->branch.bdu) {
 234                 case V3D_QPU_BRANCH_DEST_ABS:
 235                         append(disasm, ", a:unif");
 236                         break;
 237
 238                 case V3D_QPU_BRANCH_DEST_REL:
 239                         append(disasm, ", r:unif");
 240                         break;
 241
 242                 case V3D_QPU_BRANCH_DEST_LINK_REG:
 243                         append(disasm, ", lri");
 244                         break;
 245
 246                 case V3D_QPU_BRANCH_DEST_REGFILE:
 247                         append(disasm, ", rf%d", instr->branch.raddr_a);
 248                         break;
 249                 }
 250         }
 251 }
 252
 253 const char *
 254 v3d_qpu_decode(const struct v3d_device_info *devinfo,
 255                const struct v3d_qpu_instr *instr)
 256 {
 257         struct disasm_state disasm = {
 258                 .string = rzalloc_size(NULL, 1),
 259                 .offset = 0,
 260                 .devinfo = devinfo,
 261         };
 262
 263         switch (instr->type) {
 264         case V3D_QPU_INSTR_TYPE_ALU:
 265                 v3d_qpu_disasm_alu(&disasm, instr);
 266                 break;
 267
 268         case V3D_QPU_INSTR_TYPE_BRANCH:
 269                 v3d_qpu_disasm_branch(&disasm, instr);
 270                 break;
 271         }
 272
 273         return disasm.string;
 274 }
 275
 276 /**
 277  * Returns a string containing the disassembled representation of the QPU
 278  * instruction.  It is the caller's responsibility to free the return value
 279  * with ralloc_free().
 280  */
 281 const char *
 282 v3d_qpu_disasm(const struct v3d_device_info *devinfo, uint64_t inst)
 283 {
 284         struct v3d_qpu_instr instr;
 285         bool ok = v3d_qpu_instr_unpack(devinfo, inst, &instr);
 286         assert(ok); (void)ok;
 287
 288         return v3d_qpu_decode(devinfo, &instr);
 289 }
 290
 291 void
 292 v3d_qpu_dump(const struct v3d_device_info *devinfo,
 293              const struct v3d_qpu_instr *instr)
 294 {
 295         const char *decoded = v3d_qpu_decode(devinfo, instr);
 296         fprintf(stderr, "%s", decoded);
 297         ralloc_free((char *)decoded);
 298 }