src/broadcom/qpu/qpu_instr.c

   1 /*
   2  * Copyright © 2016 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <stdlib.h>
  25 #include "util/macros.h"
  26 #include "qpu_instr.h"
  27
  28 #ifndef QPU_MASK
  29 #define QPU_MASK(high, low) ((((uint64_t)1<<((high)-(low)+1))-1)<<(low))
  30 /* Using the GNU statement expression extension */
  31 #define QPU_SET_FIELD(value, field)                                       \
  32         ({                                                                \
  33                 uint64_t fieldval = (uint64_t)(value) << field ## _SHIFT; \
  34                 assert((fieldval & ~ field ## _MASK) == 0);               \
  35                 fieldval & field ## _MASK;                                \
  36          })
  37
  38 #define QPU_GET_FIELD(word, field) ((uint32_t)(((word)  & field ## _MASK) >> field ## _SHIFT))
  39
  40 #define QPU_UPDATE_FIELD(inst, value, field)                              \
  41         (((inst) & ~(field ## _MASK)) | QPU_SET_FIELD(value, field))
  42 #endif /* QPU_MASK */
  43
  44 #define VC5_QPU_OP_MUL_SHIFT                58
  45 #define VC5_QPU_OP_MUL_MASK                 QPU_MASK(63, 58)
  46
  47 #define VC5_QPU_SIG_SHIFT                   53
  48 #define VC5_QPU_SIG_MASK                    QPU_MASK(57, 53)
  49 # define VC5_QPU_SIG_THRSW_BIT              0x1
  50 # define VC5_QPU_SIG_LDUNIF_BIT             0x2
  51 # define VC5_QPU_SIG_LDTMU_BIT              0x4
  52 # define VC5_QPU_SIG_LDVARY_BIT             0x8
  53
  54 #define VC5_QPU_COND_SHIFT                  46
  55 #define VC5_QPU_COND_MASK                   QPU_MASK(52, 46)
  56
  57 #define VC5_QPU_COND_IFA                    0
  58 #define VC5_QPU_COND_IFB                    1
  59 #define VC5_QPU_COND_IFNA                   2
  60 #define VC5_QPU_COND_IFNB                   3
  61
  62 #define VC5_QPU_MM                          QPU_MASK(45, 45)
  63 #define VC5_QPU_MA                          QPU_MASK(44, 44)
  64
  65 #define V3D_QPU_WADDR_M_SHIFT               38
  66 #define V3D_QPU_WADDR_M_MASK                QPU_MASK(43, 38)
  67
  68 #define VC5_QPU_BRANCH_ADDR_LOW_SHIFT       35
  69 #define VC5_QPU_BRANCH_ADDR_LOW_MASK        QPU_MASK(55, 35)
  70
  71 #define V3D_QPU_WADDR_A_SHIFT               32
  72 #define V3D_QPU_WADDR_A_MASK                QPU_MASK(37, 32)
  73
  74 #define VC5_QPU_BRANCH_COND_SHIFT           32
  75 #define VC5_QPU_BRANCH_COND_MASK            QPU_MASK(34, 32)
  76
  77 #define VC5_QPU_BRANCH_ADDR_HIGH_SHIFT      24
  78 #define VC5_QPU_BRANCH_ADDR_HIGH_MASK       QPU_MASK(31, 24)
  79
  80 #define VC5_QPU_OP_ADD_SHIFT                24
  81 #define VC5_QPU_OP_ADD_MASK                 QPU_MASK(31, 24)
  82
  83 #define VC5_QPU_MUL_B_SHIFT                 21
  84 #define VC5_QPU_MUL_B_MASK                  QPU_MASK(23, 21)
  85
  86 #define VC5_QPU_BRANCH_MSFIGN_SHIFT         21
  87 #define VC5_QPU_BRANCH_MSFIGN_MASK          QPU_MASK(22, 21)
  88
  89 #define VC5_QPU_MUL_A_SHIFT                 18
  90 #define VC5_QPU_MUL_A_MASK                  QPU_MASK(20, 18)
  91
  92 #define VC5_QPU_ADD_B_SHIFT                 15
  93 #define VC5_QPU_ADD_B_MASK                  QPU_MASK(17, 15)
  94
  95 #define VC5_QPU_BRANCH_BDU_SHIFT            15
  96 #define VC5_QPU_BRANCH_BDU_MASK             QPU_MASK(17, 15)
  97
  98 #define VC5_QPU_BRANCH_UB                   QPU_MASK(14, 14)
  99
 100 #define VC5_QPU_ADD_A_SHIFT                 12
 101 #define VC5_QPU_ADD_A_MASK                  QPU_MASK(14, 12)
 102
 103 #define VC5_QPU_BRANCH_BDI_SHIFT            12
 104 #define VC5_QPU_BRANCH_BDI_MASK             QPU_MASK(13, 12)
 105
 106 #define VC5_QPU_RADDR_A_SHIFT               6
 107 #define VC5_QPU_RADDR_A_MASK                QPU_MASK(11, 6)
 108
 109 #define VC5_QPU_RADDR_B_SHIFT               0
 110 #define VC5_QPU_RADDR_B_MASK                QPU_MASK(5, 0)
 111
 112 const char *
 113 v3d_qpu_magic_waddr_name(enum v3d_qpu_waddr waddr)
 114 {
 115         static const char *waddr_magic[] = {
 116                 [V3D_QPU_WADDR_R0] = "r0",
 117                 [V3D_QPU_WADDR_R1] = "r1",
 118                 [V3D_QPU_WADDR_R2] = "r2",
 119                 [V3D_QPU_WADDR_R3] = "r3",
 120                 [V3D_QPU_WADDR_R4] = "r4",
 121                 [V3D_QPU_WADDR_R5] = "r5",
 122                 [V3D_QPU_WADDR_NOP] = "-",
 123                 [V3D_QPU_WADDR_TLB] = "tlb",
 124                 [V3D_QPU_WADDR_TLBU] = "tlbu",
 125                 [V3D_QPU_WADDR_TMU] = "tmu",
 126                 [V3D_QPU_WADDR_TMUL] = "tmul",
 127                 [V3D_QPU_WADDR_TMUD] = "tmud",
 128                 [V3D_QPU_WADDR_TMUA] = "tmua",
 129                 [V3D_QPU_WADDR_TMUAU] = "tmuau",
 130                 [V3D_QPU_WADDR_VPM] = "vpm",
 131                 [V3D_QPU_WADDR_VPMU] = "vpmu",
 132                 [V3D_QPU_WADDR_SYNC] = "sync",
 133                 [V3D_QPU_WADDR_SYNCU] = "syncu",
 134                 [V3D_QPU_WADDR_RECIP] = "recip",
 135                 [V3D_QPU_WADDR_RSQRT] = "rsqrt",
 136                 [V3D_QPU_WADDR_EXP] = "exp",
 137                 [V3D_QPU_WADDR_LOG] = "log",
 138                 [V3D_QPU_WADDR_SIN] = "sin",
 139                 [V3D_QPU_WADDR_RSQRT2] = "rsqrt2",
 140         };
 141
 142         return waddr_magic[waddr];
 143 }
 144
 145 const char *
 146 v3d_qpu_add_op_name(enum v3d_qpu_add_op op)
 147 {
 148         static const char *op_names[] = {
 149                 [V3D_QPU_A_FADD] = "fadd",
 150                 [V3D_QPU_A_FADDNF] = "faddnf",
 151                 [V3D_QPU_A_VFPACK] = "vfpack",
 152                 [V3D_QPU_A_ADD] = "add",
 153                 [V3D_QPU_A_SUB] = "sub",
 154                 [V3D_QPU_A_FSUB] = "fsub",
 155                 [V3D_QPU_A_MIN] = "min",
 156                 [V3D_QPU_A_MAX] = "max",
 157                 [V3D_QPU_A_UMIN] = "umin",
 158                 [V3D_QPU_A_UMAX] = "umax",
 159                 [V3D_QPU_A_SHL] = "shl",
 160                 [V3D_QPU_A_SHR] = "shr",
 161                 [V3D_QPU_A_ASR] = "asr",
 162                 [V3D_QPU_A_ROR] = "ror",
 163                 [V3D_QPU_A_FMIN] = "fmin",
 164                 [V3D_QPU_A_FMAX] = "fmax",
 165                 [V3D_QPU_A_VFMIN] = "vfmin",
 166                 [V3D_QPU_A_AND] = "and",
 167                 [V3D_QPU_A_OR] = "or",
 168                 [V3D_QPU_A_XOR] = "xor",
 169                 [V3D_QPU_A_VADD] = "vadd",
 170                 [V3D_QPU_A_VSUB] = "vsub",
 171                 [V3D_QPU_A_NOT] = "not",
 172                 [V3D_QPU_A_NEG] = "neg",
 173                 [V3D_QPU_A_FLAPUSH] = "flapush",
 174                 [V3D_QPU_A_FLBPUSH] = "flbpush",
 175                 [V3D_QPU_A_FLBPOP] = "flbpop",
 176                 [V3D_QPU_A_SETMSF] = "setmsf",
 177                 [V3D_QPU_A_SETREVF] = "setrevf",
 178                 [V3D_QPU_A_NOP] = "nop",
 179                 [V3D_QPU_A_TIDX] = "tidx",
 180                 [V3D_QPU_A_EIDX] = "eidx",
 181                 [V3D_QPU_A_LR] = "lr",
 182                 [V3D_QPU_A_VFLA] = "vfla",
 183                 [V3D_QPU_A_VFLNA] = "vflna",
 184                 [V3D_QPU_A_VFLB] = "vflb",
 185                 [V3D_QPU_A_VFLNB] = "vflnb",
 186                 [V3D_QPU_A_FXCD] = "fxcd",
 187                 [V3D_QPU_A_XCD] = "xcd",
 188                 [V3D_QPU_A_FYCD] = "fycd",
 189                 [V3D_QPU_A_YCD] = "ycd",
 190                 [V3D_QPU_A_MSF] = "msf",
 191                 [V3D_QPU_A_REVF] = "revf",
 192                 [V3D_QPU_A_VDWWT] = "vdwwt",
 193                 [V3D_QPU_A_IID] = "iid",
 194                 [V3D_QPU_A_SAMPID] = "sampid",
 195                 [V3D_QPU_A_PATCHID] = "patchid",
 196                 [V3D_QPU_A_TMUWT] = "tmuwt",
 197                 [V3D_QPU_A_VPMSETUP] = "vpmsetup",
 198                 [V3D_QPU_A_VPMWT] = "vpmwt",
 199                 [V3D_QPU_A_LDVPMV] = "ldvpmv",
 200                 [V3D_QPU_A_LDVPMD] = "ldvpmd",
 201                 [V3D_QPU_A_LDVPMP] = "ldvpmp",
 202                 [V3D_QPU_A_LDVPMG] = "ldvpmg",
 203                 [V3D_QPU_A_FCMP] = "fcmp",
 204                 [V3D_QPU_A_VFMAX] = "vfmax",
 205                 [V3D_QPU_A_FROUND] = "fround",
 206                 [V3D_QPU_A_FTOIN] = "ftoin",
 207                 [V3D_QPU_A_FTRUNC] = "ftrunc",
 208                 [V3D_QPU_A_FTOIZ] = "ftoiz",
 209                 [V3D_QPU_A_FFLOOR] = "ffloor",
 210                 [V3D_QPU_A_FTOUZ] = "ftouz",
 211                 [V3D_QPU_A_FCEIL] = "fceil",
 212                 [V3D_QPU_A_FTOC] = "ftoc",
 213                 [V3D_QPU_A_FDX] = "fdx",
 214                 [V3D_QPU_A_FDY] = "fdy",
 215                 [V3D_QPU_A_STVPMV] = "stvpmv",
 216                 [V3D_QPU_A_STVPMD] = "stvpmd",
 217                 [V3D_QPU_A_STVPMP] = "stvpmp",
 218                 [V3D_QPU_A_ITOF] = "itof",
 219                 [V3D_QPU_A_CLZ] = "clz",
 220                 [V3D_QPU_A_UTOF] = "utof",
 221         };
 222
 223         if (op >= ARRAY_SIZE(op_names))
 224                 return NULL;
 225
 226         return op_names[op];
 227 }
 228
 229 const char *
 230 v3d_qpu_mul_op_name(enum v3d_qpu_mul_op op)
 231 {
 232         static const char *op_names[] = {
 233                 [V3D_QPU_M_ADD] = "add",
 234                 [V3D_QPU_M_SUB] = "sub",
 235                 [V3D_QPU_M_UMUL24] = "umul24",
 236                 [V3D_QPU_M_VFMUL] = "vfmul",
 237                 [V3D_QPU_M_SMUL24] = "smul24",
 238                 [V3D_QPU_M_MULTOP] = "multop",
 239                 [V3D_QPU_M_FMOV] = "fmov",
 240                 [V3D_QPU_M_MOV] = "mov",
 241                 [V3D_QPU_M_NOP] = "nop",
 242                 [V3D_QPU_M_FMUL] = "fmul",
 243         };
 244
 245         if (op >= ARRAY_SIZE(op_names))
 246                 return NULL;
 247
 248         return op_names[op];
 249 }
 250
 251 const char *
 252 v3d_qpu_cond_name(enum v3d_qpu_cond cond)
 253 {
 254         switch (cond) {
 255         case V3D_QPU_COND_NONE:
 256                 return "";
 257         case V3D_QPU_COND_IFA:
 258                 return ".ifa";
 259         case V3D_QPU_COND_IFB:
 260                 return ".ifb";
 261         case V3D_QPU_COND_IFNA:
 262                 return ".ifna";
 263         case V3D_QPU_COND_IFNB:
 264                 return ".ifnb";
 265         default:
 266                 unreachable("bad cond value");
 267         }
 268 }
 269
 270 const char *
 271 v3d_qpu_branch_cond_name(enum v3d_qpu_branch_cond cond)
 272 {
 273         switch (cond) {
 274         case V3D_QPU_BRANCH_COND_ALWAYS:
 275                 return "";
 276         case V3D_QPU_BRANCH_COND_A0:
 277                 return ".a0";
 278         case V3D_QPU_BRANCH_COND_NA0:
 279                 return ".na0";
 280         case V3D_QPU_BRANCH_COND_ALLA:
 281                 return ".alla";
 282         case V3D_QPU_BRANCH_COND_ANYNA:
 283                 return ".anyna";
 284         case V3D_QPU_BRANCH_COND_ANYA:
 285                 return ".anya";
 286         case V3D_QPU_BRANCH_COND_ALLNA:
 287                 return ".allna";
 288         default:
 289                 unreachable("bad branch cond value");
 290         }
 291 }
 292
 293 const char *
 294 v3d_qpu_msfign_name(enum v3d_qpu_msfign msfign)
 295 {
 296         switch (msfign) {
 297         case V3D_QPU_MSFIGN_NONE:
 298                 return "";
 299         case V3D_QPU_MSFIGN_P:
 300                 return "p";
 301         case V3D_QPU_MSFIGN_Q:
 302                 return "q";
 303         default:
 304                 unreachable("bad branch cond value");
 305         }
 306 }
 307
 308 const char *
 309 v3d_qpu_pf_name(enum v3d_qpu_pf pf)
 310 {
 311         switch (pf) {
 312         case V3D_QPU_PF_NONE:
 313                 return "";
 314         case V3D_QPU_PF_PUSHZ:
 315                 return ".pushz";
 316         case V3D_QPU_PF_PUSHN:
 317                 return ".pushn";
 318         case V3D_QPU_PF_PUSHC:
 319                 return ".pushc";
 320         default:
 321                 unreachable("bad pf value");
 322         }
 323 }
 324
 325 const char *
 326 v3d_qpu_uf_name(enum v3d_qpu_uf uf)
 327 {
 328         switch (uf) {
 329         case V3D_QPU_UF_NONE:
 330                 return "";
 331         case V3D_QPU_UF_ANDZ:
 332                 return ".andz";
 333         case V3D_QPU_UF_ANDNZ:
 334                 return ".andnz";
 335         case V3D_QPU_UF_NORZ:
 336                 return ".norz";
 337         case V3D_QPU_UF_NORNZ:
 338                 return ".nornz";
 339         case V3D_QPU_UF_ANDN:
 340                 return ".andn";
 341         case V3D_QPU_UF_ANDNN:
 342                 return ".andnn";
 343         case V3D_QPU_UF_NORN:
 344                 return ".norn";
 345         case V3D_QPU_UF_NORNN:
 346                 return ".nornn";
 347         case V3D_QPU_UF_ANDC:
 348                 return ".andc";
 349         case V3D_QPU_UF_ANDNC:
 350                 return ".andnc";
 351         case V3D_QPU_UF_NORC:
 352                 return ".norc";
 353         case V3D_QPU_UF_NORNC:
 354                 return ".nornc";
 355         default:
 356                 unreachable("bad pf value");
 357         }
 358 }
 359
 360 const char *
 361 v3d_qpu_pack_name(enum v3d_qpu_output_pack pack)
 362 {
 363         switch (pack) {
 364         case V3D_QPU_PACK_NONE:
 365                 return "";
 366         case V3D_QPU_PACK_L:
 367                 return ".l";
 368         case V3D_QPU_PACK_H:
 369                 return ".h";
 370         default:
 371                 unreachable("bad pack value");
 372         }
 373 }
 374
 375 const char *
 376 v3d_qpu_unpack_name(enum v3d_qpu_input_unpack unpack)
 377 {
 378         switch (unpack) {
 379         case V3D_QPU_UNPACK_NONE:
 380                 return "";
 381         case V3D_QPU_UNPACK_L:
 382                 return ".l";
 383         case V3D_QPU_UNPACK_H:
 384                 return ".h";
 385         case V3D_QPU_UNPACK_ABS:
 386                 return ".abs";
 387         case V3D_QPU_UNPACK_REPLICATE_32F_16:
 388                 return ".ff";
 389         case V3D_QPU_UNPACK_REPLICATE_L_16:
 390                 return ".ll";
 391         case V3D_QPU_UNPACK_REPLICATE_H_16:
 392                 return ".hh";
 393         case V3D_QPU_UNPACK_SWAP_16:
 394                 return ".swp";
 395         default:
 396                 unreachable("bad unpack value");
 397         }
 398 }
 399
 400 #define D       1
 401 #define A       2
 402 #define B       4
 403 static const uint8_t add_op_args[] = {
 404         [V3D_QPU_A_FADD] = D | A | B,
 405         [V3D_QPU_A_FADDNF] = D | A | B,
 406         [V3D_QPU_A_VFPACK] = D | A | B,
 407         [V3D_QPU_A_ADD] = D | A | B,
 408         [V3D_QPU_A_VFPACK] = D | A | B,
 409         [V3D_QPU_A_SUB] = D | A | B,
 410         [V3D_QPU_A_VFPACK] = D | A | B,
 411         [V3D_QPU_A_FSUB] = D | A | B,
 412         [V3D_QPU_A_MIN] = D | A | B,
 413         [V3D_QPU_A_MAX] = D | A | B,
 414         [V3D_QPU_A_UMIN] = D | A | B,
 415         [V3D_QPU_A_UMAX] = D | A | B,
 416         [V3D_QPU_A_SHL] = D | A | B,
 417         [V3D_QPU_A_SHR] = D | A | B,
 418         [V3D_QPU_A_ASR] = D | A | B,
 419         [V3D_QPU_A_ROR] = D | A | B,
 420         [V3D_QPU_A_FMIN] = D | A | B,
 421         [V3D_QPU_A_FMAX] = D | A | B,
 422         [V3D_QPU_A_VFMIN] = D | A | B,
 423
 424         [V3D_QPU_A_AND] = D | A | B,
 425         [V3D_QPU_A_OR] = D | A | B,
 426         [V3D_QPU_A_XOR] = D | A | B,
 427
 428         [V3D_QPU_A_VADD] = D | A | B,
 429         [V3D_QPU_A_VSUB] = D | A | B,
 430         [V3D_QPU_A_NOT] = D | A,
 431         [V3D_QPU_A_NEG] = D | A,
 432         [V3D_QPU_A_FLAPUSH] = D | A,
 433         [V3D_QPU_A_FLBPUSH] = D | A,
 434         [V3D_QPU_A_FLBPOP] = D | A,
 435         [V3D_QPU_A_SETMSF] = D | A,
 436         [V3D_QPU_A_SETREVF] = D | A,
 437         [V3D_QPU_A_NOP] = 0,
 438         [V3D_QPU_A_TIDX] = D,
 439         [V3D_QPU_A_EIDX] = D,
 440         [V3D_QPU_A_LR] = D,
 441         [V3D_QPU_A_VFLA] = D,
 442         [V3D_QPU_A_VFLNA] = D,
 443         [V3D_QPU_A_VFLB] = D,
 444         [V3D_QPU_A_VFLNB] = D,
 445
 446         [V3D_QPU_A_FXCD] = D,
 447         [V3D_QPU_A_XCD] = D,
 448         [V3D_QPU_A_FYCD] = D,
 449         [V3D_QPU_A_YCD] = D,
 450
 451         [V3D_QPU_A_MSF] = D,
 452         [V3D_QPU_A_REVF] = D,
 453         [V3D_QPU_A_VDWWT] = D,
 454         [V3D_QPU_A_IID] = D,
 455         [V3D_QPU_A_SAMPID] = D,
 456         [V3D_QPU_A_PATCHID] = D,
 457         [V3D_QPU_A_TMUWT] = D,
 458         [V3D_QPU_A_VPMWT] = D,
 459
 460         [V3D_QPU_A_VPMSETUP] = D | A,
 461
 462         [V3D_QPU_A_LDVPMV] = D | A,
 463         [V3D_QPU_A_LDVPMD] = D | A,
 464         [V3D_QPU_A_LDVPMP] = D | A,
 465         [V3D_QPU_A_LDVPMG] = D | A | B,
 466
 467         /* FIXME: MOVABSNEG */
 468
 469         [V3D_QPU_A_FCMP] = D | A | B,
 470         [V3D_QPU_A_VFMAX] = D | A | B,
 471
 472         [V3D_QPU_A_FROUND] = D | A,
 473         [V3D_QPU_A_FTOIN] = D | A,
 474         [V3D_QPU_A_FTRUNC] = D | A,
 475         [V3D_QPU_A_FTOIZ] = D | A,
 476         [V3D_QPU_A_FFLOOR] = D | A,
 477         [V3D_QPU_A_FTOUZ] = D | A,
 478         [V3D_QPU_A_FCEIL] = D | A,
 479         [V3D_QPU_A_FTOC] = D | A,
 480
 481         [V3D_QPU_A_FDX] = D | A,
 482         [V3D_QPU_A_FDY] = D | A,
 483
 484         [V3D_QPU_A_STVPMV] = A | B,
 485         [V3D_QPU_A_STVPMD] = A | B,
 486         [V3D_QPU_A_STVPMP] = A | B,
 487
 488         [V3D_QPU_A_ITOF] = D | A,
 489         [V3D_QPU_A_CLZ] = D | A,
 490         [V3D_QPU_A_UTOF] = D | A,
 491 };
 492
 493 static const uint8_t mul_op_args[] = {
 494         [V3D_QPU_M_ADD] = D | A | B,
 495         [V3D_QPU_M_SUB] = D | A | B,
 496         [V3D_QPU_M_UMUL24] = D | A | B,
 497         [V3D_QPU_M_VFMUL] = D | A | B,
 498         [V3D_QPU_M_SMUL24] = D | A | B,
 499         [V3D_QPU_M_MULTOP] = D | A | B,
 500         [V3D_QPU_M_FMOV] = D | A,
 501         [V3D_QPU_M_NOP] = 0,
 502         [V3D_QPU_M_MOV] = D | A,
 503         [V3D_QPU_M_FMUL] = D | A | B,
 504 };
 505
 506 bool
 507 v3d_qpu_add_op_has_dst(enum v3d_qpu_add_op op)
 508 {
 509         assert(op < ARRAY_SIZE(add_op_args));
 510
 511         return add_op_args[op] & D;
 512 }
 513
 514 bool
 515 v3d_qpu_mul_op_has_dst(enum v3d_qpu_mul_op op)
 516 {
 517         assert(op < ARRAY_SIZE(mul_op_args));
 518
 519         return mul_op_args[op] & D;
 520 }
 521
 522 int
 523 v3d_qpu_add_op_num_src(enum v3d_qpu_add_op op)
 524 {
 525         assert(op < ARRAY_SIZE(add_op_args));
 526
 527         uint8_t args = add_op_args[op];
 528         if (args & B)
 529                 return 2;
 530         else if (args & A)
 531                 return 1;
 532         else
 533                 return 0;
 534 }
 535
 536 int
 537 v3d_qpu_mul_op_num_src(enum v3d_qpu_mul_op op)
 538 {
 539         assert(op < ARRAY_SIZE(mul_op_args));
 540
 541         uint8_t args = mul_op_args[op];
 542         if (args & B)
 543                 return 2;
 544         else if (args & A)
 545                 return 1;
 546         else
 547                 return 0;
 548 }
 549
 550 bool
 551 v3d_qpu_magic_waddr_is_sfu(enum v3d_qpu_waddr waddr)
 552 {
 553         switch (waddr) {
 554         case V3D_QPU_WADDR_RECIP:
 555         case V3D_QPU_WADDR_RSQRT:
 556         case V3D_QPU_WADDR_EXP:
 557         case V3D_QPU_WADDR_LOG:
 558         case V3D_QPU_WADDR_SIN:
 559         case V3D_QPU_WADDR_RSQRT2:
 560                 return true;
 561         default:
 562                 return false;
 563         }
 564 }
 565
 566 bool
 567 v3d_qpu_magic_waddr_is_tmu(enum v3d_qpu_waddr waddr)
 568 {
 569         switch (waddr) {
 570         case V3D_QPU_WADDR_TMU:
 571         case V3D_QPU_WADDR_TMUL:
 572         case V3D_QPU_WADDR_TMUD:
 573         case V3D_QPU_WADDR_TMUA:
 574         case V3D_QPU_WADDR_TMUAU:
 575                 return true;
 576         default:
 577                 return false;
 578         }
 579 }
 580
 581 bool
 582 v3d_qpu_magic_waddr_is_tlb(enum v3d_qpu_waddr waddr)
 583 {
 584         return (waddr == V3D_QPU_WADDR_TLB ||
 585                 waddr == V3D_QPU_WADDR_TLBU);
 586 }
 587
 588 bool
 589 v3d_qpu_magic_waddr_is_vpm(enum v3d_qpu_waddr waddr)
 590 {
 591         return (waddr == V3D_QPU_WADDR_VPM ||
 592                 waddr == V3D_QPU_WADDR_VPMU);
 593 }
 594
 595 bool
 596 v3d_qpu_magic_waddr_is_tsy(enum v3d_qpu_waddr waddr)
 597 {
 598         return (waddr == V3D_QPU_WADDR_SYNC ||
 599                 waddr == V3D_QPU_WADDR_SYNCU);
 600 }
 601
 602 bool
 603 v3d_qpu_writes_r3(const struct v3d_qpu_instr *inst)
 604 {
 605         return inst->sig.ldvary || inst->sig.ldvpm;
 606 }
 607
 608 bool
 609 v3d_qpu_writes_r4(const struct v3d_qpu_instr *inst)
 610 {
 611         if (inst->sig.ldtmu)
 612                 return true;
 613
 614         if (inst->type == V3D_QPU_INSTR_TYPE_ALU) {
 615                 if (inst->alu.add.magic_write &&
 616                     v3d_qpu_magic_waddr_is_sfu(inst->alu.add.waddr)) {
 617                         return true;
 618                 }
 619
 620                 if (inst->alu.mul.magic_write &&
 621                     v3d_qpu_magic_waddr_is_sfu(inst->alu.mul.waddr)) {
 622                         return true;
 623                 }
 624         }
 625
 626         return false;
 627 }
 628
 629 bool
 630 v3d_qpu_writes_r5(const struct v3d_qpu_instr *inst)
 631 {
 632         return inst->sig.ldvary || inst->sig.ldunif;
 633 }
 634
 635 bool
 636 v3d_qpu_uses_mux(const struct v3d_qpu_instr *inst, enum v3d_qpu_mux mux)
 637 {
 638         int add_nsrc = v3d_qpu_add_op_num_src(inst->alu.add.op);
 639         int mul_nsrc = v3d_qpu_mul_op_num_src(inst->alu.mul.op);
 640
 641         return ((add_nsrc > 0 && inst->alu.add.a == mux) ||
 642                 (add_nsrc > 1 && inst->alu.add.b == mux) ||
 643                 (mul_nsrc > 0 && inst->alu.mul.a == mux) ||
 644                 (mul_nsrc > 1 && inst->alu.mul.b == mux));
 645 }