src/broadcom/qpu/qpu_instr.c

   1 /*
   2  * Copyright © 2016 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <stdlib.h>
  25 #include "util/macros.h"
  26 #include "broadcom/common/v3d_device_info.h"
  27 #include "qpu_instr.h"
  28
  29 const char *
  30 v3d_qpu_magic_waddr_name(enum v3d_qpu_waddr waddr)
  31 {
  32         static const char *waddr_magic[] = {
  33                 [V3D_QPU_WADDR_R0] = "r0",
  34                 [V3D_QPU_WADDR_R1] = "r1",
  35                 [V3D_QPU_WADDR_R2] = "r2",
  36                 [V3D_QPU_WADDR_R3] = "r3",
  37                 [V3D_QPU_WADDR_R4] = "r4",
  38                 [V3D_QPU_WADDR_R5] = "r5",
  39                 [V3D_QPU_WADDR_NOP] = "-",
  40                 [V3D_QPU_WADDR_TLB] = "tlb",
  41                 [V3D_QPU_WADDR_TLBU] = "tlbu",
  42                 [V3D_QPU_WADDR_TMU] = "tmu",
  43                 [V3D_QPU_WADDR_TMUL] = "tmul",
  44                 [V3D_QPU_WADDR_TMUD] = "tmud",
  45                 [V3D_QPU_WADDR_TMUA] = "tmua",
  46                 [V3D_QPU_WADDR_TMUAU] = "tmuau",
  47                 [V3D_QPU_WADDR_VPM] = "vpm",
  48                 [V3D_QPU_WADDR_VPMU] = "vpmu",
  49                 [V3D_QPU_WADDR_SYNC] = "sync",
  50                 [V3D_QPU_WADDR_SYNCU] = "syncu",
  51                 [V3D_QPU_WADDR_RECIP] = "recip",
  52                 [V3D_QPU_WADDR_RSQRT] = "rsqrt",
  53                 [V3D_QPU_WADDR_EXP] = "exp",
  54                 [V3D_QPU_WADDR_LOG] = "log",
  55                 [V3D_QPU_WADDR_SIN] = "sin",
  56                 [V3D_QPU_WADDR_RSQRT2] = "rsqrt2",
  57         };
  58
  59         return waddr_magic[waddr];
  60 }
  61
  62 const char *
  63 v3d_qpu_add_op_name(enum v3d_qpu_add_op op)
  64 {
  65         static const char *op_names[] = {
  66                 [V3D_QPU_A_FADD] = "fadd",
  67                 [V3D_QPU_A_FADDNF] = "faddnf",
  68                 [V3D_QPU_A_VFPACK] = "vfpack",
  69                 [V3D_QPU_A_ADD] = "add",
  70                 [V3D_QPU_A_SUB] = "sub",
  71                 [V3D_QPU_A_FSUB] = "fsub",
  72                 [V3D_QPU_A_MIN] = "min",
  73                 [V3D_QPU_A_MAX] = "max",
  74                 [V3D_QPU_A_UMIN] = "umin",
  75                 [V3D_QPU_A_UMAX] = "umax",
  76                 [V3D_QPU_A_SHL] = "shl",
  77                 [V3D_QPU_A_SHR] = "shr",
  78                 [V3D_QPU_A_ASR] = "asr",
  79                 [V3D_QPU_A_ROR] = "ror",
  80                 [V3D_QPU_A_FMIN] = "fmin",
  81                 [V3D_QPU_A_FMAX] = "fmax",
  82                 [V3D_QPU_A_VFMIN] = "vfmin",
  83                 [V3D_QPU_A_AND] = "and",
  84                 [V3D_QPU_A_OR] = "or",
  85                 [V3D_QPU_A_XOR] = "xor",
  86                 [V3D_QPU_A_VADD] = "vadd",
  87                 [V3D_QPU_A_VSUB] = "vsub",
  88                 [V3D_QPU_A_NOT] = "not",
  89                 [V3D_QPU_A_NEG] = "neg",
  90                 [V3D_QPU_A_FLAPUSH] = "flapush",
  91                 [V3D_QPU_A_FLBPUSH] = "flbpush",
  92                 [V3D_QPU_A_FLBPOP] = "flbpop",
  93                 [V3D_QPU_A_SETMSF] = "setmsf",
  94                 [V3D_QPU_A_SETREVF] = "setrevf",
  95                 [V3D_QPU_A_NOP] = "nop",
  96                 [V3D_QPU_A_TIDX] = "tidx",
  97                 [V3D_QPU_A_EIDX] = "eidx",
  98                 [V3D_QPU_A_LR] = "lr",
  99                 [V3D_QPU_A_VFLA] = "vfla",
 100                 [V3D_QPU_A_VFLNA] = "vflna",
 101                 [V3D_QPU_A_VFLB] = "vflb",
 102                 [V3D_QPU_A_VFLNB] = "vflnb",
 103                 [V3D_QPU_A_FXCD] = "fxcd",
 104                 [V3D_QPU_A_XCD] = "xcd",
 105                 [V3D_QPU_A_FYCD] = "fycd",
 106                 [V3D_QPU_A_YCD] = "ycd",
 107                 [V3D_QPU_A_MSF] = "msf",
 108                 [V3D_QPU_A_REVF] = "revf",
 109                 [V3D_QPU_A_VDWWT] = "vdwwt",
 110                 [V3D_QPU_A_IID] = "iid",
 111                 [V3D_QPU_A_SAMPID] = "sampid",
 112                 [V3D_QPU_A_PATCHID] = "patchid",
 113                 [V3D_QPU_A_TMUWT] = "tmuwt",
 114                 [V3D_QPU_A_VPMSETUP] = "vpmsetup",
 115                 [V3D_QPU_A_VPMWT] = "vpmwt",
 116                 [V3D_QPU_A_LDVPMV] = "ldvpmv",
 117                 [V3D_QPU_A_LDVPMD] = "ldvpmd",
 118                 [V3D_QPU_A_LDVPMP] = "ldvpmp",
 119                 [V3D_QPU_A_LDVPMG] = "ldvpmg",
 120                 [V3D_QPU_A_FCMP] = "fcmp",
 121                 [V3D_QPU_A_VFMAX] = "vfmax",
 122                 [V3D_QPU_A_FROUND] = "fround",
 123                 [V3D_QPU_A_FTOIN] = "ftoin",
 124                 [V3D_QPU_A_FTRUNC] = "ftrunc",
 125                 [V3D_QPU_A_FTOIZ] = "ftoiz",
 126                 [V3D_QPU_A_FFLOOR] = "ffloor",
 127                 [V3D_QPU_A_FTOUZ] = "ftouz",
 128                 [V3D_QPU_A_FCEIL] = "fceil",
 129                 [V3D_QPU_A_FTOC] = "ftoc",
 130                 [V3D_QPU_A_FDX] = "fdx",
 131                 [V3D_QPU_A_FDY] = "fdy",
 132                 [V3D_QPU_A_STVPMV] = "stvpmv",
 133                 [V3D_QPU_A_STVPMD] = "stvpmd",
 134                 [V3D_QPU_A_STVPMP] = "stvpmp",
 135                 [V3D_QPU_A_ITOF] = "itof",
 136                 [V3D_QPU_A_CLZ] = "clz",
 137                 [V3D_QPU_A_UTOF] = "utof",
 138         };
 139
 140         if (op >= ARRAY_SIZE(op_names))
 141                 return NULL;
 142
 143         return op_names[op];
 144 }
 145
 146 const char *
 147 v3d_qpu_mul_op_name(enum v3d_qpu_mul_op op)
 148 {
 149         static const char *op_names[] = {
 150                 [V3D_QPU_M_ADD] = "add",
 151                 [V3D_QPU_M_SUB] = "sub",
 152                 [V3D_QPU_M_UMUL24] = "umul24",
 153                 [V3D_QPU_M_VFMUL] = "vfmul",
 154                 [V3D_QPU_M_SMUL24] = "smul24",
 155                 [V3D_QPU_M_MULTOP] = "multop",
 156                 [V3D_QPU_M_FMOV] = "fmov",
 157                 [V3D_QPU_M_MOV] = "mov",
 158                 [V3D_QPU_M_NOP] = "nop",
 159                 [V3D_QPU_M_FMUL] = "fmul",
 160         };
 161
 162         if (op >= ARRAY_SIZE(op_names))
 163                 return NULL;
 164
 165         return op_names[op];
 166 }
 167
 168 const char *
 169 v3d_qpu_cond_name(enum v3d_qpu_cond cond)
 170 {
 171         switch (cond) {
 172         case V3D_QPU_COND_NONE:
 173                 return "";
 174         case V3D_QPU_COND_IFA:
 175                 return ".ifa";
 176         case V3D_QPU_COND_IFB:
 177                 return ".ifb";
 178         case V3D_QPU_COND_IFNA:
 179                 return ".ifna";
 180         case V3D_QPU_COND_IFNB:
 181                 return ".ifnb";
 182         default:
 183                 unreachable("bad cond value");
 184         }
 185 }
 186
 187 const char *
 188 v3d_qpu_branch_cond_name(enum v3d_qpu_branch_cond cond)
 189 {
 190         switch (cond) {
 191         case V3D_QPU_BRANCH_COND_ALWAYS:
 192                 return "";
 193         case V3D_QPU_BRANCH_COND_A0:
 194                 return ".a0";
 195         case V3D_QPU_BRANCH_COND_NA0:
 196                 return ".na0";
 197         case V3D_QPU_BRANCH_COND_ALLA:
 198                 return ".alla";
 199         case V3D_QPU_BRANCH_COND_ANYNA:
 200                 return ".anyna";
 201         case V3D_QPU_BRANCH_COND_ANYA:
 202                 return ".anya";
 203         case V3D_QPU_BRANCH_COND_ALLNA:
 204                 return ".allna";
 205         default:
 206                 unreachable("bad branch cond value");
 207         }
 208 }
 209
 210 const char *
 211 v3d_qpu_msfign_name(enum v3d_qpu_msfign msfign)
 212 {
 213         switch (msfign) {
 214         case V3D_QPU_MSFIGN_NONE:
 215                 return "";
 216         case V3D_QPU_MSFIGN_P:
 217                 return "p";
 218         case V3D_QPU_MSFIGN_Q:
 219                 return "q";
 220         default:
 221                 unreachable("bad branch cond value");
 222         }
 223 }
 224
 225 const char *
 226 v3d_qpu_pf_name(enum v3d_qpu_pf pf)
 227 {
 228         switch (pf) {
 229         case V3D_QPU_PF_NONE:
 230                 return "";
 231         case V3D_QPU_PF_PUSHZ:
 232                 return ".pushz";
 233         case V3D_QPU_PF_PUSHN:
 234                 return ".pushn";
 235         case V3D_QPU_PF_PUSHC:
 236                 return ".pushc";
 237         default:
 238                 unreachable("bad pf value");
 239         }
 240 }
 241
 242 const char *
 243 v3d_qpu_uf_name(enum v3d_qpu_uf uf)
 244 {
 245         switch (uf) {
 246         case V3D_QPU_UF_NONE:
 247                 return "";
 248         case V3D_QPU_UF_ANDZ:
 249                 return ".andz";
 250         case V3D_QPU_UF_ANDNZ:
 251                 return ".andnz";
 252         case V3D_QPU_UF_NORZ:
 253                 return ".norz";
 254         case V3D_QPU_UF_NORNZ:
 255                 return ".nornz";
 256         case V3D_QPU_UF_ANDN:
 257                 return ".andn";
 258         case V3D_QPU_UF_ANDNN:
 259                 return ".andnn";
 260         case V3D_QPU_UF_NORN:
 261                 return ".norn";
 262         case V3D_QPU_UF_NORNN:
 263                 return ".nornn";
 264         case V3D_QPU_UF_ANDC:
 265                 return ".andc";
 266         case V3D_QPU_UF_ANDNC:
 267                 return ".andnc";
 268         case V3D_QPU_UF_NORC:
 269                 return ".norc";
 270         case V3D_QPU_UF_NORNC:
 271                 return ".nornc";
 272         default:
 273                 unreachable("bad pf value");
 274         }
 275 }
 276
 277 const char *
 278 v3d_qpu_pack_name(enum v3d_qpu_output_pack pack)
 279 {
 280         switch (pack) {
 281         case V3D_QPU_PACK_NONE:
 282                 return "";
 283         case V3D_QPU_PACK_L:
 284                 return ".l";
 285         case V3D_QPU_PACK_H:
 286                 return ".h";
 287         default:
 288                 unreachable("bad pack value");
 289         }
 290 }
 291
 292 const char *
 293 v3d_qpu_unpack_name(enum v3d_qpu_input_unpack unpack)
 294 {
 295         switch (unpack) {
 296         case V3D_QPU_UNPACK_NONE:
 297                 return "";
 298         case V3D_QPU_UNPACK_L:
 299                 return ".l";
 300         case V3D_QPU_UNPACK_H:
 301                 return ".h";
 302         case V3D_QPU_UNPACK_ABS:
 303                 return ".abs";
 304         case V3D_QPU_UNPACK_REPLICATE_32F_16:
 305                 return ".ff";
 306         case V3D_QPU_UNPACK_REPLICATE_L_16:
 307                 return ".ll";
 308         case V3D_QPU_UNPACK_REPLICATE_H_16:
 309                 return ".hh";
 310         case V3D_QPU_UNPACK_SWAP_16:
 311                 return ".swp";
 312         default:
 313                 unreachable("bad unpack value");
 314         }
 315 }
 316
 317 #define D       1
 318 #define A       2
 319 #define B       4
 320 static const uint8_t add_op_args[] = {
 321         [V3D_QPU_A_FADD] = D | A | B,
 322         [V3D_QPU_A_FADDNF] = D | A | B,
 323         [V3D_QPU_A_VFPACK] = D | A | B,
 324         [V3D_QPU_A_ADD] = D | A | B,
 325         [V3D_QPU_A_VFPACK] = D | A | B,
 326         [V3D_QPU_A_SUB] = D | A | B,
 327         [V3D_QPU_A_VFPACK] = D | A | B,
 328         [V3D_QPU_A_FSUB] = D | A | B,
 329         [V3D_QPU_A_MIN] = D | A | B,
 330         [V3D_QPU_A_MAX] = D | A | B,
 331         [V3D_QPU_A_UMIN] = D | A | B,
 332         [V3D_QPU_A_UMAX] = D | A | B,
 333         [V3D_QPU_A_SHL] = D | A | B,
 334         [V3D_QPU_A_SHR] = D | A | B,
 335         [V3D_QPU_A_ASR] = D | A | B,
 336         [V3D_QPU_A_ROR] = D | A | B,
 337         [V3D_QPU_A_FMIN] = D | A | B,
 338         [V3D_QPU_A_FMAX] = D | A | B,
 339         [V3D_QPU_A_VFMIN] = D | A | B,
 340
 341         [V3D_QPU_A_AND] = D | A | B,
 342         [V3D_QPU_A_OR] = D | A | B,
 343         [V3D_QPU_A_XOR] = D | A | B,
 344
 345         [V3D_QPU_A_VADD] = D | A | B,
 346         [V3D_QPU_A_VSUB] = D | A | B,
 347         [V3D_QPU_A_NOT] = D | A,
 348         [V3D_QPU_A_NEG] = D | A,
 349         [V3D_QPU_A_FLAPUSH] = D | A,
 350         [V3D_QPU_A_FLBPUSH] = D | A,
 351         [V3D_QPU_A_FLBPOP] = D | A,
 352         [V3D_QPU_A_SETMSF] = D | A,
 353         [V3D_QPU_A_SETREVF] = D | A,
 354         [V3D_QPU_A_NOP] = 0,
 355         [V3D_QPU_A_TIDX] = D,
 356         [V3D_QPU_A_EIDX] = D,
 357         [V3D_QPU_A_LR] = D,
 358         [V3D_QPU_A_VFLA] = D,
 359         [V3D_QPU_A_VFLNA] = D,
 360         [V3D_QPU_A_VFLB] = D,
 361         [V3D_QPU_A_VFLNB] = D,
 362
 363         [V3D_QPU_A_FXCD] = D,
 364         [V3D_QPU_A_XCD] = D,
 365         [V3D_QPU_A_FYCD] = D,
 366         [V3D_QPU_A_YCD] = D,
 367
 368         [V3D_QPU_A_MSF] = D,
 369         [V3D_QPU_A_REVF] = D,
 370         [V3D_QPU_A_VDWWT] = D,
 371         [V3D_QPU_A_IID] = D,
 372         [V3D_QPU_A_SAMPID] = D,
 373         [V3D_QPU_A_PATCHID] = D,
 374         [V3D_QPU_A_TMUWT] = D,
 375         [V3D_QPU_A_VPMWT] = D,
 376
 377         [V3D_QPU_A_VPMSETUP] = D | A,
 378
 379         [V3D_QPU_A_LDVPMV] = D | A,
 380         [V3D_QPU_A_LDVPMD] = D | A,
 381         [V3D_QPU_A_LDVPMP] = D | A,
 382         [V3D_QPU_A_LDVPMG] = D | A | B,
 383
 384         /* FIXME: MOVABSNEG */
 385
 386         [V3D_QPU_A_FCMP] = D | A | B,
 387         [V3D_QPU_A_VFMAX] = D | A | B,
 388
 389         [V3D_QPU_A_FROUND] = D | A,
 390         [V3D_QPU_A_FTOIN] = D | A,
 391         [V3D_QPU_A_FTRUNC] = D | A,
 392         [V3D_QPU_A_FTOIZ] = D | A,
 393         [V3D_QPU_A_FFLOOR] = D | A,
 394         [V3D_QPU_A_FTOUZ] = D | A,
 395         [V3D_QPU_A_FCEIL] = D | A,
 396         [V3D_QPU_A_FTOC] = D | A,
 397
 398         [V3D_QPU_A_FDX] = D | A,
 399         [V3D_QPU_A_FDY] = D | A,
 400
 401         [V3D_QPU_A_STVPMV] = A | B,
 402         [V3D_QPU_A_STVPMD] = A | B,
 403         [V3D_QPU_A_STVPMP] = A | B,
 404
 405         [V3D_QPU_A_ITOF] = D | A,
 406         [V3D_QPU_A_CLZ] = D | A,
 407         [V3D_QPU_A_UTOF] = D | A,
 408 };
 409
 410 static const uint8_t mul_op_args[] = {
 411         [V3D_QPU_M_ADD] = D | A | B,
 412         [V3D_QPU_M_SUB] = D | A | B,
 413         [V3D_QPU_M_UMUL24] = D | A | B,
 414         [V3D_QPU_M_VFMUL] = D | A | B,
 415         [V3D_QPU_M_SMUL24] = D | A | B,
 416         [V3D_QPU_M_MULTOP] = D | A | B,
 417         [V3D_QPU_M_FMOV] = D | A,
 418         [V3D_QPU_M_NOP] = 0,
 419         [V3D_QPU_M_MOV] = D | A,
 420         [V3D_QPU_M_FMUL] = D | A | B,
 421 };
 422
 423 bool
 424 v3d_qpu_add_op_has_dst(enum v3d_qpu_add_op op)
 425 {
 426         assert(op < ARRAY_SIZE(add_op_args));
 427
 428         return add_op_args[op] & D;
 429 }
 430
 431 bool
 432 v3d_qpu_mul_op_has_dst(enum v3d_qpu_mul_op op)
 433 {
 434         assert(op < ARRAY_SIZE(mul_op_args));
 435
 436         return mul_op_args[op] & D;
 437 }
 438
 439 int
 440 v3d_qpu_add_op_num_src(enum v3d_qpu_add_op op)
 441 {
 442         assert(op < ARRAY_SIZE(add_op_args));
 443
 444         uint8_t args = add_op_args[op];
 445         if (args & B)
 446                 return 2;
 447         else if (args & A)
 448                 return 1;
 449         else
 450                 return 0;
 451 }
 452
 453 int
 454 v3d_qpu_mul_op_num_src(enum v3d_qpu_mul_op op)
 455 {
 456         assert(op < ARRAY_SIZE(mul_op_args));
 457
 458         uint8_t args = mul_op_args[op];
 459         if (args & B)
 460                 return 2;
 461         else if (args & A)
 462                 return 1;
 463         else
 464                 return 0;
 465 }
 466
 467 bool
 468 v3d_qpu_magic_waddr_is_sfu(enum v3d_qpu_waddr waddr)
 469 {
 470         switch (waddr) {
 471         case V3D_QPU_WADDR_RECIP:
 472         case V3D_QPU_WADDR_RSQRT:
 473         case V3D_QPU_WADDR_EXP:
 474         case V3D_QPU_WADDR_LOG:
 475         case V3D_QPU_WADDR_SIN:
 476         case V3D_QPU_WADDR_RSQRT2:
 477                 return true;
 478         default:
 479                 return false;
 480         }
 481 }
 482
 483 bool
 484 v3d_qpu_magic_waddr_is_tmu(enum v3d_qpu_waddr waddr)
 485 {
 486         switch (waddr) {
 487         case V3D_QPU_WADDR_TMU:
 488         case V3D_QPU_WADDR_TMUL:
 489         case V3D_QPU_WADDR_TMUD:
 490         case V3D_QPU_WADDR_TMUA:
 491         case V3D_QPU_WADDR_TMUAU:
 492                 return true;
 493         default:
 494                 return false;
 495         }
 496 }
 497
 498 bool
 499 v3d_qpu_magic_waddr_is_tlb(enum v3d_qpu_waddr waddr)
 500 {
 501         return (waddr == V3D_QPU_WADDR_TLB ||
 502                 waddr == V3D_QPU_WADDR_TLBU);
 503 }
 504
 505 bool
 506 v3d_qpu_magic_waddr_is_vpm(enum v3d_qpu_waddr waddr)
 507 {
 508         return (waddr == V3D_QPU_WADDR_VPM ||
 509                 waddr == V3D_QPU_WADDR_VPMU);
 510 }
 511
 512 bool
 513 v3d_qpu_magic_waddr_is_tsy(enum v3d_qpu_waddr waddr)
 514 {
 515         return (waddr == V3D_QPU_WADDR_SYNC ||
 516                 waddr == V3D_QPU_WADDR_SYNCU);
 517 }
 518
 519 bool
 520 v3d_qpu_writes_r3(const struct v3d_device_info *devinfo,
 521                   const struct v3d_qpu_instr *inst)
 522 {
 523         if (inst->type == V3D_QPU_INSTR_TYPE_ALU) {
 524                 if (inst->alu.add.magic_write &&
 525                     inst->alu.add.waddr == V3D_QPU_WADDR_R3) {
 526                         return true;
 527                 }
 528
 529                 if (inst->alu.mul.magic_write &&
 530                     inst->alu.mul.waddr == V3D_QPU_WADDR_R3) {
 531                         return true;
 532                 }
 533         }
 534
 535         if (v3d_qpu_sig_writes_address(devinfo, &inst->sig) &&
 536             inst->sig_magic && inst->sig_addr == V3D_QPU_WADDR_R3) {
 537                 return true;
 538         }
 539
 540         return inst->sig.ldvary || inst->sig.ldvpm;
 541 }
 542
 543 bool
 544 v3d_qpu_writes_r4(const struct v3d_device_info *devinfo,
 545                   const struct v3d_qpu_instr *inst)
 546 {
 547         if (inst->sig.ldtmu)
 548                 return true;
 549
 550         if (inst->type == V3D_QPU_INSTR_TYPE_ALU) {
 551                 if (inst->alu.add.magic_write &&
 552                     (inst->alu.add.waddr == V3D_QPU_WADDR_R4 ||
 553                      v3d_qpu_magic_waddr_is_sfu(inst->alu.add.waddr))) {
 554                         return true;
 555                 }
 556
 557                 if (inst->alu.mul.magic_write &&
 558                     (inst->alu.mul.waddr == V3D_QPU_WADDR_R4 ||
 559                      v3d_qpu_magic_waddr_is_sfu(inst->alu.mul.waddr))) {
 560                         return true;
 561                 }
 562         }
 563
 564         if (v3d_qpu_sig_writes_address(devinfo, &inst->sig) &&
 565             inst->sig_magic && inst->sig_addr == V3D_QPU_WADDR_R4) {
 566                 return true;
 567         }
 568
 569         return false;
 570 }
 571
 572 bool
 573 v3d_qpu_writes_r5(const struct v3d_device_info *devinfo,
 574                   const struct v3d_qpu_instr *inst)
 575 {
 576         if (inst->type == V3D_QPU_INSTR_TYPE_ALU) {
 577                 if (inst->alu.add.magic_write &&
 578                     inst->alu.add.waddr == V3D_QPU_WADDR_R5) {
 579                         return true;
 580                 }
 581
 582                 if (inst->alu.mul.magic_write &&
 583                     inst->alu.mul.waddr == V3D_QPU_WADDR_R5) {
 584                         return true;
 585                 }
 586         }
 587
 588         if (v3d_qpu_sig_writes_address(devinfo, &inst->sig) &&
 589             inst->sig_magic && inst->sig_addr == V3D_QPU_WADDR_R5) {
 590                 return true;
 591         }
 592
 593         return inst->sig.ldvary || inst->sig.ldunif || inst->sig.ldunifa;
 594 }
 595
 596 bool
 597 v3d_qpu_uses_mux(const struct v3d_qpu_instr *inst, enum v3d_qpu_mux mux)
 598 {
 599         int add_nsrc = v3d_qpu_add_op_num_src(inst->alu.add.op);
 600         int mul_nsrc = v3d_qpu_mul_op_num_src(inst->alu.mul.op);
 601
 602         return ((add_nsrc > 0 && inst->alu.add.a == mux) ||
 603                 (add_nsrc > 1 && inst->alu.add.b == mux) ||
 604                 (mul_nsrc > 0 && inst->alu.mul.a == mux) ||
 605                 (mul_nsrc > 1 && inst->alu.mul.b == mux));
 606 }
 607
 608 bool
 609 v3d_qpu_sig_writes_address(const struct v3d_device_info *devinfo,
 610                            const struct v3d_qpu_sig *sig)
 611 {
 612         if (devinfo->ver < 41)
 613                 return false;
 614
 615         return (sig->ldunifrf ||
 616                 sig->ldunifarf ||
 617                 sig->ldvary ||
 618                 sig->ldtmu ||
 619                 sig->ldtlb ||
 620                 sig->ldtlbu);
 621 }