2 * Copyright © 2016 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "util/macros.h"
26 #include "broadcom/common/v3d_device_info.h"
27 #include "qpu_instr.h"
30 v3d_qpu_magic_waddr_name(enum v3d_qpu_waddr waddr
)
32 static const char *waddr_magic
[] = {
33 [V3D_QPU_WADDR_R0
] = "r0",
34 [V3D_QPU_WADDR_R1
] = "r1",
35 [V3D_QPU_WADDR_R2
] = "r2",
36 [V3D_QPU_WADDR_R3
] = "r3",
37 [V3D_QPU_WADDR_R4
] = "r4",
38 [V3D_QPU_WADDR_R5
] = "r5",
39 [V3D_QPU_WADDR_NOP
] = "-",
40 [V3D_QPU_WADDR_TLB
] = "tlb",
41 [V3D_QPU_WADDR_TLBU
] = "tlbu",
42 [V3D_QPU_WADDR_TMU
] = "tmu",
43 [V3D_QPU_WADDR_TMUL
] = "tmul",
44 [V3D_QPU_WADDR_TMUD
] = "tmud",
45 [V3D_QPU_WADDR_TMUA
] = "tmua",
46 [V3D_QPU_WADDR_TMUAU
] = "tmuau",
47 [V3D_QPU_WADDR_VPM
] = "vpm",
48 [V3D_QPU_WADDR_VPMU
] = "vpmu",
49 [V3D_QPU_WADDR_SYNC
] = "sync",
50 [V3D_QPU_WADDR_SYNCU
] = "syncu",
51 [V3D_QPU_WADDR_SYNCB
] = "syncb",
52 [V3D_QPU_WADDR_RECIP
] = "recip",
53 [V3D_QPU_WADDR_RSQRT
] = "rsqrt",
54 [V3D_QPU_WADDR_EXP
] = "exp",
55 [V3D_QPU_WADDR_LOG
] = "log",
56 [V3D_QPU_WADDR_SIN
] = "sin",
57 [V3D_QPU_WADDR_RSQRT2
] = "rsqrt2",
58 [V3D_QPU_WADDR_TMUC
] = "tmuc",
59 [V3D_QPU_WADDR_TMUS
] = "tmus",
60 [V3D_QPU_WADDR_TMUT
] = "tmut",
61 [V3D_QPU_WADDR_TMUR
] = "tmur",
62 [V3D_QPU_WADDR_TMUI
] = "tmui",
63 [V3D_QPU_WADDR_TMUB
] = "tmub",
64 [V3D_QPU_WADDR_TMUDREF
] = "tmudref",
65 [V3D_QPU_WADDR_TMUOFF
] = "tmuoff",
66 [V3D_QPU_WADDR_TMUSCM
] = "tmuscm",
67 [V3D_QPU_WADDR_TMUSF
] = "tmusf",
68 [V3D_QPU_WADDR_TMUSLOD
] = "tmuslod",
69 [V3D_QPU_WADDR_TMUHS
] = "tmuhs",
70 [V3D_QPU_WADDR_TMUHSCM
] = "tmuscm",
71 [V3D_QPU_WADDR_TMUHSF
] = "tmuhsf",
72 [V3D_QPU_WADDR_TMUHSLOD
] = "tmuhslod",
73 [V3D_QPU_WADDR_R5REP
] = "r5rep",
76 return waddr_magic
[waddr
];
80 v3d_qpu_add_op_name(enum v3d_qpu_add_op op
)
82 static const char *op_names
[] = {
83 [V3D_QPU_A_FADD
] = "fadd",
84 [V3D_QPU_A_FADDNF
] = "faddnf",
85 [V3D_QPU_A_VFPACK
] = "vfpack",
86 [V3D_QPU_A_ADD
] = "add",
87 [V3D_QPU_A_SUB
] = "sub",
88 [V3D_QPU_A_FSUB
] = "fsub",
89 [V3D_QPU_A_MIN
] = "min",
90 [V3D_QPU_A_MAX
] = "max",
91 [V3D_QPU_A_UMIN
] = "umin",
92 [V3D_QPU_A_UMAX
] = "umax",
93 [V3D_QPU_A_SHL
] = "shl",
94 [V3D_QPU_A_SHR
] = "shr",
95 [V3D_QPU_A_ASR
] = "asr",
96 [V3D_QPU_A_ROR
] = "ror",
97 [V3D_QPU_A_FMIN
] = "fmin",
98 [V3D_QPU_A_FMAX
] = "fmax",
99 [V3D_QPU_A_VFMIN
] = "vfmin",
100 [V3D_QPU_A_AND
] = "and",
101 [V3D_QPU_A_OR
] = "or",
102 [V3D_QPU_A_XOR
] = "xor",
103 [V3D_QPU_A_VADD
] = "vadd",
104 [V3D_QPU_A_VSUB
] = "vsub",
105 [V3D_QPU_A_NOT
] = "not",
106 [V3D_QPU_A_NEG
] = "neg",
107 [V3D_QPU_A_FLAPUSH
] = "flapush",
108 [V3D_QPU_A_FLBPUSH
] = "flbpush",
109 [V3D_QPU_A_FLPOP
] = "flpop",
110 [V3D_QPU_A_SETMSF
] = "setmsf",
111 [V3D_QPU_A_SETREVF
] = "setrevf",
112 [V3D_QPU_A_NOP
] = "nop",
113 [V3D_QPU_A_TIDX
] = "tidx",
114 [V3D_QPU_A_EIDX
] = "eidx",
115 [V3D_QPU_A_LR
] = "lr",
116 [V3D_QPU_A_VFLA
] = "vfla",
117 [V3D_QPU_A_VFLNA
] = "vflna",
118 [V3D_QPU_A_VFLB
] = "vflb",
119 [V3D_QPU_A_VFLNB
] = "vflnb",
120 [V3D_QPU_A_FXCD
] = "fxcd",
121 [V3D_QPU_A_XCD
] = "xcd",
122 [V3D_QPU_A_FYCD
] = "fycd",
123 [V3D_QPU_A_YCD
] = "ycd",
124 [V3D_QPU_A_MSF
] = "msf",
125 [V3D_QPU_A_REVF
] = "revf",
126 [V3D_QPU_A_VDWWT
] = "vdwwt",
127 [V3D_QPU_A_IID
] = "iid",
128 [V3D_QPU_A_SAMPID
] = "sampid",
129 [V3D_QPU_A_BARRIERID
] = "barrierid",
130 [V3D_QPU_A_TMUWT
] = "tmuwt",
131 [V3D_QPU_A_VPMSETUP
] = "vpmsetup",
132 [V3D_QPU_A_VPMWT
] = "vpmwt",
133 [V3D_QPU_A_LDVPMV_IN
] = "ldvpmv_in",
134 [V3D_QPU_A_LDVPMV_OUT
] = "ldvpmv_out",
135 [V3D_QPU_A_LDVPMD_IN
] = "ldvpmd_in",
136 [V3D_QPU_A_LDVPMD_OUT
] = "ldvpmd_out",
137 [V3D_QPU_A_LDVPMP
] = "ldvpmp",
138 [V3D_QPU_A_LDVPMG_IN
] = "ldvpmg_in",
139 [V3D_QPU_A_LDVPMG_OUT
] = "ldvpmg_out",
140 [V3D_QPU_A_FCMP
] = "fcmp",
141 [V3D_QPU_A_VFMAX
] = "vfmax",
142 [V3D_QPU_A_FROUND
] = "fround",
143 [V3D_QPU_A_FTOIN
] = "ftoin",
144 [V3D_QPU_A_FTRUNC
] = "ftrunc",
145 [V3D_QPU_A_FTOIZ
] = "ftoiz",
146 [V3D_QPU_A_FFLOOR
] = "ffloor",
147 [V3D_QPU_A_FTOUZ
] = "ftouz",
148 [V3D_QPU_A_FCEIL
] = "fceil",
149 [V3D_QPU_A_FTOC
] = "ftoc",
150 [V3D_QPU_A_FDX
] = "fdx",
151 [V3D_QPU_A_FDY
] = "fdy",
152 [V3D_QPU_A_STVPMV
] = "stvpmv",
153 [V3D_QPU_A_STVPMD
] = "stvpmd",
154 [V3D_QPU_A_STVPMP
] = "stvpmp",
155 [V3D_QPU_A_ITOF
] = "itof",
156 [V3D_QPU_A_CLZ
] = "clz",
157 [V3D_QPU_A_UTOF
] = "utof",
160 if (op
>= ARRAY_SIZE(op_names
))
167 v3d_qpu_mul_op_name(enum v3d_qpu_mul_op op
)
169 static const char *op_names
[] = {
170 [V3D_QPU_M_ADD
] = "add",
171 [V3D_QPU_M_SUB
] = "sub",
172 [V3D_QPU_M_UMUL24
] = "umul24",
173 [V3D_QPU_M_VFMUL
] = "vfmul",
174 [V3D_QPU_M_SMUL24
] = "smul24",
175 [V3D_QPU_M_MULTOP
] = "multop",
176 [V3D_QPU_M_FMOV
] = "fmov",
177 [V3D_QPU_M_MOV
] = "mov",
178 [V3D_QPU_M_NOP
] = "nop",
179 [V3D_QPU_M_FMUL
] = "fmul",
182 if (op
>= ARRAY_SIZE(op_names
))
189 v3d_qpu_cond_name(enum v3d_qpu_cond cond
)
192 case V3D_QPU_COND_NONE
:
194 case V3D_QPU_COND_IFA
:
196 case V3D_QPU_COND_IFB
:
198 case V3D_QPU_COND_IFNA
:
200 case V3D_QPU_COND_IFNB
:
203 unreachable("bad cond value");
208 v3d_qpu_branch_cond_name(enum v3d_qpu_branch_cond cond
)
211 case V3D_QPU_BRANCH_COND_ALWAYS
:
213 case V3D_QPU_BRANCH_COND_A0
:
215 case V3D_QPU_BRANCH_COND_NA0
:
217 case V3D_QPU_BRANCH_COND_ALLA
:
219 case V3D_QPU_BRANCH_COND_ANYNA
:
221 case V3D_QPU_BRANCH_COND_ANYA
:
223 case V3D_QPU_BRANCH_COND_ALLNA
:
226 unreachable("bad branch cond value");
231 v3d_qpu_msfign_name(enum v3d_qpu_msfign msfign
)
234 case V3D_QPU_MSFIGN_NONE
:
236 case V3D_QPU_MSFIGN_P
:
238 case V3D_QPU_MSFIGN_Q
:
241 unreachable("bad branch cond value");
246 v3d_qpu_pf_name(enum v3d_qpu_pf pf
)
249 case V3D_QPU_PF_NONE
:
251 case V3D_QPU_PF_PUSHZ
:
253 case V3D_QPU_PF_PUSHN
:
255 case V3D_QPU_PF_PUSHC
:
258 unreachable("bad pf value");
263 v3d_qpu_uf_name(enum v3d_qpu_uf uf
)
266 case V3D_QPU_UF_NONE
:
268 case V3D_QPU_UF_ANDZ
:
270 case V3D_QPU_UF_ANDNZ
:
272 case V3D_QPU_UF_NORZ
:
274 case V3D_QPU_UF_NORNZ
:
276 case V3D_QPU_UF_ANDN
:
278 case V3D_QPU_UF_ANDNN
:
280 case V3D_QPU_UF_NORN
:
282 case V3D_QPU_UF_NORNN
:
284 case V3D_QPU_UF_ANDC
:
286 case V3D_QPU_UF_ANDNC
:
288 case V3D_QPU_UF_NORC
:
290 case V3D_QPU_UF_NORNC
:
293 unreachable("bad pf value");
298 v3d_qpu_pack_name(enum v3d_qpu_output_pack pack
)
301 case V3D_QPU_PACK_NONE
:
308 unreachable("bad pack value");
313 v3d_qpu_unpack_name(enum v3d_qpu_input_unpack unpack
)
316 case V3D_QPU_UNPACK_NONE
:
318 case V3D_QPU_UNPACK_L
:
320 case V3D_QPU_UNPACK_H
:
322 case V3D_QPU_UNPACK_ABS
:
324 case V3D_QPU_UNPACK_REPLICATE_32F_16
:
326 case V3D_QPU_UNPACK_REPLICATE_L_16
:
328 case V3D_QPU_UNPACK_REPLICATE_H_16
:
330 case V3D_QPU_UNPACK_SWAP_16
:
333 unreachable("bad unpack value");
340 static const uint8_t add_op_args
[] = {
341 [V3D_QPU_A_FADD
] = D
| A
| B
,
342 [V3D_QPU_A_FADDNF
] = D
| A
| B
,
343 [V3D_QPU_A_VFPACK
] = D
| A
| B
,
344 [V3D_QPU_A_ADD
] = D
| A
| B
,
345 [V3D_QPU_A_VFPACK
] = D
| A
| B
,
346 [V3D_QPU_A_SUB
] = D
| A
| B
,
347 [V3D_QPU_A_VFPACK
] = D
| A
| B
,
348 [V3D_QPU_A_FSUB
] = D
| A
| B
,
349 [V3D_QPU_A_MIN
] = D
| A
| B
,
350 [V3D_QPU_A_MAX
] = D
| A
| B
,
351 [V3D_QPU_A_UMIN
] = D
| A
| B
,
352 [V3D_QPU_A_UMAX
] = D
| A
| B
,
353 [V3D_QPU_A_SHL
] = D
| A
| B
,
354 [V3D_QPU_A_SHR
] = D
| A
| B
,
355 [V3D_QPU_A_ASR
] = D
| A
| B
,
356 [V3D_QPU_A_ROR
] = D
| A
| B
,
357 [V3D_QPU_A_FMIN
] = D
| A
| B
,
358 [V3D_QPU_A_FMAX
] = D
| A
| B
,
359 [V3D_QPU_A_VFMIN
] = D
| A
| B
,
361 [V3D_QPU_A_AND
] = D
| A
| B
,
362 [V3D_QPU_A_OR
] = D
| A
| B
,
363 [V3D_QPU_A_XOR
] = D
| A
| B
,
365 [V3D_QPU_A_VADD
] = D
| A
| B
,
366 [V3D_QPU_A_VSUB
] = D
| A
| B
,
367 [V3D_QPU_A_NOT
] = D
| A
,
368 [V3D_QPU_A_NEG
] = D
| A
,
369 [V3D_QPU_A_FLAPUSH
] = D
| A
,
370 [V3D_QPU_A_FLBPUSH
] = D
| A
,
371 [V3D_QPU_A_FLPOP
] = D
| A
,
372 [V3D_QPU_A_SETMSF
] = D
| A
,
373 [V3D_QPU_A_SETREVF
] = D
| A
,
375 [V3D_QPU_A_TIDX
] = D
,
376 [V3D_QPU_A_EIDX
] = D
,
378 [V3D_QPU_A_VFLA
] = D
,
379 [V3D_QPU_A_VFLNA
] = D
,
380 [V3D_QPU_A_VFLB
] = D
,
381 [V3D_QPU_A_VFLNB
] = D
,
383 [V3D_QPU_A_FXCD
] = D
,
385 [V3D_QPU_A_FYCD
] = D
,
389 [V3D_QPU_A_REVF
] = D
,
390 [V3D_QPU_A_VDWWT
] = D
,
392 [V3D_QPU_A_SAMPID
] = D
,
393 [V3D_QPU_A_BARRIERID
] = D
,
394 [V3D_QPU_A_TMUWT
] = D
,
395 [V3D_QPU_A_VPMWT
] = D
,
397 [V3D_QPU_A_VPMSETUP
] = D
| A
,
399 [V3D_QPU_A_LDVPMV_IN
] = D
| A
,
400 [V3D_QPU_A_LDVPMV_OUT
] = D
| A
,
401 [V3D_QPU_A_LDVPMD_IN
] = D
| A
,
402 [V3D_QPU_A_LDVPMD_OUT
] = D
| A
,
403 [V3D_QPU_A_LDVPMP
] = D
| A
,
404 [V3D_QPU_A_LDVPMG_IN
] = D
| A
| B
,
405 [V3D_QPU_A_LDVPMG_OUT
] = D
| A
| B
,
407 /* FIXME: MOVABSNEG */
409 [V3D_QPU_A_FCMP
] = D
| A
| B
,
410 [V3D_QPU_A_VFMAX
] = D
| A
| B
,
412 [V3D_QPU_A_FROUND
] = D
| A
,
413 [V3D_QPU_A_FTOIN
] = D
| A
,
414 [V3D_QPU_A_FTRUNC
] = D
| A
,
415 [V3D_QPU_A_FTOIZ
] = D
| A
,
416 [V3D_QPU_A_FFLOOR
] = D
| A
,
417 [V3D_QPU_A_FTOUZ
] = D
| A
,
418 [V3D_QPU_A_FCEIL
] = D
| A
,
419 [V3D_QPU_A_FTOC
] = D
| A
,
421 [V3D_QPU_A_FDX
] = D
| A
,
422 [V3D_QPU_A_FDY
] = D
| A
,
424 [V3D_QPU_A_STVPMV
] = A
| B
,
425 [V3D_QPU_A_STVPMD
] = A
| B
,
426 [V3D_QPU_A_STVPMP
] = A
| B
,
428 [V3D_QPU_A_ITOF
] = D
| A
,
429 [V3D_QPU_A_CLZ
] = D
| A
,
430 [V3D_QPU_A_UTOF
] = D
| A
,
433 static const uint8_t mul_op_args
[] = {
434 [V3D_QPU_M_ADD
] = D
| A
| B
,
435 [V3D_QPU_M_SUB
] = D
| A
| B
,
436 [V3D_QPU_M_UMUL24
] = D
| A
| B
,
437 [V3D_QPU_M_VFMUL
] = D
| A
| B
,
438 [V3D_QPU_M_SMUL24
] = D
| A
| B
,
439 [V3D_QPU_M_MULTOP
] = D
| A
| B
,
440 [V3D_QPU_M_FMOV
] = D
| A
,
442 [V3D_QPU_M_MOV
] = D
| A
,
443 [V3D_QPU_M_FMUL
] = D
| A
| B
,
447 v3d_qpu_add_op_has_dst(enum v3d_qpu_add_op op
)
449 assert(op
< ARRAY_SIZE(add_op_args
));
451 return add_op_args
[op
] & D
;
455 v3d_qpu_mul_op_has_dst(enum v3d_qpu_mul_op op
)
457 assert(op
< ARRAY_SIZE(mul_op_args
));
459 return mul_op_args
[op
] & D
;
463 v3d_qpu_add_op_num_src(enum v3d_qpu_add_op op
)
465 assert(op
< ARRAY_SIZE(add_op_args
));
467 uint8_t args
= add_op_args
[op
];
477 v3d_qpu_mul_op_num_src(enum v3d_qpu_mul_op op
)
479 assert(op
< ARRAY_SIZE(mul_op_args
));
481 uint8_t args
= mul_op_args
[op
];
491 v3d_qpu_magic_waddr_is_sfu(enum v3d_qpu_waddr waddr
)
494 case V3D_QPU_WADDR_RECIP
:
495 case V3D_QPU_WADDR_RSQRT
:
496 case V3D_QPU_WADDR_EXP
:
497 case V3D_QPU_WADDR_LOG
:
498 case V3D_QPU_WADDR_SIN
:
499 case V3D_QPU_WADDR_RSQRT2
:
507 v3d_qpu_magic_waddr_is_tmu(enum v3d_qpu_waddr waddr
)
509 /* XXX: WADDR_TMU changed to UNIFA on 4.x */
510 return ((waddr
>= V3D_QPU_WADDR_TMU
&&
511 waddr
<= V3D_QPU_WADDR_TMUAU
) ||
512 (waddr
>= V3D_QPU_WADDR_TMUC
&&
513 waddr
<= V3D_QPU_WADDR_TMUHSLOD
));
517 v3d_qpu_magic_waddr_is_tlb(enum v3d_qpu_waddr waddr
)
519 return (waddr
== V3D_QPU_WADDR_TLB
||
520 waddr
== V3D_QPU_WADDR_TLBU
);
524 v3d_qpu_magic_waddr_is_vpm(enum v3d_qpu_waddr waddr
)
526 return (waddr
== V3D_QPU_WADDR_VPM
||
527 waddr
== V3D_QPU_WADDR_VPMU
);
531 v3d_qpu_magic_waddr_is_tsy(enum v3d_qpu_waddr waddr
)
533 return (waddr
== V3D_QPU_WADDR_SYNC
||
534 waddr
== V3D_QPU_WADDR_SYNCU
);
538 v3d_qpu_add_op_reads_vpm(enum v3d_qpu_add_op op
)
541 case V3D_QPU_A_VPMSETUP
:
542 case V3D_QPU_A_VPMWT
:
543 case V3D_QPU_A_LDVPMV_IN
:
544 case V3D_QPU_A_LDVPMV_OUT
:
545 case V3D_QPU_A_LDVPMD_IN
:
546 case V3D_QPU_A_LDVPMD_OUT
:
547 case V3D_QPU_A_LDVPMP
:
548 case V3D_QPU_A_LDVPMG_IN
:
549 case V3D_QPU_A_LDVPMG_OUT
:
557 v3d_qpu_add_op_writes_vpm(enum v3d_qpu_add_op op
)
560 case V3D_QPU_A_VPMSETUP
:
561 case V3D_QPU_A_VPMWT
:
562 case V3D_QPU_A_STVPMV
:
563 case V3D_QPU_A_STVPMD
:
564 case V3D_QPU_A_STVPMP
:
572 v3d_qpu_uses_tlb(const struct v3d_qpu_instr
*inst
)
574 if (inst
->sig
.ldtlb
||
578 if (inst
->type
== V3D_QPU_INSTR_TYPE_ALU
) {
579 if (inst
->alu
.add
.magic_write
&&
580 v3d_qpu_magic_waddr_is_tlb(inst
->alu
.add
.waddr
)) {
584 if (inst
->alu
.mul
.magic_write
&&
585 v3d_qpu_magic_waddr_is_tlb(inst
->alu
.mul
.waddr
)) {
594 v3d_qpu_writes_tmu(const struct v3d_qpu_instr
*inst
)
596 return (inst
->type
== V3D_QPU_INSTR_TYPE_ALU
&&
597 ((inst
->alu
.add
.magic_write
&&
598 v3d_qpu_magic_waddr_is_tmu(inst
->alu
.add
.waddr
)) ||
599 (inst
->alu
.mul
.magic_write
&&
600 v3d_qpu_magic_waddr_is_tmu(inst
->alu
.mul
.waddr
))));
604 v3d_qpu_reads_vpm(const struct v3d_qpu_instr
*inst
)
609 if (inst
->type
== V3D_QPU_INSTR_TYPE_ALU
) {
610 if (v3d_qpu_add_op_reads_vpm(inst
->alu
.add
.op
))
618 v3d_qpu_writes_vpm(const struct v3d_qpu_instr
*inst
)
620 if (inst
->type
== V3D_QPU_INSTR_TYPE_ALU
) {
621 if (v3d_qpu_add_op_writes_vpm(inst
->alu
.add
.op
))
624 if (inst
->alu
.add
.magic_write
&&
625 v3d_qpu_magic_waddr_is_vpm(inst
->alu
.add
.waddr
)) {
629 if (inst
->alu
.mul
.magic_write
&&
630 v3d_qpu_magic_waddr_is_vpm(inst
->alu
.mul
.waddr
)) {
639 v3d_qpu_uses_vpm(const struct v3d_qpu_instr
*inst
)
641 return v3d_qpu_reads_vpm(inst
) || v3d_qpu_writes_vpm(inst
);
645 v3d_qpu_writes_r3(const struct v3d_device_info
*devinfo
,
646 const struct v3d_qpu_instr
*inst
)
648 if (inst
->type
== V3D_QPU_INSTR_TYPE_ALU
) {
649 if (inst
->alu
.add
.magic_write
&&
650 inst
->alu
.add
.waddr
== V3D_QPU_WADDR_R3
) {
654 if (inst
->alu
.mul
.magic_write
&&
655 inst
->alu
.mul
.waddr
== V3D_QPU_WADDR_R3
) {
660 if (v3d_qpu_sig_writes_address(devinfo
, &inst
->sig
) &&
661 inst
->sig_magic
&& inst
->sig_addr
== V3D_QPU_WADDR_R3
) {
665 return inst
->sig
.ldvary
|| inst
->sig
.ldvpm
;
669 v3d_qpu_writes_r4(const struct v3d_device_info
*devinfo
,
670 const struct v3d_qpu_instr
*inst
)
675 if (inst
->type
== V3D_QPU_INSTR_TYPE_ALU
) {
676 if (inst
->alu
.add
.magic_write
&&
677 (inst
->alu
.add
.waddr
== V3D_QPU_WADDR_R4
||
678 v3d_qpu_magic_waddr_is_sfu(inst
->alu
.add
.waddr
))) {
682 if (inst
->alu
.mul
.magic_write
&&
683 (inst
->alu
.mul
.waddr
== V3D_QPU_WADDR_R4
||
684 v3d_qpu_magic_waddr_is_sfu(inst
->alu
.mul
.waddr
))) {
689 if (v3d_qpu_sig_writes_address(devinfo
, &inst
->sig
) &&
690 inst
->sig_magic
&& inst
->sig_addr
== V3D_QPU_WADDR_R4
) {
698 v3d_qpu_writes_r5(const struct v3d_device_info
*devinfo
,
699 const struct v3d_qpu_instr
*inst
)
701 if (inst
->type
== V3D_QPU_INSTR_TYPE_ALU
) {
702 if (inst
->alu
.add
.magic_write
&&
703 inst
->alu
.add
.waddr
== V3D_QPU_WADDR_R5
) {
707 if (inst
->alu
.mul
.magic_write
&&
708 inst
->alu
.mul
.waddr
== V3D_QPU_WADDR_R5
) {
713 if (v3d_qpu_sig_writes_address(devinfo
, &inst
->sig
) &&
714 inst
->sig_magic
&& inst
->sig_addr
== V3D_QPU_WADDR_R5
) {
718 return inst
->sig
.ldvary
|| inst
->sig
.ldunif
|| inst
->sig
.ldunifa
;
722 v3d_qpu_uses_mux(const struct v3d_qpu_instr
*inst
, enum v3d_qpu_mux mux
)
724 int add_nsrc
= v3d_qpu_add_op_num_src(inst
->alu
.add
.op
);
725 int mul_nsrc
= v3d_qpu_mul_op_num_src(inst
->alu
.mul
.op
);
727 return ((add_nsrc
> 0 && inst
->alu
.add
.a
== mux
) ||
728 (add_nsrc
> 1 && inst
->alu
.add
.b
== mux
) ||
729 (mul_nsrc
> 0 && inst
->alu
.mul
.a
== mux
) ||
730 (mul_nsrc
> 1 && inst
->alu
.mul
.b
== mux
));
734 v3d_qpu_sig_writes_address(const struct v3d_device_info
*devinfo
,
735 const struct v3d_qpu_sig
*sig
)
737 if (devinfo
->ver
< 41)
740 return (sig
->ldunifrf
||