src/broadcom/qpu/qpu_instr.h

   1 /*
   2  * Copyright © 2016 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * @file qpu_instr.h
  26  *
  27  * Definitions of the unpacked form of QPU instructions.  Assembly and
  28  * disassembly will use this for talking about instructions, with qpu_encode.c
  29  * and qpu_decode.c handling the pack and unpack of the actual 64-bit QPU
  30  * instruction.
  31  */
  32
  33 #ifndef QPU_INSTR_H
  34 #define QPU_INSTR_H
  35
  36 #include <stdbool.h>
  37 #include <stdint.h>
  38 #include "util/macros.h"
  39
  40 struct v3d_device_info;
  41
  42 struct v3d_qpu_sig {
  43         bool thrsw:1;
  44         bool ldunif:1;
  45         bool ldtmu:1;
  46         bool ldvary:1;
  47         bool ldvpm:1;
  48         bool ldtlb:1;
  49         bool ldtlbu:1;
  50         bool small_imm:1;
  51         bool ucb:1;
  52         bool rotate:1;
  53         bool wrtmuc:1;
  54 };
  55
  56 enum v3d_qpu_cond {
  57         V3D_QPU_COND_NONE,
  58         V3D_QPU_COND_IFA,
  59         V3D_QPU_COND_IFB,
  60         V3D_QPU_COND_IFNA,
  61         V3D_QPU_COND_IFNB,
  62 };
  63
  64 enum v3d_qpu_pf {
  65         V3D_QPU_PF_NONE,
  66         V3D_QPU_PF_PUSHZ,
  67         V3D_QPU_PF_PUSHN,
  68         V3D_QPU_PF_PUSHC,
  69 };
  70
  71 enum v3d_qpu_uf {
  72         V3D_QPU_UF_NONE,
  73         V3D_QPU_UF_ANDZ,
  74         V3D_QPU_UF_ANDNZ,
  75         V3D_QPU_UF_NORNZ,
  76         V3D_QPU_UF_NORZ,
  77         V3D_QPU_UF_ANDN,
  78         V3D_QPU_UF_ANDNN,
  79         V3D_QPU_UF_NORNN,
  80         V3D_QPU_UF_NORN,
  81         V3D_QPU_UF_ANDC,
  82         V3D_QPU_UF_ANDNC,
  83         V3D_QPU_UF_NORNC,
  84         V3D_QPU_UF_NORC,
  85 };
  86
  87 enum v3d_qpu_waddr {
  88         V3D_QPU_WADDR_R0 = 0,
  89         V3D_QPU_WADDR_R1 = 1,
  90         V3D_QPU_WADDR_R2 = 2,
  91         V3D_QPU_WADDR_R3 = 3,
  92         V3D_QPU_WADDR_R4 = 4,
  93         V3D_QPU_WADDR_R5 = 5,
  94         /* 6 is reserved, but note 3.2.2.8: "Result Writes" */
  95         V3D_QPU_WADDR_NOP = 6,
  96         V3D_QPU_WADDR_TLB = 7,
  97         V3D_QPU_WADDR_TLBU = 8,
  98         V3D_QPU_WADDR_TMU = 9,
  99         V3D_QPU_WADDR_TMUL = 10,
 100         V3D_QPU_WADDR_TMUD = 11,
 101         V3D_QPU_WADDR_TMUA = 12,
 102         V3D_QPU_WADDR_TMUAU = 13,
 103         V3D_QPU_WADDR_VPM = 14,
 104         V3D_QPU_WADDR_VPMU = 15,
 105         V3D_QPU_WADDR_SYNC = 16,
 106         V3D_QPU_WADDR_SYNCU = 17,
 107         /* reserved */
 108         V3D_QPU_WADDR_RECIP = 19,
 109         V3D_QPU_WADDR_RSQRT = 20,
 110         V3D_QPU_WADDR_EXP = 21,
 111         V3D_QPU_WADDR_LOG = 22,
 112         V3D_QPU_WADDR_SIN = 23,
 113         V3D_QPU_WADDR_RSQRT2 = 24,
 114 };
 115
 116 struct v3d_qpu_flags {
 117         enum v3d_qpu_cond ac, mc;
 118         enum v3d_qpu_pf apf, mpf;
 119         enum v3d_qpu_uf auf, muf;
 120 };
 121
 122 enum v3d_qpu_add_op {
 123         V3D_QPU_A_FADD,
 124         V3D_QPU_A_FADDNF,
 125         V3D_QPU_A_VFPACK,
 126         V3D_QPU_A_ADD,
 127         V3D_QPU_A_SUB,
 128         V3D_QPU_A_FSUB,
 129         V3D_QPU_A_MIN,
 130         V3D_QPU_A_MAX,
 131         V3D_QPU_A_UMIN,
 132         V3D_QPU_A_UMAX,
 133         V3D_QPU_A_SHL,
 134         V3D_QPU_A_SHR,
 135         V3D_QPU_A_ASR,
 136         V3D_QPU_A_ROR,
 137         V3D_QPU_A_FMIN,
 138         V3D_QPU_A_FMAX,
 139         V3D_QPU_A_VFMIN,
 140         V3D_QPU_A_AND,
 141         V3D_QPU_A_OR,
 142         V3D_QPU_A_XOR,
 143         V3D_QPU_A_VADD,
 144         V3D_QPU_A_VSUB,
 145         V3D_QPU_A_NOT,
 146         V3D_QPU_A_NEG,
 147         V3D_QPU_A_FLAPUSH,
 148         V3D_QPU_A_FLBPUSH,
 149         V3D_QPU_A_FLBPOP,
 150         V3D_QPU_A_SETMSF,
 151         V3D_QPU_A_SETREVF,
 152         V3D_QPU_A_NOP,
 153         V3D_QPU_A_TIDX,
 154         V3D_QPU_A_EIDX,
 155         V3D_QPU_A_LR,
 156         V3D_QPU_A_VFLA,
 157         V3D_QPU_A_VFLNA,
 158         V3D_QPU_A_VFLB,
 159         V3D_QPU_A_VFLNB,
 160         V3D_QPU_A_FXCD,
 161         V3D_QPU_A_XCD,
 162         V3D_QPU_A_FYCD,
 163         V3D_QPU_A_YCD,
 164         V3D_QPU_A_MSF,
 165         V3D_QPU_A_REVF,
 166         V3D_QPU_A_VDWWT,
 167         V3D_QPU_A_IID,
 168         V3D_QPU_A_SAMPID,
 169         V3D_QPU_A_PATCHID,
 170         V3D_QPU_A_TMUWT,
 171         V3D_QPU_A_VPMSETUP,
 172         V3D_QPU_A_VPMWT,
 173         V3D_QPU_A_LDVPMV,
 174         V3D_QPU_A_LDVPMD,
 175         V3D_QPU_A_LDVPMP,
 176         V3D_QPU_A_LDVPMG,
 177         V3D_QPU_A_FCMP,
 178         V3D_QPU_A_VFMAX,
 179         V3D_QPU_A_FROUND,
 180         V3D_QPU_A_FTOIN,
 181         V3D_QPU_A_FTRUNC,
 182         V3D_QPU_A_FTOIZ,
 183         V3D_QPU_A_FFLOOR,
 184         V3D_QPU_A_FTOUZ,
 185         V3D_QPU_A_FCEIL,
 186         V3D_QPU_A_FTOC,
 187         V3D_QPU_A_FDX,
 188         V3D_QPU_A_FDY,
 189         V3D_QPU_A_STVPMV,
 190         V3D_QPU_A_STVPMD,
 191         V3D_QPU_A_STVPMP,
 192         V3D_QPU_A_ITOF,
 193         V3D_QPU_A_CLZ,
 194         V3D_QPU_A_UTOF,
 195 };
 196
 197 enum v3d_qpu_mul_op {
 198         V3D_QPU_M_ADD,
 199         V3D_QPU_M_SUB,
 200         V3D_QPU_M_UMUL24,
 201         V3D_QPU_M_VFMUL,
 202         V3D_QPU_M_SMUL24,
 203         V3D_QPU_M_MULTOP,
 204         V3D_QPU_M_FMOV,
 205         V3D_QPU_M_MOV,
 206         V3D_QPU_M_NOP,
 207         V3D_QPU_M_FMUL,
 208 };
 209
 210 enum v3d_qpu_output_pack {
 211         V3D_QPU_PACK_NONE,
 212         /**
 213          * Convert to 16-bit float, put in low 16 bits of destination leaving
 214          * high unmodified.
 215          */
 216         V3D_QPU_PACK_L,
 217         /**
 218          * Convert to 16-bit float, put in high 16 bits of destination leaving
 219          * low unmodified.
 220          */
 221         V3D_QPU_PACK_H,
 222 };
 223
 224 enum v3d_qpu_input_unpack {
 225         /**
 226          * No-op input unpacking.  Note that this enum's value doesn't match
 227          * the packed QPU instruction value of the field (we use 0 so that the
 228          * default on new instruction creation is no-op).
 229          */
 230         V3D_QPU_UNPACK_NONE,
 231         /** Absolute value.  Only available for some operations. */
 232         V3D_QPU_UNPACK_ABS,
 233         /** Convert low 16 bits from 16-bit float to 32-bit float. */
 234         V3D_QPU_UNPACK_L,
 235         /** Convert high 16 bits from 16-bit float to 32-bit float. */
 236         V3D_QPU_UNPACK_H,
 237
 238         /** Convert to 16f and replicate it to the high bits. */
 239         V3D_QPU_UNPACK_REPLICATE_32F_16,
 240
 241         /** Replicate low 16 bits to high */
 242         V3D_QPU_UNPACK_REPLICATE_L_16,
 243
 244         /** Replicate high 16 bits to low */
 245         V3D_QPU_UNPACK_REPLICATE_H_16,
 246
 247         /** Swap high and low 16 bits */
 248         V3D_QPU_UNPACK_SWAP_16,
 249 };
 250
 251 enum v3d_qpu_mux {
 252         V3D_QPU_MUX_R0,
 253         V3D_QPU_MUX_R1,
 254         V3D_QPU_MUX_R2,
 255         V3D_QPU_MUX_R3,
 256         V3D_QPU_MUX_R4,
 257         V3D_QPU_MUX_R5,
 258         V3D_QPU_MUX_A,
 259         V3D_QPU_MUX_B,
 260 };
 261
 262 struct v3d_qpu_alu_instr {
 263         struct {
 264                 enum v3d_qpu_add_op op;
 265                 enum v3d_qpu_mux a, b;
 266                 uint8_t waddr;
 267                 bool magic_write;
 268                 enum v3d_qpu_output_pack output_pack;
 269                 enum v3d_qpu_input_unpack a_unpack;
 270                 enum v3d_qpu_input_unpack b_unpack;
 271         } add;
 272
 273         struct {
 274                 enum v3d_qpu_mul_op op;
 275                 enum v3d_qpu_mux a, b;
 276                 uint8_t waddr;
 277                 bool magic_write;
 278                 enum v3d_qpu_output_pack output_pack;
 279                 enum v3d_qpu_input_unpack a_unpack;
 280                 enum v3d_qpu_input_unpack b_unpack;
 281         } mul;
 282 };
 283
 284 enum v3d_qpu_branch_cond {
 285         V3D_QPU_BRANCH_COND_ALWAYS,
 286         V3D_QPU_BRANCH_COND_A0,
 287         V3D_QPU_BRANCH_COND_NA0,
 288         V3D_QPU_BRANCH_COND_ALLA,
 289         V3D_QPU_BRANCH_COND_ANYNA,
 290         V3D_QPU_BRANCH_COND_ANYA,
 291         V3D_QPU_BRANCH_COND_ALLNA,
 292 };
 293
 294 enum v3d_qpu_msfign {
 295         /** Ignore multisample flags when determining branch condition. */
 296         V3D_QPU_MSFIGN_NONE,
 297         /**
 298          * If no multisample flags are set in the lane (a pixel in the FS, a
 299          * vertex in the VS), ignore the lane's condition when computing the
 300          * branch condition.
 301          */
 302         V3D_QPU_MSFIGN_P,
 303         /**
 304          * If no multisample flags are set in a 2x2 quad in the FS, ignore the
 305          * quad's a/b conditions.
 306          */
 307         V3D_QPU_MSFIGN_Q,
 308 };
 309
 310 enum v3d_qpu_branch_dest {
 311         V3D_QPU_BRANCH_DEST_ABS,
 312         V3D_QPU_BRANCH_DEST_REL,
 313         V3D_QPU_BRANCH_DEST_LINK_REG,
 314         V3D_QPU_BRANCH_DEST_REGFILE,
 315 };
 316
 317 struct v3d_qpu_branch_instr {
 318         enum v3d_qpu_branch_cond cond;
 319         enum v3d_qpu_msfign msfign;
 320
 321         /** Selects how to compute the new IP if the branch is taken. */
 322         enum v3d_qpu_branch_dest bdi;
 323
 324         /**
 325          * Selects how to compute the new uniforms pointer if the branch is
 326          * taken.  (ABS/REL implicitly load a uniform and use that)
 327          */
 328         enum v3d_qpu_branch_dest bdu;
 329
 330         /**
 331          * If set, then udest determines how the uniform stream will branch,
 332          * otherwise the uniform stream is left as is.
 333          */
 334         bool ub;
 335
 336         uint8_t raddr_a;
 337
 338         uint32_t offset;
 339 };
 340
 341 enum v3d_qpu_instr_type {
 342         V3D_QPU_INSTR_TYPE_ALU,
 343         V3D_QPU_INSTR_TYPE_BRANCH,
 344 };
 345
 346 struct v3d_qpu_instr {
 347         enum v3d_qpu_instr_type type;
 348
 349         struct v3d_qpu_sig sig;
 350         uint8_t raddr_a;
 351         uint8_t raddr_b;
 352         struct v3d_qpu_flags flags;
 353
 354         union {
 355                 struct v3d_qpu_alu_instr alu;
 356                 struct v3d_qpu_branch_instr branch;
 357         };
 358 };
 359
 360 const char *v3d_qpu_magic_waddr_name(enum v3d_qpu_waddr waddr);
 361 const char *v3d_qpu_add_op_name(enum v3d_qpu_add_op op);
 362 const char *v3d_qpu_mul_op_name(enum v3d_qpu_mul_op op);
 363 const char *v3d_qpu_cond_name(enum v3d_qpu_cond cond);
 364 const char *v3d_qpu_pf_name(enum v3d_qpu_pf pf);
 365 const char *v3d_qpu_uf_name(enum v3d_qpu_uf uf);
 366 const char *v3d_qpu_pack_name(enum v3d_qpu_output_pack pack);
 367 const char *v3d_qpu_unpack_name(enum v3d_qpu_input_unpack unpack);
 368 const char *v3d_qpu_branch_cond_name(enum v3d_qpu_branch_cond cond);
 369 const char *v3d_qpu_msfign_name(enum v3d_qpu_msfign msfign);
 370
 371 bool v3d_qpu_add_op_has_dst(enum v3d_qpu_add_op op);
 372 bool v3d_qpu_mul_op_has_dst(enum v3d_qpu_mul_op op);
 373 int v3d_qpu_add_op_num_src(enum v3d_qpu_add_op op);
 374 int v3d_qpu_mul_op_num_src(enum v3d_qpu_mul_op op);
 375
 376 bool v3d_qpu_sig_pack(const struct v3d_device_info *devinfo,
 377                       const struct v3d_qpu_sig *sig,
 378                       uint32_t *packed_sig);
 379 bool v3d_qpu_sig_unpack(const struct v3d_device_info *devinfo,
 380                         uint32_t packed_sig,
 381                         struct v3d_qpu_sig *sig);
 382
 383 bool
 384 v3d_qpu_flags_pack(const struct v3d_device_info *devinfo,
 385                    const struct v3d_qpu_flags *cond,
 386                    uint32_t *packed_cond);
 387 bool
 388 v3d_qpu_flags_unpack(const struct v3d_device_info *devinfo,
 389                      uint32_t packed_cond,
 390                      struct v3d_qpu_flags *cond);
 391
 392 bool
 393 v3d_qpu_instr_pack(const struct v3d_device_info *devinfo,
 394                    const struct v3d_qpu_instr *instr,
 395                    uint64_t *packed_instr);
 396 bool
 397 v3d_qpu_instr_unpack(const struct v3d_device_info *devinfo,
 398                      uint64_t packed_instr,
 399                      struct v3d_qpu_instr *instr);
 400
 401 bool v3d_qpu_magic_waddr_is_sfu(enum v3d_qpu_waddr waddr) ATTRIBUTE_CONST;
 402 bool v3d_qpu_magic_waddr_is_tmu(enum v3d_qpu_waddr waddr) ATTRIBUTE_CONST;
 403 bool v3d_qpu_magic_waddr_is_tlb(enum v3d_qpu_waddr waddr) ATTRIBUTE_CONST;
 404 bool v3d_qpu_magic_waddr_is_vpm(enum v3d_qpu_waddr waddr) ATTRIBUTE_CONST;
 405 bool v3d_qpu_magic_waddr_is_tsy(enum v3d_qpu_waddr waddr) ATTRIBUTE_CONST;
 406 bool v3d_qpu_writes_r3(const struct v3d_qpu_instr *instr) ATTRIBUTE_CONST;
 407 bool v3d_qpu_writes_r4(const struct v3d_qpu_instr *instr) ATTRIBUTE_CONST;
 408 bool v3d_qpu_writes_r5(const struct v3d_qpu_instr *instr) ATTRIBUTE_CONST;
 409 bool v3d_qpu_uses_mux(const struct v3d_qpu_instr *inst, enum v3d_qpu_mux mux);
 410
 411 #endif