2 * Copyright © 2016 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "util/macros.h"
27 #include "broadcom/common/v3d_device_info.h"
28 #include "qpu_instr.h"
31 #define QPU_MASK(high, low) ((((uint64_t)1<<((high)-(low)+1))-1)<<(low))
32 /* Using the GNU statement expression extension */
33 #define QPU_SET_FIELD(value, field) \
35 uint64_t fieldval = (uint64_t)(value) << field ## _SHIFT; \
36 assert((fieldval & ~ field ## _MASK) == 0); \
37 fieldval & field ## _MASK; \
40 #define QPU_GET_FIELD(word, field) ((uint32_t)(((word) & field ## _MASK) >> field ## _SHIFT))
42 #define QPU_UPDATE_FIELD(inst, value, field) \
43 (((inst) & ~(field ## _MASK)) | QPU_SET_FIELD(value, field))
46 #define VC5_QPU_OP_MUL_SHIFT 58
47 #define VC5_QPU_OP_MUL_MASK QPU_MASK(63, 58)
49 #define VC5_QPU_SIG_SHIFT 53
50 #define VC5_QPU_SIG_MASK QPU_MASK(57, 53)
52 #define VC5_QPU_COND_SHIFT 46
53 #define VC5_QPU_COND_MASK QPU_MASK(52, 46)
54 #define VC5_QPU_COND_SIG_MAGIC_ADDR (1 << 6)
56 #define VC5_QPU_MM QPU_MASK(45, 45)
57 #define VC5_QPU_MA QPU_MASK(44, 44)
59 #define V3D_QPU_WADDR_M_SHIFT 38
60 #define V3D_QPU_WADDR_M_MASK QPU_MASK(43, 38)
62 #define VC5_QPU_BRANCH_ADDR_LOW_SHIFT 35
63 #define VC5_QPU_BRANCH_ADDR_LOW_MASK QPU_MASK(55, 35)
65 #define V3D_QPU_WADDR_A_SHIFT 32
66 #define V3D_QPU_WADDR_A_MASK QPU_MASK(37, 32)
68 #define VC5_QPU_BRANCH_COND_SHIFT 32
69 #define VC5_QPU_BRANCH_COND_MASK QPU_MASK(34, 32)
71 #define VC5_QPU_BRANCH_ADDR_HIGH_SHIFT 24
72 #define VC5_QPU_BRANCH_ADDR_HIGH_MASK QPU_MASK(31, 24)
74 #define VC5_QPU_OP_ADD_SHIFT 24
75 #define VC5_QPU_OP_ADD_MASK QPU_MASK(31, 24)
77 #define VC5_QPU_MUL_B_SHIFT 21
78 #define VC5_QPU_MUL_B_MASK QPU_MASK(23, 21)
80 #define VC5_QPU_BRANCH_MSFIGN_SHIFT 21
81 #define VC5_QPU_BRANCH_MSFIGN_MASK QPU_MASK(22, 21)
83 #define VC5_QPU_MUL_A_SHIFT 18
84 #define VC5_QPU_MUL_A_MASK QPU_MASK(20, 18)
86 #define VC5_QPU_ADD_B_SHIFT 15
87 #define VC5_QPU_ADD_B_MASK QPU_MASK(17, 15)
89 #define VC5_QPU_BRANCH_BDU_SHIFT 15
90 #define VC5_QPU_BRANCH_BDU_MASK QPU_MASK(17, 15)
92 #define VC5_QPU_BRANCH_UB QPU_MASK(14, 14)
94 #define VC5_QPU_ADD_A_SHIFT 12
95 #define VC5_QPU_ADD_A_MASK QPU_MASK(14, 12)
97 #define VC5_QPU_BRANCH_BDI_SHIFT 12
98 #define VC5_QPU_BRANCH_BDI_MASK QPU_MASK(13, 12)
100 #define VC5_QPU_RADDR_A_SHIFT 6
101 #define VC5_QPU_RADDR_A_MASK QPU_MASK(11, 6)
103 #define VC5_QPU_RADDR_B_SHIFT 0
104 #define VC5_QPU_RADDR_B_MASK QPU_MASK(5, 0)
106 #define THRSW .thrsw = true
107 #define LDUNIF .ldunif = true
108 #define LDUNIFRF .ldunifrf = true
109 #define LDUNIFA .ldunifa = true
110 #define LDUNIFARF .ldunifarf = true
111 #define LDTMU .ldtmu = true
112 #define LDVARY .ldvary = true
113 #define LDVPM .ldvpm = true
114 #define SMIMM .small_imm = true
115 #define LDTLB .ldtlb = true
116 #define LDTLBU .ldtlbu = true
117 #define UCB .ucb = true
118 #define ROT .rotate = true
119 #define WRTMUC .wrtmuc = true
121 static const struct v3d_qpu_sig v33_sig_map
[] = {
126 [3] = { THRSW
, LDUNIF
},
128 [5] = { THRSW
, LDTMU
, },
129 [6] = { LDTMU
, LDUNIF
},
130 [7] = { THRSW
, LDTMU
, LDUNIF
},
132 [9] = { THRSW
, LDVARY
, },
133 [10] = { LDVARY
, LDUNIF
},
134 [11] = { THRSW
, LDVARY
, LDUNIF
},
135 [12] = { LDVARY
, LDTMU
, },
136 [13] = { THRSW
, LDVARY
, LDTMU
, },
137 [14] = { SMIMM
, LDVARY
, },
145 [25] = { THRSW
, LDVPM
, },
146 [26] = { LDVPM
, LDUNIF
},
147 [27] = { THRSW
, LDVPM
, LDUNIF
},
148 [28] = { LDVPM
, LDTMU
, },
149 [29] = { THRSW
, LDVPM
, LDTMU
, },
150 [30] = { SMIMM
, LDVPM
, },
154 static const struct v3d_qpu_sig v40_sig_map
[] = {
159 [3] = { THRSW
, LDUNIF
},
161 [5] = { THRSW
, LDTMU
, },
162 [6] = { LDTMU
, LDUNIF
},
163 [7] = { THRSW
, LDTMU
, LDUNIF
},
165 [9] = { THRSW
, LDVARY
, },
166 [10] = { LDVARY
, LDUNIF
},
167 [11] = { THRSW
, LDVARY
, LDUNIF
},
169 [14] = { SMIMM
, LDVARY
, },
174 [19] = { THRSW
, WRTMUC
},
175 [20] = { LDVARY
, WRTMUC
},
176 [21] = { THRSW
, LDVARY
, WRTMUC
},
180 [31] = { SMIMM
, LDTMU
, },
183 static const struct v3d_qpu_sig v41_sig_map
[] = {
188 [3] = { THRSW
, LDUNIF
},
190 [5] = { THRSW
, LDTMU
, },
191 [6] = { LDTMU
, LDUNIF
},
192 [7] = { THRSW
, LDTMU
, LDUNIF
},
194 [9] = { THRSW
, LDVARY
, },
195 [10] = { LDVARY
, LDUNIF
},
196 [11] = { THRSW
, LDVARY
, LDUNIF
},
198 [13] = { THRSW
, LDUNIFRF
},
199 [14] = { SMIMM
, LDVARY
, },
204 [19] = { THRSW
, WRTMUC
},
205 [20] = { LDVARY
, WRTMUC
},
206 [21] = { THRSW
, LDVARY
, WRTMUC
},
211 [25] = { LDUNIFARF
},
212 [31] = { SMIMM
, LDTMU
, },
216 v3d_qpu_sig_unpack(const struct v3d_device_info
*devinfo
,
218 struct v3d_qpu_sig
*sig
)
220 if (packed_sig
>= ARRAY_SIZE(v33_sig_map
))
223 if (devinfo
->ver
>= 41)
224 *sig
= v41_sig_map
[packed_sig
];
225 else if (devinfo
->ver
== 40)
226 *sig
= v40_sig_map
[packed_sig
];
228 *sig
= v33_sig_map
[packed_sig
];
230 /* Signals with zeroed unpacked contents after element 0 are reserved. */
231 return (packed_sig
== 0 ||
232 memcmp(sig
, &v33_sig_map
[0], sizeof(*sig
)) != 0);
236 v3d_qpu_sig_pack(const struct v3d_device_info
*devinfo
,
237 const struct v3d_qpu_sig
*sig
,
238 uint32_t *packed_sig
)
240 static const struct v3d_qpu_sig
*map
;
242 if (devinfo
->ver
>= 41)
244 else if (devinfo
->ver
== 40)
249 for (int i
= 0; i
< ARRAY_SIZE(v33_sig_map
); i
++) {
250 if (memcmp(&map
[i
], sig
, sizeof(*sig
)) == 0) {
258 static inline unsigned
261 union {float f
; unsigned ui
;} fi
;
266 static const uint32_t small_immediates
[] = {
275 0x3b800000, /* 2.0^-8 */
276 0x3c000000, /* 2.0^-7 */
277 0x3c800000, /* 2.0^-6 */
278 0x3d000000, /* 2.0^-5 */
279 0x3d800000, /* 2.0^-4 */
280 0x3e000000, /* 2.0^-3 */
281 0x3e800000, /* 2.0^-2 */
282 0x3f000000, /* 2.0^-1 */
283 0x3f800000, /* 2.0^0 */
284 0x40000000, /* 2.0^1 */
285 0x40800000, /* 2.0^2 */
286 0x41000000, /* 2.0^3 */
287 0x41800000, /* 2.0^4 */
288 0x42000000, /* 2.0^5 */
289 0x42800000, /* 2.0^6 */
290 0x43000000, /* 2.0^7 */
294 v3d_qpu_small_imm_unpack(const struct v3d_device_info
*devinfo
,
295 uint32_t packed_small_immediate
,
296 uint32_t *small_immediate
)
298 if (packed_small_immediate
>= ARRAY_SIZE(small_immediates
))
301 *small_immediate
= small_immediates
[packed_small_immediate
];
306 v3d_qpu_small_imm_pack(const struct v3d_device_info
*devinfo
,
308 uint32_t *packed_small_immediate
)
310 STATIC_ASSERT(ARRAY_SIZE(small_immediates
) == 48);
312 for (int i
= 0; i
< ARRAY_SIZE(small_immediates
); i
++) {
313 if (small_immediates
[i
] == value
) {
314 *packed_small_immediate
= i
;
323 v3d_qpu_flags_unpack(const struct v3d_device_info
*devinfo
,
324 uint32_t packed_cond
,
325 struct v3d_qpu_flags
*cond
)
327 static const enum v3d_qpu_cond cond_map
[4] = {
328 [0] = V3D_QPU_COND_IFA
,
329 [1] = V3D_QPU_COND_IFB
,
330 [2] = V3D_QPU_COND_IFNA
,
331 [3] = V3D_QPU_COND_IFNB
,
334 cond
->ac
= V3D_QPU_COND_NONE
;
335 cond
->mc
= V3D_QPU_COND_NONE
;
336 cond
->apf
= V3D_QPU_PF_NONE
;
337 cond
->mpf
= V3D_QPU_PF_NONE
;
338 cond
->auf
= V3D_QPU_UF_NONE
;
339 cond
->muf
= V3D_QPU_UF_NONE
;
341 if (packed_cond
== 0) {
343 } else if (packed_cond
>> 2 == 0) {
344 cond
->apf
= packed_cond
& 0x3;
345 } else if (packed_cond
>> 4 == 0) {
346 cond
->auf
= (packed_cond
& 0xf) - 4 + V3D_QPU_UF_ANDZ
;
347 } else if (packed_cond
== 0x10) {
349 } else if (packed_cond
>> 2 == 0x4) {
350 cond
->mpf
= packed_cond
& 0x3;
351 } else if (packed_cond
>> 4 == 0x1) {
352 cond
->muf
= (packed_cond
& 0xf) - 4 + V3D_QPU_UF_ANDZ
;
353 } else if (packed_cond
>> 4 == 0x2) {
354 cond
->ac
= ((packed_cond
>> 2) & 0x3) + V3D_QPU_COND_IFA
;
355 cond
->mpf
= packed_cond
& 0x3;
356 } else if (packed_cond
>> 4 == 0x3) {
357 cond
->mc
= ((packed_cond
>> 2) & 0x3) + V3D_QPU_COND_IFA
;
358 cond
->apf
= packed_cond
& 0x3;
359 } else if (packed_cond
>> 6) {
360 cond
->mc
= cond_map
[(packed_cond
>> 4) & 0x3];
361 if (((packed_cond
>> 2) & 0x3) == 0) {
362 cond
->ac
= cond_map
[packed_cond
& 0x3];
364 cond
->auf
= (packed_cond
& 0xf) - 4 + V3D_QPU_UF_ANDZ
;
372 v3d_qpu_flags_pack(const struct v3d_device_info
*devinfo
,
373 const struct v3d_qpu_flags
*cond
,
374 uint32_t *packed_cond
)
382 static const struct {
383 uint8_t flags_present
;
392 { AC
| MPF
, (1 << 5) },
393 { MC
, (1 << 5) | (1 << 4) },
394 { MC
| APF
, (1 << 5) | (1 << 4) },
395 { MC
| AC
, (1 << 6) },
396 { MC
| AUF
, (1 << 6) },
399 uint8_t flags_present
= 0;
400 if (cond
->ac
!= V3D_QPU_COND_NONE
)
402 if (cond
->mc
!= V3D_QPU_COND_NONE
)
404 if (cond
->apf
!= V3D_QPU_PF_NONE
)
405 flags_present
|= APF
;
406 if (cond
->mpf
!= V3D_QPU_PF_NONE
)
407 flags_present
|= MPF
;
408 if (cond
->auf
!= V3D_QPU_UF_NONE
)
409 flags_present
|= AUF
;
410 if (cond
->muf
!= V3D_QPU_UF_NONE
)
411 flags_present
|= MUF
;
413 for (int i
= 0; i
< ARRAY_SIZE(flags_table
); i
++) {
414 if (flags_table
[i
].flags_present
!= flags_present
)
417 *packed_cond
= flags_table
[i
].bits
;
419 *packed_cond
|= cond
->apf
;
420 *packed_cond
|= cond
->mpf
;
422 if (flags_present
& AUF
)
423 *packed_cond
|= cond
->auf
- V3D_QPU_UF_ANDZ
+ 4;
424 if (flags_present
& MUF
)
425 *packed_cond
|= cond
->muf
- V3D_QPU_UF_ANDZ
+ 4;
427 if (flags_present
& AC
)
428 *packed_cond
|= (cond
->ac
- V3D_QPU_COND_IFA
) << 2;
430 if (flags_present
& MC
) {
431 if (*packed_cond
& (1 << 6))
432 *packed_cond
|= (cond
->mc
-
433 V3D_QPU_COND_IFA
) << 4;
435 *packed_cond
|= (cond
->mc
-
436 V3D_QPU_COND_IFA
) << 2;
445 /* Make a mapping of the table of opcodes in the spec. The opcode is
446 * determined by a combination of the opcode field, and in the case of 0 or
447 * 1-arg opcodes, the mux_b field as well.
449 #define MUX_MASK(bot, top) (((1 << (top + 1)) - 1) - ((1 << (bot)) - 1))
450 #define ANYMUX MUX_MASK(0, 7)
453 uint8_t opcode_first
;
458 /* 0 if it's the same across V3D versions, or a specific V3D version. */
462 static const struct opcode_desc add_ops
[] = {
463 /* FADD is FADDNF depending on the order of the mux_a/mux_b. */
464 { 0, 47, ANYMUX
, ANYMUX
, V3D_QPU_A_FADD
},
465 { 0, 47, ANYMUX
, ANYMUX
, V3D_QPU_A_FADDNF
},
466 { 53, 55, ANYMUX
, ANYMUX
, V3D_QPU_A_VFPACK
},
467 { 56, 56, ANYMUX
, ANYMUX
, V3D_QPU_A_ADD
},
468 { 57, 59, ANYMUX
, ANYMUX
, V3D_QPU_A_VFPACK
},
469 { 60, 60, ANYMUX
, ANYMUX
, V3D_QPU_A_SUB
},
470 { 61, 63, ANYMUX
, ANYMUX
, V3D_QPU_A_VFPACK
},
471 { 64, 111, ANYMUX
, ANYMUX
, V3D_QPU_A_FSUB
},
472 { 120, 120, ANYMUX
, ANYMUX
, V3D_QPU_A_MIN
},
473 { 121, 121, ANYMUX
, ANYMUX
, V3D_QPU_A_MAX
},
474 { 122, 122, ANYMUX
, ANYMUX
, V3D_QPU_A_UMIN
},
475 { 123, 123, ANYMUX
, ANYMUX
, V3D_QPU_A_UMAX
},
476 { 124, 124, ANYMUX
, ANYMUX
, V3D_QPU_A_SHL
},
477 { 125, 125, ANYMUX
, ANYMUX
, V3D_QPU_A_SHR
},
478 { 126, 126, ANYMUX
, ANYMUX
, V3D_QPU_A_ASR
},
479 { 127, 127, ANYMUX
, ANYMUX
, V3D_QPU_A_ROR
},
480 /* FMIN is instead FMAX depending on the order of the mux_a/mux_b. */
481 { 128, 175, ANYMUX
, ANYMUX
, V3D_QPU_A_FMIN
},
482 { 128, 175, ANYMUX
, ANYMUX
, V3D_QPU_A_FMAX
},
483 { 176, 180, ANYMUX
, ANYMUX
, V3D_QPU_A_VFMIN
},
485 { 181, 181, ANYMUX
, ANYMUX
, V3D_QPU_A_AND
},
486 { 182, 182, ANYMUX
, ANYMUX
, V3D_QPU_A_OR
},
487 { 183, 183, ANYMUX
, ANYMUX
, V3D_QPU_A_XOR
},
489 { 184, 184, ANYMUX
, ANYMUX
, V3D_QPU_A_VADD
},
490 { 185, 185, ANYMUX
, ANYMUX
, V3D_QPU_A_VSUB
},
491 { 186, 186, 1 << 0, ANYMUX
, V3D_QPU_A_NOT
},
492 { 186, 186, 1 << 1, ANYMUX
, V3D_QPU_A_NEG
},
493 { 186, 186, 1 << 2, ANYMUX
, V3D_QPU_A_FLAPUSH
},
494 { 186, 186, 1 << 3, ANYMUX
, V3D_QPU_A_FLBPUSH
},
495 { 186, 186, 1 << 4, ANYMUX
, V3D_QPU_A_FLPOP
},
496 { 186, 186, 1 << 5, ANYMUX
, V3D_QPU_A_RECIP
},
497 { 186, 186, 1 << 6, ANYMUX
, V3D_QPU_A_SETMSF
},
498 { 186, 186, 1 << 7, ANYMUX
, V3D_QPU_A_SETREVF
},
499 { 187, 187, 1 << 0, 1 << 0, V3D_QPU_A_NOP
, 0 },
500 { 187, 187, 1 << 0, 1 << 1, V3D_QPU_A_TIDX
},
501 { 187, 187, 1 << 0, 1 << 2, V3D_QPU_A_EIDX
},
502 { 187, 187, 1 << 0, 1 << 3, V3D_QPU_A_LR
},
503 { 187, 187, 1 << 0, 1 << 4, V3D_QPU_A_VFLA
},
504 { 187, 187, 1 << 0, 1 << 5, V3D_QPU_A_VFLNA
},
505 { 187, 187, 1 << 0, 1 << 6, V3D_QPU_A_VFLB
},
506 { 187, 187, 1 << 0, 1 << 7, V3D_QPU_A_VFLNB
},
508 { 187, 187, 1 << 1, MUX_MASK(0, 2), V3D_QPU_A_FXCD
},
509 { 187, 187, 1 << 1, 1 << 3, V3D_QPU_A_XCD
},
510 { 187, 187, 1 << 1, MUX_MASK(4, 6), V3D_QPU_A_FYCD
},
511 { 187, 187, 1 << 1, 1 << 7, V3D_QPU_A_YCD
},
513 { 187, 187, 1 << 2, 1 << 0, V3D_QPU_A_MSF
},
514 { 187, 187, 1 << 2, 1 << 1, V3D_QPU_A_REVF
},
515 { 187, 187, 1 << 2, 1 << 2, V3D_QPU_A_VDWWT
, 33 },
516 { 187, 187, 1 << 2, 1 << 2, V3D_QPU_A_IID
, 40 },
517 { 187, 187, 1 << 2, 1 << 3, V3D_QPU_A_SAMPID
, 40 },
518 { 187, 187, 1 << 2, 1 << 4, V3D_QPU_A_BARRIERID
, 40 },
519 { 187, 187, 1 << 2, 1 << 5, V3D_QPU_A_TMUWT
},
520 { 187, 187, 1 << 2, 1 << 6, V3D_QPU_A_VPMWT
},
522 { 187, 187, 1 << 3, ANYMUX
, V3D_QPU_A_VPMSETUP
, 33 },
523 { 188, 188, 1 << 0, ANYMUX
, V3D_QPU_A_LDVPMV_IN
, 40 },
524 { 188, 188, 1 << 1, ANYMUX
, V3D_QPU_A_LDVPMD_IN
, 40 },
525 { 188, 188, 1 << 2, ANYMUX
, V3D_QPU_A_LDVPMP
, 40 },
526 { 188, 188, 1 << 3, ANYMUX
, V3D_QPU_A_RSQRT
, 41 },
527 { 188, 188, 1 << 4, ANYMUX
, V3D_QPU_A_EXP
, 41 },
528 { 188, 188, 1 << 5, ANYMUX
, V3D_QPU_A_LOG
, 41 },
529 { 188, 188, 1 << 6, ANYMUX
, V3D_QPU_A_SIN
, 41 },
530 { 188, 188, 1 << 7, ANYMUX
, V3D_QPU_A_RSQRT2
, 41 },
531 { 189, 189, ANYMUX
, ANYMUX
, V3D_QPU_A_LDVPMG_IN
, 40 },
533 /* FIXME: MORE COMPLICATED */
534 /* { 190, 191, ANYMUX, ANYMUX, V3D_QPU_A_VFMOVABSNEGNAB }, */
536 { 192, 239, ANYMUX
, ANYMUX
, V3D_QPU_A_FCMP
},
537 { 240, 244, ANYMUX
, ANYMUX
, V3D_QPU_A_VFMAX
},
539 { 245, 245, MUX_MASK(0, 2), ANYMUX
, V3D_QPU_A_FROUND
},
540 { 245, 245, 1 << 3, ANYMUX
, V3D_QPU_A_FTOIN
},
541 { 245, 245, MUX_MASK(4, 6), ANYMUX
, V3D_QPU_A_FTRUNC
},
542 { 245, 245, 1 << 7, ANYMUX
, V3D_QPU_A_FTOIZ
},
543 { 246, 246, MUX_MASK(0, 2), ANYMUX
, V3D_QPU_A_FFLOOR
},
544 { 246, 246, 1 << 3, ANYMUX
, V3D_QPU_A_FTOUZ
},
545 { 246, 246, MUX_MASK(4, 6), ANYMUX
, V3D_QPU_A_FCEIL
},
546 { 246, 246, 1 << 7, ANYMUX
, V3D_QPU_A_FTOC
},
548 { 247, 247, MUX_MASK(0, 2), ANYMUX
, V3D_QPU_A_FDX
},
549 { 247, 247, MUX_MASK(4, 6), ANYMUX
, V3D_QPU_A_FDY
},
551 /* The stvpms are distinguished by the waddr field. */
552 { 248, 248, ANYMUX
, ANYMUX
, V3D_QPU_A_STVPMV
},
553 { 248, 248, ANYMUX
, ANYMUX
, V3D_QPU_A_STVPMD
},
554 { 248, 248, ANYMUX
, ANYMUX
, V3D_QPU_A_STVPMP
},
556 { 252, 252, MUX_MASK(0, 2), ANYMUX
, V3D_QPU_A_ITOF
},
557 { 252, 252, 1 << 3, ANYMUX
, V3D_QPU_A_CLZ
},
558 { 252, 252, MUX_MASK(4, 6), ANYMUX
, V3D_QPU_A_UTOF
},
561 static const struct opcode_desc mul_ops
[] = {
562 { 1, 1, ANYMUX
, ANYMUX
, V3D_QPU_M_ADD
},
563 { 2, 2, ANYMUX
, ANYMUX
, V3D_QPU_M_SUB
},
564 { 3, 3, ANYMUX
, ANYMUX
, V3D_QPU_M_UMUL24
},
565 { 4, 8, ANYMUX
, ANYMUX
, V3D_QPU_M_VFMUL
},
566 { 9, 9, ANYMUX
, ANYMUX
, V3D_QPU_M_SMUL24
},
567 { 10, 10, ANYMUX
, ANYMUX
, V3D_QPU_M_MULTOP
},
568 { 14, 14, ANYMUX
, ANYMUX
, V3D_QPU_M_FMOV
},
569 { 15, 15, MUX_MASK(0, 3), ANYMUX
, V3D_QPU_M_FMOV
},
570 { 15, 15, 1 << 4, 1 << 0, V3D_QPU_M_NOP
, 0 },
571 { 15, 15, 1 << 7, ANYMUX
, V3D_QPU_M_MOV
},
572 { 16, 63, ANYMUX
, ANYMUX
, V3D_QPU_M_FMUL
},
575 static const struct opcode_desc
*
576 lookup_opcode(const struct opcode_desc
*opcodes
, size_t num_opcodes
,
577 uint32_t opcode
, uint32_t mux_a
, uint32_t mux_b
)
579 for (int i
= 0; i
< num_opcodes
; i
++) {
580 const struct opcode_desc
*op_desc
= &opcodes
[i
];
582 if (opcode
< op_desc
->opcode_first
||
583 opcode
> op_desc
->opcode_last
)
586 if (!(op_desc
->mux_b_mask
& (1 << mux_b
)))
589 if (!(op_desc
->mux_a_mask
& (1 << mux_a
)))
599 v3d_qpu_float32_unpack_unpack(uint32_t packed
,
600 enum v3d_qpu_input_unpack
*unpacked
)
604 *unpacked
= V3D_QPU_UNPACK_ABS
;
607 *unpacked
= V3D_QPU_UNPACK_NONE
;
610 *unpacked
= V3D_QPU_UNPACK_L
;
613 *unpacked
= V3D_QPU_UNPACK_H
;
621 v3d_qpu_float32_unpack_pack(enum v3d_qpu_input_unpack unpacked
,
625 case V3D_QPU_UNPACK_ABS
:
628 case V3D_QPU_UNPACK_NONE
:
631 case V3D_QPU_UNPACK_L
:
634 case V3D_QPU_UNPACK_H
:
643 v3d_qpu_float16_unpack_unpack(uint32_t packed
,
644 enum v3d_qpu_input_unpack
*unpacked
)
648 *unpacked
= V3D_QPU_UNPACK_NONE
;
651 *unpacked
= V3D_QPU_UNPACK_REPLICATE_32F_16
;
654 *unpacked
= V3D_QPU_UNPACK_REPLICATE_L_16
;
657 *unpacked
= V3D_QPU_UNPACK_REPLICATE_H_16
;
660 *unpacked
= V3D_QPU_UNPACK_SWAP_16
;
668 v3d_qpu_float16_unpack_pack(enum v3d_qpu_input_unpack unpacked
,
672 case V3D_QPU_UNPACK_NONE
:
675 case V3D_QPU_UNPACK_REPLICATE_32F_16
:
678 case V3D_QPU_UNPACK_REPLICATE_L_16
:
681 case V3D_QPU_UNPACK_REPLICATE_H_16
:
684 case V3D_QPU_UNPACK_SWAP_16
:
693 v3d_qpu_float32_pack_pack(enum v3d_qpu_input_unpack unpacked
,
697 case V3D_QPU_PACK_NONE
:
712 v3d_qpu_add_unpack(const struct v3d_device_info
*devinfo
, uint64_t packed_inst
,
713 struct v3d_qpu_instr
*instr
)
715 uint32_t op
= QPU_GET_FIELD(packed_inst
, VC5_QPU_OP_ADD
);
716 uint32_t mux_a
= QPU_GET_FIELD(packed_inst
, VC5_QPU_ADD_A
);
717 uint32_t mux_b
= QPU_GET_FIELD(packed_inst
, VC5_QPU_ADD_B
);
718 uint32_t waddr
= QPU_GET_FIELD(packed_inst
, V3D_QPU_WADDR_A
);
720 uint32_t map_op
= op
;
721 /* Some big clusters of opcodes are replicated with unpack
724 if (map_op
>= 249 && map_op
<= 251)
725 map_op
= (map_op
- 249 + 245);
726 if (map_op
>= 253 && map_op
<= 255)
727 map_op
= (map_op
- 253 + 245);
729 const struct opcode_desc
*desc
=
730 lookup_opcode(add_ops
, ARRAY_SIZE(add_ops
),
731 map_op
, mux_a
, mux_b
);
735 instr
->alu
.add
.op
= desc
->op
;
737 /* FADD/FADDNF and FMIN/FMAX are determined by the orders of the
740 if (((op
>> 2) & 3) * 8 + mux_a
> (op
& 3) * 8 + mux_b
) {
741 if (instr
->alu
.add
.op
== V3D_QPU_A_FMIN
)
742 instr
->alu
.add
.op
= V3D_QPU_A_FMAX
;
743 if (instr
->alu
.add
.op
== V3D_QPU_A_FADD
)
744 instr
->alu
.add
.op
= V3D_QPU_A_FADDNF
;
747 /* Some QPU ops require a bit more than just basic opcode and mux a/b
748 * comparisons to distinguish them.
750 switch (instr
->alu
.add
.op
) {
751 case V3D_QPU_A_STVPMV
:
752 case V3D_QPU_A_STVPMD
:
753 case V3D_QPU_A_STVPMP
:
756 instr
->alu
.add
.op
= V3D_QPU_A_STVPMV
;
759 instr
->alu
.add
.op
= V3D_QPU_A_STVPMD
;
762 instr
->alu
.add
.op
= V3D_QPU_A_STVPMP
;
772 switch (instr
->alu
.add
.op
) {
774 case V3D_QPU_A_FADDNF
:
779 case V3D_QPU_A_VFPACK
:
780 if (instr
->alu
.add
.op
!= V3D_QPU_A_VFPACK
)
781 instr
->alu
.add
.output_pack
= (op
>> 4) & 0x3;
783 instr
->alu
.add
.output_pack
= V3D_QPU_PACK_NONE
;
785 if (!v3d_qpu_float32_unpack_unpack((op
>> 2) & 0x3,
786 &instr
->alu
.add
.a_unpack
)) {
790 if (!v3d_qpu_float32_unpack_unpack((op
>> 0) & 0x3,
791 &instr
->alu
.add
.b_unpack
)) {
796 case V3D_QPU_A_FFLOOR
:
797 case V3D_QPU_A_FROUND
:
798 case V3D_QPU_A_FTRUNC
:
799 case V3D_QPU_A_FCEIL
:
802 instr
->alu
.add
.output_pack
= mux_b
& 0x3;
804 if (!v3d_qpu_float32_unpack_unpack((op
>> 2) & 0x3,
805 &instr
->alu
.add
.a_unpack
)) {
810 case V3D_QPU_A_FTOIN
:
811 case V3D_QPU_A_FTOIZ
:
812 case V3D_QPU_A_FTOUZ
:
814 instr
->alu
.add
.output_pack
= V3D_QPU_PACK_NONE
;
816 if (!v3d_qpu_float32_unpack_unpack((op
>> 2) & 0x3,
817 &instr
->alu
.add
.a_unpack
)) {
822 case V3D_QPU_A_VFMIN
:
823 case V3D_QPU_A_VFMAX
:
824 if (!v3d_qpu_float16_unpack_unpack(op
& 0x7,
825 &instr
->alu
.add
.a_unpack
)) {
829 instr
->alu
.add
.output_pack
= V3D_QPU_PACK_NONE
;
830 instr
->alu
.add
.b_unpack
= V3D_QPU_UNPACK_NONE
;
834 instr
->alu
.add
.output_pack
= V3D_QPU_PACK_NONE
;
835 instr
->alu
.add
.a_unpack
= V3D_QPU_UNPACK_NONE
;
836 instr
->alu
.add
.b_unpack
= V3D_QPU_UNPACK_NONE
;
840 instr
->alu
.add
.a
= mux_a
;
841 instr
->alu
.add
.b
= mux_b
;
842 instr
->alu
.add
.waddr
= QPU_GET_FIELD(packed_inst
, V3D_QPU_WADDR_A
);
844 instr
->alu
.add
.magic_write
= false;
845 if (packed_inst
& VC5_QPU_MA
) {
846 switch (instr
->alu
.add
.op
) {
847 case V3D_QPU_A_LDVPMV_IN
:
848 instr
->alu
.add
.op
= V3D_QPU_A_LDVPMV_OUT
;
850 case V3D_QPU_A_LDVPMD_IN
:
851 instr
->alu
.add
.op
= V3D_QPU_A_LDVPMD_OUT
;
853 case V3D_QPU_A_LDVPMG_IN
:
854 instr
->alu
.add
.op
= V3D_QPU_A_LDVPMG_OUT
;
857 instr
->alu
.add
.magic_write
= true;
866 v3d_qpu_mul_unpack(const struct v3d_device_info
*devinfo
, uint64_t packed_inst
,
867 struct v3d_qpu_instr
*instr
)
869 uint32_t op
= QPU_GET_FIELD(packed_inst
, VC5_QPU_OP_MUL
);
870 uint32_t mux_a
= QPU_GET_FIELD(packed_inst
, VC5_QPU_MUL_A
);
871 uint32_t mux_b
= QPU_GET_FIELD(packed_inst
, VC5_QPU_MUL_B
);
874 const struct opcode_desc
*desc
=
875 lookup_opcode(mul_ops
, ARRAY_SIZE(mul_ops
),
880 instr
->alu
.mul
.op
= desc
->op
;
883 switch (instr
->alu
.mul
.op
) {
885 instr
->alu
.mul
.output_pack
= ((op
>> 4) & 0x3) - 1;
887 if (!v3d_qpu_float32_unpack_unpack((op
>> 2) & 0x3,
888 &instr
->alu
.mul
.a_unpack
)) {
892 if (!v3d_qpu_float32_unpack_unpack((op
>> 0) & 0x3,
893 &instr
->alu
.mul
.b_unpack
)) {
900 instr
->alu
.mul
.output_pack
= (((op
& 1) << 1) +
903 if (!v3d_qpu_float32_unpack_unpack(mux_b
& 0x3,
904 &instr
->alu
.mul
.a_unpack
)) {
910 case V3D_QPU_M_VFMUL
:
911 instr
->alu
.mul
.output_pack
= V3D_QPU_PACK_NONE
;
913 if (!v3d_qpu_float16_unpack_unpack(((op
& 0x7) - 4) & 7,
914 &instr
->alu
.mul
.a_unpack
)) {
918 instr
->alu
.mul
.b_unpack
= V3D_QPU_UNPACK_NONE
;
923 instr
->alu
.mul
.output_pack
= V3D_QPU_PACK_NONE
;
924 instr
->alu
.mul
.a_unpack
= V3D_QPU_UNPACK_NONE
;
925 instr
->alu
.mul
.b_unpack
= V3D_QPU_UNPACK_NONE
;
929 instr
->alu
.mul
.a
= mux_a
;
930 instr
->alu
.mul
.b
= mux_b
;
931 instr
->alu
.mul
.waddr
= QPU_GET_FIELD(packed_inst
, V3D_QPU_WADDR_M
);
932 instr
->alu
.mul
.magic_write
= packed_inst
& VC5_QPU_MM
;
938 v3d_qpu_add_pack(const struct v3d_device_info
*devinfo
,
939 const struct v3d_qpu_instr
*instr
, uint64_t *packed_instr
)
941 uint32_t waddr
= instr
->alu
.add
.waddr
;
942 uint32_t mux_a
= instr
->alu
.add
.a
;
943 uint32_t mux_b
= instr
->alu
.add
.b
;
944 int nsrc
= v3d_qpu_add_op_num_src(instr
->alu
.add
.op
);
945 const struct opcode_desc
*desc
;
948 for (desc
= add_ops
; desc
!= &add_ops
[ARRAY_SIZE(add_ops
)];
950 if (desc
->op
== instr
->alu
.add
.op
)
953 if (desc
== &add_ops
[ARRAY_SIZE(add_ops
)])
956 opcode
= desc
->opcode_first
;
958 /* If an operation doesn't use an arg, its mux values may be used to
959 * identify the operation type.
962 mux_b
= ffs(desc
->mux_b_mask
) - 1;
965 mux_a
= ffs(desc
->mux_a_mask
) - 1;
967 bool no_magic_write
= false;
969 switch (instr
->alu
.add
.op
) {
970 case V3D_QPU_A_STVPMV
:
972 no_magic_write
= true;
974 case V3D_QPU_A_STVPMD
:
976 no_magic_write
= true;
978 case V3D_QPU_A_STVPMP
:
980 no_magic_write
= true;
983 case V3D_QPU_A_LDVPMV_IN
:
984 case V3D_QPU_A_LDVPMD_IN
:
985 case V3D_QPU_A_LDVPMP
:
986 case V3D_QPU_A_LDVPMG_IN
:
987 assert(!instr
->alu
.add
.magic_write
);
990 case V3D_QPU_A_LDVPMV_OUT
:
991 case V3D_QPU_A_LDVPMD_OUT
:
992 case V3D_QPU_A_LDVPMG_OUT
:
993 assert(!instr
->alu
.add
.magic_write
);
994 *packed_instr
|= VC5_QPU_MA
;
1001 switch (instr
->alu
.add
.op
) {
1002 case V3D_QPU_A_FADD
:
1003 case V3D_QPU_A_FADDNF
:
1004 case V3D_QPU_A_FSUB
:
1005 case V3D_QPU_A_FMIN
:
1006 case V3D_QPU_A_FMAX
:
1007 case V3D_QPU_A_FCMP
: {
1008 uint32_t output_pack
;
1012 if (!v3d_qpu_float32_pack_pack(instr
->alu
.add
.output_pack
,
1016 opcode
|= output_pack
<< 4;
1018 if (!v3d_qpu_float32_unpack_pack(instr
->alu
.add
.a_unpack
,
1023 if (!v3d_qpu_float32_unpack_pack(instr
->alu
.add
.b_unpack
,
1028 /* These operations with commutative operands are
1029 * distinguished by which order their operands come in.
1031 bool ordering
= a_unpack
* 8 + mux_a
> b_unpack
* 8 + mux_b
;
1032 if (((instr
->alu
.add
.op
== V3D_QPU_A_FMIN
||
1033 instr
->alu
.add
.op
== V3D_QPU_A_FADD
) && ordering
) ||
1034 ((instr
->alu
.add
.op
== V3D_QPU_A_FMAX
||
1035 instr
->alu
.add
.op
== V3D_QPU_A_FADDNF
) && !ordering
)) {
1039 a_unpack
= b_unpack
;
1047 opcode
|= a_unpack
<< 2;
1048 opcode
|= b_unpack
<< 0;
1053 case V3D_QPU_A_VFPACK
: {
1057 if (instr
->alu
.add
.a_unpack
== V3D_QPU_UNPACK_ABS
||
1058 instr
->alu
.add
.b_unpack
== V3D_QPU_UNPACK_ABS
) {
1062 if (!v3d_qpu_float32_unpack_pack(instr
->alu
.add
.a_unpack
,
1067 if (!v3d_qpu_float32_unpack_pack(instr
->alu
.add
.b_unpack
,
1072 opcode
= (opcode
& ~(1 << 2)) | (a_unpack
<< 2);
1073 opcode
= (opcode
& ~(1 << 0)) | (b_unpack
<< 0);
1078 case V3D_QPU_A_FFLOOR
:
1079 case V3D_QPU_A_FROUND
:
1080 case V3D_QPU_A_FTRUNC
:
1081 case V3D_QPU_A_FCEIL
:
1083 case V3D_QPU_A_FDY
: {
1086 if (!v3d_qpu_float32_pack_pack(instr
->alu
.add
.output_pack
,
1092 if (!v3d_qpu_float32_unpack_pack(instr
->alu
.add
.a_unpack
,
1098 opcode
= (opcode
& ~(1 << 2)) | packed
<< 2;
1102 case V3D_QPU_A_FTOIN
:
1103 case V3D_QPU_A_FTOIZ
:
1104 case V3D_QPU_A_FTOUZ
:
1105 case V3D_QPU_A_FTOC
:
1106 if (instr
->alu
.add
.output_pack
!= V3D_QPU_PACK_NONE
)
1110 if (!v3d_qpu_float32_unpack_pack(instr
->alu
.add
.a_unpack
,
1116 opcode
|= packed
<< 2;
1120 case V3D_QPU_A_VFMIN
:
1121 case V3D_QPU_A_VFMAX
:
1122 if (instr
->alu
.add
.output_pack
!= V3D_QPU_PACK_NONE
||
1123 instr
->alu
.add
.b_unpack
!= V3D_QPU_UNPACK_NONE
) {
1127 if (!v3d_qpu_float16_unpack_pack(instr
->alu
.add
.a_unpack
,
1135 if (instr
->alu
.add
.op
!= V3D_QPU_A_NOP
&&
1136 (instr
->alu
.add
.output_pack
!= V3D_QPU_PACK_NONE
||
1137 instr
->alu
.add
.a_unpack
!= V3D_QPU_UNPACK_NONE
||
1138 instr
->alu
.add
.b_unpack
!= V3D_QPU_UNPACK_NONE
)) {
1144 *packed_instr
|= QPU_SET_FIELD(mux_a
, VC5_QPU_ADD_A
);
1145 *packed_instr
|= QPU_SET_FIELD(mux_b
, VC5_QPU_ADD_B
);
1146 *packed_instr
|= QPU_SET_FIELD(opcode
, VC5_QPU_OP_ADD
);
1147 *packed_instr
|= QPU_SET_FIELD(waddr
, V3D_QPU_WADDR_A
);
1148 if (instr
->alu
.add
.magic_write
&& !no_magic_write
)
1149 *packed_instr
|= VC5_QPU_MA
;
1155 v3d_qpu_mul_pack(const struct v3d_device_info
*devinfo
,
1156 const struct v3d_qpu_instr
*instr
, uint64_t *packed_instr
)
1158 uint32_t mux_a
= instr
->alu
.mul
.a
;
1159 uint32_t mux_b
= instr
->alu
.mul
.b
;
1160 int nsrc
= v3d_qpu_mul_op_num_src(instr
->alu
.mul
.op
);
1161 const struct opcode_desc
*desc
;
1163 for (desc
= mul_ops
; desc
!= &mul_ops
[ARRAY_SIZE(mul_ops
)];
1165 if (desc
->op
== instr
->alu
.mul
.op
)
1168 if (desc
== &mul_ops
[ARRAY_SIZE(mul_ops
)])
1171 uint32_t opcode
= desc
->opcode_first
;
1173 /* Some opcodes have a single valid value for their mux a/b, so set
1174 * that here. If mux a/b determine packing, it will be set below.
1177 mux_b
= ffs(desc
->mux_b_mask
) - 1;
1180 mux_a
= ffs(desc
->mux_a_mask
) - 1;
1182 switch (instr
->alu
.mul
.op
) {
1183 case V3D_QPU_M_FMUL
: {
1186 if (!v3d_qpu_float32_pack_pack(instr
->alu
.mul
.output_pack
,
1190 /* No need for a +1 because desc->opcode_first has a 1 in this
1193 opcode
+= packed
<< 4;
1195 if (!v3d_qpu_float32_unpack_pack(instr
->alu
.mul
.a_unpack
,
1199 opcode
|= packed
<< 2;
1201 if (!v3d_qpu_float32_unpack_pack(instr
->alu
.mul
.b_unpack
,
1205 opcode
|= packed
<< 0;
1209 case V3D_QPU_M_FMOV
: {
1212 if (!v3d_qpu_float32_pack_pack(instr
->alu
.mul
.output_pack
,
1216 opcode
|= (packed
>> 1) & 1;
1217 mux_b
= (packed
& 1) << 2;
1219 if (!v3d_qpu_float32_unpack_pack(instr
->alu
.mul
.a_unpack
,
1227 case V3D_QPU_M_VFMUL
: {
1230 if (instr
->alu
.mul
.output_pack
!= V3D_QPU_PACK_NONE
)
1233 if (!v3d_qpu_float16_unpack_pack(instr
->alu
.mul
.a_unpack
,
1237 if (instr
->alu
.mul
.a_unpack
== V3D_QPU_UNPACK_SWAP_16
)
1240 opcode
|= (packed
+ 4) & 7;
1242 if (instr
->alu
.mul
.b_unpack
!= V3D_QPU_UNPACK_NONE
)
1252 *packed_instr
|= QPU_SET_FIELD(mux_a
, VC5_QPU_MUL_A
);
1253 *packed_instr
|= QPU_SET_FIELD(mux_b
, VC5_QPU_MUL_B
);
1255 *packed_instr
|= QPU_SET_FIELD(opcode
, VC5_QPU_OP_MUL
);
1256 *packed_instr
|= QPU_SET_FIELD(instr
->alu
.mul
.waddr
, V3D_QPU_WADDR_M
);
1257 if (instr
->alu
.mul
.magic_write
)
1258 *packed_instr
|= VC5_QPU_MM
;
1264 v3d_qpu_instr_unpack_alu(const struct v3d_device_info
*devinfo
,
1265 uint64_t packed_instr
,
1266 struct v3d_qpu_instr
*instr
)
1268 instr
->type
= V3D_QPU_INSTR_TYPE_ALU
;
1270 if (!v3d_qpu_sig_unpack(devinfo
,
1271 QPU_GET_FIELD(packed_instr
, VC5_QPU_SIG
),
1275 uint32_t packed_cond
= QPU_GET_FIELD(packed_instr
, VC5_QPU_COND
);
1276 if (v3d_qpu_sig_writes_address(devinfo
, &instr
->sig
)) {
1277 instr
->sig_addr
= packed_cond
& ~VC5_QPU_COND_SIG_MAGIC_ADDR
;
1278 instr
->sig_magic
= packed_cond
& VC5_QPU_COND_SIG_MAGIC_ADDR
;
1280 instr
->flags
.ac
= V3D_QPU_COND_NONE
;
1281 instr
->flags
.mc
= V3D_QPU_COND_NONE
;
1282 instr
->flags
.apf
= V3D_QPU_PF_NONE
;
1283 instr
->flags
.mpf
= V3D_QPU_PF_NONE
;
1284 instr
->flags
.auf
= V3D_QPU_UF_NONE
;
1285 instr
->flags
.muf
= V3D_QPU_UF_NONE
;
1287 if (!v3d_qpu_flags_unpack(devinfo
, packed_cond
, &instr
->flags
))
1291 instr
->raddr_a
= QPU_GET_FIELD(packed_instr
, VC5_QPU_RADDR_A
);
1292 instr
->raddr_b
= QPU_GET_FIELD(packed_instr
, VC5_QPU_RADDR_B
);
1294 if (!v3d_qpu_add_unpack(devinfo
, packed_instr
, instr
))
1297 if (!v3d_qpu_mul_unpack(devinfo
, packed_instr
, instr
))
1304 v3d_qpu_instr_unpack_branch(const struct v3d_device_info
*devinfo
,
1305 uint64_t packed_instr
,
1306 struct v3d_qpu_instr
*instr
)
1308 instr
->type
= V3D_QPU_INSTR_TYPE_BRANCH
;
1310 uint32_t cond
= QPU_GET_FIELD(packed_instr
, VC5_QPU_BRANCH_COND
);
1312 instr
->branch
.cond
= V3D_QPU_BRANCH_COND_ALWAYS
;
1313 else if (V3D_QPU_BRANCH_COND_A0
+ (cond
- 2) <=
1314 V3D_QPU_BRANCH_COND_ALLNA
)
1315 instr
->branch
.cond
= V3D_QPU_BRANCH_COND_A0
+ (cond
- 2);
1319 uint32_t msfign
= QPU_GET_FIELD(packed_instr
, VC5_QPU_BRANCH_MSFIGN
);
1322 instr
->branch
.msfign
= msfign
;
1324 instr
->branch
.bdi
= QPU_GET_FIELD(packed_instr
, VC5_QPU_BRANCH_BDI
);
1326 instr
->branch
.ub
= packed_instr
& VC5_QPU_BRANCH_UB
;
1327 if (instr
->branch
.ub
) {
1328 instr
->branch
.bdu
= QPU_GET_FIELD(packed_instr
,
1329 VC5_QPU_BRANCH_BDU
);
1332 instr
->branch
.raddr_a
= QPU_GET_FIELD(packed_instr
,
1335 instr
->branch
.offset
= 0;
1337 instr
->branch
.offset
+=
1338 QPU_GET_FIELD(packed_instr
,
1339 VC5_QPU_BRANCH_ADDR_LOW
) << 3;
1341 instr
->branch
.offset
+=
1342 QPU_GET_FIELD(packed_instr
,
1343 VC5_QPU_BRANCH_ADDR_HIGH
) << 24;
1349 v3d_qpu_instr_unpack(const struct v3d_device_info
*devinfo
,
1350 uint64_t packed_instr
,
1351 struct v3d_qpu_instr
*instr
)
1353 if (QPU_GET_FIELD(packed_instr
, VC5_QPU_OP_MUL
) != 0) {
1354 return v3d_qpu_instr_unpack_alu(devinfo
, packed_instr
, instr
);
1356 uint32_t sig
= QPU_GET_FIELD(packed_instr
, VC5_QPU_SIG
);
1358 if ((sig
& 24) == 16) {
1359 return v3d_qpu_instr_unpack_branch(devinfo
, packed_instr
,
1368 v3d_qpu_instr_pack_alu(const struct v3d_device_info
*devinfo
,
1369 const struct v3d_qpu_instr
*instr
,
1370 uint64_t *packed_instr
)
1373 if (!v3d_qpu_sig_pack(devinfo
, &instr
->sig
, &sig
))
1375 *packed_instr
|= QPU_SET_FIELD(sig
, VC5_QPU_SIG
);
1377 if (instr
->type
== V3D_QPU_INSTR_TYPE_ALU
) {
1378 *packed_instr
|= QPU_SET_FIELD(instr
->raddr_a
, VC5_QPU_RADDR_A
);
1379 *packed_instr
|= QPU_SET_FIELD(instr
->raddr_b
, VC5_QPU_RADDR_B
);
1381 if (!v3d_qpu_add_pack(devinfo
, instr
, packed_instr
))
1383 if (!v3d_qpu_mul_pack(devinfo
, instr
, packed_instr
))
1387 if (v3d_qpu_sig_writes_address(devinfo
, &instr
->sig
)) {
1388 if (instr
->flags
.ac
!= V3D_QPU_COND_NONE
||
1389 instr
->flags
.mc
!= V3D_QPU_COND_NONE
||
1390 instr
->flags
.apf
!= V3D_QPU_PF_NONE
||
1391 instr
->flags
.mpf
!= V3D_QPU_PF_NONE
||
1392 instr
->flags
.auf
!= V3D_QPU_UF_NONE
||
1393 instr
->flags
.muf
!= V3D_QPU_UF_NONE
) {
1397 flags
= instr
->sig_addr
;
1398 if (instr
->sig_magic
)
1399 flags
|= VC5_QPU_COND_SIG_MAGIC_ADDR
;
1401 if (!v3d_qpu_flags_pack(devinfo
, &instr
->flags
, &flags
))
1405 *packed_instr
|= QPU_SET_FIELD(flags
, VC5_QPU_COND
);
1407 if (v3d_qpu_sig_writes_address(devinfo
, &instr
->sig
))
1415 v3d_qpu_instr_pack_branch(const struct v3d_device_info
*devinfo
,
1416 const struct v3d_qpu_instr
*instr
,
1417 uint64_t *packed_instr
)
1419 *packed_instr
|= QPU_SET_FIELD(16, VC5_QPU_SIG
);
1421 if (instr
->branch
.cond
!= V3D_QPU_BRANCH_COND_ALWAYS
) {
1422 *packed_instr
|= QPU_SET_FIELD(2 + (instr
->branch
.cond
-
1423 V3D_QPU_BRANCH_COND_A0
),
1424 VC5_QPU_BRANCH_COND
);
1427 *packed_instr
|= QPU_SET_FIELD(instr
->branch
.msfign
,
1428 VC5_QPU_BRANCH_MSFIGN
);
1430 *packed_instr
|= QPU_SET_FIELD(instr
->branch
.bdi
,
1431 VC5_QPU_BRANCH_BDI
);
1433 if (instr
->branch
.ub
) {
1434 *packed_instr
|= VC5_QPU_BRANCH_UB
;
1435 *packed_instr
|= QPU_SET_FIELD(instr
->branch
.bdu
,
1436 VC5_QPU_BRANCH_BDU
);
1439 switch (instr
->branch
.bdi
) {
1440 case V3D_QPU_BRANCH_DEST_ABS
:
1441 case V3D_QPU_BRANCH_DEST_REL
:
1442 *packed_instr
|= QPU_SET_FIELD(instr
->branch
.msfign
,
1443 VC5_QPU_BRANCH_MSFIGN
);
1445 *packed_instr
|= QPU_SET_FIELD((instr
->branch
.offset
&
1447 VC5_QPU_BRANCH_ADDR_LOW
);
1449 *packed_instr
|= QPU_SET_FIELD(instr
->branch
.offset
>> 24,
1450 VC5_QPU_BRANCH_ADDR_HIGH
);
1452 case V3D_QPU_BRANCH_DEST_REGFILE
:
1453 *packed_instr
|= QPU_SET_FIELD(instr
->branch
.raddr_a
,
1465 v3d_qpu_instr_pack(const struct v3d_device_info
*devinfo
,
1466 const struct v3d_qpu_instr
*instr
,
1467 uint64_t *packed_instr
)
1471 switch (instr
->type
) {
1472 case V3D_QPU_INSTR_TYPE_ALU
:
1473 return v3d_qpu_instr_pack_alu(devinfo
, instr
, packed_instr
);
1474 case V3D_QPU_INSTR_TYPE_BRANCH
:
1475 return v3d_qpu_instr_pack_branch(devinfo
, instr
, packed_instr
);