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broadcom/vc5: Add support for QPU pack/unpack/disasm of small immediates.
[mesa.git] / src / broadcom / qpu / qpu_pack.c
1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <string.h>
25 #include "util/macros.h"
26
27 #include "broadcom/common/v3d_device_info.h"
28 #include "qpu_instr.h"
29
30 #ifndef QPU_MASK
31 #define QPU_MASK(high, low) ((((uint64_t)1<<((high)-(low)+1))-1)<<(low))
32 /* Using the GNU statement expression extension */
33 #define QPU_SET_FIELD(value, field) \
34 ({ \
35 uint64_t fieldval = (uint64_t)(value) << field ## _SHIFT; \
36 assert((fieldval & ~ field ## _MASK) == 0); \
37 fieldval & field ## _MASK; \
38 })
39
40 #define QPU_GET_FIELD(word, field) ((uint32_t)(((word) & field ## _MASK) >> field ## _SHIFT))
41
42 #define QPU_UPDATE_FIELD(inst, value, field) \
43 (((inst) & ~(field ## _MASK)) | QPU_SET_FIELD(value, field))
44 #endif /* QPU_MASK */
45
46 #define VC5_QPU_OP_MUL_SHIFT 58
47 #define VC5_QPU_OP_MUL_MASK QPU_MASK(63, 58)
48
49 #define VC5_QPU_SIG_SHIFT 53
50 #define VC5_QPU_SIG_MASK QPU_MASK(57, 53)
51
52 #define VC5_QPU_COND_SHIFT 46
53 #define VC5_QPU_COND_MASK QPU_MASK(52, 46)
54 #define VC5_QPU_COND_SIG_MAGIC_ADDR (1 << 6)
55
56 #define VC5_QPU_MM QPU_MASK(45, 45)
57 #define VC5_QPU_MA QPU_MASK(44, 44)
58
59 #define V3D_QPU_WADDR_M_SHIFT 38
60 #define V3D_QPU_WADDR_M_MASK QPU_MASK(43, 38)
61
62 #define VC5_QPU_BRANCH_ADDR_LOW_SHIFT 35
63 #define VC5_QPU_BRANCH_ADDR_LOW_MASK QPU_MASK(55, 35)
64
65 #define V3D_QPU_WADDR_A_SHIFT 32
66 #define V3D_QPU_WADDR_A_MASK QPU_MASK(37, 32)
67
68 #define VC5_QPU_BRANCH_COND_SHIFT 32
69 #define VC5_QPU_BRANCH_COND_MASK QPU_MASK(34, 32)
70
71 #define VC5_QPU_BRANCH_ADDR_HIGH_SHIFT 24
72 #define VC5_QPU_BRANCH_ADDR_HIGH_MASK QPU_MASK(31, 24)
73
74 #define VC5_QPU_OP_ADD_SHIFT 24
75 #define VC5_QPU_OP_ADD_MASK QPU_MASK(31, 24)
76
77 #define VC5_QPU_MUL_B_SHIFT 21
78 #define VC5_QPU_MUL_B_MASK QPU_MASK(23, 21)
79
80 #define VC5_QPU_BRANCH_MSFIGN_SHIFT 21
81 #define VC5_QPU_BRANCH_MSFIGN_MASK QPU_MASK(22, 21)
82
83 #define VC5_QPU_MUL_A_SHIFT 18
84 #define VC5_QPU_MUL_A_MASK QPU_MASK(20, 18)
85
86 #define VC5_QPU_ADD_B_SHIFT 15
87 #define VC5_QPU_ADD_B_MASK QPU_MASK(17, 15)
88
89 #define VC5_QPU_BRANCH_BDU_SHIFT 15
90 #define VC5_QPU_BRANCH_BDU_MASK QPU_MASK(17, 15)
91
92 #define VC5_QPU_BRANCH_UB QPU_MASK(14, 14)
93
94 #define VC5_QPU_ADD_A_SHIFT 12
95 #define VC5_QPU_ADD_A_MASK QPU_MASK(14, 12)
96
97 #define VC5_QPU_BRANCH_BDI_SHIFT 12
98 #define VC5_QPU_BRANCH_BDI_MASK QPU_MASK(13, 12)
99
100 #define VC5_QPU_RADDR_A_SHIFT 6
101 #define VC5_QPU_RADDR_A_MASK QPU_MASK(11, 6)
102
103 #define VC5_QPU_RADDR_B_SHIFT 0
104 #define VC5_QPU_RADDR_B_MASK QPU_MASK(5, 0)
105
106 #define THRSW .thrsw = true
107 #define LDUNIF .ldunif = true
108 #define LDUNIFRF .ldunifrf = true
109 #define LDUNIFA .ldunifa = true
110 #define LDUNIFARF .ldunifarf = true
111 #define LDTMU .ldtmu = true
112 #define LDVARY .ldvary = true
113 #define LDVPM .ldvpm = true
114 #define SMIMM .small_imm = true
115 #define LDTLB .ldtlb = true
116 #define LDTLBU .ldtlbu = true
117 #define UCB .ucb = true
118 #define ROT .rotate = true
119 #define WRTMUC .wrtmuc = true
120
121 static const struct v3d_qpu_sig v33_sig_map[] = {
122 /* MISC R3 R4 R5 */
123 [0] = { },
124 [1] = { THRSW, },
125 [2] = { LDUNIF },
126 [3] = { THRSW, LDUNIF },
127 [4] = { LDTMU, },
128 [5] = { THRSW, LDTMU, },
129 [6] = { LDTMU, LDUNIF },
130 [7] = { THRSW, LDTMU, LDUNIF },
131 [8] = { LDVARY, },
132 [9] = { THRSW, LDVARY, },
133 [10] = { LDVARY, LDUNIF },
134 [11] = { THRSW, LDVARY, LDUNIF },
135 [12] = { LDVARY, LDTMU, },
136 [13] = { THRSW, LDVARY, LDTMU, },
137 [14] = { SMIMM, LDVARY, },
138 [15] = { SMIMM, },
139 [16] = { LDTLB, },
140 [17] = { LDTLBU, },
141 /* 18-21 reserved */
142 [22] = { UCB, },
143 [23] = { ROT, },
144 [24] = { LDVPM, },
145 [25] = { THRSW, LDVPM, },
146 [26] = { LDVPM, LDUNIF },
147 [27] = { THRSW, LDVPM, LDUNIF },
148 [28] = { LDVPM, LDTMU, },
149 [29] = { THRSW, LDVPM, LDTMU, },
150 [30] = { SMIMM, LDVPM, },
151 [31] = { SMIMM, },
152 };
153
154 static const struct v3d_qpu_sig v40_sig_map[] = {
155 /* MISC R3 R4 R5 */
156 [0] = { },
157 [1] = { THRSW, },
158 [2] = { LDUNIF },
159 [3] = { THRSW, LDUNIF },
160 [4] = { LDTMU, },
161 [5] = { THRSW, LDTMU, },
162 [6] = { LDTMU, LDUNIF },
163 [7] = { THRSW, LDTMU, LDUNIF },
164 [8] = { LDVARY, },
165 [9] = { THRSW, LDVARY, },
166 [10] = { LDVARY, LDUNIF },
167 [11] = { THRSW, LDVARY, LDUNIF },
168 /* 12-13 reserved */
169 [14] = { SMIMM, LDVARY, },
170 [15] = { SMIMM, },
171 [16] = { LDTLB, },
172 [17] = { LDTLBU, },
173 [18] = { WRTMUC },
174 [19] = { THRSW, WRTMUC },
175 [20] = { LDVARY, WRTMUC },
176 [21] = { THRSW, LDVARY, WRTMUC },
177 [22] = { UCB, },
178 [23] = { ROT, },
179 /* 24-30 reserved */
180 [31] = { SMIMM, LDTMU, },
181 };
182
183 static const struct v3d_qpu_sig v41_sig_map[] = {
184 /* MISC phys R5 */
185 [0] = { },
186 [1] = { THRSW, },
187 [2] = { LDUNIF },
188 [3] = { THRSW, LDUNIF },
189 [4] = { LDTMU, },
190 [5] = { THRSW, LDTMU, },
191 [6] = { LDTMU, LDUNIF },
192 [7] = { THRSW, LDTMU, LDUNIF },
193 [8] = { LDVARY, },
194 [9] = { THRSW, LDVARY, },
195 [10] = { LDVARY, LDUNIF },
196 [11] = { THRSW, LDVARY, LDUNIF },
197 [12] = { LDUNIFRF },
198 [13] = { THRSW, LDUNIFRF },
199 [14] = { SMIMM, LDVARY, },
200 [15] = { SMIMM, },
201 [16] = { LDTLB, },
202 [17] = { LDTLBU, },
203 [18] = { WRTMUC },
204 [19] = { THRSW, WRTMUC },
205 [20] = { LDVARY, WRTMUC },
206 [21] = { THRSW, LDVARY, WRTMUC },
207 [22] = { UCB, },
208 [23] = { ROT, },
209 /* 24-30 reserved */
210 [24] = { LDUNIFA},
211 [25] = { LDUNIFARF },
212 [31] = { SMIMM, LDTMU, },
213 };
214
215 bool
216 v3d_qpu_sig_unpack(const struct v3d_device_info *devinfo,
217 uint32_t packed_sig,
218 struct v3d_qpu_sig *sig)
219 {
220 if (packed_sig >= ARRAY_SIZE(v33_sig_map))
221 return false;
222
223 if (devinfo->ver >= 41)
224 *sig = v41_sig_map[packed_sig];
225 else if (devinfo->ver == 40)
226 *sig = v40_sig_map[packed_sig];
227 else
228 *sig = v33_sig_map[packed_sig];
229
230 /* Signals with zeroed unpacked contents after element 0 are reserved. */
231 return (packed_sig == 0 ||
232 memcmp(sig, &v33_sig_map[0], sizeof(*sig)) != 0);
233 }
234
235 bool
236 v3d_qpu_sig_pack(const struct v3d_device_info *devinfo,
237 const struct v3d_qpu_sig *sig,
238 uint32_t *packed_sig)
239 {
240 static const struct v3d_qpu_sig *map;
241
242 if (devinfo->ver >= 41)
243 map = v41_sig_map;
244 else if (devinfo->ver == 40)
245 map = v40_sig_map;
246 else
247 map = v33_sig_map;
248
249 for (int i = 0; i < ARRAY_SIZE(v33_sig_map); i++) {
250 if (memcmp(&map[i], sig, sizeof(*sig)) == 0) {
251 *packed_sig = i;
252 return true;
253 }
254 }
255
256 return false;
257 }
258 static inline unsigned
259 fui( float f )
260 {
261 union {float f; unsigned ui;} fi;
262 fi.f = f;
263 return fi.ui;
264 }
265
266 static const uint32_t small_immediates[] = {
267 0, 1, 2, 3,
268 4, 5, 6, 7,
269 8, 9, 10, 11,
270 12, 13, 14, 15,
271 -16, -15, -14, -13,
272 -12, -11, -10, -9,
273 -8, -7, -6, -5,
274 -4, -3, -2, -1,
275 0x3b800000, /* 2.0^-8 */
276 0x3c000000, /* 2.0^-7 */
277 0x3c800000, /* 2.0^-6 */
278 0x3d000000, /* 2.0^-5 */
279 0x3d800000, /* 2.0^-4 */
280 0x3e000000, /* 2.0^-3 */
281 0x3e800000, /* 2.0^-2 */
282 0x3f000000, /* 2.0^-1 */
283 0x3f800000, /* 2.0^0 */
284 0x40000000, /* 2.0^1 */
285 0x40800000, /* 2.0^2 */
286 0x41000000, /* 2.0^3 */
287 0x41800000, /* 2.0^4 */
288 0x42000000, /* 2.0^5 */
289 0x42800000, /* 2.0^6 */
290 0x43000000, /* 2.0^7 */
291 };
292
293 bool
294 v3d_qpu_small_imm_unpack(const struct v3d_device_info *devinfo,
295 uint32_t packed_small_immediate,
296 uint32_t *small_immediate)
297 {
298 if (packed_small_immediate >= ARRAY_SIZE(small_immediates))
299 return false;
300
301 *small_immediate = small_immediates[packed_small_immediate];
302 return true;
303 }
304
305 bool
306 v3d_qpu_small_imm_pack(const struct v3d_device_info *devinfo,
307 uint32_t value,
308 uint32_t *packed_small_immediate)
309 {
310 STATIC_ASSERT(ARRAY_SIZE(small_immediates) == 48);
311
312 for (int i = 0; i < ARRAY_SIZE(small_immediates); i++) {
313 if (small_immediates[i] == value) {
314 *packed_small_immediate = i;
315 return true;
316 }
317 }
318
319 return false;
320 }
321
322 bool
323 v3d_qpu_flags_unpack(const struct v3d_device_info *devinfo,
324 uint32_t packed_cond,
325 struct v3d_qpu_flags *cond)
326 {
327 static const enum v3d_qpu_cond cond_map[4] = {
328 [0] = V3D_QPU_COND_IFA,
329 [1] = V3D_QPU_COND_IFB,
330 [2] = V3D_QPU_COND_IFNA,
331 [3] = V3D_QPU_COND_IFNB,
332 };
333
334 cond->ac = V3D_QPU_COND_NONE;
335 cond->mc = V3D_QPU_COND_NONE;
336 cond->apf = V3D_QPU_PF_NONE;
337 cond->mpf = V3D_QPU_PF_NONE;
338 cond->auf = V3D_QPU_UF_NONE;
339 cond->muf = V3D_QPU_UF_NONE;
340
341 if (packed_cond == 0) {
342 return true;
343 } else if (packed_cond >> 2 == 0) {
344 cond->apf = packed_cond & 0x3;
345 } else if (packed_cond >> 4 == 0) {
346 cond->auf = (packed_cond & 0xf) - 4 + V3D_QPU_UF_ANDZ;
347 } else if (packed_cond == 0x10) {
348 return false;
349 } else if (packed_cond >> 2 == 0x4) {
350 cond->mpf = packed_cond & 0x3;
351 } else if (packed_cond >> 4 == 0x1) {
352 cond->muf = (packed_cond & 0xf) - 4 + V3D_QPU_UF_ANDZ;
353 } else if (packed_cond >> 4 == 0x2) {
354 cond->ac = ((packed_cond >> 2) & 0x3) + V3D_QPU_COND_IFA;
355 cond->mpf = packed_cond & 0x3;
356 } else if (packed_cond >> 4 == 0x3) {
357 cond->mc = ((packed_cond >> 2) & 0x3) + V3D_QPU_COND_IFA;
358 cond->apf = packed_cond & 0x3;
359 } else if (packed_cond >> 6) {
360 cond->mc = cond_map[(packed_cond >> 4) & 0x3];
361 if (((packed_cond >> 2) & 0x3) == 0) {
362 cond->ac = cond_map[packed_cond & 0x3];
363 } else {
364 cond->auf = (packed_cond & 0xf) - 4 + V3D_QPU_UF_ANDZ;
365 }
366 }
367
368 return true;
369 }
370
371 bool
372 v3d_qpu_flags_pack(const struct v3d_device_info *devinfo,
373 const struct v3d_qpu_flags *cond,
374 uint32_t *packed_cond)
375 {
376 #define AC (1 << 0)
377 #define MC (1 << 1)
378 #define APF (1 << 2)
379 #define MPF (1 << 3)
380 #define AUF (1 << 4)
381 #define MUF (1 << 5)
382 static const struct {
383 uint8_t flags_present;
384 uint8_t bits;
385 } flags_table[] = {
386 { 0, 0 },
387 { APF, 0 },
388 { AUF, 0 },
389 { MPF, (1 << 4) },
390 { MUF, (1 << 4) },
391 { AC, (1 << 5) },
392 { AC | MPF, (1 << 5) },
393 { MC, (1 << 5) | (1 << 4) },
394 { MC | APF, (1 << 5) | (1 << 4) },
395 { MC | AC, (1 << 6) },
396 { MC | AUF, (1 << 6) },
397 };
398
399 uint8_t flags_present = 0;
400 if (cond->ac != V3D_QPU_COND_NONE)
401 flags_present |= AC;
402 if (cond->mc != V3D_QPU_COND_NONE)
403 flags_present |= MC;
404 if (cond->apf != V3D_QPU_PF_NONE)
405 flags_present |= APF;
406 if (cond->mpf != V3D_QPU_PF_NONE)
407 flags_present |= MPF;
408 if (cond->auf != V3D_QPU_UF_NONE)
409 flags_present |= AUF;
410 if (cond->muf != V3D_QPU_UF_NONE)
411 flags_present |= MUF;
412
413 for (int i = 0; i < ARRAY_SIZE(flags_table); i++) {
414 if (flags_table[i].flags_present != flags_present)
415 continue;
416
417 *packed_cond = flags_table[i].bits;
418
419 *packed_cond |= cond->apf;
420 *packed_cond |= cond->mpf;
421
422 if (flags_present & AUF)
423 *packed_cond |= cond->auf - V3D_QPU_UF_ANDZ + 4;
424 if (flags_present & MUF)
425 *packed_cond |= cond->muf - V3D_QPU_UF_ANDZ + 4;
426
427 if (flags_present & AC)
428 *packed_cond |= (cond->ac - V3D_QPU_COND_IFA) << 2;
429
430 if (flags_present & MC) {
431 if (*packed_cond & (1 << 6))
432 *packed_cond |= (cond->mc -
433 V3D_QPU_COND_IFA) << 4;
434 else
435 *packed_cond |= (cond->mc -
436 V3D_QPU_COND_IFA) << 2;
437 }
438
439 return true;
440 }
441
442 return false;
443 }
444
445 /* Make a mapping of the table of opcodes in the spec. The opcode is
446 * determined by a combination of the opcode field, and in the case of 0 or
447 * 1-arg opcodes, the mux_b field as well.
448 */
449 #define MUX_MASK(bot, top) (((1 << (top + 1)) - 1) - ((1 << (bot)) - 1))
450 #define ANYMUX MUX_MASK(0, 7)
451
452 struct opcode_desc {
453 uint8_t opcode_first;
454 uint8_t opcode_last;
455 uint8_t mux_b_mask;
456 uint8_t mux_a_mask;
457 uint8_t op;
458 /* 0 if it's the same across V3D versions, or a specific V3D version. */
459 uint8_t ver;
460 };
461
462 static const struct opcode_desc add_ops[] = {
463 /* FADD is FADDNF depending on the order of the mux_a/mux_b. */
464 { 0, 47, ANYMUX, ANYMUX, V3D_QPU_A_FADD },
465 { 0, 47, ANYMUX, ANYMUX, V3D_QPU_A_FADDNF },
466 { 53, 55, ANYMUX, ANYMUX, V3D_QPU_A_VFPACK },
467 { 56, 56, ANYMUX, ANYMUX, V3D_QPU_A_ADD },
468 { 57, 59, ANYMUX, ANYMUX, V3D_QPU_A_VFPACK },
469 { 60, 60, ANYMUX, ANYMUX, V3D_QPU_A_SUB },
470 { 61, 63, ANYMUX, ANYMUX, V3D_QPU_A_VFPACK },
471 { 64, 111, ANYMUX, ANYMUX, V3D_QPU_A_FSUB },
472 { 120, 120, ANYMUX, ANYMUX, V3D_QPU_A_MIN },
473 { 121, 121, ANYMUX, ANYMUX, V3D_QPU_A_MAX },
474 { 122, 122, ANYMUX, ANYMUX, V3D_QPU_A_UMIN },
475 { 123, 123, ANYMUX, ANYMUX, V3D_QPU_A_UMAX },
476 { 124, 124, ANYMUX, ANYMUX, V3D_QPU_A_SHL },
477 { 125, 125, ANYMUX, ANYMUX, V3D_QPU_A_SHR },
478 { 126, 126, ANYMUX, ANYMUX, V3D_QPU_A_ASR },
479 { 127, 127, ANYMUX, ANYMUX, V3D_QPU_A_ROR },
480 /* FMIN is instead FMAX depending on the order of the mux_a/mux_b. */
481 { 128, 175, ANYMUX, ANYMUX, V3D_QPU_A_FMIN },
482 { 128, 175, ANYMUX, ANYMUX, V3D_QPU_A_FMAX },
483 { 176, 180, ANYMUX, ANYMUX, V3D_QPU_A_VFMIN },
484
485 { 181, 181, ANYMUX, ANYMUX, V3D_QPU_A_AND },
486 { 182, 182, ANYMUX, ANYMUX, V3D_QPU_A_OR },
487 { 183, 183, ANYMUX, ANYMUX, V3D_QPU_A_XOR },
488
489 { 184, 184, ANYMUX, ANYMUX, V3D_QPU_A_VADD },
490 { 185, 185, ANYMUX, ANYMUX, V3D_QPU_A_VSUB },
491 { 186, 186, 1 << 0, ANYMUX, V3D_QPU_A_NOT },
492 { 186, 186, 1 << 1, ANYMUX, V3D_QPU_A_NEG },
493 { 186, 186, 1 << 2, ANYMUX, V3D_QPU_A_FLAPUSH },
494 { 186, 186, 1 << 3, ANYMUX, V3D_QPU_A_FLBPUSH },
495 { 186, 186, 1 << 4, ANYMUX, V3D_QPU_A_FLBPOP },
496 { 186, 186, 1 << 6, ANYMUX, V3D_QPU_A_SETMSF },
497 { 186, 186, 1 << 7, ANYMUX, V3D_QPU_A_SETREVF },
498 { 187, 187, 1 << 0, 1 << 0, V3D_QPU_A_NOP, 0 },
499 { 187, 187, 1 << 0, 1 << 1, V3D_QPU_A_TIDX },
500 { 187, 187, 1 << 0, 1 << 2, V3D_QPU_A_EIDX },
501 { 187, 187, 1 << 0, 1 << 3, V3D_QPU_A_LR },
502 { 187, 187, 1 << 0, 1 << 4, V3D_QPU_A_VFLA },
503 { 187, 187, 1 << 0, 1 << 5, V3D_QPU_A_VFLNA },
504 { 187, 187, 1 << 0, 1 << 6, V3D_QPU_A_VFLB },
505 { 187, 187, 1 << 0, 1 << 7, V3D_QPU_A_VFLNB },
506
507 { 187, 187, 1 << 1, MUX_MASK(0, 2), V3D_QPU_A_FXCD },
508 { 187, 187, 1 << 1, 1 << 3, V3D_QPU_A_XCD },
509 { 187, 187, 1 << 1, MUX_MASK(4, 6), V3D_QPU_A_FYCD },
510 { 187, 187, 1 << 1, 1 << 7, V3D_QPU_A_YCD },
511
512 { 187, 187, 1 << 2, 1 << 0, V3D_QPU_A_MSF },
513 { 187, 187, 1 << 2, 1 << 1, V3D_QPU_A_REVF },
514 { 187, 187, 1 << 2, 1 << 2, V3D_QPU_A_VDWWT },
515 { 187, 187, 1 << 2, 1 << 5, V3D_QPU_A_TMUWT },
516 { 187, 187, 1 << 2, 1 << 6, V3D_QPU_A_VPMWT },
517
518 { 187, 187, 1 << 3, ANYMUX, V3D_QPU_A_VPMSETUP },
519
520 /* FIXME: MORE COMPLICATED */
521 /* { 190, 191, ANYMUX, ANYMUX, V3D_QPU_A_VFMOVABSNEGNAB }, */
522
523 { 192, 239, ANYMUX, ANYMUX, V3D_QPU_A_FCMP },
524 { 240, 244, ANYMUX, ANYMUX, V3D_QPU_A_VFMAX },
525
526 { 245, 245, MUX_MASK(0, 2), ANYMUX, V3D_QPU_A_FROUND },
527 { 245, 245, 1 << 3, ANYMUX, V3D_QPU_A_FTOIN },
528 { 245, 245, MUX_MASK(4, 6), ANYMUX, V3D_QPU_A_FTRUNC },
529 { 245, 245, 1 << 7, ANYMUX, V3D_QPU_A_FTOIZ },
530 { 246, 246, MUX_MASK(0, 2), ANYMUX, V3D_QPU_A_FFLOOR },
531 { 246, 246, 1 << 3, ANYMUX, V3D_QPU_A_FTOUZ },
532 { 246, 246, MUX_MASK(4, 6), ANYMUX, V3D_QPU_A_FCEIL },
533 { 246, 246, 1 << 7, ANYMUX, V3D_QPU_A_FTOC },
534
535 { 247, 247, MUX_MASK(0, 2), ANYMUX, V3D_QPU_A_FDX },
536 { 247, 247, MUX_MASK(4, 6), ANYMUX, V3D_QPU_A_FDY },
537
538 /* The stvpms are distinguished by the waddr field. */
539 { 248, 248, ANYMUX, ANYMUX, V3D_QPU_A_STVPMV },
540 { 248, 248, ANYMUX, ANYMUX, V3D_QPU_A_STVPMD },
541 { 248, 248, ANYMUX, ANYMUX, V3D_QPU_A_STVPMP },
542
543 { 252, 252, MUX_MASK(0, 2), ANYMUX, V3D_QPU_A_ITOF },
544 { 252, 252, 1 << 3, ANYMUX, V3D_QPU_A_CLZ },
545 { 252, 252, MUX_MASK(4, 6), ANYMUX, V3D_QPU_A_UTOF },
546 };
547
548 static const struct opcode_desc mul_ops[] = {
549 { 1, 1, ANYMUX, ANYMUX, V3D_QPU_M_ADD },
550 { 2, 2, ANYMUX, ANYMUX, V3D_QPU_M_SUB },
551 { 3, 3, ANYMUX, ANYMUX, V3D_QPU_M_UMUL24 },
552 { 4, 8, ANYMUX, ANYMUX, V3D_QPU_M_VFMUL },
553 { 9, 9, ANYMUX, ANYMUX, V3D_QPU_M_SMUL24 },
554 { 10, 10, ANYMUX, ANYMUX, V3D_QPU_M_MULTOP },
555 { 14, 14, ANYMUX, ANYMUX, V3D_QPU_M_FMOV },
556 { 15, 15, MUX_MASK(0, 3), ANYMUX, V3D_QPU_M_FMOV },
557 { 15, 15, 1 << 4, 1 << 0, V3D_QPU_M_NOP, 0 },
558 { 15, 15, 1 << 7, ANYMUX, V3D_QPU_M_MOV },
559 { 16, 63, ANYMUX, ANYMUX, V3D_QPU_M_FMUL },
560 };
561
562 static const struct opcode_desc *
563 lookup_opcode(const struct opcode_desc *opcodes, size_t num_opcodes,
564 uint32_t opcode, uint32_t mux_a, uint32_t mux_b)
565 {
566 for (int i = 0; i < num_opcodes; i++) {
567 const struct opcode_desc *op_desc = &opcodes[i];
568
569 if (opcode < op_desc->opcode_first ||
570 opcode > op_desc->opcode_last)
571 continue;
572
573 if (!(op_desc->mux_b_mask & (1 << mux_b)))
574 continue;
575
576 if (!(op_desc->mux_a_mask & (1 << mux_a)))
577 continue;
578
579 return op_desc;
580 }
581
582 return NULL;
583 }
584
585 static bool
586 v3d_qpu_float32_unpack_unpack(uint32_t packed,
587 enum v3d_qpu_input_unpack *unpacked)
588 {
589 switch (packed) {
590 case 0:
591 *unpacked = V3D_QPU_UNPACK_ABS;
592 return true;
593 case 1:
594 *unpacked = V3D_QPU_UNPACK_NONE;
595 return true;
596 case 2:
597 *unpacked = V3D_QPU_UNPACK_L;
598 return true;
599 case 3:
600 *unpacked = V3D_QPU_UNPACK_H;
601 return true;
602 default:
603 return false;
604 }
605 }
606
607 static bool
608 v3d_qpu_float32_unpack_pack(enum v3d_qpu_input_unpack unpacked,
609 uint32_t *packed)
610 {
611 switch (unpacked) {
612 case V3D_QPU_UNPACK_ABS:
613 *packed = 0;
614 return true;
615 case V3D_QPU_UNPACK_NONE:
616 *packed = 1;
617 return true;
618 case V3D_QPU_UNPACK_L:
619 *packed = 2;
620 return true;
621 case V3D_QPU_UNPACK_H:
622 *packed = 3;
623 return true;
624 default:
625 return false;
626 }
627 }
628
629 static bool
630 v3d_qpu_float16_unpack_unpack(uint32_t packed,
631 enum v3d_qpu_input_unpack *unpacked)
632 {
633 switch (packed) {
634 case 0:
635 *unpacked = V3D_QPU_UNPACK_NONE;
636 return true;
637 case 1:
638 *unpacked = V3D_QPU_UNPACK_REPLICATE_32F_16;
639 return true;
640 case 2:
641 *unpacked = V3D_QPU_UNPACK_REPLICATE_L_16;
642 return true;
643 case 3:
644 *unpacked = V3D_QPU_UNPACK_REPLICATE_H_16;
645 return true;
646 case 4:
647 *unpacked = V3D_QPU_UNPACK_SWAP_16;
648 return true;
649 default:
650 return false;
651 }
652 }
653
654 static bool
655 v3d_qpu_float16_unpack_pack(enum v3d_qpu_input_unpack unpacked,
656 uint32_t *packed)
657 {
658 switch (unpacked) {
659 case V3D_QPU_UNPACK_NONE:
660 *packed = 0;
661 return true;
662 case V3D_QPU_UNPACK_REPLICATE_32F_16:
663 *packed = 1;
664 return true;
665 case V3D_QPU_UNPACK_REPLICATE_L_16:
666 *packed = 2;
667 return true;
668 case V3D_QPU_UNPACK_REPLICATE_H_16:
669 *packed = 3;
670 return true;
671 case V3D_QPU_UNPACK_SWAP_16:
672 *packed = 4;
673 return true;
674 default:
675 return false;
676 }
677 }
678
679 static bool
680 v3d_qpu_float32_pack_pack(enum v3d_qpu_input_unpack unpacked,
681 uint32_t *packed)
682 {
683 switch (unpacked) {
684 case V3D_QPU_PACK_NONE:
685 *packed = 0;
686 return true;
687 case V3D_QPU_PACK_L:
688 *packed = 1;
689 return true;
690 case V3D_QPU_PACK_H:
691 *packed = 2;
692 return true;
693 default:
694 return false;
695 }
696 }
697
698 static bool
699 v3d_qpu_add_unpack(const struct v3d_device_info *devinfo, uint64_t packed_inst,
700 struct v3d_qpu_instr *instr)
701 {
702 uint32_t op = QPU_GET_FIELD(packed_inst, VC5_QPU_OP_ADD);
703 uint32_t mux_a = QPU_GET_FIELD(packed_inst, VC5_QPU_ADD_A);
704 uint32_t mux_b = QPU_GET_FIELD(packed_inst, VC5_QPU_ADD_B);
705 uint32_t waddr = QPU_GET_FIELD(packed_inst, V3D_QPU_WADDR_A);
706
707 uint32_t map_op = op;
708 /* Some big clusters of opcodes are replicated with unpack
709 * flags
710 */
711 if (map_op >= 249 && map_op <= 251)
712 map_op = (map_op - 249 + 245);
713 if (map_op >= 253 && map_op <= 255)
714 map_op = (map_op - 253 + 245);
715
716 const struct opcode_desc *desc =
717 lookup_opcode(add_ops, ARRAY_SIZE(add_ops),
718 map_op, mux_a, mux_b);
719 if (!desc)
720 return false;
721
722 instr->alu.add.op = desc->op;
723
724 /* FADD/FADDNF and FMIN/FMAX are determined by the orders of the
725 * operands.
726 */
727 if (((op >> 2) & 3) * 8 + mux_a > (op & 3) * 8 + mux_b) {
728 if (instr->alu.add.op == V3D_QPU_A_FMIN)
729 instr->alu.add.op = V3D_QPU_A_FMAX;
730 if (instr->alu.add.op == V3D_QPU_A_FADD)
731 instr->alu.add.op = V3D_QPU_A_FADDNF;
732 }
733
734 /* Some QPU ops require a bit more than just basic opcode and mux a/b
735 * comparisons to distinguish them.
736 */
737 switch (instr->alu.add.op) {
738 case V3D_QPU_A_STVPMV:
739 case V3D_QPU_A_STVPMD:
740 case V3D_QPU_A_STVPMP:
741 switch (waddr) {
742 case 0:
743 instr->alu.add.op = V3D_QPU_A_STVPMV;
744 break;
745 case 1:
746 instr->alu.add.op = V3D_QPU_A_STVPMD;
747 break;
748 case 2:
749 instr->alu.add.op = V3D_QPU_A_STVPMP;
750 break;
751 default:
752 return false;
753 }
754 break;
755 default:
756 break;
757 }
758
759 switch (instr->alu.add.op) {
760 case V3D_QPU_A_FADD:
761 case V3D_QPU_A_FADDNF:
762 case V3D_QPU_A_FSUB:
763 case V3D_QPU_A_FMIN:
764 case V3D_QPU_A_FMAX:
765 case V3D_QPU_A_FCMP:
766 instr->alu.add.output_pack = (op >> 4) & 0x3;
767
768 if (!v3d_qpu_float32_unpack_unpack((op >> 2) & 0x3,
769 &instr->alu.add.a_unpack)) {
770 return false;
771 }
772
773 if (!v3d_qpu_float32_unpack_unpack((op >> 0) & 0x3,
774 &instr->alu.add.b_unpack)) {
775 return false;
776 }
777 break;
778
779 case V3D_QPU_A_FFLOOR:
780 case V3D_QPU_A_FROUND:
781 case V3D_QPU_A_FTRUNC:
782 case V3D_QPU_A_FCEIL:
783 case V3D_QPU_A_FDX:
784 case V3D_QPU_A_FDY:
785 instr->alu.add.output_pack = mux_b & 0x3;
786
787 if (!v3d_qpu_float32_unpack_unpack((op >> 2) & 0x3,
788 &instr->alu.add.a_unpack)) {
789 return false;
790 }
791 break;
792
793 case V3D_QPU_A_FTOIN:
794 case V3D_QPU_A_FTOIZ:
795 case V3D_QPU_A_FTOUZ:
796 case V3D_QPU_A_FTOC:
797 instr->alu.add.output_pack = V3D_QPU_PACK_NONE;
798
799 if (!v3d_qpu_float32_unpack_unpack((op >> 2) & 0x3,
800 &instr->alu.add.a_unpack)) {
801 return false;
802 }
803 break;
804
805 case V3D_QPU_A_VFMIN:
806 case V3D_QPU_A_VFMAX:
807 if (!v3d_qpu_float16_unpack_unpack(op & 0x7,
808 &instr->alu.add.a_unpack)) {
809 return false;
810 }
811
812 instr->alu.add.output_pack = V3D_QPU_PACK_NONE;
813 instr->alu.add.b_unpack = V3D_QPU_UNPACK_NONE;
814 break;
815
816 default:
817 instr->alu.add.output_pack = V3D_QPU_PACK_NONE;
818 instr->alu.add.a_unpack = V3D_QPU_UNPACK_NONE;
819 instr->alu.add.b_unpack = V3D_QPU_UNPACK_NONE;
820 break;
821 }
822
823 instr->alu.add.a = mux_a;
824 instr->alu.add.b = mux_b;
825 instr->alu.add.waddr = QPU_GET_FIELD(packed_inst, V3D_QPU_WADDR_A);
826 instr->alu.add.magic_write = packed_inst & VC5_QPU_MA;
827
828 return true;
829 }
830
831 static bool
832 v3d_qpu_mul_unpack(const struct v3d_device_info *devinfo, uint64_t packed_inst,
833 struct v3d_qpu_instr *instr)
834 {
835 uint32_t op = QPU_GET_FIELD(packed_inst, VC5_QPU_OP_MUL);
836 uint32_t mux_a = QPU_GET_FIELD(packed_inst, VC5_QPU_MUL_A);
837 uint32_t mux_b = QPU_GET_FIELD(packed_inst, VC5_QPU_MUL_B);
838
839 {
840 const struct opcode_desc *desc =
841 lookup_opcode(mul_ops, ARRAY_SIZE(mul_ops),
842 op, mux_a, mux_b);
843 if (!desc)
844 return false;
845
846 instr->alu.mul.op = desc->op;
847 }
848
849 switch (instr->alu.mul.op) {
850 case V3D_QPU_M_FMUL:
851 instr->alu.mul.output_pack = ((op >> 4) & 0x3) - 1;
852
853 if (!v3d_qpu_float32_unpack_unpack((op >> 2) & 0x3,
854 &instr->alu.mul.a_unpack)) {
855 return false;
856 }
857
858 if (!v3d_qpu_float32_unpack_unpack((op >> 0) & 0x3,
859 &instr->alu.mul.b_unpack)) {
860 return false;
861 }
862
863 break;
864
865 case V3D_QPU_M_FMOV:
866 instr->alu.mul.output_pack = (((op & 1) << 1) +
867 ((mux_b >> 2) & 1));
868
869 if (!v3d_qpu_float32_unpack_unpack(mux_b & 0x3,
870 &instr->alu.mul.a_unpack)) {
871 return false;
872 }
873
874 break;
875
876 case V3D_QPU_M_VFMUL:
877 instr->alu.mul.output_pack = V3D_QPU_PACK_NONE;
878
879 if (!v3d_qpu_float16_unpack_unpack(((op & 0x7) - 4) & 7,
880 &instr->alu.mul.a_unpack)) {
881 return false;
882 }
883
884 instr->alu.mul.b_unpack = V3D_QPU_UNPACK_NONE;
885
886 break;
887
888 default:
889 instr->alu.mul.output_pack = V3D_QPU_PACK_NONE;
890 instr->alu.mul.a_unpack = V3D_QPU_UNPACK_NONE;
891 instr->alu.mul.b_unpack = V3D_QPU_UNPACK_NONE;
892 break;
893 }
894
895 instr->alu.mul.a = mux_a;
896 instr->alu.mul.b = mux_b;
897 instr->alu.mul.waddr = QPU_GET_FIELD(packed_inst, V3D_QPU_WADDR_M);
898 instr->alu.mul.magic_write = packed_inst & VC5_QPU_MM;
899
900 return true;
901 }
902
903 static bool
904 v3d_qpu_add_pack(const struct v3d_device_info *devinfo,
905 const struct v3d_qpu_instr *instr, uint64_t *packed_instr)
906 {
907 uint32_t waddr = instr->alu.add.waddr;
908 uint32_t mux_a = instr->alu.add.a;
909 uint32_t mux_b = instr->alu.add.b;
910 int nsrc = v3d_qpu_add_op_num_src(instr->alu.add.op);
911 const struct opcode_desc *desc;
912
913 int opcode;
914 for (desc = add_ops; desc != &add_ops[ARRAY_SIZE(add_ops)];
915 desc++) {
916 if (desc->op == instr->alu.add.op)
917 break;
918 }
919 if (desc == &add_ops[ARRAY_SIZE(add_ops)])
920 return false;
921
922 opcode = desc->opcode_first;
923
924 /* If an operation doesn't use an arg, its mux values may be used to
925 * identify the operation type.
926 */
927 if (nsrc < 2)
928 mux_b = ffs(desc->mux_b_mask) - 1;
929
930 if (nsrc < 1)
931 mux_a = ffs(desc->mux_a_mask) - 1;
932
933 switch (instr->alu.add.op) {
934 case V3D_QPU_A_STVPMV:
935 waddr = 0;
936 break;
937 case V3D_QPU_A_STVPMD:
938 waddr = 1;
939 break;
940 case V3D_QPU_A_STVPMP:
941 waddr = 2;
942 break;
943 default:
944 break;
945 }
946
947 switch (instr->alu.add.op) {
948 case V3D_QPU_A_FADD:
949 case V3D_QPU_A_FADDNF:
950 case V3D_QPU_A_FSUB:
951 case V3D_QPU_A_FMIN:
952 case V3D_QPU_A_FMAX:
953 case V3D_QPU_A_FCMP: {
954 uint32_t output_pack;
955 uint32_t a_unpack;
956 uint32_t b_unpack;
957
958 if (!v3d_qpu_float32_pack_pack(instr->alu.add.output_pack,
959 &output_pack)) {
960 return false;
961 }
962 opcode |= output_pack << 4;
963
964 if (!v3d_qpu_float32_unpack_pack(instr->alu.add.a_unpack,
965 &a_unpack)) {
966 return false;
967 }
968
969 if (!v3d_qpu_float32_unpack_pack(instr->alu.add.b_unpack,
970 &b_unpack)) {
971 return false;
972 }
973
974 /* These operations with commutative operands are
975 * distinguished by which order their operands come in.
976 */
977 bool ordering = a_unpack * 8 + mux_a > b_unpack * 8 + mux_b;
978 if (((instr->alu.add.op == V3D_QPU_A_FMIN ||
979 instr->alu.add.op == V3D_QPU_A_FADD) && ordering) ||
980 ((instr->alu.add.op == V3D_QPU_A_FMAX ||
981 instr->alu.add.op == V3D_QPU_A_FADDNF) && !ordering)) {
982 uint32_t temp;
983
984 temp = a_unpack;
985 a_unpack = b_unpack;
986 b_unpack = temp;
987
988 temp = mux_a;
989 mux_a = mux_b;
990 mux_b = temp;
991 }
992
993 opcode |= a_unpack << 2;
994 opcode |= b_unpack << 0;
995 break;
996 }
997
998 case V3D_QPU_A_FFLOOR:
999 case V3D_QPU_A_FROUND:
1000 case V3D_QPU_A_FTRUNC:
1001 case V3D_QPU_A_FCEIL:
1002 case V3D_QPU_A_FDX:
1003 case V3D_QPU_A_FDY: {
1004 uint32_t packed;
1005
1006 if (!v3d_qpu_float32_pack_pack(instr->alu.add.output_pack,
1007 &packed)) {
1008 return false;
1009 }
1010 mux_b |= packed;
1011
1012 if (!v3d_qpu_float32_unpack_pack(instr->alu.add.a_unpack,
1013 &packed)) {
1014 return false;
1015 }
1016 if (packed == 0)
1017 return false;
1018 opcode |= packed << 2;
1019 break;
1020 }
1021
1022 case V3D_QPU_A_FTOIN:
1023 case V3D_QPU_A_FTOIZ:
1024 case V3D_QPU_A_FTOUZ:
1025 case V3D_QPU_A_FTOC:
1026 if (instr->alu.add.output_pack != V3D_QPU_PACK_NONE)
1027 return false;
1028
1029 uint32_t packed;
1030 if (!v3d_qpu_float32_unpack_pack(instr->alu.add.a_unpack,
1031 &packed)) {
1032 return false;
1033 }
1034 if (packed == 0)
1035 return false;
1036 opcode |= packed << 2;
1037
1038 break;
1039
1040 case V3D_QPU_A_VFMIN:
1041 case V3D_QPU_A_VFMAX:
1042 if (instr->alu.add.output_pack != V3D_QPU_PACK_NONE ||
1043 instr->alu.add.b_unpack != V3D_QPU_UNPACK_NONE) {
1044 return false;
1045 }
1046
1047 if (!v3d_qpu_float16_unpack_pack(instr->alu.add.a_unpack,
1048 &packed)) {
1049 return false;
1050 }
1051 opcode |= packed;
1052 break;
1053
1054 default:
1055 if (instr->alu.add.op != V3D_QPU_A_NOP &&
1056 (instr->alu.add.output_pack != V3D_QPU_PACK_NONE ||
1057 instr->alu.add.a_unpack != V3D_QPU_UNPACK_NONE ||
1058 instr->alu.add.b_unpack != V3D_QPU_UNPACK_NONE)) {
1059 return false;
1060 }
1061 break;
1062 }
1063
1064 *packed_instr |= QPU_SET_FIELD(mux_a, VC5_QPU_ADD_A);
1065 *packed_instr |= QPU_SET_FIELD(mux_b, VC5_QPU_ADD_B);
1066 *packed_instr |= QPU_SET_FIELD(opcode, VC5_QPU_OP_ADD);
1067 *packed_instr |= QPU_SET_FIELD(waddr, V3D_QPU_WADDR_A);
1068 if (instr->alu.add.magic_write)
1069 *packed_instr |= VC5_QPU_MA;
1070
1071 return true;
1072 }
1073
1074 static bool
1075 v3d_qpu_mul_pack(const struct v3d_device_info *devinfo,
1076 const struct v3d_qpu_instr *instr, uint64_t *packed_instr)
1077 {
1078 uint32_t mux_a = instr->alu.mul.a;
1079 uint32_t mux_b = instr->alu.mul.b;
1080 int nsrc = v3d_qpu_mul_op_num_src(instr->alu.mul.op);
1081 const struct opcode_desc *desc;
1082
1083 for (desc = mul_ops; desc != &mul_ops[ARRAY_SIZE(mul_ops)];
1084 desc++) {
1085 if (desc->op == instr->alu.mul.op)
1086 break;
1087 }
1088 if (desc == &mul_ops[ARRAY_SIZE(mul_ops)])
1089 return false;
1090
1091 uint32_t opcode = desc->opcode_first;
1092
1093 /* Some opcodes have a single valid value for their mux a/b, so set
1094 * that here. If mux a/b determine packing, it will be set below.
1095 */
1096 if (nsrc < 2)
1097 mux_b = ffs(desc->mux_b_mask) - 1;
1098
1099 if (nsrc < 1)
1100 mux_a = ffs(desc->mux_a_mask) - 1;
1101
1102 switch (instr->alu.mul.op) {
1103 case V3D_QPU_M_FMUL: {
1104 uint32_t packed;
1105
1106 if (!v3d_qpu_float32_pack_pack(instr->alu.mul.output_pack,
1107 &packed)) {
1108 return false;
1109 }
1110 /* No need for a +1 because desc->opcode_first has a 1 in this
1111 * field.
1112 */
1113 opcode += packed << 4;
1114
1115 if (!v3d_qpu_float32_unpack_pack(instr->alu.mul.a_unpack,
1116 &packed)) {
1117 return false;
1118 }
1119 opcode |= packed << 2;
1120
1121 if (!v3d_qpu_float32_unpack_pack(instr->alu.mul.b_unpack,
1122 &packed)) {
1123 return false;
1124 }
1125 opcode |= packed << 0;
1126 break;
1127 }
1128
1129 case V3D_QPU_M_FMOV: {
1130 uint32_t packed;
1131
1132 if (!v3d_qpu_float32_pack_pack(instr->alu.mul.output_pack,
1133 &packed)) {
1134 return false;
1135 }
1136 opcode |= (packed >> 1) & 1;
1137 mux_b = (packed & 1) << 2;
1138
1139 if (!v3d_qpu_float32_unpack_pack(instr->alu.mul.a_unpack,
1140 &packed)) {
1141 return false;
1142 }
1143 mux_b |= packed;
1144 break;
1145 }
1146
1147 case V3D_QPU_M_VFMUL: {
1148 uint32_t packed;
1149
1150 if (instr->alu.mul.output_pack != V3D_QPU_PACK_NONE)
1151 return false;
1152
1153 if (!v3d_qpu_float16_unpack_pack(instr->alu.mul.a_unpack,
1154 &packed)) {
1155 return false;
1156 }
1157 if (instr->alu.mul.a_unpack == V3D_QPU_UNPACK_SWAP_16)
1158 opcode = 8;
1159 else
1160 opcode |= (packed + 4) & 7;
1161
1162 if (instr->alu.mul.b_unpack != V3D_QPU_UNPACK_NONE)
1163 return false;
1164
1165 break;
1166 }
1167
1168 default:
1169 break;
1170 }
1171
1172 *packed_instr |= QPU_SET_FIELD(mux_a, VC5_QPU_MUL_A);
1173 *packed_instr |= QPU_SET_FIELD(mux_b, VC5_QPU_MUL_B);
1174
1175 *packed_instr |= QPU_SET_FIELD(opcode, VC5_QPU_OP_MUL);
1176 *packed_instr |= QPU_SET_FIELD(instr->alu.mul.waddr, V3D_QPU_WADDR_M);
1177 if (instr->alu.mul.magic_write)
1178 *packed_instr |= VC5_QPU_MM;
1179
1180 return true;
1181 }
1182
1183 static bool
1184 v3d_qpu_instr_unpack_alu(const struct v3d_device_info *devinfo,
1185 uint64_t packed_instr,
1186 struct v3d_qpu_instr *instr)
1187 {
1188 instr->type = V3D_QPU_INSTR_TYPE_ALU;
1189
1190 if (!v3d_qpu_sig_unpack(devinfo,
1191 QPU_GET_FIELD(packed_instr, VC5_QPU_SIG),
1192 &instr->sig))
1193 return false;
1194
1195 uint32_t packed_cond = QPU_GET_FIELD(packed_instr, VC5_QPU_COND);
1196 if (v3d_qpu_sig_writes_address(devinfo, &instr->sig)) {
1197 instr->sig_addr = packed_cond & ~VC5_QPU_COND_SIG_MAGIC_ADDR;
1198 instr->sig_magic = packed_cond & VC5_QPU_COND_SIG_MAGIC_ADDR;
1199
1200 instr->flags.ac = V3D_QPU_COND_NONE;
1201 instr->flags.mc = V3D_QPU_COND_NONE;
1202 instr->flags.apf = V3D_QPU_PF_NONE;
1203 instr->flags.mpf = V3D_QPU_PF_NONE;
1204 instr->flags.auf = V3D_QPU_UF_NONE;
1205 instr->flags.muf = V3D_QPU_UF_NONE;
1206 } else {
1207 if (!v3d_qpu_flags_unpack(devinfo, packed_cond, &instr->flags))
1208 return false;
1209 }
1210
1211 instr->raddr_a = QPU_GET_FIELD(packed_instr, VC5_QPU_RADDR_A);
1212 instr->raddr_b = QPU_GET_FIELD(packed_instr, VC5_QPU_RADDR_B);
1213
1214 if (!v3d_qpu_add_unpack(devinfo, packed_instr, instr))
1215 return false;
1216
1217 if (!v3d_qpu_mul_unpack(devinfo, packed_instr, instr))
1218 return false;
1219
1220 return true;
1221 }
1222
1223 static bool
1224 v3d_qpu_instr_unpack_branch(const struct v3d_device_info *devinfo,
1225 uint64_t packed_instr,
1226 struct v3d_qpu_instr *instr)
1227 {
1228 instr->type = V3D_QPU_INSTR_TYPE_BRANCH;
1229
1230 uint32_t cond = QPU_GET_FIELD(packed_instr, VC5_QPU_BRANCH_COND);
1231 if (cond == 0)
1232 instr->branch.cond = V3D_QPU_BRANCH_COND_ALWAYS;
1233 else if (V3D_QPU_BRANCH_COND_A0 + (cond - 2) <=
1234 V3D_QPU_BRANCH_COND_ALLNA)
1235 instr->branch.cond = V3D_QPU_BRANCH_COND_A0 + (cond - 2);
1236 else
1237 return false;
1238
1239 uint32_t msfign = QPU_GET_FIELD(packed_instr, VC5_QPU_BRANCH_MSFIGN);
1240 if (msfign == 3)
1241 return false;
1242 instr->branch.msfign = msfign;
1243
1244 instr->branch.bdi = QPU_GET_FIELD(packed_instr, VC5_QPU_BRANCH_BDI);
1245
1246 instr->branch.ub = packed_instr & VC5_QPU_BRANCH_UB;
1247 if (instr->branch.ub) {
1248 instr->branch.bdu = QPU_GET_FIELD(packed_instr,
1249 VC5_QPU_BRANCH_BDU);
1250 }
1251
1252 instr->branch.raddr_a = QPU_GET_FIELD(packed_instr,
1253 VC5_QPU_RADDR_A);
1254
1255 instr->branch.offset = 0;
1256
1257 instr->branch.offset +=
1258 QPU_GET_FIELD(packed_instr,
1259 VC5_QPU_BRANCH_ADDR_LOW) << 3;
1260
1261 instr->branch.offset +=
1262 QPU_GET_FIELD(packed_instr,
1263 VC5_QPU_BRANCH_ADDR_HIGH) << 24;
1264
1265 return true;
1266 }
1267
1268 bool
1269 v3d_qpu_instr_unpack(const struct v3d_device_info *devinfo,
1270 uint64_t packed_instr,
1271 struct v3d_qpu_instr *instr)
1272 {
1273 if (QPU_GET_FIELD(packed_instr, VC5_QPU_OP_MUL) != 0) {
1274 return v3d_qpu_instr_unpack_alu(devinfo, packed_instr, instr);
1275 } else {
1276 uint32_t sig = QPU_GET_FIELD(packed_instr, VC5_QPU_SIG);
1277
1278 if ((sig & 24) == 16) {
1279 return v3d_qpu_instr_unpack_branch(devinfo, packed_instr,
1280 instr);
1281 } else {
1282 return false;
1283 }
1284 }
1285 }
1286
1287 static bool
1288 v3d_qpu_instr_pack_alu(const struct v3d_device_info *devinfo,
1289 const struct v3d_qpu_instr *instr,
1290 uint64_t *packed_instr)
1291 {
1292 uint32_t sig;
1293 if (!v3d_qpu_sig_pack(devinfo, &instr->sig, &sig))
1294 return false;
1295 *packed_instr |= QPU_SET_FIELD(sig, VC5_QPU_SIG);
1296
1297 if (instr->type == V3D_QPU_INSTR_TYPE_ALU) {
1298 *packed_instr |= QPU_SET_FIELD(instr->raddr_a, VC5_QPU_RADDR_A);
1299 *packed_instr |= QPU_SET_FIELD(instr->raddr_b, VC5_QPU_RADDR_B);
1300
1301 if (!v3d_qpu_add_pack(devinfo, instr, packed_instr))
1302 return false;
1303 if (!v3d_qpu_mul_pack(devinfo, instr, packed_instr))
1304 return false;
1305
1306 uint32_t flags;
1307 if (v3d_qpu_sig_writes_address(devinfo, &instr->sig)) {
1308 if (instr->flags.ac != V3D_QPU_COND_NONE ||
1309 instr->flags.mc != V3D_QPU_COND_NONE ||
1310 instr->flags.apf != V3D_QPU_PF_NONE ||
1311 instr->flags.mpf != V3D_QPU_PF_NONE ||
1312 instr->flags.auf != V3D_QPU_UF_NONE ||
1313 instr->flags.muf != V3D_QPU_UF_NONE) {
1314 return false;
1315 }
1316
1317 flags = instr->sig_addr;
1318 if (instr->sig_magic)
1319 flags |= VC5_QPU_COND_SIG_MAGIC_ADDR;
1320 } else {
1321 if (!v3d_qpu_flags_pack(devinfo, &instr->flags, &flags))
1322 return false;
1323 }
1324
1325 *packed_instr |= QPU_SET_FIELD(flags, VC5_QPU_COND);
1326 } else {
1327 if (v3d_qpu_sig_writes_address(devinfo, &instr->sig))
1328 return false;
1329 }
1330
1331 return true;
1332 }
1333
1334 static bool
1335 v3d_qpu_instr_pack_branch(const struct v3d_device_info *devinfo,
1336 const struct v3d_qpu_instr *instr,
1337 uint64_t *packed_instr)
1338 {
1339 *packed_instr |= QPU_SET_FIELD(16, VC5_QPU_SIG);
1340
1341 if (instr->branch.cond != V3D_QPU_BRANCH_COND_ALWAYS) {
1342 *packed_instr |= QPU_SET_FIELD(2 + (instr->branch.cond -
1343 V3D_QPU_BRANCH_COND_A0),
1344 VC5_QPU_BRANCH_COND);
1345 }
1346
1347 *packed_instr |= QPU_SET_FIELD(instr->branch.msfign,
1348 VC5_QPU_BRANCH_MSFIGN);
1349
1350 *packed_instr |= QPU_SET_FIELD(instr->branch.bdi,
1351 VC5_QPU_BRANCH_BDI);
1352
1353 if (instr->branch.ub) {
1354 *packed_instr |= VC5_QPU_BRANCH_UB;
1355 *packed_instr |= QPU_SET_FIELD(instr->branch.bdu,
1356 VC5_QPU_BRANCH_BDU);
1357 }
1358
1359 switch (instr->branch.bdi) {
1360 case V3D_QPU_BRANCH_DEST_ABS:
1361 case V3D_QPU_BRANCH_DEST_REL:
1362 *packed_instr |= QPU_SET_FIELD(instr->branch.msfign,
1363 VC5_QPU_BRANCH_MSFIGN);
1364
1365 *packed_instr |= QPU_SET_FIELD((instr->branch.offset &
1366 ~0xff000000) >> 3,
1367 VC5_QPU_BRANCH_ADDR_LOW);
1368
1369 *packed_instr |= QPU_SET_FIELD(instr->branch.offset >> 24,
1370 VC5_QPU_BRANCH_ADDR_HIGH);
1371
1372 case V3D_QPU_BRANCH_DEST_REGFILE:
1373 *packed_instr |= QPU_SET_FIELD(instr->branch.raddr_a,
1374 VC5_QPU_RADDR_A);
1375 break;
1376
1377 default:
1378 break;
1379 }
1380
1381 return true;
1382 }
1383
1384 bool
1385 v3d_qpu_instr_pack(const struct v3d_device_info *devinfo,
1386 const struct v3d_qpu_instr *instr,
1387 uint64_t *packed_instr)
1388 {
1389 *packed_instr = 0;
1390
1391 switch (instr->type) {
1392 case V3D_QPU_INSTR_TYPE_ALU:
1393 return v3d_qpu_instr_pack_alu(devinfo, instr, packed_instr);
1394 case V3D_QPU_INSTR_TYPE_BRANCH:
1395 return v3d_qpu_instr_pack_branch(devinfo, instr, packed_instr);
1396 default:
1397 return false;
1398 }
1399 }