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v3d: Add QPU pack/unpack for the new SFU instructions.
[mesa.git] / src / broadcom / qpu / qpu_pack.c
1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <string.h>
25 #include "util/macros.h"
26
27 #include "broadcom/common/v3d_device_info.h"
28 #include "qpu_instr.h"
29
30 #ifndef QPU_MASK
31 #define QPU_MASK(high, low) ((((uint64_t)1<<((high)-(low)+1))-1)<<(low))
32 /* Using the GNU statement expression extension */
33 #define QPU_SET_FIELD(value, field) \
34 ({ \
35 uint64_t fieldval = (uint64_t)(value) << field ## _SHIFT; \
36 assert((fieldval & ~ field ## _MASK) == 0); \
37 fieldval & field ## _MASK; \
38 })
39
40 #define QPU_GET_FIELD(word, field) ((uint32_t)(((word) & field ## _MASK) >> field ## _SHIFT))
41
42 #define QPU_UPDATE_FIELD(inst, value, field) \
43 (((inst) & ~(field ## _MASK)) | QPU_SET_FIELD(value, field))
44 #endif /* QPU_MASK */
45
46 #define VC5_QPU_OP_MUL_SHIFT 58
47 #define VC5_QPU_OP_MUL_MASK QPU_MASK(63, 58)
48
49 #define VC5_QPU_SIG_SHIFT 53
50 #define VC5_QPU_SIG_MASK QPU_MASK(57, 53)
51
52 #define VC5_QPU_COND_SHIFT 46
53 #define VC5_QPU_COND_MASK QPU_MASK(52, 46)
54 #define VC5_QPU_COND_SIG_MAGIC_ADDR (1 << 6)
55
56 #define VC5_QPU_MM QPU_MASK(45, 45)
57 #define VC5_QPU_MA QPU_MASK(44, 44)
58
59 #define V3D_QPU_WADDR_M_SHIFT 38
60 #define V3D_QPU_WADDR_M_MASK QPU_MASK(43, 38)
61
62 #define VC5_QPU_BRANCH_ADDR_LOW_SHIFT 35
63 #define VC5_QPU_BRANCH_ADDR_LOW_MASK QPU_MASK(55, 35)
64
65 #define V3D_QPU_WADDR_A_SHIFT 32
66 #define V3D_QPU_WADDR_A_MASK QPU_MASK(37, 32)
67
68 #define VC5_QPU_BRANCH_COND_SHIFT 32
69 #define VC5_QPU_BRANCH_COND_MASK QPU_MASK(34, 32)
70
71 #define VC5_QPU_BRANCH_ADDR_HIGH_SHIFT 24
72 #define VC5_QPU_BRANCH_ADDR_HIGH_MASK QPU_MASK(31, 24)
73
74 #define VC5_QPU_OP_ADD_SHIFT 24
75 #define VC5_QPU_OP_ADD_MASK QPU_MASK(31, 24)
76
77 #define VC5_QPU_MUL_B_SHIFT 21
78 #define VC5_QPU_MUL_B_MASK QPU_MASK(23, 21)
79
80 #define VC5_QPU_BRANCH_MSFIGN_SHIFT 21
81 #define VC5_QPU_BRANCH_MSFIGN_MASK QPU_MASK(22, 21)
82
83 #define VC5_QPU_MUL_A_SHIFT 18
84 #define VC5_QPU_MUL_A_MASK QPU_MASK(20, 18)
85
86 #define VC5_QPU_ADD_B_SHIFT 15
87 #define VC5_QPU_ADD_B_MASK QPU_MASK(17, 15)
88
89 #define VC5_QPU_BRANCH_BDU_SHIFT 15
90 #define VC5_QPU_BRANCH_BDU_MASK QPU_MASK(17, 15)
91
92 #define VC5_QPU_BRANCH_UB QPU_MASK(14, 14)
93
94 #define VC5_QPU_ADD_A_SHIFT 12
95 #define VC5_QPU_ADD_A_MASK QPU_MASK(14, 12)
96
97 #define VC5_QPU_BRANCH_BDI_SHIFT 12
98 #define VC5_QPU_BRANCH_BDI_MASK QPU_MASK(13, 12)
99
100 #define VC5_QPU_RADDR_A_SHIFT 6
101 #define VC5_QPU_RADDR_A_MASK QPU_MASK(11, 6)
102
103 #define VC5_QPU_RADDR_B_SHIFT 0
104 #define VC5_QPU_RADDR_B_MASK QPU_MASK(5, 0)
105
106 #define THRSW .thrsw = true
107 #define LDUNIF .ldunif = true
108 #define LDUNIFRF .ldunifrf = true
109 #define LDUNIFA .ldunifa = true
110 #define LDUNIFARF .ldunifarf = true
111 #define LDTMU .ldtmu = true
112 #define LDVARY .ldvary = true
113 #define LDVPM .ldvpm = true
114 #define SMIMM .small_imm = true
115 #define LDTLB .ldtlb = true
116 #define LDTLBU .ldtlbu = true
117 #define UCB .ucb = true
118 #define ROT .rotate = true
119 #define WRTMUC .wrtmuc = true
120
121 static const struct v3d_qpu_sig v33_sig_map[] = {
122 /* MISC R3 R4 R5 */
123 [0] = { },
124 [1] = { THRSW, },
125 [2] = { LDUNIF },
126 [3] = { THRSW, LDUNIF },
127 [4] = { LDTMU, },
128 [5] = { THRSW, LDTMU, },
129 [6] = { LDTMU, LDUNIF },
130 [7] = { THRSW, LDTMU, LDUNIF },
131 [8] = { LDVARY, },
132 [9] = { THRSW, LDVARY, },
133 [10] = { LDVARY, LDUNIF },
134 [11] = { THRSW, LDVARY, LDUNIF },
135 [12] = { LDVARY, LDTMU, },
136 [13] = { THRSW, LDVARY, LDTMU, },
137 [14] = { SMIMM, LDVARY, },
138 [15] = { SMIMM, },
139 [16] = { LDTLB, },
140 [17] = { LDTLBU, },
141 /* 18-21 reserved */
142 [22] = { UCB, },
143 [23] = { ROT, },
144 [24] = { LDVPM, },
145 [25] = { THRSW, LDVPM, },
146 [26] = { LDVPM, LDUNIF },
147 [27] = { THRSW, LDVPM, LDUNIF },
148 [28] = { LDVPM, LDTMU, },
149 [29] = { THRSW, LDVPM, LDTMU, },
150 [30] = { SMIMM, LDVPM, },
151 [31] = { SMIMM, },
152 };
153
154 static const struct v3d_qpu_sig v40_sig_map[] = {
155 /* MISC R3 R4 R5 */
156 [0] = { },
157 [1] = { THRSW, },
158 [2] = { LDUNIF },
159 [3] = { THRSW, LDUNIF },
160 [4] = { LDTMU, },
161 [5] = { THRSW, LDTMU, },
162 [6] = { LDTMU, LDUNIF },
163 [7] = { THRSW, LDTMU, LDUNIF },
164 [8] = { LDVARY, },
165 [9] = { THRSW, LDVARY, },
166 [10] = { LDVARY, LDUNIF },
167 [11] = { THRSW, LDVARY, LDUNIF },
168 /* 12-13 reserved */
169 [14] = { SMIMM, LDVARY, },
170 [15] = { SMIMM, },
171 [16] = { LDTLB, },
172 [17] = { LDTLBU, },
173 [18] = { WRTMUC },
174 [19] = { THRSW, WRTMUC },
175 [20] = { LDVARY, WRTMUC },
176 [21] = { THRSW, LDVARY, WRTMUC },
177 [22] = { UCB, },
178 [23] = { ROT, },
179 /* 24-30 reserved */
180 [31] = { SMIMM, LDTMU, },
181 };
182
183 static const struct v3d_qpu_sig v41_sig_map[] = {
184 /* MISC phys R5 */
185 [0] = { },
186 [1] = { THRSW, },
187 [2] = { LDUNIF },
188 [3] = { THRSW, LDUNIF },
189 [4] = { LDTMU, },
190 [5] = { THRSW, LDTMU, },
191 [6] = { LDTMU, LDUNIF },
192 [7] = { THRSW, LDTMU, LDUNIF },
193 [8] = { LDVARY, },
194 [9] = { THRSW, LDVARY, },
195 [10] = { LDVARY, LDUNIF },
196 [11] = { THRSW, LDVARY, LDUNIF },
197 [12] = { LDUNIFRF },
198 [13] = { THRSW, LDUNIFRF },
199 [14] = { SMIMM, LDVARY, },
200 [15] = { SMIMM, },
201 [16] = { LDTLB, },
202 [17] = { LDTLBU, },
203 [18] = { WRTMUC },
204 [19] = { THRSW, WRTMUC },
205 [20] = { LDVARY, WRTMUC },
206 [21] = { THRSW, LDVARY, WRTMUC },
207 [22] = { UCB, },
208 [23] = { ROT, },
209 /* 24-30 reserved */
210 [24] = { LDUNIFA},
211 [25] = { LDUNIFARF },
212 [31] = { SMIMM, LDTMU, },
213 };
214
215 bool
216 v3d_qpu_sig_unpack(const struct v3d_device_info *devinfo,
217 uint32_t packed_sig,
218 struct v3d_qpu_sig *sig)
219 {
220 if (packed_sig >= ARRAY_SIZE(v33_sig_map))
221 return false;
222
223 if (devinfo->ver >= 41)
224 *sig = v41_sig_map[packed_sig];
225 else if (devinfo->ver == 40)
226 *sig = v40_sig_map[packed_sig];
227 else
228 *sig = v33_sig_map[packed_sig];
229
230 /* Signals with zeroed unpacked contents after element 0 are reserved. */
231 return (packed_sig == 0 ||
232 memcmp(sig, &v33_sig_map[0], sizeof(*sig)) != 0);
233 }
234
235 bool
236 v3d_qpu_sig_pack(const struct v3d_device_info *devinfo,
237 const struct v3d_qpu_sig *sig,
238 uint32_t *packed_sig)
239 {
240 static const struct v3d_qpu_sig *map;
241
242 if (devinfo->ver >= 41)
243 map = v41_sig_map;
244 else if (devinfo->ver == 40)
245 map = v40_sig_map;
246 else
247 map = v33_sig_map;
248
249 for (int i = 0; i < ARRAY_SIZE(v33_sig_map); i++) {
250 if (memcmp(&map[i], sig, sizeof(*sig)) == 0) {
251 *packed_sig = i;
252 return true;
253 }
254 }
255
256 return false;
257 }
258 static inline unsigned
259 fui( float f )
260 {
261 union {float f; unsigned ui;} fi;
262 fi.f = f;
263 return fi.ui;
264 }
265
266 static const uint32_t small_immediates[] = {
267 0, 1, 2, 3,
268 4, 5, 6, 7,
269 8, 9, 10, 11,
270 12, 13, 14, 15,
271 -16, -15, -14, -13,
272 -12, -11, -10, -9,
273 -8, -7, -6, -5,
274 -4, -3, -2, -1,
275 0x3b800000, /* 2.0^-8 */
276 0x3c000000, /* 2.0^-7 */
277 0x3c800000, /* 2.0^-6 */
278 0x3d000000, /* 2.0^-5 */
279 0x3d800000, /* 2.0^-4 */
280 0x3e000000, /* 2.0^-3 */
281 0x3e800000, /* 2.0^-2 */
282 0x3f000000, /* 2.0^-1 */
283 0x3f800000, /* 2.0^0 */
284 0x40000000, /* 2.0^1 */
285 0x40800000, /* 2.0^2 */
286 0x41000000, /* 2.0^3 */
287 0x41800000, /* 2.0^4 */
288 0x42000000, /* 2.0^5 */
289 0x42800000, /* 2.0^6 */
290 0x43000000, /* 2.0^7 */
291 };
292
293 bool
294 v3d_qpu_small_imm_unpack(const struct v3d_device_info *devinfo,
295 uint32_t packed_small_immediate,
296 uint32_t *small_immediate)
297 {
298 if (packed_small_immediate >= ARRAY_SIZE(small_immediates))
299 return false;
300
301 *small_immediate = small_immediates[packed_small_immediate];
302 return true;
303 }
304
305 bool
306 v3d_qpu_small_imm_pack(const struct v3d_device_info *devinfo,
307 uint32_t value,
308 uint32_t *packed_small_immediate)
309 {
310 STATIC_ASSERT(ARRAY_SIZE(small_immediates) == 48);
311
312 for (int i = 0; i < ARRAY_SIZE(small_immediates); i++) {
313 if (small_immediates[i] == value) {
314 *packed_small_immediate = i;
315 return true;
316 }
317 }
318
319 return false;
320 }
321
322 bool
323 v3d_qpu_flags_unpack(const struct v3d_device_info *devinfo,
324 uint32_t packed_cond,
325 struct v3d_qpu_flags *cond)
326 {
327 static const enum v3d_qpu_cond cond_map[4] = {
328 [0] = V3D_QPU_COND_IFA,
329 [1] = V3D_QPU_COND_IFB,
330 [2] = V3D_QPU_COND_IFNA,
331 [3] = V3D_QPU_COND_IFNB,
332 };
333
334 cond->ac = V3D_QPU_COND_NONE;
335 cond->mc = V3D_QPU_COND_NONE;
336 cond->apf = V3D_QPU_PF_NONE;
337 cond->mpf = V3D_QPU_PF_NONE;
338 cond->auf = V3D_QPU_UF_NONE;
339 cond->muf = V3D_QPU_UF_NONE;
340
341 if (packed_cond == 0) {
342 return true;
343 } else if (packed_cond >> 2 == 0) {
344 cond->apf = packed_cond & 0x3;
345 } else if (packed_cond >> 4 == 0) {
346 cond->auf = (packed_cond & 0xf) - 4 + V3D_QPU_UF_ANDZ;
347 } else if (packed_cond == 0x10) {
348 return false;
349 } else if (packed_cond >> 2 == 0x4) {
350 cond->mpf = packed_cond & 0x3;
351 } else if (packed_cond >> 4 == 0x1) {
352 cond->muf = (packed_cond & 0xf) - 4 + V3D_QPU_UF_ANDZ;
353 } else if (packed_cond >> 4 == 0x2) {
354 cond->ac = ((packed_cond >> 2) & 0x3) + V3D_QPU_COND_IFA;
355 cond->mpf = packed_cond & 0x3;
356 } else if (packed_cond >> 4 == 0x3) {
357 cond->mc = ((packed_cond >> 2) & 0x3) + V3D_QPU_COND_IFA;
358 cond->apf = packed_cond & 0x3;
359 } else if (packed_cond >> 6) {
360 cond->mc = cond_map[(packed_cond >> 4) & 0x3];
361 if (((packed_cond >> 2) & 0x3) == 0) {
362 cond->ac = cond_map[packed_cond & 0x3];
363 } else {
364 cond->auf = (packed_cond & 0xf) - 4 + V3D_QPU_UF_ANDZ;
365 }
366 }
367
368 return true;
369 }
370
371 bool
372 v3d_qpu_flags_pack(const struct v3d_device_info *devinfo,
373 const struct v3d_qpu_flags *cond,
374 uint32_t *packed_cond)
375 {
376 #define AC (1 << 0)
377 #define MC (1 << 1)
378 #define APF (1 << 2)
379 #define MPF (1 << 3)
380 #define AUF (1 << 4)
381 #define MUF (1 << 5)
382 static const struct {
383 uint8_t flags_present;
384 uint8_t bits;
385 } flags_table[] = {
386 { 0, 0 },
387 { APF, 0 },
388 { AUF, 0 },
389 { MPF, (1 << 4) },
390 { MUF, (1 << 4) },
391 { AC, (1 << 5) },
392 { AC | MPF, (1 << 5) },
393 { MC, (1 << 5) | (1 << 4) },
394 { MC | APF, (1 << 5) | (1 << 4) },
395 { MC | AC, (1 << 6) },
396 { MC | AUF, (1 << 6) },
397 };
398
399 uint8_t flags_present = 0;
400 if (cond->ac != V3D_QPU_COND_NONE)
401 flags_present |= AC;
402 if (cond->mc != V3D_QPU_COND_NONE)
403 flags_present |= MC;
404 if (cond->apf != V3D_QPU_PF_NONE)
405 flags_present |= APF;
406 if (cond->mpf != V3D_QPU_PF_NONE)
407 flags_present |= MPF;
408 if (cond->auf != V3D_QPU_UF_NONE)
409 flags_present |= AUF;
410 if (cond->muf != V3D_QPU_UF_NONE)
411 flags_present |= MUF;
412
413 for (int i = 0; i < ARRAY_SIZE(flags_table); i++) {
414 if (flags_table[i].flags_present != flags_present)
415 continue;
416
417 *packed_cond = flags_table[i].bits;
418
419 *packed_cond |= cond->apf;
420 *packed_cond |= cond->mpf;
421
422 if (flags_present & AUF)
423 *packed_cond |= cond->auf - V3D_QPU_UF_ANDZ + 4;
424 if (flags_present & MUF)
425 *packed_cond |= cond->muf - V3D_QPU_UF_ANDZ + 4;
426
427 if (flags_present & AC)
428 *packed_cond |= (cond->ac - V3D_QPU_COND_IFA) << 2;
429
430 if (flags_present & MC) {
431 if (*packed_cond & (1 << 6))
432 *packed_cond |= (cond->mc -
433 V3D_QPU_COND_IFA) << 4;
434 else
435 *packed_cond |= (cond->mc -
436 V3D_QPU_COND_IFA) << 2;
437 }
438
439 return true;
440 }
441
442 return false;
443 }
444
445 /* Make a mapping of the table of opcodes in the spec. The opcode is
446 * determined by a combination of the opcode field, and in the case of 0 or
447 * 1-arg opcodes, the mux_b field as well.
448 */
449 #define MUX_MASK(bot, top) (((1 << (top + 1)) - 1) - ((1 << (bot)) - 1))
450 #define ANYMUX MUX_MASK(0, 7)
451
452 struct opcode_desc {
453 uint8_t opcode_first;
454 uint8_t opcode_last;
455 uint8_t mux_b_mask;
456 uint8_t mux_a_mask;
457 uint8_t op;
458 /* 0 if it's the same across V3D versions, or a specific V3D version. */
459 uint8_t ver;
460 };
461
462 static const struct opcode_desc add_ops[] = {
463 /* FADD is FADDNF depending on the order of the mux_a/mux_b. */
464 { 0, 47, ANYMUX, ANYMUX, V3D_QPU_A_FADD },
465 { 0, 47, ANYMUX, ANYMUX, V3D_QPU_A_FADDNF },
466 { 53, 55, ANYMUX, ANYMUX, V3D_QPU_A_VFPACK },
467 { 56, 56, ANYMUX, ANYMUX, V3D_QPU_A_ADD },
468 { 57, 59, ANYMUX, ANYMUX, V3D_QPU_A_VFPACK },
469 { 60, 60, ANYMUX, ANYMUX, V3D_QPU_A_SUB },
470 { 61, 63, ANYMUX, ANYMUX, V3D_QPU_A_VFPACK },
471 { 64, 111, ANYMUX, ANYMUX, V3D_QPU_A_FSUB },
472 { 120, 120, ANYMUX, ANYMUX, V3D_QPU_A_MIN },
473 { 121, 121, ANYMUX, ANYMUX, V3D_QPU_A_MAX },
474 { 122, 122, ANYMUX, ANYMUX, V3D_QPU_A_UMIN },
475 { 123, 123, ANYMUX, ANYMUX, V3D_QPU_A_UMAX },
476 { 124, 124, ANYMUX, ANYMUX, V3D_QPU_A_SHL },
477 { 125, 125, ANYMUX, ANYMUX, V3D_QPU_A_SHR },
478 { 126, 126, ANYMUX, ANYMUX, V3D_QPU_A_ASR },
479 { 127, 127, ANYMUX, ANYMUX, V3D_QPU_A_ROR },
480 /* FMIN is instead FMAX depending on the order of the mux_a/mux_b. */
481 { 128, 175, ANYMUX, ANYMUX, V3D_QPU_A_FMIN },
482 { 128, 175, ANYMUX, ANYMUX, V3D_QPU_A_FMAX },
483 { 176, 180, ANYMUX, ANYMUX, V3D_QPU_A_VFMIN },
484
485 { 181, 181, ANYMUX, ANYMUX, V3D_QPU_A_AND },
486 { 182, 182, ANYMUX, ANYMUX, V3D_QPU_A_OR },
487 { 183, 183, ANYMUX, ANYMUX, V3D_QPU_A_XOR },
488
489 { 184, 184, ANYMUX, ANYMUX, V3D_QPU_A_VADD },
490 { 185, 185, ANYMUX, ANYMUX, V3D_QPU_A_VSUB },
491 { 186, 186, 1 << 0, ANYMUX, V3D_QPU_A_NOT },
492 { 186, 186, 1 << 1, ANYMUX, V3D_QPU_A_NEG },
493 { 186, 186, 1 << 2, ANYMUX, V3D_QPU_A_FLAPUSH },
494 { 186, 186, 1 << 3, ANYMUX, V3D_QPU_A_FLBPUSH },
495 { 186, 186, 1 << 4, ANYMUX, V3D_QPU_A_FLPOP },
496 { 186, 186, 1 << 5, ANYMUX, V3D_QPU_A_RECIP },
497 { 186, 186, 1 << 6, ANYMUX, V3D_QPU_A_SETMSF },
498 { 186, 186, 1 << 7, ANYMUX, V3D_QPU_A_SETREVF },
499 { 187, 187, 1 << 0, 1 << 0, V3D_QPU_A_NOP, 0 },
500 { 187, 187, 1 << 0, 1 << 1, V3D_QPU_A_TIDX },
501 { 187, 187, 1 << 0, 1 << 2, V3D_QPU_A_EIDX },
502 { 187, 187, 1 << 0, 1 << 3, V3D_QPU_A_LR },
503 { 187, 187, 1 << 0, 1 << 4, V3D_QPU_A_VFLA },
504 { 187, 187, 1 << 0, 1 << 5, V3D_QPU_A_VFLNA },
505 { 187, 187, 1 << 0, 1 << 6, V3D_QPU_A_VFLB },
506 { 187, 187, 1 << 0, 1 << 7, V3D_QPU_A_VFLNB },
507
508 { 187, 187, 1 << 1, MUX_MASK(0, 2), V3D_QPU_A_FXCD },
509 { 187, 187, 1 << 1, 1 << 3, V3D_QPU_A_XCD },
510 { 187, 187, 1 << 1, MUX_MASK(4, 6), V3D_QPU_A_FYCD },
511 { 187, 187, 1 << 1, 1 << 7, V3D_QPU_A_YCD },
512
513 { 187, 187, 1 << 2, 1 << 0, V3D_QPU_A_MSF },
514 { 187, 187, 1 << 2, 1 << 1, V3D_QPU_A_REVF },
515 { 187, 187, 1 << 2, 1 << 2, V3D_QPU_A_VDWWT, 33 },
516 { 187, 187, 1 << 2, 1 << 2, V3D_QPU_A_IID, 40 },
517 { 187, 187, 1 << 2, 1 << 3, V3D_QPU_A_SAMPID, 40 },
518 { 187, 187, 1 << 2, 1 << 4, V3D_QPU_A_BARRIERID, 40 },
519 { 187, 187, 1 << 2, 1 << 5, V3D_QPU_A_TMUWT },
520 { 187, 187, 1 << 2, 1 << 6, V3D_QPU_A_VPMWT },
521
522 { 187, 187, 1 << 3, ANYMUX, V3D_QPU_A_VPMSETUP, 33 },
523 { 188, 188, 1 << 0, ANYMUX, V3D_QPU_A_LDVPMV_IN, 40 },
524 { 188, 188, 1 << 1, ANYMUX, V3D_QPU_A_LDVPMD_IN, 40 },
525 { 188, 188, 1 << 2, ANYMUX, V3D_QPU_A_LDVPMP, 40 },
526 { 188, 188, 1 << 3, ANYMUX, V3D_QPU_A_RSQRT, 41 },
527 { 188, 188, 1 << 4, ANYMUX, V3D_QPU_A_EXP, 41 },
528 { 188, 188, 1 << 5, ANYMUX, V3D_QPU_A_LOG, 41 },
529 { 188, 188, 1 << 6, ANYMUX, V3D_QPU_A_SIN, 41 },
530 { 188, 188, 1 << 7, ANYMUX, V3D_QPU_A_RSQRT2, 41 },
531 { 189, 189, ANYMUX, ANYMUX, V3D_QPU_A_LDVPMG_IN, 40 },
532
533 /* FIXME: MORE COMPLICATED */
534 /* { 190, 191, ANYMUX, ANYMUX, V3D_QPU_A_VFMOVABSNEGNAB }, */
535
536 { 192, 239, ANYMUX, ANYMUX, V3D_QPU_A_FCMP },
537 { 240, 244, ANYMUX, ANYMUX, V3D_QPU_A_VFMAX },
538
539 { 245, 245, MUX_MASK(0, 2), ANYMUX, V3D_QPU_A_FROUND },
540 { 245, 245, 1 << 3, ANYMUX, V3D_QPU_A_FTOIN },
541 { 245, 245, MUX_MASK(4, 6), ANYMUX, V3D_QPU_A_FTRUNC },
542 { 245, 245, 1 << 7, ANYMUX, V3D_QPU_A_FTOIZ },
543 { 246, 246, MUX_MASK(0, 2), ANYMUX, V3D_QPU_A_FFLOOR },
544 { 246, 246, 1 << 3, ANYMUX, V3D_QPU_A_FTOUZ },
545 { 246, 246, MUX_MASK(4, 6), ANYMUX, V3D_QPU_A_FCEIL },
546 { 246, 246, 1 << 7, ANYMUX, V3D_QPU_A_FTOC },
547
548 { 247, 247, MUX_MASK(0, 2), ANYMUX, V3D_QPU_A_FDX },
549 { 247, 247, MUX_MASK(4, 6), ANYMUX, V3D_QPU_A_FDY },
550
551 /* The stvpms are distinguished by the waddr field. */
552 { 248, 248, ANYMUX, ANYMUX, V3D_QPU_A_STVPMV },
553 { 248, 248, ANYMUX, ANYMUX, V3D_QPU_A_STVPMD },
554 { 248, 248, ANYMUX, ANYMUX, V3D_QPU_A_STVPMP },
555
556 { 252, 252, MUX_MASK(0, 2), ANYMUX, V3D_QPU_A_ITOF },
557 { 252, 252, 1 << 3, ANYMUX, V3D_QPU_A_CLZ },
558 { 252, 252, MUX_MASK(4, 6), ANYMUX, V3D_QPU_A_UTOF },
559 };
560
561 static const struct opcode_desc mul_ops[] = {
562 { 1, 1, ANYMUX, ANYMUX, V3D_QPU_M_ADD },
563 { 2, 2, ANYMUX, ANYMUX, V3D_QPU_M_SUB },
564 { 3, 3, ANYMUX, ANYMUX, V3D_QPU_M_UMUL24 },
565 { 4, 8, ANYMUX, ANYMUX, V3D_QPU_M_VFMUL },
566 { 9, 9, ANYMUX, ANYMUX, V3D_QPU_M_SMUL24 },
567 { 10, 10, ANYMUX, ANYMUX, V3D_QPU_M_MULTOP },
568 { 14, 14, ANYMUX, ANYMUX, V3D_QPU_M_FMOV },
569 { 15, 15, MUX_MASK(0, 3), ANYMUX, V3D_QPU_M_FMOV },
570 { 15, 15, 1 << 4, 1 << 0, V3D_QPU_M_NOP, 0 },
571 { 15, 15, 1 << 7, ANYMUX, V3D_QPU_M_MOV },
572 { 16, 63, ANYMUX, ANYMUX, V3D_QPU_M_FMUL },
573 };
574
575 static const struct opcode_desc *
576 lookup_opcode(const struct opcode_desc *opcodes, size_t num_opcodes,
577 uint32_t opcode, uint32_t mux_a, uint32_t mux_b)
578 {
579 for (int i = 0; i < num_opcodes; i++) {
580 const struct opcode_desc *op_desc = &opcodes[i];
581
582 if (opcode < op_desc->opcode_first ||
583 opcode > op_desc->opcode_last)
584 continue;
585
586 if (!(op_desc->mux_b_mask & (1 << mux_b)))
587 continue;
588
589 if (!(op_desc->mux_a_mask & (1 << mux_a)))
590 continue;
591
592 return op_desc;
593 }
594
595 return NULL;
596 }
597
598 static bool
599 v3d_qpu_float32_unpack_unpack(uint32_t packed,
600 enum v3d_qpu_input_unpack *unpacked)
601 {
602 switch (packed) {
603 case 0:
604 *unpacked = V3D_QPU_UNPACK_ABS;
605 return true;
606 case 1:
607 *unpacked = V3D_QPU_UNPACK_NONE;
608 return true;
609 case 2:
610 *unpacked = V3D_QPU_UNPACK_L;
611 return true;
612 case 3:
613 *unpacked = V3D_QPU_UNPACK_H;
614 return true;
615 default:
616 return false;
617 }
618 }
619
620 static bool
621 v3d_qpu_float32_unpack_pack(enum v3d_qpu_input_unpack unpacked,
622 uint32_t *packed)
623 {
624 switch (unpacked) {
625 case V3D_QPU_UNPACK_ABS:
626 *packed = 0;
627 return true;
628 case V3D_QPU_UNPACK_NONE:
629 *packed = 1;
630 return true;
631 case V3D_QPU_UNPACK_L:
632 *packed = 2;
633 return true;
634 case V3D_QPU_UNPACK_H:
635 *packed = 3;
636 return true;
637 default:
638 return false;
639 }
640 }
641
642 static bool
643 v3d_qpu_float16_unpack_unpack(uint32_t packed,
644 enum v3d_qpu_input_unpack *unpacked)
645 {
646 switch (packed) {
647 case 0:
648 *unpacked = V3D_QPU_UNPACK_NONE;
649 return true;
650 case 1:
651 *unpacked = V3D_QPU_UNPACK_REPLICATE_32F_16;
652 return true;
653 case 2:
654 *unpacked = V3D_QPU_UNPACK_REPLICATE_L_16;
655 return true;
656 case 3:
657 *unpacked = V3D_QPU_UNPACK_REPLICATE_H_16;
658 return true;
659 case 4:
660 *unpacked = V3D_QPU_UNPACK_SWAP_16;
661 return true;
662 default:
663 return false;
664 }
665 }
666
667 static bool
668 v3d_qpu_float16_unpack_pack(enum v3d_qpu_input_unpack unpacked,
669 uint32_t *packed)
670 {
671 switch (unpacked) {
672 case V3D_QPU_UNPACK_NONE:
673 *packed = 0;
674 return true;
675 case V3D_QPU_UNPACK_REPLICATE_32F_16:
676 *packed = 1;
677 return true;
678 case V3D_QPU_UNPACK_REPLICATE_L_16:
679 *packed = 2;
680 return true;
681 case V3D_QPU_UNPACK_REPLICATE_H_16:
682 *packed = 3;
683 return true;
684 case V3D_QPU_UNPACK_SWAP_16:
685 *packed = 4;
686 return true;
687 default:
688 return false;
689 }
690 }
691
692 static bool
693 v3d_qpu_float32_pack_pack(enum v3d_qpu_input_unpack unpacked,
694 uint32_t *packed)
695 {
696 switch (unpacked) {
697 case V3D_QPU_PACK_NONE:
698 *packed = 0;
699 return true;
700 case V3D_QPU_PACK_L:
701 *packed = 1;
702 return true;
703 case V3D_QPU_PACK_H:
704 *packed = 2;
705 return true;
706 default:
707 return false;
708 }
709 }
710
711 static bool
712 v3d_qpu_add_unpack(const struct v3d_device_info *devinfo, uint64_t packed_inst,
713 struct v3d_qpu_instr *instr)
714 {
715 uint32_t op = QPU_GET_FIELD(packed_inst, VC5_QPU_OP_ADD);
716 uint32_t mux_a = QPU_GET_FIELD(packed_inst, VC5_QPU_ADD_A);
717 uint32_t mux_b = QPU_GET_FIELD(packed_inst, VC5_QPU_ADD_B);
718 uint32_t waddr = QPU_GET_FIELD(packed_inst, V3D_QPU_WADDR_A);
719
720 uint32_t map_op = op;
721 /* Some big clusters of opcodes are replicated with unpack
722 * flags
723 */
724 if (map_op >= 249 && map_op <= 251)
725 map_op = (map_op - 249 + 245);
726 if (map_op >= 253 && map_op <= 255)
727 map_op = (map_op - 253 + 245);
728
729 const struct opcode_desc *desc =
730 lookup_opcode(add_ops, ARRAY_SIZE(add_ops),
731 map_op, mux_a, mux_b);
732 if (!desc)
733 return false;
734
735 instr->alu.add.op = desc->op;
736
737 /* FADD/FADDNF and FMIN/FMAX are determined by the orders of the
738 * operands.
739 */
740 if (((op >> 2) & 3) * 8 + mux_a > (op & 3) * 8 + mux_b) {
741 if (instr->alu.add.op == V3D_QPU_A_FMIN)
742 instr->alu.add.op = V3D_QPU_A_FMAX;
743 if (instr->alu.add.op == V3D_QPU_A_FADD)
744 instr->alu.add.op = V3D_QPU_A_FADDNF;
745 }
746
747 /* Some QPU ops require a bit more than just basic opcode and mux a/b
748 * comparisons to distinguish them.
749 */
750 switch (instr->alu.add.op) {
751 case V3D_QPU_A_STVPMV:
752 case V3D_QPU_A_STVPMD:
753 case V3D_QPU_A_STVPMP:
754 switch (waddr) {
755 case 0:
756 instr->alu.add.op = V3D_QPU_A_STVPMV;
757 break;
758 case 1:
759 instr->alu.add.op = V3D_QPU_A_STVPMD;
760 break;
761 case 2:
762 instr->alu.add.op = V3D_QPU_A_STVPMP;
763 break;
764 default:
765 return false;
766 }
767 break;
768 default:
769 break;
770 }
771
772 switch (instr->alu.add.op) {
773 case V3D_QPU_A_FADD:
774 case V3D_QPU_A_FADDNF:
775 case V3D_QPU_A_FSUB:
776 case V3D_QPU_A_FMIN:
777 case V3D_QPU_A_FMAX:
778 case V3D_QPU_A_FCMP:
779 instr->alu.add.output_pack = (op >> 4) & 0x3;
780
781 if (!v3d_qpu_float32_unpack_unpack((op >> 2) & 0x3,
782 &instr->alu.add.a_unpack)) {
783 return false;
784 }
785
786 if (!v3d_qpu_float32_unpack_unpack((op >> 0) & 0x3,
787 &instr->alu.add.b_unpack)) {
788 return false;
789 }
790 break;
791
792 case V3D_QPU_A_FFLOOR:
793 case V3D_QPU_A_FROUND:
794 case V3D_QPU_A_FTRUNC:
795 case V3D_QPU_A_FCEIL:
796 case V3D_QPU_A_FDX:
797 case V3D_QPU_A_FDY:
798 instr->alu.add.output_pack = mux_b & 0x3;
799
800 if (!v3d_qpu_float32_unpack_unpack((op >> 2) & 0x3,
801 &instr->alu.add.a_unpack)) {
802 return false;
803 }
804 break;
805
806 case V3D_QPU_A_FTOIN:
807 case V3D_QPU_A_FTOIZ:
808 case V3D_QPU_A_FTOUZ:
809 case V3D_QPU_A_FTOC:
810 instr->alu.add.output_pack = V3D_QPU_PACK_NONE;
811
812 if (!v3d_qpu_float32_unpack_unpack((op >> 2) & 0x3,
813 &instr->alu.add.a_unpack)) {
814 return false;
815 }
816 break;
817
818 case V3D_QPU_A_VFMIN:
819 case V3D_QPU_A_VFMAX:
820 if (!v3d_qpu_float16_unpack_unpack(op & 0x7,
821 &instr->alu.add.a_unpack)) {
822 return false;
823 }
824
825 instr->alu.add.output_pack = V3D_QPU_PACK_NONE;
826 instr->alu.add.b_unpack = V3D_QPU_UNPACK_NONE;
827 break;
828
829 default:
830 instr->alu.add.output_pack = V3D_QPU_PACK_NONE;
831 instr->alu.add.a_unpack = V3D_QPU_UNPACK_NONE;
832 instr->alu.add.b_unpack = V3D_QPU_UNPACK_NONE;
833 break;
834 }
835
836 instr->alu.add.a = mux_a;
837 instr->alu.add.b = mux_b;
838 instr->alu.add.waddr = QPU_GET_FIELD(packed_inst, V3D_QPU_WADDR_A);
839
840 instr->alu.add.magic_write = false;
841 if (packed_inst & VC5_QPU_MA) {
842 switch (instr->alu.add.op) {
843 case V3D_QPU_A_LDVPMV_IN:
844 instr->alu.add.op = V3D_QPU_A_LDVPMV_OUT;
845 break;
846 case V3D_QPU_A_LDVPMD_IN:
847 instr->alu.add.op = V3D_QPU_A_LDVPMD_OUT;
848 break;
849 case V3D_QPU_A_LDVPMG_IN:
850 instr->alu.add.op = V3D_QPU_A_LDVPMG_OUT;
851 break;
852 default:
853 instr->alu.add.magic_write = true;
854 break;
855 }
856 }
857
858 return true;
859 }
860
861 static bool
862 v3d_qpu_mul_unpack(const struct v3d_device_info *devinfo, uint64_t packed_inst,
863 struct v3d_qpu_instr *instr)
864 {
865 uint32_t op = QPU_GET_FIELD(packed_inst, VC5_QPU_OP_MUL);
866 uint32_t mux_a = QPU_GET_FIELD(packed_inst, VC5_QPU_MUL_A);
867 uint32_t mux_b = QPU_GET_FIELD(packed_inst, VC5_QPU_MUL_B);
868
869 {
870 const struct opcode_desc *desc =
871 lookup_opcode(mul_ops, ARRAY_SIZE(mul_ops),
872 op, mux_a, mux_b);
873 if (!desc)
874 return false;
875
876 instr->alu.mul.op = desc->op;
877 }
878
879 switch (instr->alu.mul.op) {
880 case V3D_QPU_M_FMUL:
881 instr->alu.mul.output_pack = ((op >> 4) & 0x3) - 1;
882
883 if (!v3d_qpu_float32_unpack_unpack((op >> 2) & 0x3,
884 &instr->alu.mul.a_unpack)) {
885 return false;
886 }
887
888 if (!v3d_qpu_float32_unpack_unpack((op >> 0) & 0x3,
889 &instr->alu.mul.b_unpack)) {
890 return false;
891 }
892
893 break;
894
895 case V3D_QPU_M_FMOV:
896 instr->alu.mul.output_pack = (((op & 1) << 1) +
897 ((mux_b >> 2) & 1));
898
899 if (!v3d_qpu_float32_unpack_unpack(mux_b & 0x3,
900 &instr->alu.mul.a_unpack)) {
901 return false;
902 }
903
904 break;
905
906 case V3D_QPU_M_VFMUL:
907 instr->alu.mul.output_pack = V3D_QPU_PACK_NONE;
908
909 if (!v3d_qpu_float16_unpack_unpack(((op & 0x7) - 4) & 7,
910 &instr->alu.mul.a_unpack)) {
911 return false;
912 }
913
914 instr->alu.mul.b_unpack = V3D_QPU_UNPACK_NONE;
915
916 break;
917
918 default:
919 instr->alu.mul.output_pack = V3D_QPU_PACK_NONE;
920 instr->alu.mul.a_unpack = V3D_QPU_UNPACK_NONE;
921 instr->alu.mul.b_unpack = V3D_QPU_UNPACK_NONE;
922 break;
923 }
924
925 instr->alu.mul.a = mux_a;
926 instr->alu.mul.b = mux_b;
927 instr->alu.mul.waddr = QPU_GET_FIELD(packed_inst, V3D_QPU_WADDR_M);
928 instr->alu.mul.magic_write = packed_inst & VC5_QPU_MM;
929
930 return true;
931 }
932
933 static bool
934 v3d_qpu_add_pack(const struct v3d_device_info *devinfo,
935 const struct v3d_qpu_instr *instr, uint64_t *packed_instr)
936 {
937 uint32_t waddr = instr->alu.add.waddr;
938 uint32_t mux_a = instr->alu.add.a;
939 uint32_t mux_b = instr->alu.add.b;
940 int nsrc = v3d_qpu_add_op_num_src(instr->alu.add.op);
941 const struct opcode_desc *desc;
942
943 int opcode;
944 for (desc = add_ops; desc != &add_ops[ARRAY_SIZE(add_ops)];
945 desc++) {
946 if (desc->op == instr->alu.add.op)
947 break;
948 }
949 if (desc == &add_ops[ARRAY_SIZE(add_ops)])
950 return false;
951
952 opcode = desc->opcode_first;
953
954 /* If an operation doesn't use an arg, its mux values may be used to
955 * identify the operation type.
956 */
957 if (nsrc < 2)
958 mux_b = ffs(desc->mux_b_mask) - 1;
959
960 if (nsrc < 1)
961 mux_a = ffs(desc->mux_a_mask) - 1;
962
963 bool no_magic_write = false;
964
965 switch (instr->alu.add.op) {
966 case V3D_QPU_A_STVPMV:
967 waddr = 0;
968 no_magic_write = true;
969 break;
970 case V3D_QPU_A_STVPMD:
971 waddr = 1;
972 no_magic_write = true;
973 break;
974 case V3D_QPU_A_STVPMP:
975 waddr = 2;
976 no_magic_write = true;
977 break;
978
979 case V3D_QPU_A_LDVPMV_IN:
980 case V3D_QPU_A_LDVPMD_IN:
981 case V3D_QPU_A_LDVPMP:
982 case V3D_QPU_A_LDVPMG_IN:
983 assert(!instr->alu.add.magic_write);
984 break;
985
986 case V3D_QPU_A_LDVPMV_OUT:
987 case V3D_QPU_A_LDVPMD_OUT:
988 case V3D_QPU_A_LDVPMG_OUT:
989 assert(!instr->alu.add.magic_write);
990 *packed_instr |= VC5_QPU_MA;
991 break;
992
993 default:
994 break;
995 }
996
997 switch (instr->alu.add.op) {
998 case V3D_QPU_A_FADD:
999 case V3D_QPU_A_FADDNF:
1000 case V3D_QPU_A_FSUB:
1001 case V3D_QPU_A_FMIN:
1002 case V3D_QPU_A_FMAX:
1003 case V3D_QPU_A_FCMP: {
1004 uint32_t output_pack;
1005 uint32_t a_unpack;
1006 uint32_t b_unpack;
1007
1008 if (!v3d_qpu_float32_pack_pack(instr->alu.add.output_pack,
1009 &output_pack)) {
1010 return false;
1011 }
1012 opcode |= output_pack << 4;
1013
1014 if (!v3d_qpu_float32_unpack_pack(instr->alu.add.a_unpack,
1015 &a_unpack)) {
1016 return false;
1017 }
1018
1019 if (!v3d_qpu_float32_unpack_pack(instr->alu.add.b_unpack,
1020 &b_unpack)) {
1021 return false;
1022 }
1023
1024 /* These operations with commutative operands are
1025 * distinguished by which order their operands come in.
1026 */
1027 bool ordering = a_unpack * 8 + mux_a > b_unpack * 8 + mux_b;
1028 if (((instr->alu.add.op == V3D_QPU_A_FMIN ||
1029 instr->alu.add.op == V3D_QPU_A_FADD) && ordering) ||
1030 ((instr->alu.add.op == V3D_QPU_A_FMAX ||
1031 instr->alu.add.op == V3D_QPU_A_FADDNF) && !ordering)) {
1032 uint32_t temp;
1033
1034 temp = a_unpack;
1035 a_unpack = b_unpack;
1036 b_unpack = temp;
1037
1038 temp = mux_a;
1039 mux_a = mux_b;
1040 mux_b = temp;
1041 }
1042
1043 opcode |= a_unpack << 2;
1044 opcode |= b_unpack << 0;
1045 break;
1046 }
1047
1048 case V3D_QPU_A_FFLOOR:
1049 case V3D_QPU_A_FROUND:
1050 case V3D_QPU_A_FTRUNC:
1051 case V3D_QPU_A_FCEIL:
1052 case V3D_QPU_A_FDX:
1053 case V3D_QPU_A_FDY: {
1054 uint32_t packed;
1055
1056 if (!v3d_qpu_float32_pack_pack(instr->alu.add.output_pack,
1057 &packed)) {
1058 return false;
1059 }
1060 mux_b |= packed;
1061
1062 if (!v3d_qpu_float32_unpack_pack(instr->alu.add.a_unpack,
1063 &packed)) {
1064 return false;
1065 }
1066 if (packed == 0)
1067 return false;
1068 opcode |= packed << 2;
1069 break;
1070 }
1071
1072 case V3D_QPU_A_FTOIN:
1073 case V3D_QPU_A_FTOIZ:
1074 case V3D_QPU_A_FTOUZ:
1075 case V3D_QPU_A_FTOC:
1076 if (instr->alu.add.output_pack != V3D_QPU_PACK_NONE)
1077 return false;
1078
1079 uint32_t packed;
1080 if (!v3d_qpu_float32_unpack_pack(instr->alu.add.a_unpack,
1081 &packed)) {
1082 return false;
1083 }
1084 if (packed == 0)
1085 return false;
1086 opcode |= packed << 2;
1087
1088 break;
1089
1090 case V3D_QPU_A_VFMIN:
1091 case V3D_QPU_A_VFMAX:
1092 if (instr->alu.add.output_pack != V3D_QPU_PACK_NONE ||
1093 instr->alu.add.b_unpack != V3D_QPU_UNPACK_NONE) {
1094 return false;
1095 }
1096
1097 if (!v3d_qpu_float16_unpack_pack(instr->alu.add.a_unpack,
1098 &packed)) {
1099 return false;
1100 }
1101 opcode |= packed;
1102 break;
1103
1104 default:
1105 if (instr->alu.add.op != V3D_QPU_A_NOP &&
1106 (instr->alu.add.output_pack != V3D_QPU_PACK_NONE ||
1107 instr->alu.add.a_unpack != V3D_QPU_UNPACK_NONE ||
1108 instr->alu.add.b_unpack != V3D_QPU_UNPACK_NONE)) {
1109 return false;
1110 }
1111 break;
1112 }
1113
1114 *packed_instr |= QPU_SET_FIELD(mux_a, VC5_QPU_ADD_A);
1115 *packed_instr |= QPU_SET_FIELD(mux_b, VC5_QPU_ADD_B);
1116 *packed_instr |= QPU_SET_FIELD(opcode, VC5_QPU_OP_ADD);
1117 *packed_instr |= QPU_SET_FIELD(waddr, V3D_QPU_WADDR_A);
1118 if (instr->alu.add.magic_write && !no_magic_write)
1119 *packed_instr |= VC5_QPU_MA;
1120
1121 return true;
1122 }
1123
1124 static bool
1125 v3d_qpu_mul_pack(const struct v3d_device_info *devinfo,
1126 const struct v3d_qpu_instr *instr, uint64_t *packed_instr)
1127 {
1128 uint32_t mux_a = instr->alu.mul.a;
1129 uint32_t mux_b = instr->alu.mul.b;
1130 int nsrc = v3d_qpu_mul_op_num_src(instr->alu.mul.op);
1131 const struct opcode_desc *desc;
1132
1133 for (desc = mul_ops; desc != &mul_ops[ARRAY_SIZE(mul_ops)];
1134 desc++) {
1135 if (desc->op == instr->alu.mul.op)
1136 break;
1137 }
1138 if (desc == &mul_ops[ARRAY_SIZE(mul_ops)])
1139 return false;
1140
1141 uint32_t opcode = desc->opcode_first;
1142
1143 /* Some opcodes have a single valid value for their mux a/b, so set
1144 * that here. If mux a/b determine packing, it will be set below.
1145 */
1146 if (nsrc < 2)
1147 mux_b = ffs(desc->mux_b_mask) - 1;
1148
1149 if (nsrc < 1)
1150 mux_a = ffs(desc->mux_a_mask) - 1;
1151
1152 switch (instr->alu.mul.op) {
1153 case V3D_QPU_M_FMUL: {
1154 uint32_t packed;
1155
1156 if (!v3d_qpu_float32_pack_pack(instr->alu.mul.output_pack,
1157 &packed)) {
1158 return false;
1159 }
1160 /* No need for a +1 because desc->opcode_first has a 1 in this
1161 * field.
1162 */
1163 opcode += packed << 4;
1164
1165 if (!v3d_qpu_float32_unpack_pack(instr->alu.mul.a_unpack,
1166 &packed)) {
1167 return false;
1168 }
1169 opcode |= packed << 2;
1170
1171 if (!v3d_qpu_float32_unpack_pack(instr->alu.mul.b_unpack,
1172 &packed)) {
1173 return false;
1174 }
1175 opcode |= packed << 0;
1176 break;
1177 }
1178
1179 case V3D_QPU_M_FMOV: {
1180 uint32_t packed;
1181
1182 if (!v3d_qpu_float32_pack_pack(instr->alu.mul.output_pack,
1183 &packed)) {
1184 return false;
1185 }
1186 opcode |= (packed >> 1) & 1;
1187 mux_b = (packed & 1) << 2;
1188
1189 if (!v3d_qpu_float32_unpack_pack(instr->alu.mul.a_unpack,
1190 &packed)) {
1191 return false;
1192 }
1193 mux_b |= packed;
1194 break;
1195 }
1196
1197 case V3D_QPU_M_VFMUL: {
1198 uint32_t packed;
1199
1200 if (instr->alu.mul.output_pack != V3D_QPU_PACK_NONE)
1201 return false;
1202
1203 if (!v3d_qpu_float16_unpack_pack(instr->alu.mul.a_unpack,
1204 &packed)) {
1205 return false;
1206 }
1207 if (instr->alu.mul.a_unpack == V3D_QPU_UNPACK_SWAP_16)
1208 opcode = 8;
1209 else
1210 opcode |= (packed + 4) & 7;
1211
1212 if (instr->alu.mul.b_unpack != V3D_QPU_UNPACK_NONE)
1213 return false;
1214
1215 break;
1216 }
1217
1218 default:
1219 break;
1220 }
1221
1222 *packed_instr |= QPU_SET_FIELD(mux_a, VC5_QPU_MUL_A);
1223 *packed_instr |= QPU_SET_FIELD(mux_b, VC5_QPU_MUL_B);
1224
1225 *packed_instr |= QPU_SET_FIELD(opcode, VC5_QPU_OP_MUL);
1226 *packed_instr |= QPU_SET_FIELD(instr->alu.mul.waddr, V3D_QPU_WADDR_M);
1227 if (instr->alu.mul.magic_write)
1228 *packed_instr |= VC5_QPU_MM;
1229
1230 return true;
1231 }
1232
1233 static bool
1234 v3d_qpu_instr_unpack_alu(const struct v3d_device_info *devinfo,
1235 uint64_t packed_instr,
1236 struct v3d_qpu_instr *instr)
1237 {
1238 instr->type = V3D_QPU_INSTR_TYPE_ALU;
1239
1240 if (!v3d_qpu_sig_unpack(devinfo,
1241 QPU_GET_FIELD(packed_instr, VC5_QPU_SIG),
1242 &instr->sig))
1243 return false;
1244
1245 uint32_t packed_cond = QPU_GET_FIELD(packed_instr, VC5_QPU_COND);
1246 if (v3d_qpu_sig_writes_address(devinfo, &instr->sig)) {
1247 instr->sig_addr = packed_cond & ~VC5_QPU_COND_SIG_MAGIC_ADDR;
1248 instr->sig_magic = packed_cond & VC5_QPU_COND_SIG_MAGIC_ADDR;
1249
1250 instr->flags.ac = V3D_QPU_COND_NONE;
1251 instr->flags.mc = V3D_QPU_COND_NONE;
1252 instr->flags.apf = V3D_QPU_PF_NONE;
1253 instr->flags.mpf = V3D_QPU_PF_NONE;
1254 instr->flags.auf = V3D_QPU_UF_NONE;
1255 instr->flags.muf = V3D_QPU_UF_NONE;
1256 } else {
1257 if (!v3d_qpu_flags_unpack(devinfo, packed_cond, &instr->flags))
1258 return false;
1259 }
1260
1261 instr->raddr_a = QPU_GET_FIELD(packed_instr, VC5_QPU_RADDR_A);
1262 instr->raddr_b = QPU_GET_FIELD(packed_instr, VC5_QPU_RADDR_B);
1263
1264 if (!v3d_qpu_add_unpack(devinfo, packed_instr, instr))
1265 return false;
1266
1267 if (!v3d_qpu_mul_unpack(devinfo, packed_instr, instr))
1268 return false;
1269
1270 return true;
1271 }
1272
1273 static bool
1274 v3d_qpu_instr_unpack_branch(const struct v3d_device_info *devinfo,
1275 uint64_t packed_instr,
1276 struct v3d_qpu_instr *instr)
1277 {
1278 instr->type = V3D_QPU_INSTR_TYPE_BRANCH;
1279
1280 uint32_t cond = QPU_GET_FIELD(packed_instr, VC5_QPU_BRANCH_COND);
1281 if (cond == 0)
1282 instr->branch.cond = V3D_QPU_BRANCH_COND_ALWAYS;
1283 else if (V3D_QPU_BRANCH_COND_A0 + (cond - 2) <=
1284 V3D_QPU_BRANCH_COND_ALLNA)
1285 instr->branch.cond = V3D_QPU_BRANCH_COND_A0 + (cond - 2);
1286 else
1287 return false;
1288
1289 uint32_t msfign = QPU_GET_FIELD(packed_instr, VC5_QPU_BRANCH_MSFIGN);
1290 if (msfign == 3)
1291 return false;
1292 instr->branch.msfign = msfign;
1293
1294 instr->branch.bdi = QPU_GET_FIELD(packed_instr, VC5_QPU_BRANCH_BDI);
1295
1296 instr->branch.ub = packed_instr & VC5_QPU_BRANCH_UB;
1297 if (instr->branch.ub) {
1298 instr->branch.bdu = QPU_GET_FIELD(packed_instr,
1299 VC5_QPU_BRANCH_BDU);
1300 }
1301
1302 instr->branch.raddr_a = QPU_GET_FIELD(packed_instr,
1303 VC5_QPU_RADDR_A);
1304
1305 instr->branch.offset = 0;
1306
1307 instr->branch.offset +=
1308 QPU_GET_FIELD(packed_instr,
1309 VC5_QPU_BRANCH_ADDR_LOW) << 3;
1310
1311 instr->branch.offset +=
1312 QPU_GET_FIELD(packed_instr,
1313 VC5_QPU_BRANCH_ADDR_HIGH) << 24;
1314
1315 return true;
1316 }
1317
1318 bool
1319 v3d_qpu_instr_unpack(const struct v3d_device_info *devinfo,
1320 uint64_t packed_instr,
1321 struct v3d_qpu_instr *instr)
1322 {
1323 if (QPU_GET_FIELD(packed_instr, VC5_QPU_OP_MUL) != 0) {
1324 return v3d_qpu_instr_unpack_alu(devinfo, packed_instr, instr);
1325 } else {
1326 uint32_t sig = QPU_GET_FIELD(packed_instr, VC5_QPU_SIG);
1327
1328 if ((sig & 24) == 16) {
1329 return v3d_qpu_instr_unpack_branch(devinfo, packed_instr,
1330 instr);
1331 } else {
1332 return false;
1333 }
1334 }
1335 }
1336
1337 static bool
1338 v3d_qpu_instr_pack_alu(const struct v3d_device_info *devinfo,
1339 const struct v3d_qpu_instr *instr,
1340 uint64_t *packed_instr)
1341 {
1342 uint32_t sig;
1343 if (!v3d_qpu_sig_pack(devinfo, &instr->sig, &sig))
1344 return false;
1345 *packed_instr |= QPU_SET_FIELD(sig, VC5_QPU_SIG);
1346
1347 if (instr->type == V3D_QPU_INSTR_TYPE_ALU) {
1348 *packed_instr |= QPU_SET_FIELD(instr->raddr_a, VC5_QPU_RADDR_A);
1349 *packed_instr |= QPU_SET_FIELD(instr->raddr_b, VC5_QPU_RADDR_B);
1350
1351 if (!v3d_qpu_add_pack(devinfo, instr, packed_instr))
1352 return false;
1353 if (!v3d_qpu_mul_pack(devinfo, instr, packed_instr))
1354 return false;
1355
1356 uint32_t flags;
1357 if (v3d_qpu_sig_writes_address(devinfo, &instr->sig)) {
1358 if (instr->flags.ac != V3D_QPU_COND_NONE ||
1359 instr->flags.mc != V3D_QPU_COND_NONE ||
1360 instr->flags.apf != V3D_QPU_PF_NONE ||
1361 instr->flags.mpf != V3D_QPU_PF_NONE ||
1362 instr->flags.auf != V3D_QPU_UF_NONE ||
1363 instr->flags.muf != V3D_QPU_UF_NONE) {
1364 return false;
1365 }
1366
1367 flags = instr->sig_addr;
1368 if (instr->sig_magic)
1369 flags |= VC5_QPU_COND_SIG_MAGIC_ADDR;
1370 } else {
1371 if (!v3d_qpu_flags_pack(devinfo, &instr->flags, &flags))
1372 return false;
1373 }
1374
1375 *packed_instr |= QPU_SET_FIELD(flags, VC5_QPU_COND);
1376 } else {
1377 if (v3d_qpu_sig_writes_address(devinfo, &instr->sig))
1378 return false;
1379 }
1380
1381 return true;
1382 }
1383
1384 static bool
1385 v3d_qpu_instr_pack_branch(const struct v3d_device_info *devinfo,
1386 const struct v3d_qpu_instr *instr,
1387 uint64_t *packed_instr)
1388 {
1389 *packed_instr |= QPU_SET_FIELD(16, VC5_QPU_SIG);
1390
1391 if (instr->branch.cond != V3D_QPU_BRANCH_COND_ALWAYS) {
1392 *packed_instr |= QPU_SET_FIELD(2 + (instr->branch.cond -
1393 V3D_QPU_BRANCH_COND_A0),
1394 VC5_QPU_BRANCH_COND);
1395 }
1396
1397 *packed_instr |= QPU_SET_FIELD(instr->branch.msfign,
1398 VC5_QPU_BRANCH_MSFIGN);
1399
1400 *packed_instr |= QPU_SET_FIELD(instr->branch.bdi,
1401 VC5_QPU_BRANCH_BDI);
1402
1403 if (instr->branch.ub) {
1404 *packed_instr |= VC5_QPU_BRANCH_UB;
1405 *packed_instr |= QPU_SET_FIELD(instr->branch.bdu,
1406 VC5_QPU_BRANCH_BDU);
1407 }
1408
1409 switch (instr->branch.bdi) {
1410 case V3D_QPU_BRANCH_DEST_ABS:
1411 case V3D_QPU_BRANCH_DEST_REL:
1412 *packed_instr |= QPU_SET_FIELD(instr->branch.msfign,
1413 VC5_QPU_BRANCH_MSFIGN);
1414
1415 *packed_instr |= QPU_SET_FIELD((instr->branch.offset &
1416 ~0xff000000) >> 3,
1417 VC5_QPU_BRANCH_ADDR_LOW);
1418
1419 *packed_instr |= QPU_SET_FIELD(instr->branch.offset >> 24,
1420 VC5_QPU_BRANCH_ADDR_HIGH);
1421
1422 case V3D_QPU_BRANCH_DEST_REGFILE:
1423 *packed_instr |= QPU_SET_FIELD(instr->branch.raddr_a,
1424 VC5_QPU_RADDR_A);
1425 break;
1426
1427 default:
1428 break;
1429 }
1430
1431 return true;
1432 }
1433
1434 bool
1435 v3d_qpu_instr_pack(const struct v3d_device_info *devinfo,
1436 const struct v3d_qpu_instr *instr,
1437 uint64_t *packed_instr)
1438 {
1439 *packed_instr = 0;
1440
1441 switch (instr->type) {
1442 case V3D_QPU_INSTR_TYPE_ALU:
1443 return v3d_qpu_instr_pack_alu(devinfo, instr, packed_instr);
1444 case V3D_QPU_INSTR_TYPE_BRANCH:
1445 return v3d_qpu_instr_pack_branch(devinfo, instr, packed_instr);
1446 default:
1447 return false;
1448 }
1449 }