2 * Copyright © 2016 Broadcom
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "util/macros.h"
27 #include "broadcom/common/v3d_device_info.h"
28 #include "broadcom/qpu/qpu_disasm.h"
29 #include "broadcom/qpu/qpu_instr.h"
36 { 33, 0x3d003186bb800000ull
, "nop ; nop ; ldvary" },
37 { 33, 0x3c20318105829000ull
, "fadd r1, r1, r5 ; nop ; thrsw" },
38 { 33, 0x3c403186bb81d000ull
, "vpmsetup -, r5 ; nop ; ldunif" },
39 { 33, 0x3f003186bb800000ull
, "nop ; nop ; ldvpm" },
40 { 33, 0x3c002380b6edb000ull
, "or rf0, r3, r3 ; mov vpm, r3" },
41 { 33, 0x57403006bbb80000ull
, "nop ; fmul r0, rf0, r5 ; ldvpm; ldunif" },
43 /* vfmul input packing */
44 { 33, 0x101e8b6e8aad4000ull
, "fmax.nornn rf46, r4.l, r2.l; vfmul.ifnb rf45, r3, r5" },
45 { 33, 0x1857d3c219825000ull
, "faddnf.norc r2.l, r5.l, r4; vfmul.ifb rf15, r0.ll, r4; ldunif" },
46 { 33, 0x1c0a0dfde2294000ull
, "fcmp.ifna rf61.h, r4.abs, r2.l; vfmul rf55, r2.hh, r1" },
47 { 33, 0x2011c89b402cc000ull
, "fsub.norz rf27, r4.abs, r1.abs; vfmul.ifa rf34, r3.swp, r1" },
49 /* branch conditions */
50 { 33, 0x02000006002034c0ull
, "b.anyap rf19" },
51 { 33, 0x02679356b4201000ull
, "b.anyap -1268280496" },
52 { 33, 0x02b76a2dd0400000ull
, "b.anynaq zero_addr+0xd0b76a28" },
53 { 33, 0x0200000500402000ull
, "b.anynaq lri" },
54 { 33, 0x0216fe167301c8c0ull
, "bu.anya zero_addr+0x7316fe10, rf35" },
55 { 33, 0x020000050040e000ull
, "bu.anynaq lri, r:unif" },
56 { 33, 0x0200000300006000ull
, "bu.na0 lri, a:unif" },
58 /* Special waddr names */
59 { 33, 0x3c00318735808000ull
, "vfpack tlb, r0, r1 ; nop" },
60 { 33, 0xe0571c938e8d5000ull
, "fmax.andc recip, r5.h, r2.l; fmul.ifb rf50.h, r3.l, r4.abs; ldunif" },
61 { 33, 0xc04098d4382c9000ull
, "add.pushn rsqrt, r1, r1; fmul rf35.h, r3.abs, r1.abs; ldunif" },
62 { 33, 0x481edcd6b3184500ull
, "vfmin.norn log, r4.hh, r0; fmul.ifnb rf51, rf20.abs, r0.l" },
63 { 33, 0x041618d57c453000ull
, "shl.andn exp, r3, r2; add.ifb rf35, r1, r2" },
64 { 33, 0x7048e5da49272800ull
, "fsub.ifa rf26, r2.l, rf32; fmul.pushc sin, r1.h, r1.abs; ldunif" },
67 { 41, 0x1f010520cf60a000ull
, "fcmp.andz rf32, r2.h, r1.h; vfmul rf20, r0.hh, r3; ldunifa" },
68 { 41, 0x932045e6c16ea000ull
, "fcmp rf38, r2.abs, r5; fmul rf23.l, r3, r3.abs; ldunifarf.rf1" },
69 { 41, 0xd72f0434e43ae5c0ull
, "fcmp rf52.h, rf23, r5.abs; fmul rf16.h, rf23, r1; ldunifarf.rf60" },
70 { 41, 0xdb3048eb9d533780ull
, "fmax rf43.l, r3.h, rf30; fmul rf35.h, r4, r2.l; ldunifarf.r1" },
71 { 41, 0x733620471e6ce700ull
, "faddnf rf7.l, rf28.h, r1.l; fmul r1, r3.h, r3.abs; ldunifarf.rsqrt2" },
72 { 41, 0x9c094adef634b000ull
, "ffloor.ifb rf30.l, r3; fmul.pushz rf43.l, r5, r1.h" },
76 swap_mux(enum v3d_qpu_mux
*a
, enum v3d_qpu_mux
*b
)
78 enum v3d_qpu_mux t
= *a
;
84 swap_pack(enum v3d_qpu_input_unpack
*a
, enum v3d_qpu_input_unpack
*b
)
86 enum v3d_qpu_input_unpack t
= *a
;
92 main(int argc
, char **argv
)
94 struct v3d_device_info devinfo
= { };
97 for (int i
= 0; i
< ARRAY_SIZE(tests
); i
++) {
98 devinfo
.ver
= tests
[i
].ver
;
100 printf("Testing v%d.%d 0x%016llx... ",
101 devinfo
.ver
/ 10, devinfo
.ver
% 10,
102 (long long)tests
[i
].inst
);
104 const char *disasm_output
= v3d_qpu_disasm(&devinfo
,
107 if (strcmp(disasm_output
, tests
[i
].expected
) != 0) {
109 printf(" Expected: \"%s\"\n", tests
[i
].expected
);
110 printf(" Got: \"%s\"\n", disasm_output
);
115 struct v3d_qpu_instr instr
;
116 if (!v3d_qpu_instr_unpack(&devinfo
, tests
[i
].inst
, &instr
)) {
117 printf("FAIL (unpack) %s\n", tests
[i
].expected
);
122 if (instr
.type
== V3D_QPU_INSTR_TYPE_ALU
) {
123 switch (instr
.alu
.add
.op
) {
125 case V3D_QPU_A_FADDNF
:
128 /* Swap the operands to be sure that we test
129 * how the QPUs distinguish between these ops.
131 swap_mux(&instr
.alu
.add
.a
,
133 swap_pack(&instr
.alu
.add
.a_unpack
,
134 &instr
.alu
.add
.b_unpack
);
141 if (!v3d_qpu_instr_pack(&devinfo
, &instr
, &repack
)) {
142 printf("FAIL (pack) %s\n", tests
[i
].expected
);
147 if (repack
!= tests
[i
].inst
) {
148 printf("FAIL (repack) 0x%016llx\n", (long long)repack
);
149 printf(" Expected: \"%s\"\n", tests
[i
].expected
);
150 const char *redisasm
= v3d_qpu_disasm(&devinfo
, repack
);
151 printf(" Got: \"%s\"\n", redisasm
);