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nir: Add new system values and intrinsics for dealing with CL work offsets
[mesa.git] / src / compiler / nir / nir.c
1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Connor Abbott (cwabbott0@gmail.com)
25 *
26 */
27
28 #include "nir.h"
29 #include "nir_builder.h"
30 #include "nir_control_flow_private.h"
31 #include "util/half_float.h"
32 #include <limits.h>
33 #include <assert.h>
34 #include <math.h>
35 #include "util/u_math.h"
36
37 #include "main/menums.h" /* BITFIELD64_MASK */
38
39 nir_shader *
40 nir_shader_create(void *mem_ctx,
41 gl_shader_stage stage,
42 const nir_shader_compiler_options *options,
43 shader_info *si)
44 {
45 nir_shader *shader = rzalloc(mem_ctx, nir_shader);
46
47 exec_list_make_empty(&shader->variables);
48
49 shader->options = options;
50
51 if (si) {
52 assert(si->stage == stage);
53 shader->info = *si;
54 } else {
55 shader->info.stage = stage;
56 }
57
58 exec_list_make_empty(&shader->functions);
59
60 shader->num_inputs = 0;
61 shader->num_outputs = 0;
62 shader->num_uniforms = 0;
63 shader->num_shared = 0;
64
65 return shader;
66 }
67
68 static nir_register *
69 reg_create(void *mem_ctx, struct exec_list *list)
70 {
71 nir_register *reg = ralloc(mem_ctx, nir_register);
72
73 list_inithead(&reg->uses);
74 list_inithead(&reg->defs);
75 list_inithead(&reg->if_uses);
76
77 reg->num_components = 0;
78 reg->bit_size = 32;
79 reg->num_array_elems = 0;
80 reg->name = NULL;
81
82 exec_list_push_tail(list, &reg->node);
83
84 return reg;
85 }
86
87 nir_register *
88 nir_local_reg_create(nir_function_impl *impl)
89 {
90 nir_register *reg = reg_create(ralloc_parent(impl), &impl->registers);
91 reg->index = impl->reg_alloc++;
92
93 return reg;
94 }
95
96 void
97 nir_reg_remove(nir_register *reg)
98 {
99 exec_node_remove(&reg->node);
100 }
101
102 void
103 nir_shader_add_variable(nir_shader *shader, nir_variable *var)
104 {
105 switch (var->data.mode) {
106 case nir_var_function_temp:
107 assert(!"nir_shader_add_variable cannot be used for local variables");
108 return;
109
110 case nir_var_shader_temp:
111 case nir_var_shader_in:
112 case nir_var_shader_out:
113 case nir_var_uniform:
114 case nir_var_mem_ubo:
115 case nir_var_mem_ssbo:
116 case nir_var_mem_shared:
117 case nir_var_system_value:
118 break;
119
120 case nir_var_mem_global:
121 assert(!"nir_shader_add_variable cannot be used for global memory");
122 return;
123
124 case nir_var_mem_push_const:
125 assert(!"nir_var_push_constant is not supposed to be used for variables");
126 return;
127
128 default:
129 assert(!"invalid mode");
130 return;
131 }
132
133 exec_list_push_tail(&shader->variables, &var->node);
134 }
135
136 nir_variable *
137 nir_variable_create(nir_shader *shader, nir_variable_mode mode,
138 const struct glsl_type *type, const char *name)
139 {
140 nir_variable *var = rzalloc(shader, nir_variable);
141 var->name = ralloc_strdup(var, name);
142 var->type = type;
143 var->data.mode = mode;
144 var->data.how_declared = nir_var_declared_normally;
145
146 if ((mode == nir_var_shader_in &&
147 shader->info.stage != MESA_SHADER_VERTEX) ||
148 (mode == nir_var_shader_out &&
149 shader->info.stage != MESA_SHADER_FRAGMENT))
150 var->data.interpolation = INTERP_MODE_SMOOTH;
151
152 if (mode == nir_var_shader_in || mode == nir_var_uniform)
153 var->data.read_only = true;
154
155 nir_shader_add_variable(shader, var);
156
157 return var;
158 }
159
160 nir_variable *
161 nir_local_variable_create(nir_function_impl *impl,
162 const struct glsl_type *type, const char *name)
163 {
164 nir_variable *var = rzalloc(impl->function->shader, nir_variable);
165 var->name = ralloc_strdup(var, name);
166 var->type = type;
167 var->data.mode = nir_var_function_temp;
168
169 nir_function_impl_add_variable(impl, var);
170
171 return var;
172 }
173
174 nir_variable *
175 nir_find_variable_with_location(nir_shader *shader,
176 nir_variable_mode mode,
177 unsigned location)
178 {
179 assert(util_bitcount(mode) == 1 && mode != nir_var_function_temp);
180 nir_foreach_variable_with_modes(var, shader, mode) {
181 if (var->data.location == location)
182 return var;
183 }
184 return NULL;
185 }
186
187 nir_variable *
188 nir_find_variable_with_driver_location(nir_shader *shader,
189 nir_variable_mode mode,
190 unsigned location)
191 {
192 assert(util_bitcount(mode) == 1 && mode != nir_var_function_temp);
193 nir_foreach_variable_with_modes(var, shader, mode) {
194 if (var->data.driver_location == location)
195 return var;
196 }
197 return NULL;
198 }
199
200 nir_function *
201 nir_function_create(nir_shader *shader, const char *name)
202 {
203 nir_function *func = ralloc(shader, nir_function);
204
205 exec_list_push_tail(&shader->functions, &func->node);
206
207 func->name = ralloc_strdup(func, name);
208 func->shader = shader;
209 func->num_params = 0;
210 func->params = NULL;
211 func->impl = NULL;
212 func->is_entrypoint = false;
213
214 return func;
215 }
216
217 /* NOTE: if the instruction you are copying a src to is already added
218 * to the IR, use nir_instr_rewrite_src() instead.
219 */
220 void nir_src_copy(nir_src *dest, const nir_src *src, void *mem_ctx)
221 {
222 dest->is_ssa = src->is_ssa;
223 if (src->is_ssa) {
224 dest->ssa = src->ssa;
225 } else {
226 dest->reg.base_offset = src->reg.base_offset;
227 dest->reg.reg = src->reg.reg;
228 if (src->reg.indirect) {
229 dest->reg.indirect = ralloc(mem_ctx, nir_src);
230 nir_src_copy(dest->reg.indirect, src->reg.indirect, mem_ctx);
231 } else {
232 dest->reg.indirect = NULL;
233 }
234 }
235 }
236
237 void nir_dest_copy(nir_dest *dest, const nir_dest *src, nir_instr *instr)
238 {
239 /* Copying an SSA definition makes no sense whatsoever. */
240 assert(!src->is_ssa);
241
242 dest->is_ssa = false;
243
244 dest->reg.base_offset = src->reg.base_offset;
245 dest->reg.reg = src->reg.reg;
246 if (src->reg.indirect) {
247 dest->reg.indirect = ralloc(instr, nir_src);
248 nir_src_copy(dest->reg.indirect, src->reg.indirect, instr);
249 } else {
250 dest->reg.indirect = NULL;
251 }
252 }
253
254 void
255 nir_alu_src_copy(nir_alu_src *dest, const nir_alu_src *src,
256 nir_alu_instr *instr)
257 {
258 nir_src_copy(&dest->src, &src->src, &instr->instr);
259 dest->abs = src->abs;
260 dest->negate = src->negate;
261 for (unsigned i = 0; i < NIR_MAX_VEC_COMPONENTS; i++)
262 dest->swizzle[i] = src->swizzle[i];
263 }
264
265 void
266 nir_alu_dest_copy(nir_alu_dest *dest, const nir_alu_dest *src,
267 nir_alu_instr *instr)
268 {
269 nir_dest_copy(&dest->dest, &src->dest, &instr->instr);
270 dest->write_mask = src->write_mask;
271 dest->saturate = src->saturate;
272 }
273
274
275 static void
276 cf_init(nir_cf_node *node, nir_cf_node_type type)
277 {
278 exec_node_init(&node->node);
279 node->parent = NULL;
280 node->type = type;
281 }
282
283 nir_function_impl *
284 nir_function_impl_create_bare(nir_shader *shader)
285 {
286 nir_function_impl *impl = ralloc(shader, nir_function_impl);
287
288 impl->function = NULL;
289
290 cf_init(&impl->cf_node, nir_cf_node_function);
291
292 exec_list_make_empty(&impl->body);
293 exec_list_make_empty(&impl->registers);
294 exec_list_make_empty(&impl->locals);
295 impl->reg_alloc = 0;
296 impl->ssa_alloc = 0;
297 impl->valid_metadata = nir_metadata_none;
298 impl->structured = true;
299
300 /* create start & end blocks */
301 nir_block *start_block = nir_block_create(shader);
302 nir_block *end_block = nir_block_create(shader);
303 start_block->cf_node.parent = &impl->cf_node;
304 end_block->cf_node.parent = &impl->cf_node;
305 impl->end_block = end_block;
306
307 exec_list_push_tail(&impl->body, &start_block->cf_node.node);
308
309 start_block->successors[0] = end_block;
310 _mesa_set_add(end_block->predecessors, start_block);
311 return impl;
312 }
313
314 nir_function_impl *
315 nir_function_impl_create(nir_function *function)
316 {
317 assert(function->impl == NULL);
318
319 nir_function_impl *impl = nir_function_impl_create_bare(function->shader);
320
321 function->impl = impl;
322 impl->function = function;
323
324 return impl;
325 }
326
327 nir_block *
328 nir_block_create(nir_shader *shader)
329 {
330 nir_block *block = rzalloc(shader, nir_block);
331
332 cf_init(&block->cf_node, nir_cf_node_block);
333
334 block->successors[0] = block->successors[1] = NULL;
335 block->predecessors = _mesa_pointer_set_create(block);
336 block->imm_dom = NULL;
337 /* XXX maybe it would be worth it to defer allocation? This
338 * way it doesn't get allocated for shader refs that never run
339 * nir_calc_dominance? For example, state-tracker creates an
340 * initial IR, clones that, runs appropriate lowering pass, passes
341 * to driver which does common lowering/opt, and then stores ref
342 * which is later used to do state specific lowering and futher
343 * opt. Do any of the references not need dominance metadata?
344 */
345 block->dom_frontier = _mesa_pointer_set_create(block);
346
347 exec_list_make_empty(&block->instr_list);
348
349 return block;
350 }
351
352 static inline void
353 src_init(nir_src *src)
354 {
355 src->is_ssa = false;
356 src->reg.reg = NULL;
357 src->reg.indirect = NULL;
358 src->reg.base_offset = 0;
359 }
360
361 nir_if *
362 nir_if_create(nir_shader *shader)
363 {
364 nir_if *if_stmt = ralloc(shader, nir_if);
365
366 if_stmt->control = nir_selection_control_none;
367
368 cf_init(&if_stmt->cf_node, nir_cf_node_if);
369 src_init(&if_stmt->condition);
370
371 nir_block *then = nir_block_create(shader);
372 exec_list_make_empty(&if_stmt->then_list);
373 exec_list_push_tail(&if_stmt->then_list, &then->cf_node.node);
374 then->cf_node.parent = &if_stmt->cf_node;
375
376 nir_block *else_stmt = nir_block_create(shader);
377 exec_list_make_empty(&if_stmt->else_list);
378 exec_list_push_tail(&if_stmt->else_list, &else_stmt->cf_node.node);
379 else_stmt->cf_node.parent = &if_stmt->cf_node;
380
381 return if_stmt;
382 }
383
384 nir_loop *
385 nir_loop_create(nir_shader *shader)
386 {
387 nir_loop *loop = rzalloc(shader, nir_loop);
388
389 cf_init(&loop->cf_node, nir_cf_node_loop);
390
391 nir_block *body = nir_block_create(shader);
392 exec_list_make_empty(&loop->body);
393 exec_list_push_tail(&loop->body, &body->cf_node.node);
394 body->cf_node.parent = &loop->cf_node;
395
396 body->successors[0] = body;
397 _mesa_set_add(body->predecessors, body);
398
399 return loop;
400 }
401
402 static void
403 instr_init(nir_instr *instr, nir_instr_type type)
404 {
405 instr->type = type;
406 instr->block = NULL;
407 exec_node_init(&instr->node);
408 }
409
410 static void
411 dest_init(nir_dest *dest)
412 {
413 dest->is_ssa = false;
414 dest->reg.reg = NULL;
415 dest->reg.indirect = NULL;
416 dest->reg.base_offset = 0;
417 }
418
419 static void
420 alu_dest_init(nir_alu_dest *dest)
421 {
422 dest_init(&dest->dest);
423 dest->saturate = false;
424 dest->write_mask = 0xf;
425 }
426
427 static void
428 alu_src_init(nir_alu_src *src)
429 {
430 src_init(&src->src);
431 src->abs = src->negate = false;
432 for (int i = 0; i < NIR_MAX_VEC_COMPONENTS; ++i)
433 src->swizzle[i] = i;
434 }
435
436 nir_alu_instr *
437 nir_alu_instr_create(nir_shader *shader, nir_op op)
438 {
439 unsigned num_srcs = nir_op_infos[op].num_inputs;
440 /* TODO: don't use rzalloc */
441 nir_alu_instr *instr =
442 rzalloc_size(shader,
443 sizeof(nir_alu_instr) + num_srcs * sizeof(nir_alu_src));
444
445 instr_init(&instr->instr, nir_instr_type_alu);
446 instr->op = op;
447 alu_dest_init(&instr->dest);
448 for (unsigned i = 0; i < num_srcs; i++)
449 alu_src_init(&instr->src[i]);
450
451 return instr;
452 }
453
454 nir_deref_instr *
455 nir_deref_instr_create(nir_shader *shader, nir_deref_type deref_type)
456 {
457 nir_deref_instr *instr =
458 rzalloc_size(shader, sizeof(nir_deref_instr));
459
460 instr_init(&instr->instr, nir_instr_type_deref);
461
462 instr->deref_type = deref_type;
463 if (deref_type != nir_deref_type_var)
464 src_init(&instr->parent);
465
466 if (deref_type == nir_deref_type_array ||
467 deref_type == nir_deref_type_ptr_as_array)
468 src_init(&instr->arr.index);
469
470 dest_init(&instr->dest);
471
472 return instr;
473 }
474
475 nir_jump_instr *
476 nir_jump_instr_create(nir_shader *shader, nir_jump_type type)
477 {
478 nir_jump_instr *instr = ralloc(shader, nir_jump_instr);
479 instr_init(&instr->instr, nir_instr_type_jump);
480 src_init(&instr->condition);
481 instr->type = type;
482 instr->target = NULL;
483 instr->else_target = NULL;
484 return instr;
485 }
486
487 nir_load_const_instr *
488 nir_load_const_instr_create(nir_shader *shader, unsigned num_components,
489 unsigned bit_size)
490 {
491 nir_load_const_instr *instr =
492 rzalloc_size(shader, sizeof(*instr) + num_components * sizeof(*instr->value));
493 instr_init(&instr->instr, nir_instr_type_load_const);
494
495 nir_ssa_def_init(&instr->instr, &instr->def, num_components, bit_size, NULL);
496
497 return instr;
498 }
499
500 nir_intrinsic_instr *
501 nir_intrinsic_instr_create(nir_shader *shader, nir_intrinsic_op op)
502 {
503 unsigned num_srcs = nir_intrinsic_infos[op].num_srcs;
504 /* TODO: don't use rzalloc */
505 nir_intrinsic_instr *instr =
506 rzalloc_size(shader,
507 sizeof(nir_intrinsic_instr) + num_srcs * sizeof(nir_src));
508
509 instr_init(&instr->instr, nir_instr_type_intrinsic);
510 instr->intrinsic = op;
511
512 if (nir_intrinsic_infos[op].has_dest)
513 dest_init(&instr->dest);
514
515 for (unsigned i = 0; i < num_srcs; i++)
516 src_init(&instr->src[i]);
517
518 return instr;
519 }
520
521 nir_call_instr *
522 nir_call_instr_create(nir_shader *shader, nir_function *callee)
523 {
524 const unsigned num_params = callee->num_params;
525 nir_call_instr *instr =
526 rzalloc_size(shader, sizeof(*instr) +
527 num_params * sizeof(instr->params[0]));
528
529 instr_init(&instr->instr, nir_instr_type_call);
530 instr->callee = callee;
531 instr->num_params = num_params;
532 for (unsigned i = 0; i < num_params; i++)
533 src_init(&instr->params[i]);
534
535 return instr;
536 }
537
538 static int8_t default_tg4_offsets[4][2] =
539 {
540 { 0, 1 },
541 { 1, 1 },
542 { 1, 0 },
543 { 0, 0 },
544 };
545
546 nir_tex_instr *
547 nir_tex_instr_create(nir_shader *shader, unsigned num_srcs)
548 {
549 nir_tex_instr *instr = rzalloc(shader, nir_tex_instr);
550 instr_init(&instr->instr, nir_instr_type_tex);
551
552 dest_init(&instr->dest);
553
554 instr->num_srcs = num_srcs;
555 instr->src = ralloc_array(instr, nir_tex_src, num_srcs);
556 for (unsigned i = 0; i < num_srcs; i++)
557 src_init(&instr->src[i].src);
558
559 instr->texture_index = 0;
560 instr->sampler_index = 0;
561 memcpy(instr->tg4_offsets, default_tg4_offsets, sizeof(instr->tg4_offsets));
562
563 return instr;
564 }
565
566 void
567 nir_tex_instr_add_src(nir_tex_instr *tex,
568 nir_tex_src_type src_type,
569 nir_src src)
570 {
571 nir_tex_src *new_srcs = rzalloc_array(tex, nir_tex_src,
572 tex->num_srcs + 1);
573
574 for (unsigned i = 0; i < tex->num_srcs; i++) {
575 new_srcs[i].src_type = tex->src[i].src_type;
576 nir_instr_move_src(&tex->instr, &new_srcs[i].src,
577 &tex->src[i].src);
578 }
579
580 ralloc_free(tex->src);
581 tex->src = new_srcs;
582
583 tex->src[tex->num_srcs].src_type = src_type;
584 nir_instr_rewrite_src(&tex->instr, &tex->src[tex->num_srcs].src, src);
585 tex->num_srcs++;
586 }
587
588 void
589 nir_tex_instr_remove_src(nir_tex_instr *tex, unsigned src_idx)
590 {
591 assert(src_idx < tex->num_srcs);
592
593 /* First rewrite the source to NIR_SRC_INIT */
594 nir_instr_rewrite_src(&tex->instr, &tex->src[src_idx].src, NIR_SRC_INIT);
595
596 /* Now, move all of the other sources down */
597 for (unsigned i = src_idx + 1; i < tex->num_srcs; i++) {
598 tex->src[i-1].src_type = tex->src[i].src_type;
599 nir_instr_move_src(&tex->instr, &tex->src[i-1].src, &tex->src[i].src);
600 }
601 tex->num_srcs--;
602 }
603
604 bool
605 nir_tex_instr_has_explicit_tg4_offsets(nir_tex_instr *tex)
606 {
607 if (tex->op != nir_texop_tg4)
608 return false;
609 return memcmp(tex->tg4_offsets, default_tg4_offsets,
610 sizeof(tex->tg4_offsets)) != 0;
611 }
612
613 nir_phi_instr *
614 nir_phi_instr_create(nir_shader *shader)
615 {
616 nir_phi_instr *instr = ralloc(shader, nir_phi_instr);
617 instr_init(&instr->instr, nir_instr_type_phi);
618
619 dest_init(&instr->dest);
620 exec_list_make_empty(&instr->srcs);
621 return instr;
622 }
623
624 nir_parallel_copy_instr *
625 nir_parallel_copy_instr_create(nir_shader *shader)
626 {
627 nir_parallel_copy_instr *instr = ralloc(shader, nir_parallel_copy_instr);
628 instr_init(&instr->instr, nir_instr_type_parallel_copy);
629
630 exec_list_make_empty(&instr->entries);
631
632 return instr;
633 }
634
635 nir_ssa_undef_instr *
636 nir_ssa_undef_instr_create(nir_shader *shader,
637 unsigned num_components,
638 unsigned bit_size)
639 {
640 nir_ssa_undef_instr *instr = ralloc(shader, nir_ssa_undef_instr);
641 instr_init(&instr->instr, nir_instr_type_ssa_undef);
642
643 nir_ssa_def_init(&instr->instr, &instr->def, num_components, bit_size, NULL);
644
645 return instr;
646 }
647
648 static nir_const_value
649 const_value_float(double d, unsigned bit_size)
650 {
651 nir_const_value v;
652 memset(&v, 0, sizeof(v));
653 switch (bit_size) {
654 case 16: v.u16 = _mesa_float_to_half(d); break;
655 case 32: v.f32 = d; break;
656 case 64: v.f64 = d; break;
657 default:
658 unreachable("Invalid bit size");
659 }
660 return v;
661 }
662
663 static nir_const_value
664 const_value_int(int64_t i, unsigned bit_size)
665 {
666 nir_const_value v;
667 memset(&v, 0, sizeof(v));
668 switch (bit_size) {
669 case 1: v.b = i & 1; break;
670 case 8: v.i8 = i; break;
671 case 16: v.i16 = i; break;
672 case 32: v.i32 = i; break;
673 case 64: v.i64 = i; break;
674 default:
675 unreachable("Invalid bit size");
676 }
677 return v;
678 }
679
680 nir_const_value
681 nir_alu_binop_identity(nir_op binop, unsigned bit_size)
682 {
683 const int64_t max_int = (1ull << (bit_size - 1)) - 1;
684 const int64_t min_int = -max_int - 1;
685 switch (binop) {
686 case nir_op_iadd:
687 return const_value_int(0, bit_size);
688 case nir_op_fadd:
689 return const_value_float(0, bit_size);
690 case nir_op_imul:
691 return const_value_int(1, bit_size);
692 case nir_op_fmul:
693 return const_value_float(1, bit_size);
694 case nir_op_imin:
695 return const_value_int(max_int, bit_size);
696 case nir_op_umin:
697 return const_value_int(~0ull, bit_size);
698 case nir_op_fmin:
699 return const_value_float(INFINITY, bit_size);
700 case nir_op_imax:
701 return const_value_int(min_int, bit_size);
702 case nir_op_umax:
703 return const_value_int(0, bit_size);
704 case nir_op_fmax:
705 return const_value_float(-INFINITY, bit_size);
706 case nir_op_iand:
707 return const_value_int(~0ull, bit_size);
708 case nir_op_ior:
709 return const_value_int(0, bit_size);
710 case nir_op_ixor:
711 return const_value_int(0, bit_size);
712 default:
713 unreachable("Invalid reduction operation");
714 }
715 }
716
717 nir_function_impl *
718 nir_cf_node_get_function(nir_cf_node *node)
719 {
720 while (node->type != nir_cf_node_function) {
721 node = node->parent;
722 }
723
724 return nir_cf_node_as_function(node);
725 }
726
727 /* Reduces a cursor by trying to convert everything to after and trying to
728 * go up to block granularity when possible.
729 */
730 static nir_cursor
731 reduce_cursor(nir_cursor cursor)
732 {
733 switch (cursor.option) {
734 case nir_cursor_before_block:
735 if (exec_list_is_empty(&cursor.block->instr_list)) {
736 /* Empty block. After is as good as before. */
737 cursor.option = nir_cursor_after_block;
738 }
739 return cursor;
740
741 case nir_cursor_after_block:
742 return cursor;
743
744 case nir_cursor_before_instr: {
745 nir_instr *prev_instr = nir_instr_prev(cursor.instr);
746 if (prev_instr) {
747 /* Before this instruction is after the previous */
748 cursor.instr = prev_instr;
749 cursor.option = nir_cursor_after_instr;
750 } else {
751 /* No previous instruction. Switch to before block */
752 cursor.block = cursor.instr->block;
753 cursor.option = nir_cursor_before_block;
754 }
755 return reduce_cursor(cursor);
756 }
757
758 case nir_cursor_after_instr:
759 if (nir_instr_next(cursor.instr) == NULL) {
760 /* This is the last instruction, switch to after block */
761 cursor.option = nir_cursor_after_block;
762 cursor.block = cursor.instr->block;
763 }
764 return cursor;
765
766 default:
767 unreachable("Inavlid cursor option");
768 }
769 }
770
771 bool
772 nir_cursors_equal(nir_cursor a, nir_cursor b)
773 {
774 /* Reduced cursors should be unique */
775 a = reduce_cursor(a);
776 b = reduce_cursor(b);
777
778 return a.block == b.block && a.option == b.option;
779 }
780
781 static bool
782 add_use_cb(nir_src *src, void *state)
783 {
784 nir_instr *instr = state;
785
786 src->parent_instr = instr;
787 list_addtail(&src->use_link,
788 src->is_ssa ? &src->ssa->uses : &src->reg.reg->uses);
789
790 return true;
791 }
792
793 static bool
794 add_ssa_def_cb(nir_ssa_def *def, void *state)
795 {
796 nir_instr *instr = state;
797
798 if (instr->block && def->index == UINT_MAX) {
799 nir_function_impl *impl =
800 nir_cf_node_get_function(&instr->block->cf_node);
801
802 def->index = impl->ssa_alloc++;
803 }
804
805 return true;
806 }
807
808 static bool
809 add_reg_def_cb(nir_dest *dest, void *state)
810 {
811 nir_instr *instr = state;
812
813 if (!dest->is_ssa) {
814 dest->reg.parent_instr = instr;
815 list_addtail(&dest->reg.def_link, &dest->reg.reg->defs);
816 }
817
818 return true;
819 }
820
821 static void
822 add_defs_uses(nir_instr *instr)
823 {
824 nir_foreach_src(instr, add_use_cb, instr);
825 nir_foreach_dest(instr, add_reg_def_cb, instr);
826 nir_foreach_ssa_def(instr, add_ssa_def_cb, instr);
827 }
828
829 void
830 nir_instr_insert(nir_cursor cursor, nir_instr *instr)
831 {
832 switch (cursor.option) {
833 case nir_cursor_before_block:
834 /* Only allow inserting jumps into empty blocks. */
835 if (instr->type == nir_instr_type_jump)
836 assert(exec_list_is_empty(&cursor.block->instr_list));
837
838 instr->block = cursor.block;
839 add_defs_uses(instr);
840 exec_list_push_head(&cursor.block->instr_list, &instr->node);
841 break;
842 case nir_cursor_after_block: {
843 /* Inserting instructions after a jump is illegal. */
844 nir_instr *last = nir_block_last_instr(cursor.block);
845 assert(last == NULL || last->type != nir_instr_type_jump);
846 (void) last;
847
848 instr->block = cursor.block;
849 add_defs_uses(instr);
850 exec_list_push_tail(&cursor.block->instr_list, &instr->node);
851 break;
852 }
853 case nir_cursor_before_instr:
854 assert(instr->type != nir_instr_type_jump);
855 instr->block = cursor.instr->block;
856 add_defs_uses(instr);
857 exec_node_insert_node_before(&cursor.instr->node, &instr->node);
858 break;
859 case nir_cursor_after_instr:
860 /* Inserting instructions after a jump is illegal. */
861 assert(cursor.instr->type != nir_instr_type_jump);
862
863 /* Only allow inserting jumps at the end of the block. */
864 if (instr->type == nir_instr_type_jump)
865 assert(cursor.instr == nir_block_last_instr(cursor.instr->block));
866
867 instr->block = cursor.instr->block;
868 add_defs_uses(instr);
869 exec_node_insert_after(&cursor.instr->node, &instr->node);
870 break;
871 }
872
873 if (instr->type == nir_instr_type_jump)
874 nir_handle_add_jump(instr->block);
875 }
876
877 static bool
878 src_is_valid(const nir_src *src)
879 {
880 return src->is_ssa ? (src->ssa != NULL) : (src->reg.reg != NULL);
881 }
882
883 static bool
884 remove_use_cb(nir_src *src, void *state)
885 {
886 (void) state;
887
888 if (src_is_valid(src))
889 list_del(&src->use_link);
890
891 return true;
892 }
893
894 static bool
895 remove_def_cb(nir_dest *dest, void *state)
896 {
897 (void) state;
898
899 if (!dest->is_ssa)
900 list_del(&dest->reg.def_link);
901
902 return true;
903 }
904
905 static void
906 remove_defs_uses(nir_instr *instr)
907 {
908 nir_foreach_dest(instr, remove_def_cb, instr);
909 nir_foreach_src(instr, remove_use_cb, instr);
910 }
911
912 void nir_instr_remove_v(nir_instr *instr)
913 {
914 remove_defs_uses(instr);
915 exec_node_remove(&instr->node);
916
917 if (instr->type == nir_instr_type_jump) {
918 nir_jump_instr *jump_instr = nir_instr_as_jump(instr);
919 nir_handle_remove_jump(instr->block, jump_instr->type);
920 }
921 }
922
923 /*@}*/
924
925 void
926 nir_index_local_regs(nir_function_impl *impl)
927 {
928 unsigned index = 0;
929 foreach_list_typed(nir_register, reg, node, &impl->registers) {
930 reg->index = index++;
931 }
932 impl->reg_alloc = index;
933 }
934
935 static bool
936 visit_alu_dest(nir_alu_instr *instr, nir_foreach_dest_cb cb, void *state)
937 {
938 return cb(&instr->dest.dest, state);
939 }
940
941 static bool
942 visit_deref_dest(nir_deref_instr *instr, nir_foreach_dest_cb cb, void *state)
943 {
944 return cb(&instr->dest, state);
945 }
946
947 static bool
948 visit_intrinsic_dest(nir_intrinsic_instr *instr, nir_foreach_dest_cb cb,
949 void *state)
950 {
951 if (nir_intrinsic_infos[instr->intrinsic].has_dest)
952 return cb(&instr->dest, state);
953
954 return true;
955 }
956
957 static bool
958 visit_texture_dest(nir_tex_instr *instr, nir_foreach_dest_cb cb,
959 void *state)
960 {
961 return cb(&instr->dest, state);
962 }
963
964 static bool
965 visit_phi_dest(nir_phi_instr *instr, nir_foreach_dest_cb cb, void *state)
966 {
967 return cb(&instr->dest, state);
968 }
969
970 static bool
971 visit_parallel_copy_dest(nir_parallel_copy_instr *instr,
972 nir_foreach_dest_cb cb, void *state)
973 {
974 nir_foreach_parallel_copy_entry(entry, instr) {
975 if (!cb(&entry->dest, state))
976 return false;
977 }
978
979 return true;
980 }
981
982 bool
983 nir_foreach_dest(nir_instr *instr, nir_foreach_dest_cb cb, void *state)
984 {
985 switch (instr->type) {
986 case nir_instr_type_alu:
987 return visit_alu_dest(nir_instr_as_alu(instr), cb, state);
988 case nir_instr_type_deref:
989 return visit_deref_dest(nir_instr_as_deref(instr), cb, state);
990 case nir_instr_type_intrinsic:
991 return visit_intrinsic_dest(nir_instr_as_intrinsic(instr), cb, state);
992 case nir_instr_type_tex:
993 return visit_texture_dest(nir_instr_as_tex(instr), cb, state);
994 case nir_instr_type_phi:
995 return visit_phi_dest(nir_instr_as_phi(instr), cb, state);
996 case nir_instr_type_parallel_copy:
997 return visit_parallel_copy_dest(nir_instr_as_parallel_copy(instr),
998 cb, state);
999
1000 case nir_instr_type_load_const:
1001 case nir_instr_type_ssa_undef:
1002 case nir_instr_type_call:
1003 case nir_instr_type_jump:
1004 break;
1005
1006 default:
1007 unreachable("Invalid instruction type");
1008 break;
1009 }
1010
1011 return true;
1012 }
1013
1014 struct foreach_ssa_def_state {
1015 nir_foreach_ssa_def_cb cb;
1016 void *client_state;
1017 };
1018
1019 static inline bool
1020 nir_ssa_def_visitor(nir_dest *dest, void *void_state)
1021 {
1022 struct foreach_ssa_def_state *state = void_state;
1023
1024 if (dest->is_ssa)
1025 return state->cb(&dest->ssa, state->client_state);
1026 else
1027 return true;
1028 }
1029
1030 bool
1031 nir_foreach_ssa_def(nir_instr *instr, nir_foreach_ssa_def_cb cb, void *state)
1032 {
1033 switch (instr->type) {
1034 case nir_instr_type_alu:
1035 case nir_instr_type_deref:
1036 case nir_instr_type_tex:
1037 case nir_instr_type_intrinsic:
1038 case nir_instr_type_phi:
1039 case nir_instr_type_parallel_copy: {
1040 struct foreach_ssa_def_state foreach_state = {cb, state};
1041 return nir_foreach_dest(instr, nir_ssa_def_visitor, &foreach_state);
1042 }
1043
1044 case nir_instr_type_load_const:
1045 return cb(&nir_instr_as_load_const(instr)->def, state);
1046 case nir_instr_type_ssa_undef:
1047 return cb(&nir_instr_as_ssa_undef(instr)->def, state);
1048 case nir_instr_type_call:
1049 case nir_instr_type_jump:
1050 return true;
1051 default:
1052 unreachable("Invalid instruction type");
1053 }
1054 }
1055
1056 nir_ssa_def *
1057 nir_instr_ssa_def(nir_instr *instr)
1058 {
1059 switch (instr->type) {
1060 case nir_instr_type_alu:
1061 assert(nir_instr_as_alu(instr)->dest.dest.is_ssa);
1062 return &nir_instr_as_alu(instr)->dest.dest.ssa;
1063
1064 case nir_instr_type_deref:
1065 assert(nir_instr_as_deref(instr)->dest.is_ssa);
1066 return &nir_instr_as_deref(instr)->dest.ssa;
1067
1068 case nir_instr_type_tex:
1069 assert(nir_instr_as_tex(instr)->dest.is_ssa);
1070 return &nir_instr_as_tex(instr)->dest.ssa;
1071
1072 case nir_instr_type_intrinsic: {
1073 nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
1074 if (nir_intrinsic_infos[intrin->intrinsic].has_dest) {
1075 assert(intrin->dest.is_ssa);
1076 return &intrin->dest.ssa;
1077 } else {
1078 return NULL;
1079 }
1080 }
1081
1082 case nir_instr_type_phi:
1083 assert(nir_instr_as_phi(instr)->dest.is_ssa);
1084 return &nir_instr_as_phi(instr)->dest.ssa;
1085
1086 case nir_instr_type_parallel_copy:
1087 unreachable("Parallel copies are unsupported by this function");
1088
1089 case nir_instr_type_load_const:
1090 return &nir_instr_as_load_const(instr)->def;
1091
1092 case nir_instr_type_ssa_undef:
1093 return &nir_instr_as_ssa_undef(instr)->def;
1094
1095 case nir_instr_type_call:
1096 case nir_instr_type_jump:
1097 return NULL;
1098 }
1099
1100 unreachable("Invalid instruction type");
1101 }
1102
1103 static bool
1104 visit_src(nir_src *src, nir_foreach_src_cb cb, void *state)
1105 {
1106 if (!cb(src, state))
1107 return false;
1108 if (!src->is_ssa && src->reg.indirect)
1109 return cb(src->reg.indirect, state);
1110 return true;
1111 }
1112
1113 static bool
1114 visit_alu_src(nir_alu_instr *instr, nir_foreach_src_cb cb, void *state)
1115 {
1116 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1117 if (!visit_src(&instr->src[i].src, cb, state))
1118 return false;
1119
1120 return true;
1121 }
1122
1123 static bool
1124 visit_deref_instr_src(nir_deref_instr *instr,
1125 nir_foreach_src_cb cb, void *state)
1126 {
1127 if (instr->deref_type != nir_deref_type_var) {
1128 if (!visit_src(&instr->parent, cb, state))
1129 return false;
1130 }
1131
1132 if (instr->deref_type == nir_deref_type_array ||
1133 instr->deref_type == nir_deref_type_ptr_as_array) {
1134 if (!visit_src(&instr->arr.index, cb, state))
1135 return false;
1136 }
1137
1138 return true;
1139 }
1140
1141 static bool
1142 visit_tex_src(nir_tex_instr *instr, nir_foreach_src_cb cb, void *state)
1143 {
1144 for (unsigned i = 0; i < instr->num_srcs; i++) {
1145 if (!visit_src(&instr->src[i].src, cb, state))
1146 return false;
1147 }
1148
1149 return true;
1150 }
1151
1152 static bool
1153 visit_intrinsic_src(nir_intrinsic_instr *instr, nir_foreach_src_cb cb,
1154 void *state)
1155 {
1156 unsigned num_srcs = nir_intrinsic_infos[instr->intrinsic].num_srcs;
1157 for (unsigned i = 0; i < num_srcs; i++) {
1158 if (!visit_src(&instr->src[i], cb, state))
1159 return false;
1160 }
1161
1162 return true;
1163 }
1164
1165 static bool
1166 visit_call_src(nir_call_instr *instr, nir_foreach_src_cb cb, void *state)
1167 {
1168 for (unsigned i = 0; i < instr->num_params; i++) {
1169 if (!visit_src(&instr->params[i], cb, state))
1170 return false;
1171 }
1172
1173 return true;
1174 }
1175
1176 static bool
1177 visit_phi_src(nir_phi_instr *instr, nir_foreach_src_cb cb, void *state)
1178 {
1179 nir_foreach_phi_src(src, instr) {
1180 if (!visit_src(&src->src, cb, state))
1181 return false;
1182 }
1183
1184 return true;
1185 }
1186
1187 static bool
1188 visit_parallel_copy_src(nir_parallel_copy_instr *instr,
1189 nir_foreach_src_cb cb, void *state)
1190 {
1191 nir_foreach_parallel_copy_entry(entry, instr) {
1192 if (!visit_src(&entry->src, cb, state))
1193 return false;
1194 }
1195
1196 return true;
1197 }
1198
1199 static bool
1200 visit_jump_src(nir_jump_instr *instr, nir_foreach_src_cb cb, void *state)
1201 {
1202 if (instr->type != nir_jump_goto_if)
1203 return true;
1204
1205 return visit_src(&instr->condition, cb, state);
1206 }
1207
1208 typedef struct {
1209 void *state;
1210 nir_foreach_src_cb cb;
1211 } visit_dest_indirect_state;
1212
1213 static bool
1214 visit_dest_indirect(nir_dest *dest, void *_state)
1215 {
1216 visit_dest_indirect_state *state = (visit_dest_indirect_state *) _state;
1217
1218 if (!dest->is_ssa && dest->reg.indirect)
1219 return state->cb(dest->reg.indirect, state->state);
1220
1221 return true;
1222 }
1223
1224 bool
1225 nir_foreach_src(nir_instr *instr, nir_foreach_src_cb cb, void *state)
1226 {
1227 switch (instr->type) {
1228 case nir_instr_type_alu:
1229 if (!visit_alu_src(nir_instr_as_alu(instr), cb, state))
1230 return false;
1231 break;
1232 case nir_instr_type_deref:
1233 if (!visit_deref_instr_src(nir_instr_as_deref(instr), cb, state))
1234 return false;
1235 break;
1236 case nir_instr_type_intrinsic:
1237 if (!visit_intrinsic_src(nir_instr_as_intrinsic(instr), cb, state))
1238 return false;
1239 break;
1240 case nir_instr_type_tex:
1241 if (!visit_tex_src(nir_instr_as_tex(instr), cb, state))
1242 return false;
1243 break;
1244 case nir_instr_type_call:
1245 if (!visit_call_src(nir_instr_as_call(instr), cb, state))
1246 return false;
1247 break;
1248 case nir_instr_type_load_const:
1249 /* Constant load instructions have no regular sources */
1250 break;
1251 case nir_instr_type_phi:
1252 if (!visit_phi_src(nir_instr_as_phi(instr), cb, state))
1253 return false;
1254 break;
1255 case nir_instr_type_parallel_copy:
1256 if (!visit_parallel_copy_src(nir_instr_as_parallel_copy(instr),
1257 cb, state))
1258 return false;
1259 break;
1260 case nir_instr_type_jump:
1261 return visit_jump_src(nir_instr_as_jump(instr), cb, state);
1262 case nir_instr_type_ssa_undef:
1263 return true;
1264
1265 default:
1266 unreachable("Invalid instruction type");
1267 break;
1268 }
1269
1270 visit_dest_indirect_state dest_state;
1271 dest_state.state = state;
1272 dest_state.cb = cb;
1273 return nir_foreach_dest(instr, visit_dest_indirect, &dest_state);
1274 }
1275
1276 bool
1277 nir_foreach_phi_src_leaving_block(nir_block *block,
1278 nir_foreach_src_cb cb,
1279 void *state)
1280 {
1281 for (unsigned i = 0; i < ARRAY_SIZE(block->successors); i++) {
1282 if (block->successors[i] == NULL)
1283 continue;
1284
1285 nir_foreach_instr(instr, block->successors[i]) {
1286 if (instr->type != nir_instr_type_phi)
1287 break;
1288
1289 nir_phi_instr *phi = nir_instr_as_phi(instr);
1290 nir_foreach_phi_src(phi_src, phi) {
1291 if (phi_src->pred == block) {
1292 if (!cb(&phi_src->src, state))
1293 return false;
1294 }
1295 }
1296 }
1297 }
1298
1299 return true;
1300 }
1301
1302 nir_const_value
1303 nir_const_value_for_float(double f, unsigned bit_size)
1304 {
1305 nir_const_value v;
1306 memset(&v, 0, sizeof(v));
1307
1308 switch (bit_size) {
1309 case 16:
1310 v.u16 = _mesa_float_to_half(f);
1311 break;
1312 case 32:
1313 v.f32 = f;
1314 break;
1315 case 64:
1316 v.f64 = f;
1317 break;
1318 default:
1319 unreachable("Invalid bit size");
1320 }
1321
1322 return v;
1323 }
1324
1325 double
1326 nir_const_value_as_float(nir_const_value value, unsigned bit_size)
1327 {
1328 switch (bit_size) {
1329 case 16: return _mesa_half_to_float(value.u16);
1330 case 32: return value.f32;
1331 case 64: return value.f64;
1332 default:
1333 unreachable("Invalid bit size");
1334 }
1335 }
1336
1337 nir_const_value *
1338 nir_src_as_const_value(nir_src src)
1339 {
1340 if (!src.is_ssa)
1341 return NULL;
1342
1343 if (src.ssa->parent_instr->type != nir_instr_type_load_const)
1344 return NULL;
1345
1346 nir_load_const_instr *load = nir_instr_as_load_const(src.ssa->parent_instr);
1347
1348 return load->value;
1349 }
1350
1351 /**
1352 * Returns true if the source is known to be dynamically uniform. Otherwise it
1353 * returns false which means it may or may not be dynamically uniform but it
1354 * can't be determined.
1355 */
1356 bool
1357 nir_src_is_dynamically_uniform(nir_src src)
1358 {
1359 if (!src.is_ssa)
1360 return false;
1361
1362 /* Constants are trivially dynamically uniform */
1363 if (src.ssa->parent_instr->type == nir_instr_type_load_const)
1364 return true;
1365
1366 /* As are uniform variables */
1367 if (src.ssa->parent_instr->type == nir_instr_type_intrinsic) {
1368 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(src.ssa->parent_instr);
1369 if (intr->intrinsic == nir_intrinsic_load_uniform &&
1370 nir_src_is_dynamically_uniform(intr->src[0]))
1371 return true;
1372 }
1373
1374 /* Operating together dynamically uniform expressions produces a
1375 * dynamically uniform result
1376 */
1377 if (src.ssa->parent_instr->type == nir_instr_type_alu) {
1378 nir_alu_instr *alu = nir_instr_as_alu(src.ssa->parent_instr);
1379 for (int i = 0; i < nir_op_infos[alu->op].num_inputs; i++) {
1380 if (!nir_src_is_dynamically_uniform(alu->src[i].src))
1381 return false;
1382 }
1383
1384 return true;
1385 }
1386
1387 /* XXX: this could have many more tests, such as when a sampler function is
1388 * called with dynamically uniform arguments.
1389 */
1390 return false;
1391 }
1392
1393 static void
1394 src_remove_all_uses(nir_src *src)
1395 {
1396 for (; src; src = src->is_ssa ? NULL : src->reg.indirect) {
1397 if (!src_is_valid(src))
1398 continue;
1399
1400 list_del(&src->use_link);
1401 }
1402 }
1403
1404 static void
1405 src_add_all_uses(nir_src *src, nir_instr *parent_instr, nir_if *parent_if)
1406 {
1407 for (; src; src = src->is_ssa ? NULL : src->reg.indirect) {
1408 if (!src_is_valid(src))
1409 continue;
1410
1411 if (parent_instr) {
1412 src->parent_instr = parent_instr;
1413 if (src->is_ssa)
1414 list_addtail(&src->use_link, &src->ssa->uses);
1415 else
1416 list_addtail(&src->use_link, &src->reg.reg->uses);
1417 } else {
1418 assert(parent_if);
1419 src->parent_if = parent_if;
1420 if (src->is_ssa)
1421 list_addtail(&src->use_link, &src->ssa->if_uses);
1422 else
1423 list_addtail(&src->use_link, &src->reg.reg->if_uses);
1424 }
1425 }
1426 }
1427
1428 void
1429 nir_instr_rewrite_src(nir_instr *instr, nir_src *src, nir_src new_src)
1430 {
1431 assert(!src_is_valid(src) || src->parent_instr == instr);
1432
1433 src_remove_all_uses(src);
1434 *src = new_src;
1435 src_add_all_uses(src, instr, NULL);
1436 }
1437
1438 void
1439 nir_instr_move_src(nir_instr *dest_instr, nir_src *dest, nir_src *src)
1440 {
1441 assert(!src_is_valid(dest) || dest->parent_instr == dest_instr);
1442
1443 src_remove_all_uses(dest);
1444 src_remove_all_uses(src);
1445 *dest = *src;
1446 *src = NIR_SRC_INIT;
1447 src_add_all_uses(dest, dest_instr, NULL);
1448 }
1449
1450 void
1451 nir_if_rewrite_condition(nir_if *if_stmt, nir_src new_src)
1452 {
1453 nir_src *src = &if_stmt->condition;
1454 assert(!src_is_valid(src) || src->parent_if == if_stmt);
1455
1456 src_remove_all_uses(src);
1457 *src = new_src;
1458 src_add_all_uses(src, NULL, if_stmt);
1459 }
1460
1461 void
1462 nir_instr_rewrite_dest(nir_instr *instr, nir_dest *dest, nir_dest new_dest)
1463 {
1464 if (dest->is_ssa) {
1465 /* We can only overwrite an SSA destination if it has no uses. */
1466 assert(list_is_empty(&dest->ssa.uses) && list_is_empty(&dest->ssa.if_uses));
1467 } else {
1468 list_del(&dest->reg.def_link);
1469 if (dest->reg.indirect)
1470 src_remove_all_uses(dest->reg.indirect);
1471 }
1472
1473 /* We can't re-write with an SSA def */
1474 assert(!new_dest.is_ssa);
1475
1476 nir_dest_copy(dest, &new_dest, instr);
1477
1478 dest->reg.parent_instr = instr;
1479 list_addtail(&dest->reg.def_link, &new_dest.reg.reg->defs);
1480
1481 if (dest->reg.indirect)
1482 src_add_all_uses(dest->reg.indirect, instr, NULL);
1483 }
1484
1485 /* note: does *not* take ownership of 'name' */
1486 void
1487 nir_ssa_def_init(nir_instr *instr, nir_ssa_def *def,
1488 unsigned num_components,
1489 unsigned bit_size, const char *name)
1490 {
1491 def->name = ralloc_strdup(instr, name);
1492 def->live_index = UINT_MAX; /* Something clearly OOB */
1493 def->parent_instr = instr;
1494 list_inithead(&def->uses);
1495 list_inithead(&def->if_uses);
1496 def->num_components = num_components;
1497 def->bit_size = bit_size;
1498 def->divergent = true; /* This is the safer default */
1499
1500 if (instr->block) {
1501 nir_function_impl *impl =
1502 nir_cf_node_get_function(&instr->block->cf_node);
1503
1504 def->index = impl->ssa_alloc++;
1505 } else {
1506 def->index = UINT_MAX;
1507 }
1508 }
1509
1510 /* note: does *not* take ownership of 'name' */
1511 void
1512 nir_ssa_dest_init(nir_instr *instr, nir_dest *dest,
1513 unsigned num_components, unsigned bit_size,
1514 const char *name)
1515 {
1516 dest->is_ssa = true;
1517 nir_ssa_def_init(instr, &dest->ssa, num_components, bit_size, name);
1518 }
1519
1520 void
1521 nir_ssa_def_rewrite_uses(nir_ssa_def *def, nir_src new_src)
1522 {
1523 assert(!new_src.is_ssa || def != new_src.ssa);
1524
1525 nir_foreach_use_safe(use_src, def)
1526 nir_instr_rewrite_src(use_src->parent_instr, use_src, new_src);
1527
1528 nir_foreach_if_use_safe(use_src, def)
1529 nir_if_rewrite_condition(use_src->parent_if, new_src);
1530 }
1531
1532 static bool
1533 is_instr_between(nir_instr *start, nir_instr *end, nir_instr *between)
1534 {
1535 assert(start->block == end->block);
1536
1537 if (between->block != start->block)
1538 return false;
1539
1540 /* Search backwards looking for "between" */
1541 while (start != end) {
1542 if (between == end)
1543 return true;
1544
1545 end = nir_instr_prev(end);
1546 assert(end);
1547 }
1548
1549 return false;
1550 }
1551
1552 /* Replaces all uses of the given SSA def with the given source but only if
1553 * the use comes after the after_me instruction. This can be useful if you
1554 * are emitting code to fix up the result of some instruction: you can freely
1555 * use the result in that code and then call rewrite_uses_after and pass the
1556 * last fixup instruction as after_me and it will replace all of the uses you
1557 * want without touching the fixup code.
1558 *
1559 * This function assumes that after_me is in the same block as
1560 * def->parent_instr and that after_me comes after def->parent_instr.
1561 */
1562 void
1563 nir_ssa_def_rewrite_uses_after(nir_ssa_def *def, nir_src new_src,
1564 nir_instr *after_me)
1565 {
1566 if (new_src.is_ssa && def == new_src.ssa)
1567 return;
1568
1569 nir_foreach_use_safe(use_src, def) {
1570 assert(use_src->parent_instr != def->parent_instr);
1571 /* Since def already dominates all of its uses, the only way a use can
1572 * not be dominated by after_me is if it is between def and after_me in
1573 * the instruction list.
1574 */
1575 if (!is_instr_between(def->parent_instr, after_me, use_src->parent_instr))
1576 nir_instr_rewrite_src(use_src->parent_instr, use_src, new_src);
1577 }
1578
1579 nir_foreach_if_use_safe(use_src, def)
1580 nir_if_rewrite_condition(use_src->parent_if, new_src);
1581 }
1582
1583 nir_component_mask_t
1584 nir_ssa_def_components_read(const nir_ssa_def *def)
1585 {
1586 nir_component_mask_t read_mask = 0;
1587 nir_foreach_use(use, def) {
1588 if (use->parent_instr->type == nir_instr_type_alu) {
1589 nir_alu_instr *alu = nir_instr_as_alu(use->parent_instr);
1590 nir_alu_src *alu_src = exec_node_data(nir_alu_src, use, src);
1591 int src_idx = alu_src - &alu->src[0];
1592 assert(src_idx >= 0 && src_idx < nir_op_infos[alu->op].num_inputs);
1593 read_mask |= nir_alu_instr_src_read_mask(alu, src_idx);
1594 } else {
1595 return (1 << def->num_components) - 1;
1596 }
1597 }
1598
1599 if (!list_is_empty(&def->if_uses))
1600 read_mask |= 1;
1601
1602 return read_mask;
1603 }
1604
1605 nir_block *
1606 nir_block_unstructured_next(nir_block *block)
1607 {
1608 if (block == NULL) {
1609 /* nir_foreach_block_unstructured_safe() will call this function on a
1610 * NULL block after the last iteration, but it won't use the result so
1611 * just return NULL here.
1612 */
1613 return NULL;
1614 }
1615
1616 nir_cf_node *cf_next = nir_cf_node_next(&block->cf_node);
1617 if (cf_next == NULL && block->cf_node.parent->type == nir_cf_node_function)
1618 return NULL;
1619
1620 if (cf_next && cf_next->type == nir_cf_node_block)
1621 return nir_cf_node_as_block(cf_next);
1622
1623 return nir_block_cf_tree_next(block);
1624 }
1625
1626 nir_block *
1627 nir_unstructured_start_block(nir_function_impl *impl)
1628 {
1629 return nir_start_block(impl);
1630 }
1631
1632 nir_block *
1633 nir_block_cf_tree_next(nir_block *block)
1634 {
1635 if (block == NULL) {
1636 /* nir_foreach_block_safe() will call this function on a NULL block
1637 * after the last iteration, but it won't use the result so just return
1638 * NULL here.
1639 */
1640 return NULL;
1641 }
1642
1643 assert(nir_cf_node_get_function(&block->cf_node)->structured);
1644
1645 nir_cf_node *cf_next = nir_cf_node_next(&block->cf_node);
1646 if (cf_next)
1647 return nir_cf_node_cf_tree_first(cf_next);
1648
1649 nir_cf_node *parent = block->cf_node.parent;
1650
1651 switch (parent->type) {
1652 case nir_cf_node_if: {
1653 /* Are we at the end of the if? Go to the beginning of the else */
1654 nir_if *if_stmt = nir_cf_node_as_if(parent);
1655 if (block == nir_if_last_then_block(if_stmt))
1656 return nir_if_first_else_block(if_stmt);
1657
1658 assert(block == nir_if_last_else_block(if_stmt));
1659 }
1660 /* fallthrough */
1661
1662 case nir_cf_node_loop:
1663 return nir_cf_node_as_block(nir_cf_node_next(parent));
1664
1665 case nir_cf_node_function:
1666 return NULL;
1667
1668 default:
1669 unreachable("unknown cf node type");
1670 }
1671 }
1672
1673 nir_block *
1674 nir_block_cf_tree_prev(nir_block *block)
1675 {
1676 if (block == NULL) {
1677 /* do this for consistency with nir_block_cf_tree_next() */
1678 return NULL;
1679 }
1680
1681 assert(nir_cf_node_get_function(&block->cf_node)->structured);
1682
1683 nir_cf_node *cf_prev = nir_cf_node_prev(&block->cf_node);
1684 if (cf_prev)
1685 return nir_cf_node_cf_tree_last(cf_prev);
1686
1687 nir_cf_node *parent = block->cf_node.parent;
1688
1689 switch (parent->type) {
1690 case nir_cf_node_if: {
1691 /* Are we at the beginning of the else? Go to the end of the if */
1692 nir_if *if_stmt = nir_cf_node_as_if(parent);
1693 if (block == nir_if_first_else_block(if_stmt))
1694 return nir_if_last_then_block(if_stmt);
1695
1696 assert(block == nir_if_first_then_block(if_stmt));
1697 }
1698 /* fallthrough */
1699
1700 case nir_cf_node_loop:
1701 return nir_cf_node_as_block(nir_cf_node_prev(parent));
1702
1703 case nir_cf_node_function:
1704 return NULL;
1705
1706 default:
1707 unreachable("unknown cf node type");
1708 }
1709 }
1710
1711 nir_block *nir_cf_node_cf_tree_first(nir_cf_node *node)
1712 {
1713 switch (node->type) {
1714 case nir_cf_node_function: {
1715 nir_function_impl *impl = nir_cf_node_as_function(node);
1716 return nir_start_block(impl);
1717 }
1718
1719 case nir_cf_node_if: {
1720 nir_if *if_stmt = nir_cf_node_as_if(node);
1721 return nir_if_first_then_block(if_stmt);
1722 }
1723
1724 case nir_cf_node_loop: {
1725 nir_loop *loop = nir_cf_node_as_loop(node);
1726 return nir_loop_first_block(loop);
1727 }
1728
1729 case nir_cf_node_block: {
1730 return nir_cf_node_as_block(node);
1731 }
1732
1733 default:
1734 unreachable("unknown node type");
1735 }
1736 }
1737
1738 nir_block *nir_cf_node_cf_tree_last(nir_cf_node *node)
1739 {
1740 switch (node->type) {
1741 case nir_cf_node_function: {
1742 nir_function_impl *impl = nir_cf_node_as_function(node);
1743 return nir_impl_last_block(impl);
1744 }
1745
1746 case nir_cf_node_if: {
1747 nir_if *if_stmt = nir_cf_node_as_if(node);
1748 return nir_if_last_else_block(if_stmt);
1749 }
1750
1751 case nir_cf_node_loop: {
1752 nir_loop *loop = nir_cf_node_as_loop(node);
1753 return nir_loop_last_block(loop);
1754 }
1755
1756 case nir_cf_node_block: {
1757 return nir_cf_node_as_block(node);
1758 }
1759
1760 default:
1761 unreachable("unknown node type");
1762 }
1763 }
1764
1765 nir_block *nir_cf_node_cf_tree_next(nir_cf_node *node)
1766 {
1767 if (node->type == nir_cf_node_block)
1768 return nir_block_cf_tree_next(nir_cf_node_as_block(node));
1769 else if (node->type == nir_cf_node_function)
1770 return NULL;
1771 else
1772 return nir_cf_node_as_block(nir_cf_node_next(node));
1773 }
1774
1775 nir_if *
1776 nir_block_get_following_if(nir_block *block)
1777 {
1778 if (exec_node_is_tail_sentinel(&block->cf_node.node))
1779 return NULL;
1780
1781 if (nir_cf_node_is_last(&block->cf_node))
1782 return NULL;
1783
1784 nir_cf_node *next_node = nir_cf_node_next(&block->cf_node);
1785
1786 if (next_node->type != nir_cf_node_if)
1787 return NULL;
1788
1789 return nir_cf_node_as_if(next_node);
1790 }
1791
1792 nir_loop *
1793 nir_block_get_following_loop(nir_block *block)
1794 {
1795 if (exec_node_is_tail_sentinel(&block->cf_node.node))
1796 return NULL;
1797
1798 if (nir_cf_node_is_last(&block->cf_node))
1799 return NULL;
1800
1801 nir_cf_node *next_node = nir_cf_node_next(&block->cf_node);
1802
1803 if (next_node->type != nir_cf_node_loop)
1804 return NULL;
1805
1806 return nir_cf_node_as_loop(next_node);
1807 }
1808
1809 void
1810 nir_index_blocks(nir_function_impl *impl)
1811 {
1812 unsigned index = 0;
1813
1814 if (impl->valid_metadata & nir_metadata_block_index)
1815 return;
1816
1817 nir_foreach_block_unstructured(block, impl) {
1818 block->index = index++;
1819 }
1820
1821 /* The end_block isn't really part of the program, which is why its index
1822 * is >= num_blocks.
1823 */
1824 impl->num_blocks = impl->end_block->index = index;
1825 }
1826
1827 static bool
1828 index_ssa_def_cb(nir_ssa_def *def, void *state)
1829 {
1830 unsigned *index = (unsigned *) state;
1831 def->index = (*index)++;
1832
1833 return true;
1834 }
1835
1836 /**
1837 * The indices are applied top-to-bottom which has the very nice property
1838 * that, if A dominates B, then A->index <= B->index.
1839 */
1840 void
1841 nir_index_ssa_defs(nir_function_impl *impl)
1842 {
1843 unsigned index = 0;
1844
1845 nir_foreach_block_unstructured(block, impl) {
1846 nir_foreach_instr(instr, block)
1847 nir_foreach_ssa_def(instr, index_ssa_def_cb, &index);
1848 }
1849
1850 impl->ssa_alloc = index;
1851 }
1852
1853 /**
1854 * The indices are applied top-to-bottom which has the very nice property
1855 * that, if A dominates B, then A->index <= B->index.
1856 */
1857 unsigned
1858 nir_index_instrs(nir_function_impl *impl)
1859 {
1860 unsigned index = 0;
1861
1862 nir_foreach_block(block, impl) {
1863 nir_foreach_instr(instr, block)
1864 instr->index = index++;
1865 }
1866
1867 return index;
1868 }
1869
1870 unsigned
1871 nir_shader_index_vars(nir_shader *shader, nir_variable_mode modes)
1872 {
1873 unsigned count = 0;
1874 nir_foreach_variable_with_modes(var, shader, modes)
1875 var->index = count++;
1876 return count;
1877 }
1878
1879 unsigned
1880 nir_function_impl_index_vars(nir_function_impl *impl)
1881 {
1882 unsigned count = 0;
1883 nir_foreach_function_temp_variable(var, impl)
1884 var->index = count++;
1885 return count;
1886 }
1887
1888 static nir_instr *
1889 cursor_next_instr(nir_cursor cursor)
1890 {
1891 switch (cursor.option) {
1892 case nir_cursor_before_block:
1893 for (nir_block *block = cursor.block; block;
1894 block = nir_block_cf_tree_next(block)) {
1895 nir_instr *instr = nir_block_first_instr(block);
1896 if (instr)
1897 return instr;
1898 }
1899 return NULL;
1900
1901 case nir_cursor_after_block:
1902 cursor.block = nir_block_cf_tree_next(cursor.block);
1903 if (cursor.block == NULL)
1904 return NULL;
1905
1906 cursor.option = nir_cursor_before_block;
1907 return cursor_next_instr(cursor);
1908
1909 case nir_cursor_before_instr:
1910 return cursor.instr;
1911
1912 case nir_cursor_after_instr:
1913 if (nir_instr_next(cursor.instr))
1914 return nir_instr_next(cursor.instr);
1915
1916 cursor.option = nir_cursor_after_block;
1917 cursor.block = cursor.instr->block;
1918 return cursor_next_instr(cursor);
1919 }
1920
1921 unreachable("Inavlid cursor option");
1922 }
1923
1924 ASSERTED static bool
1925 dest_is_ssa(nir_dest *dest, void *_state)
1926 {
1927 (void) _state;
1928 return dest->is_ssa;
1929 }
1930
1931 bool
1932 nir_function_impl_lower_instructions(nir_function_impl *impl,
1933 nir_instr_filter_cb filter,
1934 nir_lower_instr_cb lower,
1935 void *cb_data)
1936 {
1937 nir_builder b;
1938 nir_builder_init(&b, impl);
1939
1940 nir_metadata preserved = nir_metadata_block_index |
1941 nir_metadata_dominance;
1942
1943 bool progress = false;
1944 nir_cursor iter = nir_before_cf_list(&impl->body);
1945 nir_instr *instr;
1946 while ((instr = cursor_next_instr(iter)) != NULL) {
1947 if (filter && !filter(instr, cb_data)) {
1948 iter = nir_after_instr(instr);
1949 continue;
1950 }
1951
1952 assert(nir_foreach_dest(instr, dest_is_ssa, NULL));
1953 nir_ssa_def *old_def = nir_instr_ssa_def(instr);
1954 if (old_def == NULL) {
1955 iter = nir_after_instr(instr);
1956 continue;
1957 }
1958
1959 /* We're about to ask the callback to generate a replacement for instr.
1960 * Save off the uses from instr's SSA def so we know what uses to
1961 * rewrite later. If we use nir_ssa_def_rewrite_uses, it fails in the
1962 * case where the generated replacement code uses the result of instr
1963 * itself. If we use nir_ssa_def_rewrite_uses_after (which is the
1964 * normal solution to this problem), it doesn't work well if control-
1965 * flow is inserted as part of the replacement, doesn't handle cases
1966 * where the replacement is something consumed by instr, and suffers
1967 * from performance issues. This is the only way to 100% guarantee
1968 * that we rewrite the correct set efficiently.
1969 */
1970 struct list_head old_uses, old_if_uses;
1971 list_replace(&old_def->uses, &old_uses);
1972 list_inithead(&old_def->uses);
1973 list_replace(&old_def->if_uses, &old_if_uses);
1974 list_inithead(&old_def->if_uses);
1975
1976 b.cursor = nir_after_instr(instr);
1977 nir_ssa_def *new_def = lower(&b, instr, cb_data);
1978 if (new_def && new_def != NIR_LOWER_INSTR_PROGRESS) {
1979 assert(old_def != NULL);
1980 if (new_def->parent_instr->block != instr->block)
1981 preserved = nir_metadata_none;
1982
1983 nir_src new_src = nir_src_for_ssa(new_def);
1984 list_for_each_entry_safe(nir_src, use_src, &old_uses, use_link)
1985 nir_instr_rewrite_src(use_src->parent_instr, use_src, new_src);
1986
1987 list_for_each_entry_safe(nir_src, use_src, &old_if_uses, use_link)
1988 nir_if_rewrite_condition(use_src->parent_if, new_src);
1989
1990 if (list_is_empty(&old_def->uses) && list_is_empty(&old_def->if_uses)) {
1991 iter = nir_instr_remove(instr);
1992 } else {
1993 iter = nir_after_instr(instr);
1994 }
1995 progress = true;
1996 } else {
1997 /* We didn't end up lowering after all. Put the uses back */
1998 if (old_def) {
1999 list_replace(&old_uses, &old_def->uses);
2000 list_replace(&old_if_uses, &old_def->if_uses);
2001 }
2002 iter = nir_after_instr(instr);
2003
2004 if (new_def == NIR_LOWER_INSTR_PROGRESS)
2005 progress = true;
2006 }
2007 }
2008
2009 if (progress) {
2010 nir_metadata_preserve(impl, preserved);
2011 } else {
2012 nir_metadata_preserve(impl, nir_metadata_all);
2013 }
2014
2015 return progress;
2016 }
2017
2018 bool
2019 nir_shader_lower_instructions(nir_shader *shader,
2020 nir_instr_filter_cb filter,
2021 nir_lower_instr_cb lower,
2022 void *cb_data)
2023 {
2024 bool progress = false;
2025
2026 nir_foreach_function(function, shader) {
2027 if (function->impl &&
2028 nir_function_impl_lower_instructions(function->impl,
2029 filter, lower, cb_data))
2030 progress = true;
2031 }
2032
2033 return progress;
2034 }
2035
2036 nir_intrinsic_op
2037 nir_intrinsic_from_system_value(gl_system_value val)
2038 {
2039 switch (val) {
2040 case SYSTEM_VALUE_VERTEX_ID:
2041 return nir_intrinsic_load_vertex_id;
2042 case SYSTEM_VALUE_INSTANCE_ID:
2043 return nir_intrinsic_load_instance_id;
2044 case SYSTEM_VALUE_DRAW_ID:
2045 return nir_intrinsic_load_draw_id;
2046 case SYSTEM_VALUE_BASE_INSTANCE:
2047 return nir_intrinsic_load_base_instance;
2048 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
2049 return nir_intrinsic_load_vertex_id_zero_base;
2050 case SYSTEM_VALUE_IS_INDEXED_DRAW:
2051 return nir_intrinsic_load_is_indexed_draw;
2052 case SYSTEM_VALUE_FIRST_VERTEX:
2053 return nir_intrinsic_load_first_vertex;
2054 case SYSTEM_VALUE_BASE_VERTEX:
2055 return nir_intrinsic_load_base_vertex;
2056 case SYSTEM_VALUE_INVOCATION_ID:
2057 return nir_intrinsic_load_invocation_id;
2058 case SYSTEM_VALUE_FRAG_COORD:
2059 return nir_intrinsic_load_frag_coord;
2060 case SYSTEM_VALUE_POINT_COORD:
2061 return nir_intrinsic_load_point_coord;
2062 case SYSTEM_VALUE_LINE_COORD:
2063 return nir_intrinsic_load_line_coord;
2064 case SYSTEM_VALUE_FRONT_FACE:
2065 return nir_intrinsic_load_front_face;
2066 case SYSTEM_VALUE_SAMPLE_ID:
2067 return nir_intrinsic_load_sample_id;
2068 case SYSTEM_VALUE_SAMPLE_POS:
2069 return nir_intrinsic_load_sample_pos;
2070 case SYSTEM_VALUE_SAMPLE_MASK_IN:
2071 return nir_intrinsic_load_sample_mask_in;
2072 case SYSTEM_VALUE_LOCAL_INVOCATION_ID:
2073 return nir_intrinsic_load_local_invocation_id;
2074 case SYSTEM_VALUE_LOCAL_INVOCATION_INDEX:
2075 return nir_intrinsic_load_local_invocation_index;
2076 case SYSTEM_VALUE_WORK_GROUP_ID:
2077 return nir_intrinsic_load_work_group_id;
2078 case SYSTEM_VALUE_NUM_WORK_GROUPS:
2079 return nir_intrinsic_load_num_work_groups;
2080 case SYSTEM_VALUE_PRIMITIVE_ID:
2081 return nir_intrinsic_load_primitive_id;
2082 case SYSTEM_VALUE_TESS_COORD:
2083 return nir_intrinsic_load_tess_coord;
2084 case SYSTEM_VALUE_TESS_LEVEL_OUTER:
2085 return nir_intrinsic_load_tess_level_outer;
2086 case SYSTEM_VALUE_TESS_LEVEL_INNER:
2087 return nir_intrinsic_load_tess_level_inner;
2088 case SYSTEM_VALUE_TESS_LEVEL_OUTER_DEFAULT:
2089 return nir_intrinsic_load_tess_level_outer_default;
2090 case SYSTEM_VALUE_TESS_LEVEL_INNER_DEFAULT:
2091 return nir_intrinsic_load_tess_level_inner_default;
2092 case SYSTEM_VALUE_VERTICES_IN:
2093 return nir_intrinsic_load_patch_vertices_in;
2094 case SYSTEM_VALUE_HELPER_INVOCATION:
2095 return nir_intrinsic_load_helper_invocation;
2096 case SYSTEM_VALUE_COLOR0:
2097 return nir_intrinsic_load_color0;
2098 case SYSTEM_VALUE_COLOR1:
2099 return nir_intrinsic_load_color1;
2100 case SYSTEM_VALUE_VIEW_INDEX:
2101 return nir_intrinsic_load_view_index;
2102 case SYSTEM_VALUE_SUBGROUP_SIZE:
2103 return nir_intrinsic_load_subgroup_size;
2104 case SYSTEM_VALUE_SUBGROUP_INVOCATION:
2105 return nir_intrinsic_load_subgroup_invocation;
2106 case SYSTEM_VALUE_SUBGROUP_EQ_MASK:
2107 return nir_intrinsic_load_subgroup_eq_mask;
2108 case SYSTEM_VALUE_SUBGROUP_GE_MASK:
2109 return nir_intrinsic_load_subgroup_ge_mask;
2110 case SYSTEM_VALUE_SUBGROUP_GT_MASK:
2111 return nir_intrinsic_load_subgroup_gt_mask;
2112 case SYSTEM_VALUE_SUBGROUP_LE_MASK:
2113 return nir_intrinsic_load_subgroup_le_mask;
2114 case SYSTEM_VALUE_SUBGROUP_LT_MASK:
2115 return nir_intrinsic_load_subgroup_lt_mask;
2116 case SYSTEM_VALUE_NUM_SUBGROUPS:
2117 return nir_intrinsic_load_num_subgroups;
2118 case SYSTEM_VALUE_SUBGROUP_ID:
2119 return nir_intrinsic_load_subgroup_id;
2120 case SYSTEM_VALUE_LOCAL_GROUP_SIZE:
2121 return nir_intrinsic_load_local_group_size;
2122 case SYSTEM_VALUE_GLOBAL_INVOCATION_ID:
2123 return nir_intrinsic_load_global_invocation_id;
2124 case SYSTEM_VALUE_BASE_GLOBAL_INVOCATION_ID:
2125 return nir_intrinsic_load_base_global_invocation_id;
2126 case SYSTEM_VALUE_GLOBAL_INVOCATION_INDEX:
2127 return nir_intrinsic_load_global_invocation_index;
2128 case SYSTEM_VALUE_WORK_DIM:
2129 return nir_intrinsic_load_work_dim;
2130 case SYSTEM_VALUE_USER_DATA_AMD:
2131 return nir_intrinsic_load_user_data_amd;
2132 default:
2133 unreachable("system value does not directly correspond to intrinsic");
2134 }
2135 }
2136
2137 gl_system_value
2138 nir_system_value_from_intrinsic(nir_intrinsic_op intrin)
2139 {
2140 switch (intrin) {
2141 case nir_intrinsic_load_vertex_id:
2142 return SYSTEM_VALUE_VERTEX_ID;
2143 case nir_intrinsic_load_instance_id:
2144 return SYSTEM_VALUE_INSTANCE_ID;
2145 case nir_intrinsic_load_draw_id:
2146 return SYSTEM_VALUE_DRAW_ID;
2147 case nir_intrinsic_load_base_instance:
2148 return SYSTEM_VALUE_BASE_INSTANCE;
2149 case nir_intrinsic_load_vertex_id_zero_base:
2150 return SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
2151 case nir_intrinsic_load_first_vertex:
2152 return SYSTEM_VALUE_FIRST_VERTEX;
2153 case nir_intrinsic_load_is_indexed_draw:
2154 return SYSTEM_VALUE_IS_INDEXED_DRAW;
2155 case nir_intrinsic_load_base_vertex:
2156 return SYSTEM_VALUE_BASE_VERTEX;
2157 case nir_intrinsic_load_invocation_id:
2158 return SYSTEM_VALUE_INVOCATION_ID;
2159 case nir_intrinsic_load_frag_coord:
2160 return SYSTEM_VALUE_FRAG_COORD;
2161 case nir_intrinsic_load_point_coord:
2162 return SYSTEM_VALUE_POINT_COORD;
2163 case nir_intrinsic_load_line_coord:
2164 return SYSTEM_VALUE_LINE_COORD;
2165 case nir_intrinsic_load_front_face:
2166 return SYSTEM_VALUE_FRONT_FACE;
2167 case nir_intrinsic_load_sample_id:
2168 return SYSTEM_VALUE_SAMPLE_ID;
2169 case nir_intrinsic_load_sample_pos:
2170 return SYSTEM_VALUE_SAMPLE_POS;
2171 case nir_intrinsic_load_sample_mask_in:
2172 return SYSTEM_VALUE_SAMPLE_MASK_IN;
2173 case nir_intrinsic_load_local_invocation_id:
2174 return SYSTEM_VALUE_LOCAL_INVOCATION_ID;
2175 case nir_intrinsic_load_local_invocation_index:
2176 return SYSTEM_VALUE_LOCAL_INVOCATION_INDEX;
2177 case nir_intrinsic_load_num_work_groups:
2178 return SYSTEM_VALUE_NUM_WORK_GROUPS;
2179 case nir_intrinsic_load_work_group_id:
2180 return SYSTEM_VALUE_WORK_GROUP_ID;
2181 case nir_intrinsic_load_primitive_id:
2182 return SYSTEM_VALUE_PRIMITIVE_ID;
2183 case nir_intrinsic_load_tess_coord:
2184 return SYSTEM_VALUE_TESS_COORD;
2185 case nir_intrinsic_load_tess_level_outer:
2186 return SYSTEM_VALUE_TESS_LEVEL_OUTER;
2187 case nir_intrinsic_load_tess_level_inner:
2188 return SYSTEM_VALUE_TESS_LEVEL_INNER;
2189 case nir_intrinsic_load_tess_level_outer_default:
2190 return SYSTEM_VALUE_TESS_LEVEL_OUTER_DEFAULT;
2191 case nir_intrinsic_load_tess_level_inner_default:
2192 return SYSTEM_VALUE_TESS_LEVEL_INNER_DEFAULT;
2193 case nir_intrinsic_load_patch_vertices_in:
2194 return SYSTEM_VALUE_VERTICES_IN;
2195 case nir_intrinsic_load_helper_invocation:
2196 return SYSTEM_VALUE_HELPER_INVOCATION;
2197 case nir_intrinsic_load_color0:
2198 return SYSTEM_VALUE_COLOR0;
2199 case nir_intrinsic_load_color1:
2200 return SYSTEM_VALUE_COLOR1;
2201 case nir_intrinsic_load_view_index:
2202 return SYSTEM_VALUE_VIEW_INDEX;
2203 case nir_intrinsic_load_subgroup_size:
2204 return SYSTEM_VALUE_SUBGROUP_SIZE;
2205 case nir_intrinsic_load_subgroup_invocation:
2206 return SYSTEM_VALUE_SUBGROUP_INVOCATION;
2207 case nir_intrinsic_load_subgroup_eq_mask:
2208 return SYSTEM_VALUE_SUBGROUP_EQ_MASK;
2209 case nir_intrinsic_load_subgroup_ge_mask:
2210 return SYSTEM_VALUE_SUBGROUP_GE_MASK;
2211 case nir_intrinsic_load_subgroup_gt_mask:
2212 return SYSTEM_VALUE_SUBGROUP_GT_MASK;
2213 case nir_intrinsic_load_subgroup_le_mask:
2214 return SYSTEM_VALUE_SUBGROUP_LE_MASK;
2215 case nir_intrinsic_load_subgroup_lt_mask:
2216 return SYSTEM_VALUE_SUBGROUP_LT_MASK;
2217 case nir_intrinsic_load_num_subgroups:
2218 return SYSTEM_VALUE_NUM_SUBGROUPS;
2219 case nir_intrinsic_load_subgroup_id:
2220 return SYSTEM_VALUE_SUBGROUP_ID;
2221 case nir_intrinsic_load_local_group_size:
2222 return SYSTEM_VALUE_LOCAL_GROUP_SIZE;
2223 case nir_intrinsic_load_global_invocation_id:
2224 return SYSTEM_VALUE_GLOBAL_INVOCATION_ID;
2225 case nir_intrinsic_load_base_global_invocation_id:
2226 return SYSTEM_VALUE_BASE_GLOBAL_INVOCATION_ID;
2227 case nir_intrinsic_load_global_invocation_index:
2228 return SYSTEM_VALUE_GLOBAL_INVOCATION_INDEX;
2229 case nir_intrinsic_load_work_dim:
2230 return SYSTEM_VALUE_WORK_DIM;
2231 case nir_intrinsic_load_user_data_amd:
2232 return SYSTEM_VALUE_USER_DATA_AMD;
2233 default:
2234 unreachable("intrinsic doesn't produce a system value");
2235 }
2236 }
2237
2238 /* OpenGL utility method that remaps the location attributes if they are
2239 * doubles. Not needed for vulkan due the differences on the input location
2240 * count for doubles on vulkan vs OpenGL
2241 *
2242 * The bitfield returned in dual_slot is one bit for each double input slot in
2243 * the original OpenGL single-slot input numbering. The mapping from old
2244 * locations to new locations is as follows:
2245 *
2246 * new_loc = loc + util_bitcount(dual_slot & BITFIELD64_MASK(loc))
2247 */
2248 void
2249 nir_remap_dual_slot_attributes(nir_shader *shader, uint64_t *dual_slot)
2250 {
2251 assert(shader->info.stage == MESA_SHADER_VERTEX);
2252
2253 *dual_slot = 0;
2254 nir_foreach_shader_in_variable(var, shader) {
2255 if (glsl_type_is_dual_slot(glsl_without_array(var->type))) {
2256 unsigned slots = glsl_count_attribute_slots(var->type, true);
2257 *dual_slot |= BITFIELD64_MASK(slots) << var->data.location;
2258 }
2259 }
2260
2261 nir_foreach_shader_in_variable(var, shader) {
2262 var->data.location +=
2263 util_bitcount64(*dual_slot & BITFIELD64_MASK(var->data.location));
2264 }
2265 }
2266
2267 /* Returns an attribute mask that has been re-compacted using the given
2268 * dual_slot mask.
2269 */
2270 uint64_t
2271 nir_get_single_slot_attribs_mask(uint64_t attribs, uint64_t dual_slot)
2272 {
2273 while (dual_slot) {
2274 unsigned loc = u_bit_scan64(&dual_slot);
2275 /* mask of all bits up to and including loc */
2276 uint64_t mask = BITFIELD64_MASK(loc + 1);
2277 attribs = (attribs & mask) | ((attribs & ~mask) >> 1);
2278 }
2279 return attribs;
2280 }
2281
2282 void
2283 nir_rewrite_image_intrinsic(nir_intrinsic_instr *intrin, nir_ssa_def *src,
2284 bool bindless)
2285 {
2286 enum gl_access_qualifier access = nir_intrinsic_access(intrin);
2287
2288 switch (intrin->intrinsic) {
2289 #define CASE(op) \
2290 case nir_intrinsic_image_deref_##op: \
2291 intrin->intrinsic = bindless ? nir_intrinsic_bindless_image_##op \
2292 : nir_intrinsic_image_##op; \
2293 break;
2294 CASE(load)
2295 CASE(store)
2296 CASE(atomic_add)
2297 CASE(atomic_imin)
2298 CASE(atomic_umin)
2299 CASE(atomic_imax)
2300 CASE(atomic_umax)
2301 CASE(atomic_and)
2302 CASE(atomic_or)
2303 CASE(atomic_xor)
2304 CASE(atomic_exchange)
2305 CASE(atomic_comp_swap)
2306 CASE(atomic_fadd)
2307 CASE(atomic_inc_wrap)
2308 CASE(atomic_dec_wrap)
2309 CASE(size)
2310 CASE(samples)
2311 CASE(load_raw_intel)
2312 CASE(store_raw_intel)
2313 #undef CASE
2314 default:
2315 unreachable("Unhanded image intrinsic");
2316 }
2317
2318 nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);
2319 nir_variable *var = nir_deref_instr_get_variable(deref);
2320
2321 nir_intrinsic_set_image_dim(intrin, glsl_get_sampler_dim(deref->type));
2322 nir_intrinsic_set_image_array(intrin, glsl_sampler_type_is_array(deref->type));
2323 nir_intrinsic_set_access(intrin, access | var->data.access);
2324 nir_intrinsic_set_format(intrin, var->data.image.format);
2325
2326 nir_instr_rewrite_src(&intrin->instr, &intrin->src[0],
2327 nir_src_for_ssa(src));
2328 }
2329
2330 unsigned
2331 nir_image_intrinsic_coord_components(const nir_intrinsic_instr *instr)
2332 {
2333 enum glsl_sampler_dim dim = nir_intrinsic_image_dim(instr);
2334 int coords = glsl_get_sampler_dim_coordinate_components(dim);
2335 if (dim == GLSL_SAMPLER_DIM_CUBE)
2336 return coords;
2337 else
2338 return coords + nir_intrinsic_image_array(instr);
2339 }