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nir: Add a lowering pass to split 64bit phis
[mesa.git] / src / compiler / nir / nir.c
1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Connor Abbott (cwabbott0@gmail.com)
25 *
26 */
27
28 #include "nir.h"
29 #include "nir_builder.h"
30 #include "nir_control_flow_private.h"
31 #include "util/half_float.h"
32 #include <limits.h>
33 #include <assert.h>
34 #include <math.h>
35 #include "util/u_math.h"
36
37 #include "main/menums.h" /* BITFIELD64_MASK */
38
39 nir_shader *
40 nir_shader_create(void *mem_ctx,
41 gl_shader_stage stage,
42 const nir_shader_compiler_options *options,
43 shader_info *si)
44 {
45 nir_shader *shader = rzalloc(mem_ctx, nir_shader);
46
47 exec_list_make_empty(&shader->variables);
48
49 shader->options = options;
50
51 if (si) {
52 assert(si->stage == stage);
53 shader->info = *si;
54 } else {
55 shader->info.stage = stage;
56 }
57
58 exec_list_make_empty(&shader->functions);
59
60 shader->num_inputs = 0;
61 shader->num_outputs = 0;
62 shader->num_uniforms = 0;
63 shader->num_shared = 0;
64
65 return shader;
66 }
67
68 static nir_register *
69 reg_create(void *mem_ctx, struct exec_list *list)
70 {
71 nir_register *reg = ralloc(mem_ctx, nir_register);
72
73 list_inithead(&reg->uses);
74 list_inithead(&reg->defs);
75 list_inithead(&reg->if_uses);
76
77 reg->num_components = 0;
78 reg->bit_size = 32;
79 reg->num_array_elems = 0;
80 reg->name = NULL;
81
82 exec_list_push_tail(list, &reg->node);
83
84 return reg;
85 }
86
87 nir_register *
88 nir_local_reg_create(nir_function_impl *impl)
89 {
90 nir_register *reg = reg_create(ralloc_parent(impl), &impl->registers);
91 reg->index = impl->reg_alloc++;
92
93 return reg;
94 }
95
96 void
97 nir_reg_remove(nir_register *reg)
98 {
99 exec_node_remove(&reg->node);
100 }
101
102 void
103 nir_shader_add_variable(nir_shader *shader, nir_variable *var)
104 {
105 switch (var->data.mode) {
106 case nir_var_function_temp:
107 assert(!"nir_shader_add_variable cannot be used for local variables");
108 return;
109
110 case nir_var_shader_temp:
111 case nir_var_shader_in:
112 case nir_var_shader_out:
113 case nir_var_uniform:
114 case nir_var_mem_ubo:
115 case nir_var_mem_ssbo:
116 case nir_var_mem_shared:
117 case nir_var_system_value:
118 break;
119
120 case nir_var_mem_global:
121 assert(!"nir_shader_add_variable cannot be used for global memory");
122 return;
123
124 case nir_var_mem_push_const:
125 assert(!"nir_var_push_constant is not supposed to be used for variables");
126 return;
127
128 default:
129 assert(!"invalid mode");
130 return;
131 }
132
133 exec_list_push_tail(&shader->variables, &var->node);
134 }
135
136 nir_variable *
137 nir_variable_create(nir_shader *shader, nir_variable_mode mode,
138 const struct glsl_type *type, const char *name)
139 {
140 nir_variable *var = rzalloc(shader, nir_variable);
141 var->name = ralloc_strdup(var, name);
142 var->type = type;
143 var->data.mode = mode;
144 var->data.how_declared = nir_var_declared_normally;
145
146 if ((mode == nir_var_shader_in &&
147 shader->info.stage != MESA_SHADER_VERTEX &&
148 shader->info.stage != MESA_SHADER_KERNEL) ||
149 (mode == nir_var_shader_out &&
150 shader->info.stage != MESA_SHADER_FRAGMENT))
151 var->data.interpolation = INTERP_MODE_SMOOTH;
152
153 if (mode == nir_var_shader_in || mode == nir_var_uniform)
154 var->data.read_only = true;
155
156 nir_shader_add_variable(shader, var);
157
158 return var;
159 }
160
161 nir_variable *
162 nir_local_variable_create(nir_function_impl *impl,
163 const struct glsl_type *type, const char *name)
164 {
165 nir_variable *var = rzalloc(impl->function->shader, nir_variable);
166 var->name = ralloc_strdup(var, name);
167 var->type = type;
168 var->data.mode = nir_var_function_temp;
169
170 nir_function_impl_add_variable(impl, var);
171
172 return var;
173 }
174
175 nir_variable *
176 nir_find_variable_with_location(nir_shader *shader,
177 nir_variable_mode mode,
178 unsigned location)
179 {
180 assert(util_bitcount(mode) == 1 && mode != nir_var_function_temp);
181 nir_foreach_variable_with_modes(var, shader, mode) {
182 if (var->data.location == location)
183 return var;
184 }
185 return NULL;
186 }
187
188 nir_variable *
189 nir_find_variable_with_driver_location(nir_shader *shader,
190 nir_variable_mode mode,
191 unsigned location)
192 {
193 assert(util_bitcount(mode) == 1 && mode != nir_var_function_temp);
194 nir_foreach_variable_with_modes(var, shader, mode) {
195 if (var->data.driver_location == location)
196 return var;
197 }
198 return NULL;
199 }
200
201 nir_function *
202 nir_function_create(nir_shader *shader, const char *name)
203 {
204 nir_function *func = ralloc(shader, nir_function);
205
206 exec_list_push_tail(&shader->functions, &func->node);
207
208 func->name = ralloc_strdup(func, name);
209 func->shader = shader;
210 func->num_params = 0;
211 func->params = NULL;
212 func->impl = NULL;
213 func->is_entrypoint = false;
214
215 return func;
216 }
217
218 /* NOTE: if the instruction you are copying a src to is already added
219 * to the IR, use nir_instr_rewrite_src() instead.
220 */
221 void nir_src_copy(nir_src *dest, const nir_src *src, void *mem_ctx)
222 {
223 dest->is_ssa = src->is_ssa;
224 if (src->is_ssa) {
225 dest->ssa = src->ssa;
226 } else {
227 dest->reg.base_offset = src->reg.base_offset;
228 dest->reg.reg = src->reg.reg;
229 if (src->reg.indirect) {
230 dest->reg.indirect = ralloc(mem_ctx, nir_src);
231 nir_src_copy(dest->reg.indirect, src->reg.indirect, mem_ctx);
232 } else {
233 dest->reg.indirect = NULL;
234 }
235 }
236 }
237
238 void nir_dest_copy(nir_dest *dest, const nir_dest *src, nir_instr *instr)
239 {
240 /* Copying an SSA definition makes no sense whatsoever. */
241 assert(!src->is_ssa);
242
243 dest->is_ssa = false;
244
245 dest->reg.base_offset = src->reg.base_offset;
246 dest->reg.reg = src->reg.reg;
247 if (src->reg.indirect) {
248 dest->reg.indirect = ralloc(instr, nir_src);
249 nir_src_copy(dest->reg.indirect, src->reg.indirect, instr);
250 } else {
251 dest->reg.indirect = NULL;
252 }
253 }
254
255 void
256 nir_alu_src_copy(nir_alu_src *dest, const nir_alu_src *src,
257 nir_alu_instr *instr)
258 {
259 nir_src_copy(&dest->src, &src->src, &instr->instr);
260 dest->abs = src->abs;
261 dest->negate = src->negate;
262 for (unsigned i = 0; i < NIR_MAX_VEC_COMPONENTS; i++)
263 dest->swizzle[i] = src->swizzle[i];
264 }
265
266 void
267 nir_alu_dest_copy(nir_alu_dest *dest, const nir_alu_dest *src,
268 nir_alu_instr *instr)
269 {
270 nir_dest_copy(&dest->dest, &src->dest, &instr->instr);
271 dest->write_mask = src->write_mask;
272 dest->saturate = src->saturate;
273 }
274
275
276 static void
277 cf_init(nir_cf_node *node, nir_cf_node_type type)
278 {
279 exec_node_init(&node->node);
280 node->parent = NULL;
281 node->type = type;
282 }
283
284 nir_function_impl *
285 nir_function_impl_create_bare(nir_shader *shader)
286 {
287 nir_function_impl *impl = ralloc(shader, nir_function_impl);
288
289 impl->function = NULL;
290
291 cf_init(&impl->cf_node, nir_cf_node_function);
292
293 exec_list_make_empty(&impl->body);
294 exec_list_make_empty(&impl->registers);
295 exec_list_make_empty(&impl->locals);
296 impl->reg_alloc = 0;
297 impl->ssa_alloc = 0;
298 impl->valid_metadata = nir_metadata_none;
299 impl->structured = true;
300
301 /* create start & end blocks */
302 nir_block *start_block = nir_block_create(shader);
303 nir_block *end_block = nir_block_create(shader);
304 start_block->cf_node.parent = &impl->cf_node;
305 end_block->cf_node.parent = &impl->cf_node;
306 impl->end_block = end_block;
307
308 exec_list_push_tail(&impl->body, &start_block->cf_node.node);
309
310 start_block->successors[0] = end_block;
311 _mesa_set_add(end_block->predecessors, start_block);
312 return impl;
313 }
314
315 nir_function_impl *
316 nir_function_impl_create(nir_function *function)
317 {
318 assert(function->impl == NULL);
319
320 nir_function_impl *impl = nir_function_impl_create_bare(function->shader);
321
322 function->impl = impl;
323 impl->function = function;
324
325 return impl;
326 }
327
328 nir_block *
329 nir_block_create(nir_shader *shader)
330 {
331 nir_block *block = rzalloc(shader, nir_block);
332
333 cf_init(&block->cf_node, nir_cf_node_block);
334
335 block->successors[0] = block->successors[1] = NULL;
336 block->predecessors = _mesa_pointer_set_create(block);
337 block->imm_dom = NULL;
338 /* XXX maybe it would be worth it to defer allocation? This
339 * way it doesn't get allocated for shader refs that never run
340 * nir_calc_dominance? For example, state-tracker creates an
341 * initial IR, clones that, runs appropriate lowering pass, passes
342 * to driver which does common lowering/opt, and then stores ref
343 * which is later used to do state specific lowering and futher
344 * opt. Do any of the references not need dominance metadata?
345 */
346 block->dom_frontier = _mesa_pointer_set_create(block);
347
348 exec_list_make_empty(&block->instr_list);
349
350 return block;
351 }
352
353 static inline void
354 src_init(nir_src *src)
355 {
356 src->is_ssa = false;
357 src->reg.reg = NULL;
358 src->reg.indirect = NULL;
359 src->reg.base_offset = 0;
360 }
361
362 nir_if *
363 nir_if_create(nir_shader *shader)
364 {
365 nir_if *if_stmt = ralloc(shader, nir_if);
366
367 if_stmt->control = nir_selection_control_none;
368
369 cf_init(&if_stmt->cf_node, nir_cf_node_if);
370 src_init(&if_stmt->condition);
371
372 nir_block *then = nir_block_create(shader);
373 exec_list_make_empty(&if_stmt->then_list);
374 exec_list_push_tail(&if_stmt->then_list, &then->cf_node.node);
375 then->cf_node.parent = &if_stmt->cf_node;
376
377 nir_block *else_stmt = nir_block_create(shader);
378 exec_list_make_empty(&if_stmt->else_list);
379 exec_list_push_tail(&if_stmt->else_list, &else_stmt->cf_node.node);
380 else_stmt->cf_node.parent = &if_stmt->cf_node;
381
382 return if_stmt;
383 }
384
385 nir_loop *
386 nir_loop_create(nir_shader *shader)
387 {
388 nir_loop *loop = rzalloc(shader, nir_loop);
389
390 cf_init(&loop->cf_node, nir_cf_node_loop);
391
392 nir_block *body = nir_block_create(shader);
393 exec_list_make_empty(&loop->body);
394 exec_list_push_tail(&loop->body, &body->cf_node.node);
395 body->cf_node.parent = &loop->cf_node;
396
397 body->successors[0] = body;
398 _mesa_set_add(body->predecessors, body);
399
400 return loop;
401 }
402
403 static void
404 instr_init(nir_instr *instr, nir_instr_type type)
405 {
406 instr->type = type;
407 instr->block = NULL;
408 exec_node_init(&instr->node);
409 }
410
411 static void
412 dest_init(nir_dest *dest)
413 {
414 dest->is_ssa = false;
415 dest->reg.reg = NULL;
416 dest->reg.indirect = NULL;
417 dest->reg.base_offset = 0;
418 }
419
420 static void
421 alu_dest_init(nir_alu_dest *dest)
422 {
423 dest_init(&dest->dest);
424 dest->saturate = false;
425 dest->write_mask = 0xf;
426 }
427
428 static void
429 alu_src_init(nir_alu_src *src)
430 {
431 src_init(&src->src);
432 src->abs = src->negate = false;
433 for (int i = 0; i < NIR_MAX_VEC_COMPONENTS; ++i)
434 src->swizzle[i] = i;
435 }
436
437 nir_alu_instr *
438 nir_alu_instr_create(nir_shader *shader, nir_op op)
439 {
440 unsigned num_srcs = nir_op_infos[op].num_inputs;
441 /* TODO: don't use rzalloc */
442 nir_alu_instr *instr =
443 rzalloc_size(shader,
444 sizeof(nir_alu_instr) + num_srcs * sizeof(nir_alu_src));
445
446 instr_init(&instr->instr, nir_instr_type_alu);
447 instr->op = op;
448 alu_dest_init(&instr->dest);
449 for (unsigned i = 0; i < num_srcs; i++)
450 alu_src_init(&instr->src[i]);
451
452 return instr;
453 }
454
455 nir_deref_instr *
456 nir_deref_instr_create(nir_shader *shader, nir_deref_type deref_type)
457 {
458 nir_deref_instr *instr =
459 rzalloc_size(shader, sizeof(nir_deref_instr));
460
461 instr_init(&instr->instr, nir_instr_type_deref);
462
463 instr->deref_type = deref_type;
464 if (deref_type != nir_deref_type_var)
465 src_init(&instr->parent);
466
467 if (deref_type == nir_deref_type_array ||
468 deref_type == nir_deref_type_ptr_as_array)
469 src_init(&instr->arr.index);
470
471 dest_init(&instr->dest);
472
473 return instr;
474 }
475
476 nir_jump_instr *
477 nir_jump_instr_create(nir_shader *shader, nir_jump_type type)
478 {
479 nir_jump_instr *instr = ralloc(shader, nir_jump_instr);
480 instr_init(&instr->instr, nir_instr_type_jump);
481 src_init(&instr->condition);
482 instr->type = type;
483 instr->target = NULL;
484 instr->else_target = NULL;
485 return instr;
486 }
487
488 nir_load_const_instr *
489 nir_load_const_instr_create(nir_shader *shader, unsigned num_components,
490 unsigned bit_size)
491 {
492 nir_load_const_instr *instr =
493 rzalloc_size(shader, sizeof(*instr) + num_components * sizeof(*instr->value));
494 instr_init(&instr->instr, nir_instr_type_load_const);
495
496 nir_ssa_def_init(&instr->instr, &instr->def, num_components, bit_size, NULL);
497
498 return instr;
499 }
500
501 nir_intrinsic_instr *
502 nir_intrinsic_instr_create(nir_shader *shader, nir_intrinsic_op op)
503 {
504 unsigned num_srcs = nir_intrinsic_infos[op].num_srcs;
505 /* TODO: don't use rzalloc */
506 nir_intrinsic_instr *instr =
507 rzalloc_size(shader,
508 sizeof(nir_intrinsic_instr) + num_srcs * sizeof(nir_src));
509
510 instr_init(&instr->instr, nir_instr_type_intrinsic);
511 instr->intrinsic = op;
512
513 if (nir_intrinsic_infos[op].has_dest)
514 dest_init(&instr->dest);
515
516 for (unsigned i = 0; i < num_srcs; i++)
517 src_init(&instr->src[i]);
518
519 return instr;
520 }
521
522 nir_call_instr *
523 nir_call_instr_create(nir_shader *shader, nir_function *callee)
524 {
525 const unsigned num_params = callee->num_params;
526 nir_call_instr *instr =
527 rzalloc_size(shader, sizeof(*instr) +
528 num_params * sizeof(instr->params[0]));
529
530 instr_init(&instr->instr, nir_instr_type_call);
531 instr->callee = callee;
532 instr->num_params = num_params;
533 for (unsigned i = 0; i < num_params; i++)
534 src_init(&instr->params[i]);
535
536 return instr;
537 }
538
539 static int8_t default_tg4_offsets[4][2] =
540 {
541 { 0, 1 },
542 { 1, 1 },
543 { 1, 0 },
544 { 0, 0 },
545 };
546
547 nir_tex_instr *
548 nir_tex_instr_create(nir_shader *shader, unsigned num_srcs)
549 {
550 nir_tex_instr *instr = rzalloc(shader, nir_tex_instr);
551 instr_init(&instr->instr, nir_instr_type_tex);
552
553 dest_init(&instr->dest);
554
555 instr->num_srcs = num_srcs;
556 instr->src = ralloc_array(instr, nir_tex_src, num_srcs);
557 for (unsigned i = 0; i < num_srcs; i++)
558 src_init(&instr->src[i].src);
559
560 instr->texture_index = 0;
561 instr->sampler_index = 0;
562 memcpy(instr->tg4_offsets, default_tg4_offsets, sizeof(instr->tg4_offsets));
563
564 return instr;
565 }
566
567 void
568 nir_tex_instr_add_src(nir_tex_instr *tex,
569 nir_tex_src_type src_type,
570 nir_src src)
571 {
572 nir_tex_src *new_srcs = rzalloc_array(tex, nir_tex_src,
573 tex->num_srcs + 1);
574
575 for (unsigned i = 0; i < tex->num_srcs; i++) {
576 new_srcs[i].src_type = tex->src[i].src_type;
577 nir_instr_move_src(&tex->instr, &new_srcs[i].src,
578 &tex->src[i].src);
579 }
580
581 ralloc_free(tex->src);
582 tex->src = new_srcs;
583
584 tex->src[tex->num_srcs].src_type = src_type;
585 nir_instr_rewrite_src(&tex->instr, &tex->src[tex->num_srcs].src, src);
586 tex->num_srcs++;
587 }
588
589 void
590 nir_tex_instr_remove_src(nir_tex_instr *tex, unsigned src_idx)
591 {
592 assert(src_idx < tex->num_srcs);
593
594 /* First rewrite the source to NIR_SRC_INIT */
595 nir_instr_rewrite_src(&tex->instr, &tex->src[src_idx].src, NIR_SRC_INIT);
596
597 /* Now, move all of the other sources down */
598 for (unsigned i = src_idx + 1; i < tex->num_srcs; i++) {
599 tex->src[i-1].src_type = tex->src[i].src_type;
600 nir_instr_move_src(&tex->instr, &tex->src[i-1].src, &tex->src[i].src);
601 }
602 tex->num_srcs--;
603 }
604
605 bool
606 nir_tex_instr_has_explicit_tg4_offsets(nir_tex_instr *tex)
607 {
608 if (tex->op != nir_texop_tg4)
609 return false;
610 return memcmp(tex->tg4_offsets, default_tg4_offsets,
611 sizeof(tex->tg4_offsets)) != 0;
612 }
613
614 nir_phi_instr *
615 nir_phi_instr_create(nir_shader *shader)
616 {
617 nir_phi_instr *instr = ralloc(shader, nir_phi_instr);
618 instr_init(&instr->instr, nir_instr_type_phi);
619
620 dest_init(&instr->dest);
621 exec_list_make_empty(&instr->srcs);
622 return instr;
623 }
624
625 nir_parallel_copy_instr *
626 nir_parallel_copy_instr_create(nir_shader *shader)
627 {
628 nir_parallel_copy_instr *instr = ralloc(shader, nir_parallel_copy_instr);
629 instr_init(&instr->instr, nir_instr_type_parallel_copy);
630
631 exec_list_make_empty(&instr->entries);
632
633 return instr;
634 }
635
636 nir_ssa_undef_instr *
637 nir_ssa_undef_instr_create(nir_shader *shader,
638 unsigned num_components,
639 unsigned bit_size)
640 {
641 nir_ssa_undef_instr *instr = ralloc(shader, nir_ssa_undef_instr);
642 instr_init(&instr->instr, nir_instr_type_ssa_undef);
643
644 nir_ssa_def_init(&instr->instr, &instr->def, num_components, bit_size, NULL);
645
646 return instr;
647 }
648
649 static nir_const_value
650 const_value_float(double d, unsigned bit_size)
651 {
652 nir_const_value v;
653 memset(&v, 0, sizeof(v));
654 switch (bit_size) {
655 case 16: v.u16 = _mesa_float_to_half(d); break;
656 case 32: v.f32 = d; break;
657 case 64: v.f64 = d; break;
658 default:
659 unreachable("Invalid bit size");
660 }
661 return v;
662 }
663
664 static nir_const_value
665 const_value_int(int64_t i, unsigned bit_size)
666 {
667 nir_const_value v;
668 memset(&v, 0, sizeof(v));
669 switch (bit_size) {
670 case 1: v.b = i & 1; break;
671 case 8: v.i8 = i; break;
672 case 16: v.i16 = i; break;
673 case 32: v.i32 = i; break;
674 case 64: v.i64 = i; break;
675 default:
676 unreachable("Invalid bit size");
677 }
678 return v;
679 }
680
681 nir_const_value
682 nir_alu_binop_identity(nir_op binop, unsigned bit_size)
683 {
684 const int64_t max_int = (1ull << (bit_size - 1)) - 1;
685 const int64_t min_int = -max_int - 1;
686 switch (binop) {
687 case nir_op_iadd:
688 return const_value_int(0, bit_size);
689 case nir_op_fadd:
690 return const_value_float(0, bit_size);
691 case nir_op_imul:
692 return const_value_int(1, bit_size);
693 case nir_op_fmul:
694 return const_value_float(1, bit_size);
695 case nir_op_imin:
696 return const_value_int(max_int, bit_size);
697 case nir_op_umin:
698 return const_value_int(~0ull, bit_size);
699 case nir_op_fmin:
700 return const_value_float(INFINITY, bit_size);
701 case nir_op_imax:
702 return const_value_int(min_int, bit_size);
703 case nir_op_umax:
704 return const_value_int(0, bit_size);
705 case nir_op_fmax:
706 return const_value_float(-INFINITY, bit_size);
707 case nir_op_iand:
708 return const_value_int(~0ull, bit_size);
709 case nir_op_ior:
710 return const_value_int(0, bit_size);
711 case nir_op_ixor:
712 return const_value_int(0, bit_size);
713 default:
714 unreachable("Invalid reduction operation");
715 }
716 }
717
718 nir_function_impl *
719 nir_cf_node_get_function(nir_cf_node *node)
720 {
721 while (node->type != nir_cf_node_function) {
722 node = node->parent;
723 }
724
725 return nir_cf_node_as_function(node);
726 }
727
728 /* Reduces a cursor by trying to convert everything to after and trying to
729 * go up to block granularity when possible.
730 */
731 static nir_cursor
732 reduce_cursor(nir_cursor cursor)
733 {
734 switch (cursor.option) {
735 case nir_cursor_before_block:
736 if (exec_list_is_empty(&cursor.block->instr_list)) {
737 /* Empty block. After is as good as before. */
738 cursor.option = nir_cursor_after_block;
739 }
740 return cursor;
741
742 case nir_cursor_after_block:
743 return cursor;
744
745 case nir_cursor_before_instr: {
746 nir_instr *prev_instr = nir_instr_prev(cursor.instr);
747 if (prev_instr) {
748 /* Before this instruction is after the previous */
749 cursor.instr = prev_instr;
750 cursor.option = nir_cursor_after_instr;
751 } else {
752 /* No previous instruction. Switch to before block */
753 cursor.block = cursor.instr->block;
754 cursor.option = nir_cursor_before_block;
755 }
756 return reduce_cursor(cursor);
757 }
758
759 case nir_cursor_after_instr:
760 if (nir_instr_next(cursor.instr) == NULL) {
761 /* This is the last instruction, switch to after block */
762 cursor.option = nir_cursor_after_block;
763 cursor.block = cursor.instr->block;
764 }
765 return cursor;
766
767 default:
768 unreachable("Inavlid cursor option");
769 }
770 }
771
772 bool
773 nir_cursors_equal(nir_cursor a, nir_cursor b)
774 {
775 /* Reduced cursors should be unique */
776 a = reduce_cursor(a);
777 b = reduce_cursor(b);
778
779 return a.block == b.block && a.option == b.option;
780 }
781
782 static bool
783 add_use_cb(nir_src *src, void *state)
784 {
785 nir_instr *instr = state;
786
787 src->parent_instr = instr;
788 list_addtail(&src->use_link,
789 src->is_ssa ? &src->ssa->uses : &src->reg.reg->uses);
790
791 return true;
792 }
793
794 static bool
795 add_ssa_def_cb(nir_ssa_def *def, void *state)
796 {
797 nir_instr *instr = state;
798
799 if (instr->block && def->index == UINT_MAX) {
800 nir_function_impl *impl =
801 nir_cf_node_get_function(&instr->block->cf_node);
802
803 def->index = impl->ssa_alloc++;
804 }
805
806 return true;
807 }
808
809 static bool
810 add_reg_def_cb(nir_dest *dest, void *state)
811 {
812 nir_instr *instr = state;
813
814 if (!dest->is_ssa) {
815 dest->reg.parent_instr = instr;
816 list_addtail(&dest->reg.def_link, &dest->reg.reg->defs);
817 }
818
819 return true;
820 }
821
822 static void
823 add_defs_uses(nir_instr *instr)
824 {
825 nir_foreach_src(instr, add_use_cb, instr);
826 nir_foreach_dest(instr, add_reg_def_cb, instr);
827 nir_foreach_ssa_def(instr, add_ssa_def_cb, instr);
828 }
829
830 void
831 nir_instr_insert(nir_cursor cursor, nir_instr *instr)
832 {
833 switch (cursor.option) {
834 case nir_cursor_before_block:
835 /* Only allow inserting jumps into empty blocks. */
836 if (instr->type == nir_instr_type_jump)
837 assert(exec_list_is_empty(&cursor.block->instr_list));
838
839 instr->block = cursor.block;
840 add_defs_uses(instr);
841 exec_list_push_head(&cursor.block->instr_list, &instr->node);
842 break;
843 case nir_cursor_after_block: {
844 /* Inserting instructions after a jump is illegal. */
845 nir_instr *last = nir_block_last_instr(cursor.block);
846 assert(last == NULL || last->type != nir_instr_type_jump);
847 (void) last;
848
849 instr->block = cursor.block;
850 add_defs_uses(instr);
851 exec_list_push_tail(&cursor.block->instr_list, &instr->node);
852 break;
853 }
854 case nir_cursor_before_instr:
855 assert(instr->type != nir_instr_type_jump);
856 instr->block = cursor.instr->block;
857 add_defs_uses(instr);
858 exec_node_insert_node_before(&cursor.instr->node, &instr->node);
859 break;
860 case nir_cursor_after_instr:
861 /* Inserting instructions after a jump is illegal. */
862 assert(cursor.instr->type != nir_instr_type_jump);
863
864 /* Only allow inserting jumps at the end of the block. */
865 if (instr->type == nir_instr_type_jump)
866 assert(cursor.instr == nir_block_last_instr(cursor.instr->block));
867
868 instr->block = cursor.instr->block;
869 add_defs_uses(instr);
870 exec_node_insert_after(&cursor.instr->node, &instr->node);
871 break;
872 }
873
874 if (instr->type == nir_instr_type_jump)
875 nir_handle_add_jump(instr->block);
876 }
877
878 static bool
879 src_is_valid(const nir_src *src)
880 {
881 return src->is_ssa ? (src->ssa != NULL) : (src->reg.reg != NULL);
882 }
883
884 static bool
885 remove_use_cb(nir_src *src, void *state)
886 {
887 (void) state;
888
889 if (src_is_valid(src))
890 list_del(&src->use_link);
891
892 return true;
893 }
894
895 static bool
896 remove_def_cb(nir_dest *dest, void *state)
897 {
898 (void) state;
899
900 if (!dest->is_ssa)
901 list_del(&dest->reg.def_link);
902
903 return true;
904 }
905
906 static void
907 remove_defs_uses(nir_instr *instr)
908 {
909 nir_foreach_dest(instr, remove_def_cb, instr);
910 nir_foreach_src(instr, remove_use_cb, instr);
911 }
912
913 void nir_instr_remove_v(nir_instr *instr)
914 {
915 remove_defs_uses(instr);
916 exec_node_remove(&instr->node);
917
918 if (instr->type == nir_instr_type_jump) {
919 nir_jump_instr *jump_instr = nir_instr_as_jump(instr);
920 nir_handle_remove_jump(instr->block, jump_instr->type);
921 }
922 }
923
924 /*@}*/
925
926 void
927 nir_index_local_regs(nir_function_impl *impl)
928 {
929 unsigned index = 0;
930 foreach_list_typed(nir_register, reg, node, &impl->registers) {
931 reg->index = index++;
932 }
933 impl->reg_alloc = index;
934 }
935
936 static bool
937 visit_alu_dest(nir_alu_instr *instr, nir_foreach_dest_cb cb, void *state)
938 {
939 return cb(&instr->dest.dest, state);
940 }
941
942 static bool
943 visit_deref_dest(nir_deref_instr *instr, nir_foreach_dest_cb cb, void *state)
944 {
945 return cb(&instr->dest, state);
946 }
947
948 static bool
949 visit_intrinsic_dest(nir_intrinsic_instr *instr, nir_foreach_dest_cb cb,
950 void *state)
951 {
952 if (nir_intrinsic_infos[instr->intrinsic].has_dest)
953 return cb(&instr->dest, state);
954
955 return true;
956 }
957
958 static bool
959 visit_texture_dest(nir_tex_instr *instr, nir_foreach_dest_cb cb,
960 void *state)
961 {
962 return cb(&instr->dest, state);
963 }
964
965 static bool
966 visit_phi_dest(nir_phi_instr *instr, nir_foreach_dest_cb cb, void *state)
967 {
968 return cb(&instr->dest, state);
969 }
970
971 static bool
972 visit_parallel_copy_dest(nir_parallel_copy_instr *instr,
973 nir_foreach_dest_cb cb, void *state)
974 {
975 nir_foreach_parallel_copy_entry(entry, instr) {
976 if (!cb(&entry->dest, state))
977 return false;
978 }
979
980 return true;
981 }
982
983 bool
984 nir_foreach_dest(nir_instr *instr, nir_foreach_dest_cb cb, void *state)
985 {
986 switch (instr->type) {
987 case nir_instr_type_alu:
988 return visit_alu_dest(nir_instr_as_alu(instr), cb, state);
989 case nir_instr_type_deref:
990 return visit_deref_dest(nir_instr_as_deref(instr), cb, state);
991 case nir_instr_type_intrinsic:
992 return visit_intrinsic_dest(nir_instr_as_intrinsic(instr), cb, state);
993 case nir_instr_type_tex:
994 return visit_texture_dest(nir_instr_as_tex(instr), cb, state);
995 case nir_instr_type_phi:
996 return visit_phi_dest(nir_instr_as_phi(instr), cb, state);
997 case nir_instr_type_parallel_copy:
998 return visit_parallel_copy_dest(nir_instr_as_parallel_copy(instr),
999 cb, state);
1000
1001 case nir_instr_type_load_const:
1002 case nir_instr_type_ssa_undef:
1003 case nir_instr_type_call:
1004 case nir_instr_type_jump:
1005 break;
1006
1007 default:
1008 unreachable("Invalid instruction type");
1009 break;
1010 }
1011
1012 return true;
1013 }
1014
1015 struct foreach_ssa_def_state {
1016 nir_foreach_ssa_def_cb cb;
1017 void *client_state;
1018 };
1019
1020 static inline bool
1021 nir_ssa_def_visitor(nir_dest *dest, void *void_state)
1022 {
1023 struct foreach_ssa_def_state *state = void_state;
1024
1025 if (dest->is_ssa)
1026 return state->cb(&dest->ssa, state->client_state);
1027 else
1028 return true;
1029 }
1030
1031 bool
1032 nir_foreach_ssa_def(nir_instr *instr, nir_foreach_ssa_def_cb cb, void *state)
1033 {
1034 switch (instr->type) {
1035 case nir_instr_type_alu:
1036 case nir_instr_type_deref:
1037 case nir_instr_type_tex:
1038 case nir_instr_type_intrinsic:
1039 case nir_instr_type_phi:
1040 case nir_instr_type_parallel_copy: {
1041 struct foreach_ssa_def_state foreach_state = {cb, state};
1042 return nir_foreach_dest(instr, nir_ssa_def_visitor, &foreach_state);
1043 }
1044
1045 case nir_instr_type_load_const:
1046 return cb(&nir_instr_as_load_const(instr)->def, state);
1047 case nir_instr_type_ssa_undef:
1048 return cb(&nir_instr_as_ssa_undef(instr)->def, state);
1049 case nir_instr_type_call:
1050 case nir_instr_type_jump:
1051 return true;
1052 default:
1053 unreachable("Invalid instruction type");
1054 }
1055 }
1056
1057 nir_ssa_def *
1058 nir_instr_ssa_def(nir_instr *instr)
1059 {
1060 switch (instr->type) {
1061 case nir_instr_type_alu:
1062 assert(nir_instr_as_alu(instr)->dest.dest.is_ssa);
1063 return &nir_instr_as_alu(instr)->dest.dest.ssa;
1064
1065 case nir_instr_type_deref:
1066 assert(nir_instr_as_deref(instr)->dest.is_ssa);
1067 return &nir_instr_as_deref(instr)->dest.ssa;
1068
1069 case nir_instr_type_tex:
1070 assert(nir_instr_as_tex(instr)->dest.is_ssa);
1071 return &nir_instr_as_tex(instr)->dest.ssa;
1072
1073 case nir_instr_type_intrinsic: {
1074 nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
1075 if (nir_intrinsic_infos[intrin->intrinsic].has_dest) {
1076 assert(intrin->dest.is_ssa);
1077 return &intrin->dest.ssa;
1078 } else {
1079 return NULL;
1080 }
1081 }
1082
1083 case nir_instr_type_phi:
1084 assert(nir_instr_as_phi(instr)->dest.is_ssa);
1085 return &nir_instr_as_phi(instr)->dest.ssa;
1086
1087 case nir_instr_type_parallel_copy:
1088 unreachable("Parallel copies are unsupported by this function");
1089
1090 case nir_instr_type_load_const:
1091 return &nir_instr_as_load_const(instr)->def;
1092
1093 case nir_instr_type_ssa_undef:
1094 return &nir_instr_as_ssa_undef(instr)->def;
1095
1096 case nir_instr_type_call:
1097 case nir_instr_type_jump:
1098 return NULL;
1099 }
1100
1101 unreachable("Invalid instruction type");
1102 }
1103
1104 static bool
1105 visit_src(nir_src *src, nir_foreach_src_cb cb, void *state)
1106 {
1107 if (!cb(src, state))
1108 return false;
1109 if (!src->is_ssa && src->reg.indirect)
1110 return cb(src->reg.indirect, state);
1111 return true;
1112 }
1113
1114 static bool
1115 visit_alu_src(nir_alu_instr *instr, nir_foreach_src_cb cb, void *state)
1116 {
1117 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1118 if (!visit_src(&instr->src[i].src, cb, state))
1119 return false;
1120
1121 return true;
1122 }
1123
1124 static bool
1125 visit_deref_instr_src(nir_deref_instr *instr,
1126 nir_foreach_src_cb cb, void *state)
1127 {
1128 if (instr->deref_type != nir_deref_type_var) {
1129 if (!visit_src(&instr->parent, cb, state))
1130 return false;
1131 }
1132
1133 if (instr->deref_type == nir_deref_type_array ||
1134 instr->deref_type == nir_deref_type_ptr_as_array) {
1135 if (!visit_src(&instr->arr.index, cb, state))
1136 return false;
1137 }
1138
1139 return true;
1140 }
1141
1142 static bool
1143 visit_tex_src(nir_tex_instr *instr, nir_foreach_src_cb cb, void *state)
1144 {
1145 for (unsigned i = 0; i < instr->num_srcs; i++) {
1146 if (!visit_src(&instr->src[i].src, cb, state))
1147 return false;
1148 }
1149
1150 return true;
1151 }
1152
1153 static bool
1154 visit_intrinsic_src(nir_intrinsic_instr *instr, nir_foreach_src_cb cb,
1155 void *state)
1156 {
1157 unsigned num_srcs = nir_intrinsic_infos[instr->intrinsic].num_srcs;
1158 for (unsigned i = 0; i < num_srcs; i++) {
1159 if (!visit_src(&instr->src[i], cb, state))
1160 return false;
1161 }
1162
1163 return true;
1164 }
1165
1166 static bool
1167 visit_call_src(nir_call_instr *instr, nir_foreach_src_cb cb, void *state)
1168 {
1169 for (unsigned i = 0; i < instr->num_params; i++) {
1170 if (!visit_src(&instr->params[i], cb, state))
1171 return false;
1172 }
1173
1174 return true;
1175 }
1176
1177 static bool
1178 visit_phi_src(nir_phi_instr *instr, nir_foreach_src_cb cb, void *state)
1179 {
1180 nir_foreach_phi_src(src, instr) {
1181 if (!visit_src(&src->src, cb, state))
1182 return false;
1183 }
1184
1185 return true;
1186 }
1187
1188 static bool
1189 visit_parallel_copy_src(nir_parallel_copy_instr *instr,
1190 nir_foreach_src_cb cb, void *state)
1191 {
1192 nir_foreach_parallel_copy_entry(entry, instr) {
1193 if (!visit_src(&entry->src, cb, state))
1194 return false;
1195 }
1196
1197 return true;
1198 }
1199
1200 static bool
1201 visit_jump_src(nir_jump_instr *instr, nir_foreach_src_cb cb, void *state)
1202 {
1203 if (instr->type != nir_jump_goto_if)
1204 return true;
1205
1206 return visit_src(&instr->condition, cb, state);
1207 }
1208
1209 typedef struct {
1210 void *state;
1211 nir_foreach_src_cb cb;
1212 } visit_dest_indirect_state;
1213
1214 static bool
1215 visit_dest_indirect(nir_dest *dest, void *_state)
1216 {
1217 visit_dest_indirect_state *state = (visit_dest_indirect_state *) _state;
1218
1219 if (!dest->is_ssa && dest->reg.indirect)
1220 return state->cb(dest->reg.indirect, state->state);
1221
1222 return true;
1223 }
1224
1225 bool
1226 nir_foreach_src(nir_instr *instr, nir_foreach_src_cb cb, void *state)
1227 {
1228 switch (instr->type) {
1229 case nir_instr_type_alu:
1230 if (!visit_alu_src(nir_instr_as_alu(instr), cb, state))
1231 return false;
1232 break;
1233 case nir_instr_type_deref:
1234 if (!visit_deref_instr_src(nir_instr_as_deref(instr), cb, state))
1235 return false;
1236 break;
1237 case nir_instr_type_intrinsic:
1238 if (!visit_intrinsic_src(nir_instr_as_intrinsic(instr), cb, state))
1239 return false;
1240 break;
1241 case nir_instr_type_tex:
1242 if (!visit_tex_src(nir_instr_as_tex(instr), cb, state))
1243 return false;
1244 break;
1245 case nir_instr_type_call:
1246 if (!visit_call_src(nir_instr_as_call(instr), cb, state))
1247 return false;
1248 break;
1249 case nir_instr_type_load_const:
1250 /* Constant load instructions have no regular sources */
1251 break;
1252 case nir_instr_type_phi:
1253 if (!visit_phi_src(nir_instr_as_phi(instr), cb, state))
1254 return false;
1255 break;
1256 case nir_instr_type_parallel_copy:
1257 if (!visit_parallel_copy_src(nir_instr_as_parallel_copy(instr),
1258 cb, state))
1259 return false;
1260 break;
1261 case nir_instr_type_jump:
1262 return visit_jump_src(nir_instr_as_jump(instr), cb, state);
1263 case nir_instr_type_ssa_undef:
1264 return true;
1265
1266 default:
1267 unreachable("Invalid instruction type");
1268 break;
1269 }
1270
1271 visit_dest_indirect_state dest_state;
1272 dest_state.state = state;
1273 dest_state.cb = cb;
1274 return nir_foreach_dest(instr, visit_dest_indirect, &dest_state);
1275 }
1276
1277 bool
1278 nir_foreach_phi_src_leaving_block(nir_block *block,
1279 nir_foreach_src_cb cb,
1280 void *state)
1281 {
1282 for (unsigned i = 0; i < ARRAY_SIZE(block->successors); i++) {
1283 if (block->successors[i] == NULL)
1284 continue;
1285
1286 nir_foreach_instr(instr, block->successors[i]) {
1287 if (instr->type != nir_instr_type_phi)
1288 break;
1289
1290 nir_phi_instr *phi = nir_instr_as_phi(instr);
1291 nir_foreach_phi_src(phi_src, phi) {
1292 if (phi_src->pred == block) {
1293 if (!cb(&phi_src->src, state))
1294 return false;
1295 }
1296 }
1297 }
1298 }
1299
1300 return true;
1301 }
1302
1303 nir_const_value
1304 nir_const_value_for_float(double f, unsigned bit_size)
1305 {
1306 nir_const_value v;
1307 memset(&v, 0, sizeof(v));
1308
1309 switch (bit_size) {
1310 case 16:
1311 v.u16 = _mesa_float_to_half(f);
1312 break;
1313 case 32:
1314 v.f32 = f;
1315 break;
1316 case 64:
1317 v.f64 = f;
1318 break;
1319 default:
1320 unreachable("Invalid bit size");
1321 }
1322
1323 return v;
1324 }
1325
1326 double
1327 nir_const_value_as_float(nir_const_value value, unsigned bit_size)
1328 {
1329 switch (bit_size) {
1330 case 16: return _mesa_half_to_float(value.u16);
1331 case 32: return value.f32;
1332 case 64: return value.f64;
1333 default:
1334 unreachable("Invalid bit size");
1335 }
1336 }
1337
1338 nir_const_value *
1339 nir_src_as_const_value(nir_src src)
1340 {
1341 if (!src.is_ssa)
1342 return NULL;
1343
1344 if (src.ssa->parent_instr->type != nir_instr_type_load_const)
1345 return NULL;
1346
1347 nir_load_const_instr *load = nir_instr_as_load_const(src.ssa->parent_instr);
1348
1349 return load->value;
1350 }
1351
1352 /**
1353 * Returns true if the source is known to be dynamically uniform. Otherwise it
1354 * returns false which means it may or may not be dynamically uniform but it
1355 * can't be determined.
1356 */
1357 bool
1358 nir_src_is_dynamically_uniform(nir_src src)
1359 {
1360 if (!src.is_ssa)
1361 return false;
1362
1363 /* Constants are trivially dynamically uniform */
1364 if (src.ssa->parent_instr->type == nir_instr_type_load_const)
1365 return true;
1366
1367 /* As are uniform variables */
1368 if (src.ssa->parent_instr->type == nir_instr_type_intrinsic) {
1369 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(src.ssa->parent_instr);
1370 if (intr->intrinsic == nir_intrinsic_load_uniform &&
1371 nir_src_is_dynamically_uniform(intr->src[0]))
1372 return true;
1373 }
1374
1375 /* Operating together dynamically uniform expressions produces a
1376 * dynamically uniform result
1377 */
1378 if (src.ssa->parent_instr->type == nir_instr_type_alu) {
1379 nir_alu_instr *alu = nir_instr_as_alu(src.ssa->parent_instr);
1380 for (int i = 0; i < nir_op_infos[alu->op].num_inputs; i++) {
1381 if (!nir_src_is_dynamically_uniform(alu->src[i].src))
1382 return false;
1383 }
1384
1385 return true;
1386 }
1387
1388 /* XXX: this could have many more tests, such as when a sampler function is
1389 * called with dynamically uniform arguments.
1390 */
1391 return false;
1392 }
1393
1394 static void
1395 src_remove_all_uses(nir_src *src)
1396 {
1397 for (; src; src = src->is_ssa ? NULL : src->reg.indirect) {
1398 if (!src_is_valid(src))
1399 continue;
1400
1401 list_del(&src->use_link);
1402 }
1403 }
1404
1405 static void
1406 src_add_all_uses(nir_src *src, nir_instr *parent_instr, nir_if *parent_if)
1407 {
1408 for (; src; src = src->is_ssa ? NULL : src->reg.indirect) {
1409 if (!src_is_valid(src))
1410 continue;
1411
1412 if (parent_instr) {
1413 src->parent_instr = parent_instr;
1414 if (src->is_ssa)
1415 list_addtail(&src->use_link, &src->ssa->uses);
1416 else
1417 list_addtail(&src->use_link, &src->reg.reg->uses);
1418 } else {
1419 assert(parent_if);
1420 src->parent_if = parent_if;
1421 if (src->is_ssa)
1422 list_addtail(&src->use_link, &src->ssa->if_uses);
1423 else
1424 list_addtail(&src->use_link, &src->reg.reg->if_uses);
1425 }
1426 }
1427 }
1428
1429 void
1430 nir_instr_rewrite_src(nir_instr *instr, nir_src *src, nir_src new_src)
1431 {
1432 assert(!src_is_valid(src) || src->parent_instr == instr);
1433
1434 src_remove_all_uses(src);
1435 *src = new_src;
1436 src_add_all_uses(src, instr, NULL);
1437 }
1438
1439 void
1440 nir_instr_move_src(nir_instr *dest_instr, nir_src *dest, nir_src *src)
1441 {
1442 assert(!src_is_valid(dest) || dest->parent_instr == dest_instr);
1443
1444 src_remove_all_uses(dest);
1445 src_remove_all_uses(src);
1446 *dest = *src;
1447 *src = NIR_SRC_INIT;
1448 src_add_all_uses(dest, dest_instr, NULL);
1449 }
1450
1451 void
1452 nir_if_rewrite_condition(nir_if *if_stmt, nir_src new_src)
1453 {
1454 nir_src *src = &if_stmt->condition;
1455 assert(!src_is_valid(src) || src->parent_if == if_stmt);
1456
1457 src_remove_all_uses(src);
1458 *src = new_src;
1459 src_add_all_uses(src, NULL, if_stmt);
1460 }
1461
1462 void
1463 nir_instr_rewrite_dest(nir_instr *instr, nir_dest *dest, nir_dest new_dest)
1464 {
1465 if (dest->is_ssa) {
1466 /* We can only overwrite an SSA destination if it has no uses. */
1467 assert(list_is_empty(&dest->ssa.uses) && list_is_empty(&dest->ssa.if_uses));
1468 } else {
1469 list_del(&dest->reg.def_link);
1470 if (dest->reg.indirect)
1471 src_remove_all_uses(dest->reg.indirect);
1472 }
1473
1474 /* We can't re-write with an SSA def */
1475 assert(!new_dest.is_ssa);
1476
1477 nir_dest_copy(dest, &new_dest, instr);
1478
1479 dest->reg.parent_instr = instr;
1480 list_addtail(&dest->reg.def_link, &new_dest.reg.reg->defs);
1481
1482 if (dest->reg.indirect)
1483 src_add_all_uses(dest->reg.indirect, instr, NULL);
1484 }
1485
1486 /* note: does *not* take ownership of 'name' */
1487 void
1488 nir_ssa_def_init(nir_instr *instr, nir_ssa_def *def,
1489 unsigned num_components,
1490 unsigned bit_size, const char *name)
1491 {
1492 def->name = ralloc_strdup(instr, name);
1493 def->live_index = UINT_MAX; /* Something clearly OOB */
1494 def->parent_instr = instr;
1495 list_inithead(&def->uses);
1496 list_inithead(&def->if_uses);
1497 def->num_components = num_components;
1498 def->bit_size = bit_size;
1499 def->divergent = true; /* This is the safer default */
1500
1501 if (instr->block) {
1502 nir_function_impl *impl =
1503 nir_cf_node_get_function(&instr->block->cf_node);
1504
1505 def->index = impl->ssa_alloc++;
1506 } else {
1507 def->index = UINT_MAX;
1508 }
1509 }
1510
1511 /* note: does *not* take ownership of 'name' */
1512 void
1513 nir_ssa_dest_init(nir_instr *instr, nir_dest *dest,
1514 unsigned num_components, unsigned bit_size,
1515 const char *name)
1516 {
1517 dest->is_ssa = true;
1518 nir_ssa_def_init(instr, &dest->ssa, num_components, bit_size, name);
1519 }
1520
1521 void
1522 nir_ssa_def_rewrite_uses(nir_ssa_def *def, nir_src new_src)
1523 {
1524 assert(!new_src.is_ssa || def != new_src.ssa);
1525
1526 nir_foreach_use_safe(use_src, def)
1527 nir_instr_rewrite_src(use_src->parent_instr, use_src, new_src);
1528
1529 nir_foreach_if_use_safe(use_src, def)
1530 nir_if_rewrite_condition(use_src->parent_if, new_src);
1531 }
1532
1533 static bool
1534 is_instr_between(nir_instr *start, nir_instr *end, nir_instr *between)
1535 {
1536 assert(start->block == end->block);
1537
1538 if (between->block != start->block)
1539 return false;
1540
1541 /* Search backwards looking for "between" */
1542 while (start != end) {
1543 if (between == end)
1544 return true;
1545
1546 end = nir_instr_prev(end);
1547 assert(end);
1548 }
1549
1550 return false;
1551 }
1552
1553 /* Replaces all uses of the given SSA def with the given source but only if
1554 * the use comes after the after_me instruction. This can be useful if you
1555 * are emitting code to fix up the result of some instruction: you can freely
1556 * use the result in that code and then call rewrite_uses_after and pass the
1557 * last fixup instruction as after_me and it will replace all of the uses you
1558 * want without touching the fixup code.
1559 *
1560 * This function assumes that after_me is in the same block as
1561 * def->parent_instr and that after_me comes after def->parent_instr.
1562 */
1563 void
1564 nir_ssa_def_rewrite_uses_after(nir_ssa_def *def, nir_src new_src,
1565 nir_instr *after_me)
1566 {
1567 if (new_src.is_ssa && def == new_src.ssa)
1568 return;
1569
1570 nir_foreach_use_safe(use_src, def) {
1571 assert(use_src->parent_instr != def->parent_instr);
1572 /* Since def already dominates all of its uses, the only way a use can
1573 * not be dominated by after_me is if it is between def and after_me in
1574 * the instruction list.
1575 */
1576 if (!is_instr_between(def->parent_instr, after_me, use_src->parent_instr))
1577 nir_instr_rewrite_src(use_src->parent_instr, use_src, new_src);
1578 }
1579
1580 nir_foreach_if_use_safe(use_src, def)
1581 nir_if_rewrite_condition(use_src->parent_if, new_src);
1582 }
1583
1584 nir_component_mask_t
1585 nir_ssa_def_components_read(const nir_ssa_def *def)
1586 {
1587 nir_component_mask_t read_mask = 0;
1588 nir_foreach_use(use, def) {
1589 if (use->parent_instr->type == nir_instr_type_alu) {
1590 nir_alu_instr *alu = nir_instr_as_alu(use->parent_instr);
1591 nir_alu_src *alu_src = exec_node_data(nir_alu_src, use, src);
1592 int src_idx = alu_src - &alu->src[0];
1593 assert(src_idx >= 0 && src_idx < nir_op_infos[alu->op].num_inputs);
1594 read_mask |= nir_alu_instr_src_read_mask(alu, src_idx);
1595 } else {
1596 return (1 << def->num_components) - 1;
1597 }
1598 }
1599
1600 if (!list_is_empty(&def->if_uses))
1601 read_mask |= 1;
1602
1603 return read_mask;
1604 }
1605
1606 nir_block *
1607 nir_block_unstructured_next(nir_block *block)
1608 {
1609 if (block == NULL) {
1610 /* nir_foreach_block_unstructured_safe() will call this function on a
1611 * NULL block after the last iteration, but it won't use the result so
1612 * just return NULL here.
1613 */
1614 return NULL;
1615 }
1616
1617 nir_cf_node *cf_next = nir_cf_node_next(&block->cf_node);
1618 if (cf_next == NULL && block->cf_node.parent->type == nir_cf_node_function)
1619 return NULL;
1620
1621 if (cf_next && cf_next->type == nir_cf_node_block)
1622 return nir_cf_node_as_block(cf_next);
1623
1624 return nir_block_cf_tree_next(block);
1625 }
1626
1627 nir_block *
1628 nir_unstructured_start_block(nir_function_impl *impl)
1629 {
1630 return nir_start_block(impl);
1631 }
1632
1633 nir_block *
1634 nir_block_cf_tree_next(nir_block *block)
1635 {
1636 if (block == NULL) {
1637 /* nir_foreach_block_safe() will call this function on a NULL block
1638 * after the last iteration, but it won't use the result so just return
1639 * NULL here.
1640 */
1641 return NULL;
1642 }
1643
1644 assert(nir_cf_node_get_function(&block->cf_node)->structured);
1645
1646 nir_cf_node *cf_next = nir_cf_node_next(&block->cf_node);
1647 if (cf_next)
1648 return nir_cf_node_cf_tree_first(cf_next);
1649
1650 nir_cf_node *parent = block->cf_node.parent;
1651
1652 switch (parent->type) {
1653 case nir_cf_node_if: {
1654 /* Are we at the end of the if? Go to the beginning of the else */
1655 nir_if *if_stmt = nir_cf_node_as_if(parent);
1656 if (block == nir_if_last_then_block(if_stmt))
1657 return nir_if_first_else_block(if_stmt);
1658
1659 assert(block == nir_if_last_else_block(if_stmt));
1660 }
1661 /* fallthrough */
1662
1663 case nir_cf_node_loop:
1664 return nir_cf_node_as_block(nir_cf_node_next(parent));
1665
1666 case nir_cf_node_function:
1667 return NULL;
1668
1669 default:
1670 unreachable("unknown cf node type");
1671 }
1672 }
1673
1674 nir_block *
1675 nir_block_cf_tree_prev(nir_block *block)
1676 {
1677 if (block == NULL) {
1678 /* do this for consistency with nir_block_cf_tree_next() */
1679 return NULL;
1680 }
1681
1682 assert(nir_cf_node_get_function(&block->cf_node)->structured);
1683
1684 nir_cf_node *cf_prev = nir_cf_node_prev(&block->cf_node);
1685 if (cf_prev)
1686 return nir_cf_node_cf_tree_last(cf_prev);
1687
1688 nir_cf_node *parent = block->cf_node.parent;
1689
1690 switch (parent->type) {
1691 case nir_cf_node_if: {
1692 /* Are we at the beginning of the else? Go to the end of the if */
1693 nir_if *if_stmt = nir_cf_node_as_if(parent);
1694 if (block == nir_if_first_else_block(if_stmt))
1695 return nir_if_last_then_block(if_stmt);
1696
1697 assert(block == nir_if_first_then_block(if_stmt));
1698 }
1699 /* fallthrough */
1700
1701 case nir_cf_node_loop:
1702 return nir_cf_node_as_block(nir_cf_node_prev(parent));
1703
1704 case nir_cf_node_function:
1705 return NULL;
1706
1707 default:
1708 unreachable("unknown cf node type");
1709 }
1710 }
1711
1712 nir_block *nir_cf_node_cf_tree_first(nir_cf_node *node)
1713 {
1714 switch (node->type) {
1715 case nir_cf_node_function: {
1716 nir_function_impl *impl = nir_cf_node_as_function(node);
1717 return nir_start_block(impl);
1718 }
1719
1720 case nir_cf_node_if: {
1721 nir_if *if_stmt = nir_cf_node_as_if(node);
1722 return nir_if_first_then_block(if_stmt);
1723 }
1724
1725 case nir_cf_node_loop: {
1726 nir_loop *loop = nir_cf_node_as_loop(node);
1727 return nir_loop_first_block(loop);
1728 }
1729
1730 case nir_cf_node_block: {
1731 return nir_cf_node_as_block(node);
1732 }
1733
1734 default:
1735 unreachable("unknown node type");
1736 }
1737 }
1738
1739 nir_block *nir_cf_node_cf_tree_last(nir_cf_node *node)
1740 {
1741 switch (node->type) {
1742 case nir_cf_node_function: {
1743 nir_function_impl *impl = nir_cf_node_as_function(node);
1744 return nir_impl_last_block(impl);
1745 }
1746
1747 case nir_cf_node_if: {
1748 nir_if *if_stmt = nir_cf_node_as_if(node);
1749 return nir_if_last_else_block(if_stmt);
1750 }
1751
1752 case nir_cf_node_loop: {
1753 nir_loop *loop = nir_cf_node_as_loop(node);
1754 return nir_loop_last_block(loop);
1755 }
1756
1757 case nir_cf_node_block: {
1758 return nir_cf_node_as_block(node);
1759 }
1760
1761 default:
1762 unreachable("unknown node type");
1763 }
1764 }
1765
1766 nir_block *nir_cf_node_cf_tree_next(nir_cf_node *node)
1767 {
1768 if (node->type == nir_cf_node_block)
1769 return nir_block_cf_tree_next(nir_cf_node_as_block(node));
1770 else if (node->type == nir_cf_node_function)
1771 return NULL;
1772 else
1773 return nir_cf_node_as_block(nir_cf_node_next(node));
1774 }
1775
1776 nir_if *
1777 nir_block_get_following_if(nir_block *block)
1778 {
1779 if (exec_node_is_tail_sentinel(&block->cf_node.node))
1780 return NULL;
1781
1782 if (nir_cf_node_is_last(&block->cf_node))
1783 return NULL;
1784
1785 nir_cf_node *next_node = nir_cf_node_next(&block->cf_node);
1786
1787 if (next_node->type != nir_cf_node_if)
1788 return NULL;
1789
1790 return nir_cf_node_as_if(next_node);
1791 }
1792
1793 nir_loop *
1794 nir_block_get_following_loop(nir_block *block)
1795 {
1796 if (exec_node_is_tail_sentinel(&block->cf_node.node))
1797 return NULL;
1798
1799 if (nir_cf_node_is_last(&block->cf_node))
1800 return NULL;
1801
1802 nir_cf_node *next_node = nir_cf_node_next(&block->cf_node);
1803
1804 if (next_node->type != nir_cf_node_loop)
1805 return NULL;
1806
1807 return nir_cf_node_as_loop(next_node);
1808 }
1809
1810 void
1811 nir_index_blocks(nir_function_impl *impl)
1812 {
1813 unsigned index = 0;
1814
1815 if (impl->valid_metadata & nir_metadata_block_index)
1816 return;
1817
1818 nir_foreach_block_unstructured(block, impl) {
1819 block->index = index++;
1820 }
1821
1822 /* The end_block isn't really part of the program, which is why its index
1823 * is >= num_blocks.
1824 */
1825 impl->num_blocks = impl->end_block->index = index;
1826 }
1827
1828 static bool
1829 index_ssa_def_cb(nir_ssa_def *def, void *state)
1830 {
1831 unsigned *index = (unsigned *) state;
1832 def->index = (*index)++;
1833
1834 return true;
1835 }
1836
1837 /**
1838 * The indices are applied top-to-bottom which has the very nice property
1839 * that, if A dominates B, then A->index <= B->index.
1840 */
1841 void
1842 nir_index_ssa_defs(nir_function_impl *impl)
1843 {
1844 unsigned index = 0;
1845
1846 nir_foreach_block_unstructured(block, impl) {
1847 nir_foreach_instr(instr, block)
1848 nir_foreach_ssa_def(instr, index_ssa_def_cb, &index);
1849 }
1850
1851 impl->ssa_alloc = index;
1852 }
1853
1854 /**
1855 * The indices are applied top-to-bottom which has the very nice property
1856 * that, if A dominates B, then A->index <= B->index.
1857 */
1858 unsigned
1859 nir_index_instrs(nir_function_impl *impl)
1860 {
1861 unsigned index = 0;
1862
1863 nir_foreach_block(block, impl) {
1864 nir_foreach_instr(instr, block)
1865 instr->index = index++;
1866 }
1867
1868 return index;
1869 }
1870
1871 unsigned
1872 nir_shader_index_vars(nir_shader *shader, nir_variable_mode modes)
1873 {
1874 unsigned count = 0;
1875 nir_foreach_variable_with_modes(var, shader, modes)
1876 var->index = count++;
1877 return count;
1878 }
1879
1880 unsigned
1881 nir_function_impl_index_vars(nir_function_impl *impl)
1882 {
1883 unsigned count = 0;
1884 nir_foreach_function_temp_variable(var, impl)
1885 var->index = count++;
1886 return count;
1887 }
1888
1889 static nir_instr *
1890 cursor_next_instr(nir_cursor cursor)
1891 {
1892 switch (cursor.option) {
1893 case nir_cursor_before_block:
1894 for (nir_block *block = cursor.block; block;
1895 block = nir_block_cf_tree_next(block)) {
1896 nir_instr *instr = nir_block_first_instr(block);
1897 if (instr)
1898 return instr;
1899 }
1900 return NULL;
1901
1902 case nir_cursor_after_block:
1903 cursor.block = nir_block_cf_tree_next(cursor.block);
1904 if (cursor.block == NULL)
1905 return NULL;
1906
1907 cursor.option = nir_cursor_before_block;
1908 return cursor_next_instr(cursor);
1909
1910 case nir_cursor_before_instr:
1911 return cursor.instr;
1912
1913 case nir_cursor_after_instr:
1914 if (nir_instr_next(cursor.instr))
1915 return nir_instr_next(cursor.instr);
1916
1917 cursor.option = nir_cursor_after_block;
1918 cursor.block = cursor.instr->block;
1919 return cursor_next_instr(cursor);
1920 }
1921
1922 unreachable("Inavlid cursor option");
1923 }
1924
1925 ASSERTED static bool
1926 dest_is_ssa(nir_dest *dest, void *_state)
1927 {
1928 (void) _state;
1929 return dest->is_ssa;
1930 }
1931
1932 bool
1933 nir_function_impl_lower_instructions(nir_function_impl *impl,
1934 nir_instr_filter_cb filter,
1935 nir_lower_instr_cb lower,
1936 void *cb_data)
1937 {
1938 nir_builder b;
1939 nir_builder_init(&b, impl);
1940
1941 nir_metadata preserved = nir_metadata_block_index |
1942 nir_metadata_dominance;
1943
1944 bool progress = false;
1945 nir_cursor iter = nir_before_cf_list(&impl->body);
1946 nir_instr *instr;
1947 while ((instr = cursor_next_instr(iter)) != NULL) {
1948 if (filter && !filter(instr, cb_data)) {
1949 iter = nir_after_instr(instr);
1950 continue;
1951 }
1952
1953 assert(nir_foreach_dest(instr, dest_is_ssa, NULL));
1954 nir_ssa_def *old_def = nir_instr_ssa_def(instr);
1955 if (old_def == NULL) {
1956 iter = nir_after_instr(instr);
1957 continue;
1958 }
1959
1960 /* We're about to ask the callback to generate a replacement for instr.
1961 * Save off the uses from instr's SSA def so we know what uses to
1962 * rewrite later. If we use nir_ssa_def_rewrite_uses, it fails in the
1963 * case where the generated replacement code uses the result of instr
1964 * itself. If we use nir_ssa_def_rewrite_uses_after (which is the
1965 * normal solution to this problem), it doesn't work well if control-
1966 * flow is inserted as part of the replacement, doesn't handle cases
1967 * where the replacement is something consumed by instr, and suffers
1968 * from performance issues. This is the only way to 100% guarantee
1969 * that we rewrite the correct set efficiently.
1970 */
1971 struct list_head old_uses, old_if_uses;
1972 list_replace(&old_def->uses, &old_uses);
1973 list_inithead(&old_def->uses);
1974 list_replace(&old_def->if_uses, &old_if_uses);
1975 list_inithead(&old_def->if_uses);
1976
1977 b.cursor = nir_after_instr(instr);
1978 nir_ssa_def *new_def = lower(&b, instr, cb_data);
1979 if (new_def && new_def != NIR_LOWER_INSTR_PROGRESS) {
1980 assert(old_def != NULL);
1981 if (new_def->parent_instr->block != instr->block)
1982 preserved = nir_metadata_none;
1983
1984 nir_src new_src = nir_src_for_ssa(new_def);
1985 list_for_each_entry_safe(nir_src, use_src, &old_uses, use_link)
1986 nir_instr_rewrite_src(use_src->parent_instr, use_src, new_src);
1987
1988 list_for_each_entry_safe(nir_src, use_src, &old_if_uses, use_link)
1989 nir_if_rewrite_condition(use_src->parent_if, new_src);
1990
1991 if (list_is_empty(&old_def->uses) && list_is_empty(&old_def->if_uses)) {
1992 iter = nir_instr_remove(instr);
1993 } else {
1994 iter = nir_after_instr(instr);
1995 }
1996 progress = true;
1997 } else {
1998 /* We didn't end up lowering after all. Put the uses back */
1999 if (old_def) {
2000 list_replace(&old_uses, &old_def->uses);
2001 list_replace(&old_if_uses, &old_def->if_uses);
2002 }
2003 iter = nir_after_instr(instr);
2004
2005 if (new_def == NIR_LOWER_INSTR_PROGRESS)
2006 progress = true;
2007 }
2008 }
2009
2010 if (progress) {
2011 nir_metadata_preserve(impl, preserved);
2012 } else {
2013 nir_metadata_preserve(impl, nir_metadata_all);
2014 }
2015
2016 return progress;
2017 }
2018
2019 bool
2020 nir_shader_lower_instructions(nir_shader *shader,
2021 nir_instr_filter_cb filter,
2022 nir_lower_instr_cb lower,
2023 void *cb_data)
2024 {
2025 bool progress = false;
2026
2027 nir_foreach_function(function, shader) {
2028 if (function->impl &&
2029 nir_function_impl_lower_instructions(function->impl,
2030 filter, lower, cb_data))
2031 progress = true;
2032 }
2033
2034 return progress;
2035 }
2036
2037 nir_intrinsic_op
2038 nir_intrinsic_from_system_value(gl_system_value val)
2039 {
2040 switch (val) {
2041 case SYSTEM_VALUE_VERTEX_ID:
2042 return nir_intrinsic_load_vertex_id;
2043 case SYSTEM_VALUE_INSTANCE_ID:
2044 return nir_intrinsic_load_instance_id;
2045 case SYSTEM_VALUE_DRAW_ID:
2046 return nir_intrinsic_load_draw_id;
2047 case SYSTEM_VALUE_BASE_INSTANCE:
2048 return nir_intrinsic_load_base_instance;
2049 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
2050 return nir_intrinsic_load_vertex_id_zero_base;
2051 case SYSTEM_VALUE_IS_INDEXED_DRAW:
2052 return nir_intrinsic_load_is_indexed_draw;
2053 case SYSTEM_VALUE_FIRST_VERTEX:
2054 return nir_intrinsic_load_first_vertex;
2055 case SYSTEM_VALUE_BASE_VERTEX:
2056 return nir_intrinsic_load_base_vertex;
2057 case SYSTEM_VALUE_INVOCATION_ID:
2058 return nir_intrinsic_load_invocation_id;
2059 case SYSTEM_VALUE_FRAG_COORD:
2060 return nir_intrinsic_load_frag_coord;
2061 case SYSTEM_VALUE_POINT_COORD:
2062 return nir_intrinsic_load_point_coord;
2063 case SYSTEM_VALUE_LINE_COORD:
2064 return nir_intrinsic_load_line_coord;
2065 case SYSTEM_VALUE_FRONT_FACE:
2066 return nir_intrinsic_load_front_face;
2067 case SYSTEM_VALUE_SAMPLE_ID:
2068 return nir_intrinsic_load_sample_id;
2069 case SYSTEM_VALUE_SAMPLE_POS:
2070 return nir_intrinsic_load_sample_pos;
2071 case SYSTEM_VALUE_SAMPLE_MASK_IN:
2072 return nir_intrinsic_load_sample_mask_in;
2073 case SYSTEM_VALUE_LOCAL_INVOCATION_ID:
2074 return nir_intrinsic_load_local_invocation_id;
2075 case SYSTEM_VALUE_LOCAL_INVOCATION_INDEX:
2076 return nir_intrinsic_load_local_invocation_index;
2077 case SYSTEM_VALUE_WORK_GROUP_ID:
2078 return nir_intrinsic_load_work_group_id;
2079 case SYSTEM_VALUE_NUM_WORK_GROUPS:
2080 return nir_intrinsic_load_num_work_groups;
2081 case SYSTEM_VALUE_PRIMITIVE_ID:
2082 return nir_intrinsic_load_primitive_id;
2083 case SYSTEM_VALUE_TESS_COORD:
2084 return nir_intrinsic_load_tess_coord;
2085 case SYSTEM_VALUE_TESS_LEVEL_OUTER:
2086 return nir_intrinsic_load_tess_level_outer;
2087 case SYSTEM_VALUE_TESS_LEVEL_INNER:
2088 return nir_intrinsic_load_tess_level_inner;
2089 case SYSTEM_VALUE_TESS_LEVEL_OUTER_DEFAULT:
2090 return nir_intrinsic_load_tess_level_outer_default;
2091 case SYSTEM_VALUE_TESS_LEVEL_INNER_DEFAULT:
2092 return nir_intrinsic_load_tess_level_inner_default;
2093 case SYSTEM_VALUE_VERTICES_IN:
2094 return nir_intrinsic_load_patch_vertices_in;
2095 case SYSTEM_VALUE_HELPER_INVOCATION:
2096 return nir_intrinsic_load_helper_invocation;
2097 case SYSTEM_VALUE_COLOR0:
2098 return nir_intrinsic_load_color0;
2099 case SYSTEM_VALUE_COLOR1:
2100 return nir_intrinsic_load_color1;
2101 case SYSTEM_VALUE_VIEW_INDEX:
2102 return nir_intrinsic_load_view_index;
2103 case SYSTEM_VALUE_SUBGROUP_SIZE:
2104 return nir_intrinsic_load_subgroup_size;
2105 case SYSTEM_VALUE_SUBGROUP_INVOCATION:
2106 return nir_intrinsic_load_subgroup_invocation;
2107 case SYSTEM_VALUE_SUBGROUP_EQ_MASK:
2108 return nir_intrinsic_load_subgroup_eq_mask;
2109 case SYSTEM_VALUE_SUBGROUP_GE_MASK:
2110 return nir_intrinsic_load_subgroup_ge_mask;
2111 case SYSTEM_VALUE_SUBGROUP_GT_MASK:
2112 return nir_intrinsic_load_subgroup_gt_mask;
2113 case SYSTEM_VALUE_SUBGROUP_LE_MASK:
2114 return nir_intrinsic_load_subgroup_le_mask;
2115 case SYSTEM_VALUE_SUBGROUP_LT_MASK:
2116 return nir_intrinsic_load_subgroup_lt_mask;
2117 case SYSTEM_VALUE_NUM_SUBGROUPS:
2118 return nir_intrinsic_load_num_subgroups;
2119 case SYSTEM_VALUE_SUBGROUP_ID:
2120 return nir_intrinsic_load_subgroup_id;
2121 case SYSTEM_VALUE_LOCAL_GROUP_SIZE:
2122 return nir_intrinsic_load_local_group_size;
2123 case SYSTEM_VALUE_GLOBAL_INVOCATION_ID:
2124 return nir_intrinsic_load_global_invocation_id;
2125 case SYSTEM_VALUE_BASE_GLOBAL_INVOCATION_ID:
2126 return nir_intrinsic_load_base_global_invocation_id;
2127 case SYSTEM_VALUE_GLOBAL_INVOCATION_INDEX:
2128 return nir_intrinsic_load_global_invocation_index;
2129 case SYSTEM_VALUE_WORK_DIM:
2130 return nir_intrinsic_load_work_dim;
2131 case SYSTEM_VALUE_USER_DATA_AMD:
2132 return nir_intrinsic_load_user_data_amd;
2133 default:
2134 unreachable("system value does not directly correspond to intrinsic");
2135 }
2136 }
2137
2138 gl_system_value
2139 nir_system_value_from_intrinsic(nir_intrinsic_op intrin)
2140 {
2141 switch (intrin) {
2142 case nir_intrinsic_load_vertex_id:
2143 return SYSTEM_VALUE_VERTEX_ID;
2144 case nir_intrinsic_load_instance_id:
2145 return SYSTEM_VALUE_INSTANCE_ID;
2146 case nir_intrinsic_load_draw_id:
2147 return SYSTEM_VALUE_DRAW_ID;
2148 case nir_intrinsic_load_base_instance:
2149 return SYSTEM_VALUE_BASE_INSTANCE;
2150 case nir_intrinsic_load_vertex_id_zero_base:
2151 return SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
2152 case nir_intrinsic_load_first_vertex:
2153 return SYSTEM_VALUE_FIRST_VERTEX;
2154 case nir_intrinsic_load_is_indexed_draw:
2155 return SYSTEM_VALUE_IS_INDEXED_DRAW;
2156 case nir_intrinsic_load_base_vertex:
2157 return SYSTEM_VALUE_BASE_VERTEX;
2158 case nir_intrinsic_load_invocation_id:
2159 return SYSTEM_VALUE_INVOCATION_ID;
2160 case nir_intrinsic_load_frag_coord:
2161 return SYSTEM_VALUE_FRAG_COORD;
2162 case nir_intrinsic_load_point_coord:
2163 return SYSTEM_VALUE_POINT_COORD;
2164 case nir_intrinsic_load_line_coord:
2165 return SYSTEM_VALUE_LINE_COORD;
2166 case nir_intrinsic_load_front_face:
2167 return SYSTEM_VALUE_FRONT_FACE;
2168 case nir_intrinsic_load_sample_id:
2169 return SYSTEM_VALUE_SAMPLE_ID;
2170 case nir_intrinsic_load_sample_pos:
2171 return SYSTEM_VALUE_SAMPLE_POS;
2172 case nir_intrinsic_load_sample_mask_in:
2173 return SYSTEM_VALUE_SAMPLE_MASK_IN;
2174 case nir_intrinsic_load_local_invocation_id:
2175 return SYSTEM_VALUE_LOCAL_INVOCATION_ID;
2176 case nir_intrinsic_load_local_invocation_index:
2177 return SYSTEM_VALUE_LOCAL_INVOCATION_INDEX;
2178 case nir_intrinsic_load_num_work_groups:
2179 return SYSTEM_VALUE_NUM_WORK_GROUPS;
2180 case nir_intrinsic_load_work_group_id:
2181 return SYSTEM_VALUE_WORK_GROUP_ID;
2182 case nir_intrinsic_load_primitive_id:
2183 return SYSTEM_VALUE_PRIMITIVE_ID;
2184 case nir_intrinsic_load_tess_coord:
2185 return SYSTEM_VALUE_TESS_COORD;
2186 case nir_intrinsic_load_tess_level_outer:
2187 return SYSTEM_VALUE_TESS_LEVEL_OUTER;
2188 case nir_intrinsic_load_tess_level_inner:
2189 return SYSTEM_VALUE_TESS_LEVEL_INNER;
2190 case nir_intrinsic_load_tess_level_outer_default:
2191 return SYSTEM_VALUE_TESS_LEVEL_OUTER_DEFAULT;
2192 case nir_intrinsic_load_tess_level_inner_default:
2193 return SYSTEM_VALUE_TESS_LEVEL_INNER_DEFAULT;
2194 case nir_intrinsic_load_patch_vertices_in:
2195 return SYSTEM_VALUE_VERTICES_IN;
2196 case nir_intrinsic_load_helper_invocation:
2197 return SYSTEM_VALUE_HELPER_INVOCATION;
2198 case nir_intrinsic_load_color0:
2199 return SYSTEM_VALUE_COLOR0;
2200 case nir_intrinsic_load_color1:
2201 return SYSTEM_VALUE_COLOR1;
2202 case nir_intrinsic_load_view_index:
2203 return SYSTEM_VALUE_VIEW_INDEX;
2204 case nir_intrinsic_load_subgroup_size:
2205 return SYSTEM_VALUE_SUBGROUP_SIZE;
2206 case nir_intrinsic_load_subgroup_invocation:
2207 return SYSTEM_VALUE_SUBGROUP_INVOCATION;
2208 case nir_intrinsic_load_subgroup_eq_mask:
2209 return SYSTEM_VALUE_SUBGROUP_EQ_MASK;
2210 case nir_intrinsic_load_subgroup_ge_mask:
2211 return SYSTEM_VALUE_SUBGROUP_GE_MASK;
2212 case nir_intrinsic_load_subgroup_gt_mask:
2213 return SYSTEM_VALUE_SUBGROUP_GT_MASK;
2214 case nir_intrinsic_load_subgroup_le_mask:
2215 return SYSTEM_VALUE_SUBGROUP_LE_MASK;
2216 case nir_intrinsic_load_subgroup_lt_mask:
2217 return SYSTEM_VALUE_SUBGROUP_LT_MASK;
2218 case nir_intrinsic_load_num_subgroups:
2219 return SYSTEM_VALUE_NUM_SUBGROUPS;
2220 case nir_intrinsic_load_subgroup_id:
2221 return SYSTEM_VALUE_SUBGROUP_ID;
2222 case nir_intrinsic_load_local_group_size:
2223 return SYSTEM_VALUE_LOCAL_GROUP_SIZE;
2224 case nir_intrinsic_load_global_invocation_id:
2225 return SYSTEM_VALUE_GLOBAL_INVOCATION_ID;
2226 case nir_intrinsic_load_base_global_invocation_id:
2227 return SYSTEM_VALUE_BASE_GLOBAL_INVOCATION_ID;
2228 case nir_intrinsic_load_global_invocation_index:
2229 return SYSTEM_VALUE_GLOBAL_INVOCATION_INDEX;
2230 case nir_intrinsic_load_work_dim:
2231 return SYSTEM_VALUE_WORK_DIM;
2232 case nir_intrinsic_load_user_data_amd:
2233 return SYSTEM_VALUE_USER_DATA_AMD;
2234 default:
2235 unreachable("intrinsic doesn't produce a system value");
2236 }
2237 }
2238
2239 /* OpenGL utility method that remaps the location attributes if they are
2240 * doubles. Not needed for vulkan due the differences on the input location
2241 * count for doubles on vulkan vs OpenGL
2242 *
2243 * The bitfield returned in dual_slot is one bit for each double input slot in
2244 * the original OpenGL single-slot input numbering. The mapping from old
2245 * locations to new locations is as follows:
2246 *
2247 * new_loc = loc + util_bitcount(dual_slot & BITFIELD64_MASK(loc))
2248 */
2249 void
2250 nir_remap_dual_slot_attributes(nir_shader *shader, uint64_t *dual_slot)
2251 {
2252 assert(shader->info.stage == MESA_SHADER_VERTEX);
2253
2254 *dual_slot = 0;
2255 nir_foreach_shader_in_variable(var, shader) {
2256 if (glsl_type_is_dual_slot(glsl_without_array(var->type))) {
2257 unsigned slots = glsl_count_attribute_slots(var->type, true);
2258 *dual_slot |= BITFIELD64_MASK(slots) << var->data.location;
2259 }
2260 }
2261
2262 nir_foreach_shader_in_variable(var, shader) {
2263 var->data.location +=
2264 util_bitcount64(*dual_slot & BITFIELD64_MASK(var->data.location));
2265 }
2266 }
2267
2268 /* Returns an attribute mask that has been re-compacted using the given
2269 * dual_slot mask.
2270 */
2271 uint64_t
2272 nir_get_single_slot_attribs_mask(uint64_t attribs, uint64_t dual_slot)
2273 {
2274 while (dual_slot) {
2275 unsigned loc = u_bit_scan64(&dual_slot);
2276 /* mask of all bits up to and including loc */
2277 uint64_t mask = BITFIELD64_MASK(loc + 1);
2278 attribs = (attribs & mask) | ((attribs & ~mask) >> 1);
2279 }
2280 return attribs;
2281 }
2282
2283 void
2284 nir_rewrite_image_intrinsic(nir_intrinsic_instr *intrin, nir_ssa_def *src,
2285 bool bindless)
2286 {
2287 enum gl_access_qualifier access = nir_intrinsic_access(intrin);
2288
2289 switch (intrin->intrinsic) {
2290 #define CASE(op) \
2291 case nir_intrinsic_image_deref_##op: \
2292 intrin->intrinsic = bindless ? nir_intrinsic_bindless_image_##op \
2293 : nir_intrinsic_image_##op; \
2294 break;
2295 CASE(load)
2296 CASE(store)
2297 CASE(atomic_add)
2298 CASE(atomic_imin)
2299 CASE(atomic_umin)
2300 CASE(atomic_imax)
2301 CASE(atomic_umax)
2302 CASE(atomic_and)
2303 CASE(atomic_or)
2304 CASE(atomic_xor)
2305 CASE(atomic_exchange)
2306 CASE(atomic_comp_swap)
2307 CASE(atomic_fadd)
2308 CASE(atomic_inc_wrap)
2309 CASE(atomic_dec_wrap)
2310 CASE(size)
2311 CASE(samples)
2312 CASE(load_raw_intel)
2313 CASE(store_raw_intel)
2314 #undef CASE
2315 default:
2316 unreachable("Unhanded image intrinsic");
2317 }
2318
2319 nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);
2320 nir_variable *var = nir_deref_instr_get_variable(deref);
2321
2322 nir_intrinsic_set_image_dim(intrin, glsl_get_sampler_dim(deref->type));
2323 nir_intrinsic_set_image_array(intrin, glsl_sampler_type_is_array(deref->type));
2324 nir_intrinsic_set_access(intrin, access | var->data.access);
2325 nir_intrinsic_set_format(intrin, var->data.image.format);
2326
2327 nir_instr_rewrite_src(&intrin->instr, &intrin->src[0],
2328 nir_src_for_ssa(src));
2329 }
2330
2331 unsigned
2332 nir_image_intrinsic_coord_components(const nir_intrinsic_instr *instr)
2333 {
2334 enum glsl_sampler_dim dim = nir_intrinsic_image_dim(instr);
2335 int coords = glsl_get_sampler_dim_coordinate_components(dim);
2336 if (dim == GLSL_SAMPLER_DIM_CUBE)
2337 return coords;
2338 else
2339 return coords + nir_intrinsic_image_array(instr);
2340 }