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spirv: extract switch parsing into its own function
[mesa.git] / src / compiler / nir / nir.c
1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Connor Abbott (cwabbott0@gmail.com)
25 *
26 */
27
28 #include "nir.h"
29 #include "nir_builder.h"
30 #include "nir_control_flow_private.h"
31 #include "util/half_float.h"
32 #include <limits.h>
33 #include <assert.h>
34 #include <math.h>
35 #include "util/u_math.h"
36
37 #include "main/menums.h" /* BITFIELD64_MASK */
38
39 nir_shader *
40 nir_shader_create(void *mem_ctx,
41 gl_shader_stage stage,
42 const nir_shader_compiler_options *options,
43 shader_info *si)
44 {
45 nir_shader *shader = rzalloc(mem_ctx, nir_shader);
46
47 exec_list_make_empty(&shader->variables);
48
49 shader->options = options;
50
51 if (si) {
52 assert(si->stage == stage);
53 shader->info = *si;
54 } else {
55 shader->info.stage = stage;
56 }
57
58 exec_list_make_empty(&shader->functions);
59
60 shader->num_inputs = 0;
61 shader->num_outputs = 0;
62 shader->num_uniforms = 0;
63 shader->num_shared = 0;
64
65 return shader;
66 }
67
68 static nir_register *
69 reg_create(void *mem_ctx, struct exec_list *list)
70 {
71 nir_register *reg = ralloc(mem_ctx, nir_register);
72
73 list_inithead(&reg->uses);
74 list_inithead(&reg->defs);
75 list_inithead(&reg->if_uses);
76
77 reg->num_components = 0;
78 reg->bit_size = 32;
79 reg->num_array_elems = 0;
80 reg->name = NULL;
81
82 exec_list_push_tail(list, &reg->node);
83
84 return reg;
85 }
86
87 nir_register *
88 nir_local_reg_create(nir_function_impl *impl)
89 {
90 nir_register *reg = reg_create(ralloc_parent(impl), &impl->registers);
91 reg->index = impl->reg_alloc++;
92
93 return reg;
94 }
95
96 void
97 nir_reg_remove(nir_register *reg)
98 {
99 exec_node_remove(&reg->node);
100 }
101
102 void
103 nir_shader_add_variable(nir_shader *shader, nir_variable *var)
104 {
105 switch (var->data.mode) {
106 case nir_var_function_temp:
107 assert(!"nir_shader_add_variable cannot be used for local variables");
108 return;
109
110 case nir_var_shader_temp:
111 case nir_var_shader_in:
112 case nir_var_shader_out:
113 case nir_var_uniform:
114 case nir_var_mem_ubo:
115 case nir_var_mem_ssbo:
116 case nir_var_mem_shared:
117 case nir_var_system_value:
118 break;
119
120 case nir_var_mem_global:
121 assert(!"nir_shader_add_variable cannot be used for global memory");
122 return;
123
124 case nir_var_mem_push_const:
125 assert(!"nir_var_push_constant is not supposed to be used for variables");
126 return;
127
128 default:
129 assert(!"invalid mode");
130 return;
131 }
132
133 exec_list_push_tail(&shader->variables, &var->node);
134 }
135
136 nir_variable *
137 nir_variable_create(nir_shader *shader, nir_variable_mode mode,
138 const struct glsl_type *type, const char *name)
139 {
140 nir_variable *var = rzalloc(shader, nir_variable);
141 var->name = ralloc_strdup(var, name);
142 var->type = type;
143 var->data.mode = mode;
144 var->data.how_declared = nir_var_declared_normally;
145
146 if ((mode == nir_var_shader_in &&
147 shader->info.stage != MESA_SHADER_VERTEX) ||
148 (mode == nir_var_shader_out &&
149 shader->info.stage != MESA_SHADER_FRAGMENT))
150 var->data.interpolation = INTERP_MODE_SMOOTH;
151
152 if (mode == nir_var_shader_in || mode == nir_var_uniform)
153 var->data.read_only = true;
154
155 nir_shader_add_variable(shader, var);
156
157 return var;
158 }
159
160 nir_variable *
161 nir_local_variable_create(nir_function_impl *impl,
162 const struct glsl_type *type, const char *name)
163 {
164 nir_variable *var = rzalloc(impl->function->shader, nir_variable);
165 var->name = ralloc_strdup(var, name);
166 var->type = type;
167 var->data.mode = nir_var_function_temp;
168
169 nir_function_impl_add_variable(impl, var);
170
171 return var;
172 }
173
174 nir_variable *
175 nir_find_variable_with_location(nir_shader *shader,
176 nir_variable_mode mode,
177 unsigned location)
178 {
179 assert(util_bitcount(mode) == 1 && mode != nir_var_function_temp);
180 nir_foreach_variable_with_modes(var, shader, mode) {
181 if (var->data.location == location)
182 return var;
183 }
184 return NULL;
185 }
186
187 nir_variable *
188 nir_find_variable_with_driver_location(nir_shader *shader,
189 nir_variable_mode mode,
190 unsigned location)
191 {
192 assert(util_bitcount(mode) == 1 && mode != nir_var_function_temp);
193 nir_foreach_variable_with_modes(var, shader, mode) {
194 if (var->data.driver_location == location)
195 return var;
196 }
197 return NULL;
198 }
199
200 nir_function *
201 nir_function_create(nir_shader *shader, const char *name)
202 {
203 nir_function *func = ralloc(shader, nir_function);
204
205 exec_list_push_tail(&shader->functions, &func->node);
206
207 func->name = ralloc_strdup(func, name);
208 func->shader = shader;
209 func->num_params = 0;
210 func->params = NULL;
211 func->impl = NULL;
212 func->is_entrypoint = false;
213
214 return func;
215 }
216
217 /* NOTE: if the instruction you are copying a src to is already added
218 * to the IR, use nir_instr_rewrite_src() instead.
219 */
220 void nir_src_copy(nir_src *dest, const nir_src *src, void *mem_ctx)
221 {
222 dest->is_ssa = src->is_ssa;
223 if (src->is_ssa) {
224 dest->ssa = src->ssa;
225 } else {
226 dest->reg.base_offset = src->reg.base_offset;
227 dest->reg.reg = src->reg.reg;
228 if (src->reg.indirect) {
229 dest->reg.indirect = ralloc(mem_ctx, nir_src);
230 nir_src_copy(dest->reg.indirect, src->reg.indirect, mem_ctx);
231 } else {
232 dest->reg.indirect = NULL;
233 }
234 }
235 }
236
237 void nir_dest_copy(nir_dest *dest, const nir_dest *src, nir_instr *instr)
238 {
239 /* Copying an SSA definition makes no sense whatsoever. */
240 assert(!src->is_ssa);
241
242 dest->is_ssa = false;
243
244 dest->reg.base_offset = src->reg.base_offset;
245 dest->reg.reg = src->reg.reg;
246 if (src->reg.indirect) {
247 dest->reg.indirect = ralloc(instr, nir_src);
248 nir_src_copy(dest->reg.indirect, src->reg.indirect, instr);
249 } else {
250 dest->reg.indirect = NULL;
251 }
252 }
253
254 void
255 nir_alu_src_copy(nir_alu_src *dest, const nir_alu_src *src,
256 nir_alu_instr *instr)
257 {
258 nir_src_copy(&dest->src, &src->src, &instr->instr);
259 dest->abs = src->abs;
260 dest->negate = src->negate;
261 for (unsigned i = 0; i < NIR_MAX_VEC_COMPONENTS; i++)
262 dest->swizzle[i] = src->swizzle[i];
263 }
264
265 void
266 nir_alu_dest_copy(nir_alu_dest *dest, const nir_alu_dest *src,
267 nir_alu_instr *instr)
268 {
269 nir_dest_copy(&dest->dest, &src->dest, &instr->instr);
270 dest->write_mask = src->write_mask;
271 dest->saturate = src->saturate;
272 }
273
274
275 static void
276 cf_init(nir_cf_node *node, nir_cf_node_type type)
277 {
278 exec_node_init(&node->node);
279 node->parent = NULL;
280 node->type = type;
281 }
282
283 nir_function_impl *
284 nir_function_impl_create_bare(nir_shader *shader)
285 {
286 nir_function_impl *impl = ralloc(shader, nir_function_impl);
287
288 impl->function = NULL;
289
290 cf_init(&impl->cf_node, nir_cf_node_function);
291
292 exec_list_make_empty(&impl->body);
293 exec_list_make_empty(&impl->registers);
294 exec_list_make_empty(&impl->locals);
295 impl->reg_alloc = 0;
296 impl->ssa_alloc = 0;
297 impl->valid_metadata = nir_metadata_none;
298 impl->structured = true;
299
300 /* create start & end blocks */
301 nir_block *start_block = nir_block_create(shader);
302 nir_block *end_block = nir_block_create(shader);
303 start_block->cf_node.parent = &impl->cf_node;
304 end_block->cf_node.parent = &impl->cf_node;
305 impl->end_block = end_block;
306
307 exec_list_push_tail(&impl->body, &start_block->cf_node.node);
308
309 start_block->successors[0] = end_block;
310 _mesa_set_add(end_block->predecessors, start_block);
311 return impl;
312 }
313
314 nir_function_impl *
315 nir_function_impl_create(nir_function *function)
316 {
317 assert(function->impl == NULL);
318
319 nir_function_impl *impl = nir_function_impl_create_bare(function->shader);
320
321 function->impl = impl;
322 impl->function = function;
323
324 return impl;
325 }
326
327 nir_block *
328 nir_block_create(nir_shader *shader)
329 {
330 nir_block *block = rzalloc(shader, nir_block);
331
332 cf_init(&block->cf_node, nir_cf_node_block);
333
334 block->successors[0] = block->successors[1] = NULL;
335 block->predecessors = _mesa_pointer_set_create(block);
336 block->imm_dom = NULL;
337 /* XXX maybe it would be worth it to defer allocation? This
338 * way it doesn't get allocated for shader refs that never run
339 * nir_calc_dominance? For example, state-tracker creates an
340 * initial IR, clones that, runs appropriate lowering pass, passes
341 * to driver which does common lowering/opt, and then stores ref
342 * which is later used to do state specific lowering and futher
343 * opt. Do any of the references not need dominance metadata?
344 */
345 block->dom_frontier = _mesa_pointer_set_create(block);
346
347 exec_list_make_empty(&block->instr_list);
348
349 return block;
350 }
351
352 static inline void
353 src_init(nir_src *src)
354 {
355 src->is_ssa = false;
356 src->reg.reg = NULL;
357 src->reg.indirect = NULL;
358 src->reg.base_offset = 0;
359 }
360
361 nir_if *
362 nir_if_create(nir_shader *shader)
363 {
364 nir_if *if_stmt = ralloc(shader, nir_if);
365
366 if_stmt->control = nir_selection_control_none;
367
368 cf_init(&if_stmt->cf_node, nir_cf_node_if);
369 src_init(&if_stmt->condition);
370
371 nir_block *then = nir_block_create(shader);
372 exec_list_make_empty(&if_stmt->then_list);
373 exec_list_push_tail(&if_stmt->then_list, &then->cf_node.node);
374 then->cf_node.parent = &if_stmt->cf_node;
375
376 nir_block *else_stmt = nir_block_create(shader);
377 exec_list_make_empty(&if_stmt->else_list);
378 exec_list_push_tail(&if_stmt->else_list, &else_stmt->cf_node.node);
379 else_stmt->cf_node.parent = &if_stmt->cf_node;
380
381 return if_stmt;
382 }
383
384 nir_loop *
385 nir_loop_create(nir_shader *shader)
386 {
387 nir_loop *loop = rzalloc(shader, nir_loop);
388
389 cf_init(&loop->cf_node, nir_cf_node_loop);
390
391 nir_block *body = nir_block_create(shader);
392 exec_list_make_empty(&loop->body);
393 exec_list_push_tail(&loop->body, &body->cf_node.node);
394 body->cf_node.parent = &loop->cf_node;
395
396 body->successors[0] = body;
397 _mesa_set_add(body->predecessors, body);
398
399 return loop;
400 }
401
402 static void
403 instr_init(nir_instr *instr, nir_instr_type type)
404 {
405 instr->type = type;
406 instr->block = NULL;
407 exec_node_init(&instr->node);
408 }
409
410 static void
411 dest_init(nir_dest *dest)
412 {
413 dest->is_ssa = false;
414 dest->reg.reg = NULL;
415 dest->reg.indirect = NULL;
416 dest->reg.base_offset = 0;
417 }
418
419 static void
420 alu_dest_init(nir_alu_dest *dest)
421 {
422 dest_init(&dest->dest);
423 dest->saturate = false;
424 dest->write_mask = 0xf;
425 }
426
427 static void
428 alu_src_init(nir_alu_src *src)
429 {
430 src_init(&src->src);
431 src->abs = src->negate = false;
432 for (int i = 0; i < NIR_MAX_VEC_COMPONENTS; ++i)
433 src->swizzle[i] = i;
434 }
435
436 nir_alu_instr *
437 nir_alu_instr_create(nir_shader *shader, nir_op op)
438 {
439 unsigned num_srcs = nir_op_infos[op].num_inputs;
440 /* TODO: don't use rzalloc */
441 nir_alu_instr *instr =
442 rzalloc_size(shader,
443 sizeof(nir_alu_instr) + num_srcs * sizeof(nir_alu_src));
444
445 instr_init(&instr->instr, nir_instr_type_alu);
446 instr->op = op;
447 alu_dest_init(&instr->dest);
448 for (unsigned i = 0; i < num_srcs; i++)
449 alu_src_init(&instr->src[i]);
450
451 return instr;
452 }
453
454 nir_deref_instr *
455 nir_deref_instr_create(nir_shader *shader, nir_deref_type deref_type)
456 {
457 nir_deref_instr *instr =
458 rzalloc_size(shader, sizeof(nir_deref_instr));
459
460 instr_init(&instr->instr, nir_instr_type_deref);
461
462 instr->deref_type = deref_type;
463 if (deref_type != nir_deref_type_var)
464 src_init(&instr->parent);
465
466 if (deref_type == nir_deref_type_array ||
467 deref_type == nir_deref_type_ptr_as_array)
468 src_init(&instr->arr.index);
469
470 dest_init(&instr->dest);
471
472 return instr;
473 }
474
475 nir_jump_instr *
476 nir_jump_instr_create(nir_shader *shader, nir_jump_type type)
477 {
478 nir_jump_instr *instr = ralloc(shader, nir_jump_instr);
479 instr_init(&instr->instr, nir_instr_type_jump);
480 src_init(&instr->condition);
481 instr->type = type;
482 instr->target = NULL;
483 instr->else_target = NULL;
484 return instr;
485 }
486
487 nir_load_const_instr *
488 nir_load_const_instr_create(nir_shader *shader, unsigned num_components,
489 unsigned bit_size)
490 {
491 nir_load_const_instr *instr =
492 rzalloc_size(shader, sizeof(*instr) + num_components * sizeof(*instr->value));
493 instr_init(&instr->instr, nir_instr_type_load_const);
494
495 nir_ssa_def_init(&instr->instr, &instr->def, num_components, bit_size, NULL);
496
497 return instr;
498 }
499
500 nir_intrinsic_instr *
501 nir_intrinsic_instr_create(nir_shader *shader, nir_intrinsic_op op)
502 {
503 unsigned num_srcs = nir_intrinsic_infos[op].num_srcs;
504 /* TODO: don't use rzalloc */
505 nir_intrinsic_instr *instr =
506 rzalloc_size(shader,
507 sizeof(nir_intrinsic_instr) + num_srcs * sizeof(nir_src));
508
509 instr_init(&instr->instr, nir_instr_type_intrinsic);
510 instr->intrinsic = op;
511
512 if (nir_intrinsic_infos[op].has_dest)
513 dest_init(&instr->dest);
514
515 for (unsigned i = 0; i < num_srcs; i++)
516 src_init(&instr->src[i]);
517
518 return instr;
519 }
520
521 nir_call_instr *
522 nir_call_instr_create(nir_shader *shader, nir_function *callee)
523 {
524 const unsigned num_params = callee->num_params;
525 nir_call_instr *instr =
526 rzalloc_size(shader, sizeof(*instr) +
527 num_params * sizeof(instr->params[0]));
528
529 instr_init(&instr->instr, nir_instr_type_call);
530 instr->callee = callee;
531 instr->num_params = num_params;
532 for (unsigned i = 0; i < num_params; i++)
533 src_init(&instr->params[i]);
534
535 return instr;
536 }
537
538 static int8_t default_tg4_offsets[4][2] =
539 {
540 { 0, 1 },
541 { 1, 1 },
542 { 1, 0 },
543 { 0, 0 },
544 };
545
546 nir_tex_instr *
547 nir_tex_instr_create(nir_shader *shader, unsigned num_srcs)
548 {
549 nir_tex_instr *instr = rzalloc(shader, nir_tex_instr);
550 instr_init(&instr->instr, nir_instr_type_tex);
551
552 dest_init(&instr->dest);
553
554 instr->num_srcs = num_srcs;
555 instr->src = ralloc_array(instr, nir_tex_src, num_srcs);
556 for (unsigned i = 0; i < num_srcs; i++)
557 src_init(&instr->src[i].src);
558
559 instr->texture_index = 0;
560 instr->sampler_index = 0;
561 memcpy(instr->tg4_offsets, default_tg4_offsets, sizeof(instr->tg4_offsets));
562
563 return instr;
564 }
565
566 void
567 nir_tex_instr_add_src(nir_tex_instr *tex,
568 nir_tex_src_type src_type,
569 nir_src src)
570 {
571 nir_tex_src *new_srcs = rzalloc_array(tex, nir_tex_src,
572 tex->num_srcs + 1);
573
574 for (unsigned i = 0; i < tex->num_srcs; i++) {
575 new_srcs[i].src_type = tex->src[i].src_type;
576 nir_instr_move_src(&tex->instr, &new_srcs[i].src,
577 &tex->src[i].src);
578 }
579
580 ralloc_free(tex->src);
581 tex->src = new_srcs;
582
583 tex->src[tex->num_srcs].src_type = src_type;
584 nir_instr_rewrite_src(&tex->instr, &tex->src[tex->num_srcs].src, src);
585 tex->num_srcs++;
586 }
587
588 void
589 nir_tex_instr_remove_src(nir_tex_instr *tex, unsigned src_idx)
590 {
591 assert(src_idx < tex->num_srcs);
592
593 /* First rewrite the source to NIR_SRC_INIT */
594 nir_instr_rewrite_src(&tex->instr, &tex->src[src_idx].src, NIR_SRC_INIT);
595
596 /* Now, move all of the other sources down */
597 for (unsigned i = src_idx + 1; i < tex->num_srcs; i++) {
598 tex->src[i-1].src_type = tex->src[i].src_type;
599 nir_instr_move_src(&tex->instr, &tex->src[i-1].src, &tex->src[i].src);
600 }
601 tex->num_srcs--;
602 }
603
604 bool
605 nir_tex_instr_has_explicit_tg4_offsets(nir_tex_instr *tex)
606 {
607 if (tex->op != nir_texop_tg4)
608 return false;
609 return memcmp(tex->tg4_offsets, default_tg4_offsets,
610 sizeof(tex->tg4_offsets)) != 0;
611 }
612
613 nir_phi_instr *
614 nir_phi_instr_create(nir_shader *shader)
615 {
616 nir_phi_instr *instr = ralloc(shader, nir_phi_instr);
617 instr_init(&instr->instr, nir_instr_type_phi);
618
619 dest_init(&instr->dest);
620 exec_list_make_empty(&instr->srcs);
621 return instr;
622 }
623
624 nir_parallel_copy_instr *
625 nir_parallel_copy_instr_create(nir_shader *shader)
626 {
627 nir_parallel_copy_instr *instr = ralloc(shader, nir_parallel_copy_instr);
628 instr_init(&instr->instr, nir_instr_type_parallel_copy);
629
630 exec_list_make_empty(&instr->entries);
631
632 return instr;
633 }
634
635 nir_ssa_undef_instr *
636 nir_ssa_undef_instr_create(nir_shader *shader,
637 unsigned num_components,
638 unsigned bit_size)
639 {
640 nir_ssa_undef_instr *instr = ralloc(shader, nir_ssa_undef_instr);
641 instr_init(&instr->instr, nir_instr_type_ssa_undef);
642
643 nir_ssa_def_init(&instr->instr, &instr->def, num_components, bit_size, NULL);
644
645 return instr;
646 }
647
648 static nir_const_value
649 const_value_float(double d, unsigned bit_size)
650 {
651 nir_const_value v;
652 memset(&v, 0, sizeof(v));
653 switch (bit_size) {
654 case 16: v.u16 = _mesa_float_to_half(d); break;
655 case 32: v.f32 = d; break;
656 case 64: v.f64 = d; break;
657 default:
658 unreachable("Invalid bit size");
659 }
660 return v;
661 }
662
663 static nir_const_value
664 const_value_int(int64_t i, unsigned bit_size)
665 {
666 nir_const_value v;
667 memset(&v, 0, sizeof(v));
668 switch (bit_size) {
669 case 1: v.b = i & 1; break;
670 case 8: v.i8 = i; break;
671 case 16: v.i16 = i; break;
672 case 32: v.i32 = i; break;
673 case 64: v.i64 = i; break;
674 default:
675 unreachable("Invalid bit size");
676 }
677 return v;
678 }
679
680 nir_const_value
681 nir_alu_binop_identity(nir_op binop, unsigned bit_size)
682 {
683 const int64_t max_int = (1ull << (bit_size - 1)) - 1;
684 const int64_t min_int = -max_int - 1;
685 switch (binop) {
686 case nir_op_iadd:
687 return const_value_int(0, bit_size);
688 case nir_op_fadd:
689 return const_value_float(0, bit_size);
690 case nir_op_imul:
691 return const_value_int(1, bit_size);
692 case nir_op_fmul:
693 return const_value_float(1, bit_size);
694 case nir_op_imin:
695 return const_value_int(max_int, bit_size);
696 case nir_op_umin:
697 return const_value_int(~0ull, bit_size);
698 case nir_op_fmin:
699 return const_value_float(INFINITY, bit_size);
700 case nir_op_imax:
701 return const_value_int(min_int, bit_size);
702 case nir_op_umax:
703 return const_value_int(0, bit_size);
704 case nir_op_fmax:
705 return const_value_float(-INFINITY, bit_size);
706 case nir_op_iand:
707 return const_value_int(~0ull, bit_size);
708 case nir_op_ior:
709 return const_value_int(0, bit_size);
710 case nir_op_ixor:
711 return const_value_int(0, bit_size);
712 default:
713 unreachable("Invalid reduction operation");
714 }
715 }
716
717 nir_function_impl *
718 nir_cf_node_get_function(nir_cf_node *node)
719 {
720 while (node->type != nir_cf_node_function) {
721 node = node->parent;
722 }
723
724 return nir_cf_node_as_function(node);
725 }
726
727 /* Reduces a cursor by trying to convert everything to after and trying to
728 * go up to block granularity when possible.
729 */
730 static nir_cursor
731 reduce_cursor(nir_cursor cursor)
732 {
733 switch (cursor.option) {
734 case nir_cursor_before_block:
735 assert(nir_cf_node_prev(&cursor.block->cf_node) == NULL ||
736 nir_cf_node_prev(&cursor.block->cf_node)->type != nir_cf_node_block);
737 if (exec_list_is_empty(&cursor.block->instr_list)) {
738 /* Empty block. After is as good as before. */
739 cursor.option = nir_cursor_after_block;
740 }
741 return cursor;
742
743 case nir_cursor_after_block:
744 return cursor;
745
746 case nir_cursor_before_instr: {
747 nir_instr *prev_instr = nir_instr_prev(cursor.instr);
748 if (prev_instr) {
749 /* Before this instruction is after the previous */
750 cursor.instr = prev_instr;
751 cursor.option = nir_cursor_after_instr;
752 } else {
753 /* No previous instruction. Switch to before block */
754 cursor.block = cursor.instr->block;
755 cursor.option = nir_cursor_before_block;
756 }
757 return reduce_cursor(cursor);
758 }
759
760 case nir_cursor_after_instr:
761 if (nir_instr_next(cursor.instr) == NULL) {
762 /* This is the last instruction, switch to after block */
763 cursor.option = nir_cursor_after_block;
764 cursor.block = cursor.instr->block;
765 }
766 return cursor;
767
768 default:
769 unreachable("Inavlid cursor option");
770 }
771 }
772
773 bool
774 nir_cursors_equal(nir_cursor a, nir_cursor b)
775 {
776 /* Reduced cursors should be unique */
777 a = reduce_cursor(a);
778 b = reduce_cursor(b);
779
780 return a.block == b.block && a.option == b.option;
781 }
782
783 static bool
784 add_use_cb(nir_src *src, void *state)
785 {
786 nir_instr *instr = state;
787
788 src->parent_instr = instr;
789 list_addtail(&src->use_link,
790 src->is_ssa ? &src->ssa->uses : &src->reg.reg->uses);
791
792 return true;
793 }
794
795 static bool
796 add_ssa_def_cb(nir_ssa_def *def, void *state)
797 {
798 nir_instr *instr = state;
799
800 if (instr->block && def->index == UINT_MAX) {
801 nir_function_impl *impl =
802 nir_cf_node_get_function(&instr->block->cf_node);
803
804 def->index = impl->ssa_alloc++;
805 }
806
807 return true;
808 }
809
810 static bool
811 add_reg_def_cb(nir_dest *dest, void *state)
812 {
813 nir_instr *instr = state;
814
815 if (!dest->is_ssa) {
816 dest->reg.parent_instr = instr;
817 list_addtail(&dest->reg.def_link, &dest->reg.reg->defs);
818 }
819
820 return true;
821 }
822
823 static void
824 add_defs_uses(nir_instr *instr)
825 {
826 nir_foreach_src(instr, add_use_cb, instr);
827 nir_foreach_dest(instr, add_reg_def_cb, instr);
828 nir_foreach_ssa_def(instr, add_ssa_def_cb, instr);
829 }
830
831 void
832 nir_instr_insert(nir_cursor cursor, nir_instr *instr)
833 {
834 switch (cursor.option) {
835 case nir_cursor_before_block:
836 /* Only allow inserting jumps into empty blocks. */
837 if (instr->type == nir_instr_type_jump)
838 assert(exec_list_is_empty(&cursor.block->instr_list));
839
840 instr->block = cursor.block;
841 add_defs_uses(instr);
842 exec_list_push_head(&cursor.block->instr_list, &instr->node);
843 break;
844 case nir_cursor_after_block: {
845 /* Inserting instructions after a jump is illegal. */
846 nir_instr *last = nir_block_last_instr(cursor.block);
847 assert(last == NULL || last->type != nir_instr_type_jump);
848 (void) last;
849
850 instr->block = cursor.block;
851 add_defs_uses(instr);
852 exec_list_push_tail(&cursor.block->instr_list, &instr->node);
853 break;
854 }
855 case nir_cursor_before_instr:
856 assert(instr->type != nir_instr_type_jump);
857 instr->block = cursor.instr->block;
858 add_defs_uses(instr);
859 exec_node_insert_node_before(&cursor.instr->node, &instr->node);
860 break;
861 case nir_cursor_after_instr:
862 /* Inserting instructions after a jump is illegal. */
863 assert(cursor.instr->type != nir_instr_type_jump);
864
865 /* Only allow inserting jumps at the end of the block. */
866 if (instr->type == nir_instr_type_jump)
867 assert(cursor.instr == nir_block_last_instr(cursor.instr->block));
868
869 instr->block = cursor.instr->block;
870 add_defs_uses(instr);
871 exec_node_insert_after(&cursor.instr->node, &instr->node);
872 break;
873 }
874
875 if (instr->type == nir_instr_type_jump)
876 nir_handle_add_jump(instr->block);
877 }
878
879 static bool
880 src_is_valid(const nir_src *src)
881 {
882 return src->is_ssa ? (src->ssa != NULL) : (src->reg.reg != NULL);
883 }
884
885 static bool
886 remove_use_cb(nir_src *src, void *state)
887 {
888 (void) state;
889
890 if (src_is_valid(src))
891 list_del(&src->use_link);
892
893 return true;
894 }
895
896 static bool
897 remove_def_cb(nir_dest *dest, void *state)
898 {
899 (void) state;
900
901 if (!dest->is_ssa)
902 list_del(&dest->reg.def_link);
903
904 return true;
905 }
906
907 static void
908 remove_defs_uses(nir_instr *instr)
909 {
910 nir_foreach_dest(instr, remove_def_cb, instr);
911 nir_foreach_src(instr, remove_use_cb, instr);
912 }
913
914 void nir_instr_remove_v(nir_instr *instr)
915 {
916 remove_defs_uses(instr);
917 exec_node_remove(&instr->node);
918
919 if (instr->type == nir_instr_type_jump) {
920 nir_jump_instr *jump_instr = nir_instr_as_jump(instr);
921 nir_handle_remove_jump(instr->block, jump_instr->type);
922 }
923 }
924
925 /*@}*/
926
927 void
928 nir_index_local_regs(nir_function_impl *impl)
929 {
930 unsigned index = 0;
931 foreach_list_typed(nir_register, reg, node, &impl->registers) {
932 reg->index = index++;
933 }
934 impl->reg_alloc = index;
935 }
936
937 static bool
938 visit_alu_dest(nir_alu_instr *instr, nir_foreach_dest_cb cb, void *state)
939 {
940 return cb(&instr->dest.dest, state);
941 }
942
943 static bool
944 visit_deref_dest(nir_deref_instr *instr, nir_foreach_dest_cb cb, void *state)
945 {
946 return cb(&instr->dest, state);
947 }
948
949 static bool
950 visit_intrinsic_dest(nir_intrinsic_instr *instr, nir_foreach_dest_cb cb,
951 void *state)
952 {
953 if (nir_intrinsic_infos[instr->intrinsic].has_dest)
954 return cb(&instr->dest, state);
955
956 return true;
957 }
958
959 static bool
960 visit_texture_dest(nir_tex_instr *instr, nir_foreach_dest_cb cb,
961 void *state)
962 {
963 return cb(&instr->dest, state);
964 }
965
966 static bool
967 visit_phi_dest(nir_phi_instr *instr, nir_foreach_dest_cb cb, void *state)
968 {
969 return cb(&instr->dest, state);
970 }
971
972 static bool
973 visit_parallel_copy_dest(nir_parallel_copy_instr *instr,
974 nir_foreach_dest_cb cb, void *state)
975 {
976 nir_foreach_parallel_copy_entry(entry, instr) {
977 if (!cb(&entry->dest, state))
978 return false;
979 }
980
981 return true;
982 }
983
984 bool
985 nir_foreach_dest(nir_instr *instr, nir_foreach_dest_cb cb, void *state)
986 {
987 switch (instr->type) {
988 case nir_instr_type_alu:
989 return visit_alu_dest(nir_instr_as_alu(instr), cb, state);
990 case nir_instr_type_deref:
991 return visit_deref_dest(nir_instr_as_deref(instr), cb, state);
992 case nir_instr_type_intrinsic:
993 return visit_intrinsic_dest(nir_instr_as_intrinsic(instr), cb, state);
994 case nir_instr_type_tex:
995 return visit_texture_dest(nir_instr_as_tex(instr), cb, state);
996 case nir_instr_type_phi:
997 return visit_phi_dest(nir_instr_as_phi(instr), cb, state);
998 case nir_instr_type_parallel_copy:
999 return visit_parallel_copy_dest(nir_instr_as_parallel_copy(instr),
1000 cb, state);
1001
1002 case nir_instr_type_load_const:
1003 case nir_instr_type_ssa_undef:
1004 case nir_instr_type_call:
1005 case nir_instr_type_jump:
1006 break;
1007
1008 default:
1009 unreachable("Invalid instruction type");
1010 break;
1011 }
1012
1013 return true;
1014 }
1015
1016 struct foreach_ssa_def_state {
1017 nir_foreach_ssa_def_cb cb;
1018 void *client_state;
1019 };
1020
1021 static inline bool
1022 nir_ssa_def_visitor(nir_dest *dest, void *void_state)
1023 {
1024 struct foreach_ssa_def_state *state = void_state;
1025
1026 if (dest->is_ssa)
1027 return state->cb(&dest->ssa, state->client_state);
1028 else
1029 return true;
1030 }
1031
1032 bool
1033 nir_foreach_ssa_def(nir_instr *instr, nir_foreach_ssa_def_cb cb, void *state)
1034 {
1035 switch (instr->type) {
1036 case nir_instr_type_alu:
1037 case nir_instr_type_deref:
1038 case nir_instr_type_tex:
1039 case nir_instr_type_intrinsic:
1040 case nir_instr_type_phi:
1041 case nir_instr_type_parallel_copy: {
1042 struct foreach_ssa_def_state foreach_state = {cb, state};
1043 return nir_foreach_dest(instr, nir_ssa_def_visitor, &foreach_state);
1044 }
1045
1046 case nir_instr_type_load_const:
1047 return cb(&nir_instr_as_load_const(instr)->def, state);
1048 case nir_instr_type_ssa_undef:
1049 return cb(&nir_instr_as_ssa_undef(instr)->def, state);
1050 case nir_instr_type_call:
1051 case nir_instr_type_jump:
1052 return true;
1053 default:
1054 unreachable("Invalid instruction type");
1055 }
1056 }
1057
1058 nir_ssa_def *
1059 nir_instr_ssa_def(nir_instr *instr)
1060 {
1061 switch (instr->type) {
1062 case nir_instr_type_alu:
1063 assert(nir_instr_as_alu(instr)->dest.dest.is_ssa);
1064 return &nir_instr_as_alu(instr)->dest.dest.ssa;
1065
1066 case nir_instr_type_deref:
1067 assert(nir_instr_as_deref(instr)->dest.is_ssa);
1068 return &nir_instr_as_deref(instr)->dest.ssa;
1069
1070 case nir_instr_type_tex:
1071 assert(nir_instr_as_tex(instr)->dest.is_ssa);
1072 return &nir_instr_as_tex(instr)->dest.ssa;
1073
1074 case nir_instr_type_intrinsic: {
1075 nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
1076 if (nir_intrinsic_infos[intrin->intrinsic].has_dest) {
1077 assert(intrin->dest.is_ssa);
1078 return &intrin->dest.ssa;
1079 } else {
1080 return NULL;
1081 }
1082 }
1083
1084 case nir_instr_type_phi:
1085 assert(nir_instr_as_phi(instr)->dest.is_ssa);
1086 return &nir_instr_as_phi(instr)->dest.ssa;
1087
1088 case nir_instr_type_parallel_copy:
1089 unreachable("Parallel copies are unsupported by this function");
1090
1091 case nir_instr_type_load_const:
1092 return &nir_instr_as_load_const(instr)->def;
1093
1094 case nir_instr_type_ssa_undef:
1095 return &nir_instr_as_ssa_undef(instr)->def;
1096
1097 case nir_instr_type_call:
1098 case nir_instr_type_jump:
1099 return NULL;
1100 }
1101
1102 unreachable("Invalid instruction type");
1103 }
1104
1105 static bool
1106 visit_src(nir_src *src, nir_foreach_src_cb cb, void *state)
1107 {
1108 if (!cb(src, state))
1109 return false;
1110 if (!src->is_ssa && src->reg.indirect)
1111 return cb(src->reg.indirect, state);
1112 return true;
1113 }
1114
1115 static bool
1116 visit_alu_src(nir_alu_instr *instr, nir_foreach_src_cb cb, void *state)
1117 {
1118 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1119 if (!visit_src(&instr->src[i].src, cb, state))
1120 return false;
1121
1122 return true;
1123 }
1124
1125 static bool
1126 visit_deref_instr_src(nir_deref_instr *instr,
1127 nir_foreach_src_cb cb, void *state)
1128 {
1129 if (instr->deref_type != nir_deref_type_var) {
1130 if (!visit_src(&instr->parent, cb, state))
1131 return false;
1132 }
1133
1134 if (instr->deref_type == nir_deref_type_array ||
1135 instr->deref_type == nir_deref_type_ptr_as_array) {
1136 if (!visit_src(&instr->arr.index, cb, state))
1137 return false;
1138 }
1139
1140 return true;
1141 }
1142
1143 static bool
1144 visit_tex_src(nir_tex_instr *instr, nir_foreach_src_cb cb, void *state)
1145 {
1146 for (unsigned i = 0; i < instr->num_srcs; i++) {
1147 if (!visit_src(&instr->src[i].src, cb, state))
1148 return false;
1149 }
1150
1151 return true;
1152 }
1153
1154 static bool
1155 visit_intrinsic_src(nir_intrinsic_instr *instr, nir_foreach_src_cb cb,
1156 void *state)
1157 {
1158 unsigned num_srcs = nir_intrinsic_infos[instr->intrinsic].num_srcs;
1159 for (unsigned i = 0; i < num_srcs; i++) {
1160 if (!visit_src(&instr->src[i], cb, state))
1161 return false;
1162 }
1163
1164 return true;
1165 }
1166
1167 static bool
1168 visit_call_src(nir_call_instr *instr, nir_foreach_src_cb cb, void *state)
1169 {
1170 for (unsigned i = 0; i < instr->num_params; i++) {
1171 if (!visit_src(&instr->params[i], cb, state))
1172 return false;
1173 }
1174
1175 return true;
1176 }
1177
1178 static bool
1179 visit_phi_src(nir_phi_instr *instr, nir_foreach_src_cb cb, void *state)
1180 {
1181 nir_foreach_phi_src(src, instr) {
1182 if (!visit_src(&src->src, cb, state))
1183 return false;
1184 }
1185
1186 return true;
1187 }
1188
1189 static bool
1190 visit_parallel_copy_src(nir_parallel_copy_instr *instr,
1191 nir_foreach_src_cb cb, void *state)
1192 {
1193 nir_foreach_parallel_copy_entry(entry, instr) {
1194 if (!visit_src(&entry->src, cb, state))
1195 return false;
1196 }
1197
1198 return true;
1199 }
1200
1201 static bool
1202 visit_jump_src(nir_jump_instr *instr, nir_foreach_src_cb cb, void *state)
1203 {
1204 if (instr->type != nir_jump_goto_if)
1205 return true;
1206
1207 return visit_src(&instr->condition, cb, state);
1208 }
1209
1210 typedef struct {
1211 void *state;
1212 nir_foreach_src_cb cb;
1213 } visit_dest_indirect_state;
1214
1215 static bool
1216 visit_dest_indirect(nir_dest *dest, void *_state)
1217 {
1218 visit_dest_indirect_state *state = (visit_dest_indirect_state *) _state;
1219
1220 if (!dest->is_ssa && dest->reg.indirect)
1221 return state->cb(dest->reg.indirect, state->state);
1222
1223 return true;
1224 }
1225
1226 bool
1227 nir_foreach_src(nir_instr *instr, nir_foreach_src_cb cb, void *state)
1228 {
1229 switch (instr->type) {
1230 case nir_instr_type_alu:
1231 if (!visit_alu_src(nir_instr_as_alu(instr), cb, state))
1232 return false;
1233 break;
1234 case nir_instr_type_deref:
1235 if (!visit_deref_instr_src(nir_instr_as_deref(instr), cb, state))
1236 return false;
1237 break;
1238 case nir_instr_type_intrinsic:
1239 if (!visit_intrinsic_src(nir_instr_as_intrinsic(instr), cb, state))
1240 return false;
1241 break;
1242 case nir_instr_type_tex:
1243 if (!visit_tex_src(nir_instr_as_tex(instr), cb, state))
1244 return false;
1245 break;
1246 case nir_instr_type_call:
1247 if (!visit_call_src(nir_instr_as_call(instr), cb, state))
1248 return false;
1249 break;
1250 case nir_instr_type_load_const:
1251 /* Constant load instructions have no regular sources */
1252 break;
1253 case nir_instr_type_phi:
1254 if (!visit_phi_src(nir_instr_as_phi(instr), cb, state))
1255 return false;
1256 break;
1257 case nir_instr_type_parallel_copy:
1258 if (!visit_parallel_copy_src(nir_instr_as_parallel_copy(instr),
1259 cb, state))
1260 return false;
1261 break;
1262 case nir_instr_type_jump:
1263 return visit_jump_src(nir_instr_as_jump(instr), cb, state);
1264 case nir_instr_type_ssa_undef:
1265 return true;
1266
1267 default:
1268 unreachable("Invalid instruction type");
1269 break;
1270 }
1271
1272 visit_dest_indirect_state dest_state;
1273 dest_state.state = state;
1274 dest_state.cb = cb;
1275 return nir_foreach_dest(instr, visit_dest_indirect, &dest_state);
1276 }
1277
1278 bool
1279 nir_foreach_phi_src_leaving_block(nir_block *block,
1280 nir_foreach_src_cb cb,
1281 void *state)
1282 {
1283 for (unsigned i = 0; i < ARRAY_SIZE(block->successors); i++) {
1284 if (block->successors[i] == NULL)
1285 continue;
1286
1287 nir_foreach_instr(instr, block->successors[i]) {
1288 if (instr->type != nir_instr_type_phi)
1289 break;
1290
1291 nir_phi_instr *phi = nir_instr_as_phi(instr);
1292 nir_foreach_phi_src(phi_src, phi) {
1293 if (phi_src->pred == block) {
1294 if (!cb(&phi_src->src, state))
1295 return false;
1296 }
1297 }
1298 }
1299 }
1300
1301 return true;
1302 }
1303
1304 nir_const_value
1305 nir_const_value_for_float(double f, unsigned bit_size)
1306 {
1307 nir_const_value v;
1308 memset(&v, 0, sizeof(v));
1309
1310 switch (bit_size) {
1311 case 16:
1312 v.u16 = _mesa_float_to_half(f);
1313 break;
1314 case 32:
1315 v.f32 = f;
1316 break;
1317 case 64:
1318 v.f64 = f;
1319 break;
1320 default:
1321 unreachable("Invalid bit size");
1322 }
1323
1324 return v;
1325 }
1326
1327 double
1328 nir_const_value_as_float(nir_const_value value, unsigned bit_size)
1329 {
1330 switch (bit_size) {
1331 case 16: return _mesa_half_to_float(value.u16);
1332 case 32: return value.f32;
1333 case 64: return value.f64;
1334 default:
1335 unreachable("Invalid bit size");
1336 }
1337 }
1338
1339 nir_const_value *
1340 nir_src_as_const_value(nir_src src)
1341 {
1342 if (!src.is_ssa)
1343 return NULL;
1344
1345 if (src.ssa->parent_instr->type != nir_instr_type_load_const)
1346 return NULL;
1347
1348 nir_load_const_instr *load = nir_instr_as_load_const(src.ssa->parent_instr);
1349
1350 return load->value;
1351 }
1352
1353 /**
1354 * Returns true if the source is known to be dynamically uniform. Otherwise it
1355 * returns false which means it may or may not be dynamically uniform but it
1356 * can't be determined.
1357 */
1358 bool
1359 nir_src_is_dynamically_uniform(nir_src src)
1360 {
1361 if (!src.is_ssa)
1362 return false;
1363
1364 /* Constants are trivially dynamically uniform */
1365 if (src.ssa->parent_instr->type == nir_instr_type_load_const)
1366 return true;
1367
1368 /* As are uniform variables */
1369 if (src.ssa->parent_instr->type == nir_instr_type_intrinsic) {
1370 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(src.ssa->parent_instr);
1371 if (intr->intrinsic == nir_intrinsic_load_uniform &&
1372 nir_src_is_dynamically_uniform(intr->src[0]))
1373 return true;
1374 }
1375
1376 /* Operating together dynamically uniform expressions produces a
1377 * dynamically uniform result
1378 */
1379 if (src.ssa->parent_instr->type == nir_instr_type_alu) {
1380 nir_alu_instr *alu = nir_instr_as_alu(src.ssa->parent_instr);
1381 for (int i = 0; i < nir_op_infos[alu->op].num_inputs; i++) {
1382 if (!nir_src_is_dynamically_uniform(alu->src[i].src))
1383 return false;
1384 }
1385
1386 return true;
1387 }
1388
1389 /* XXX: this could have many more tests, such as when a sampler function is
1390 * called with dynamically uniform arguments.
1391 */
1392 return false;
1393 }
1394
1395 static void
1396 src_remove_all_uses(nir_src *src)
1397 {
1398 for (; src; src = src->is_ssa ? NULL : src->reg.indirect) {
1399 if (!src_is_valid(src))
1400 continue;
1401
1402 list_del(&src->use_link);
1403 }
1404 }
1405
1406 static void
1407 src_add_all_uses(nir_src *src, nir_instr *parent_instr, nir_if *parent_if)
1408 {
1409 for (; src; src = src->is_ssa ? NULL : src->reg.indirect) {
1410 if (!src_is_valid(src))
1411 continue;
1412
1413 if (parent_instr) {
1414 src->parent_instr = parent_instr;
1415 if (src->is_ssa)
1416 list_addtail(&src->use_link, &src->ssa->uses);
1417 else
1418 list_addtail(&src->use_link, &src->reg.reg->uses);
1419 } else {
1420 assert(parent_if);
1421 src->parent_if = parent_if;
1422 if (src->is_ssa)
1423 list_addtail(&src->use_link, &src->ssa->if_uses);
1424 else
1425 list_addtail(&src->use_link, &src->reg.reg->if_uses);
1426 }
1427 }
1428 }
1429
1430 void
1431 nir_instr_rewrite_src(nir_instr *instr, nir_src *src, nir_src new_src)
1432 {
1433 assert(!src_is_valid(src) || src->parent_instr == instr);
1434
1435 src_remove_all_uses(src);
1436 *src = new_src;
1437 src_add_all_uses(src, instr, NULL);
1438 }
1439
1440 void
1441 nir_instr_move_src(nir_instr *dest_instr, nir_src *dest, nir_src *src)
1442 {
1443 assert(!src_is_valid(dest) || dest->parent_instr == dest_instr);
1444
1445 src_remove_all_uses(dest);
1446 src_remove_all_uses(src);
1447 *dest = *src;
1448 *src = NIR_SRC_INIT;
1449 src_add_all_uses(dest, dest_instr, NULL);
1450 }
1451
1452 void
1453 nir_if_rewrite_condition(nir_if *if_stmt, nir_src new_src)
1454 {
1455 nir_src *src = &if_stmt->condition;
1456 assert(!src_is_valid(src) || src->parent_if == if_stmt);
1457
1458 src_remove_all_uses(src);
1459 *src = new_src;
1460 src_add_all_uses(src, NULL, if_stmt);
1461 }
1462
1463 void
1464 nir_instr_rewrite_dest(nir_instr *instr, nir_dest *dest, nir_dest new_dest)
1465 {
1466 if (dest->is_ssa) {
1467 /* We can only overwrite an SSA destination if it has no uses. */
1468 assert(list_is_empty(&dest->ssa.uses) && list_is_empty(&dest->ssa.if_uses));
1469 } else {
1470 list_del(&dest->reg.def_link);
1471 if (dest->reg.indirect)
1472 src_remove_all_uses(dest->reg.indirect);
1473 }
1474
1475 /* We can't re-write with an SSA def */
1476 assert(!new_dest.is_ssa);
1477
1478 nir_dest_copy(dest, &new_dest, instr);
1479
1480 dest->reg.parent_instr = instr;
1481 list_addtail(&dest->reg.def_link, &new_dest.reg.reg->defs);
1482
1483 if (dest->reg.indirect)
1484 src_add_all_uses(dest->reg.indirect, instr, NULL);
1485 }
1486
1487 /* note: does *not* take ownership of 'name' */
1488 void
1489 nir_ssa_def_init(nir_instr *instr, nir_ssa_def *def,
1490 unsigned num_components,
1491 unsigned bit_size, const char *name)
1492 {
1493 def->name = ralloc_strdup(instr, name);
1494 def->parent_instr = instr;
1495 list_inithead(&def->uses);
1496 list_inithead(&def->if_uses);
1497 def->num_components = num_components;
1498 def->bit_size = bit_size;
1499 def->divergent = true; /* This is the safer default */
1500
1501 if (instr->block) {
1502 nir_function_impl *impl =
1503 nir_cf_node_get_function(&instr->block->cf_node);
1504
1505 def->index = impl->ssa_alloc++;
1506 } else {
1507 def->index = UINT_MAX;
1508 }
1509 }
1510
1511 /* note: does *not* take ownership of 'name' */
1512 void
1513 nir_ssa_dest_init(nir_instr *instr, nir_dest *dest,
1514 unsigned num_components, unsigned bit_size,
1515 const char *name)
1516 {
1517 dest->is_ssa = true;
1518 nir_ssa_def_init(instr, &dest->ssa, num_components, bit_size, name);
1519 }
1520
1521 void
1522 nir_ssa_def_rewrite_uses(nir_ssa_def *def, nir_src new_src)
1523 {
1524 assert(!new_src.is_ssa || def != new_src.ssa);
1525
1526 nir_foreach_use_safe(use_src, def)
1527 nir_instr_rewrite_src(use_src->parent_instr, use_src, new_src);
1528
1529 nir_foreach_if_use_safe(use_src, def)
1530 nir_if_rewrite_condition(use_src->parent_if, new_src);
1531 }
1532
1533 static bool
1534 is_instr_between(nir_instr *start, nir_instr *end, nir_instr *between)
1535 {
1536 assert(start->block == end->block);
1537
1538 if (between->block != start->block)
1539 return false;
1540
1541 /* Search backwards looking for "between" */
1542 while (start != end) {
1543 if (between == end)
1544 return true;
1545
1546 end = nir_instr_prev(end);
1547 assert(end);
1548 }
1549
1550 return false;
1551 }
1552
1553 /* Replaces all uses of the given SSA def with the given source but only if
1554 * the use comes after the after_me instruction. This can be useful if you
1555 * are emitting code to fix up the result of some instruction: you can freely
1556 * use the result in that code and then call rewrite_uses_after and pass the
1557 * last fixup instruction as after_me and it will replace all of the uses you
1558 * want without touching the fixup code.
1559 *
1560 * This function assumes that after_me is in the same block as
1561 * def->parent_instr and that after_me comes after def->parent_instr.
1562 */
1563 void
1564 nir_ssa_def_rewrite_uses_after(nir_ssa_def *def, nir_src new_src,
1565 nir_instr *after_me)
1566 {
1567 if (new_src.is_ssa && def == new_src.ssa)
1568 return;
1569
1570 nir_foreach_use_safe(use_src, def) {
1571 assert(use_src->parent_instr != def->parent_instr);
1572 /* Since def already dominates all of its uses, the only way a use can
1573 * not be dominated by after_me is if it is between def and after_me in
1574 * the instruction list.
1575 */
1576 if (!is_instr_between(def->parent_instr, after_me, use_src->parent_instr))
1577 nir_instr_rewrite_src(use_src->parent_instr, use_src, new_src);
1578 }
1579
1580 nir_foreach_if_use_safe(use_src, def)
1581 nir_if_rewrite_condition(use_src->parent_if, new_src);
1582 }
1583
1584 nir_component_mask_t
1585 nir_ssa_def_components_read(const nir_ssa_def *def)
1586 {
1587 nir_component_mask_t read_mask = 0;
1588 nir_foreach_use(use, def) {
1589 if (use->parent_instr->type == nir_instr_type_alu) {
1590 nir_alu_instr *alu = nir_instr_as_alu(use->parent_instr);
1591 nir_alu_src *alu_src = exec_node_data(nir_alu_src, use, src);
1592 int src_idx = alu_src - &alu->src[0];
1593 assert(src_idx >= 0 && src_idx < nir_op_infos[alu->op].num_inputs);
1594 read_mask |= nir_alu_instr_src_read_mask(alu, src_idx);
1595 } else {
1596 return (1 << def->num_components) - 1;
1597 }
1598 }
1599
1600 if (!list_is_empty(&def->if_uses))
1601 read_mask |= 1;
1602
1603 return read_mask;
1604 }
1605
1606 nir_block *
1607 nir_block_unstructured_next(nir_block *block)
1608 {
1609 if (block == NULL) {
1610 /* nir_foreach_block_unstructured_safe() will call this function on a
1611 * NULL block after the last iteration, but it won't use the result so
1612 * just return NULL here.
1613 */
1614 return NULL;
1615 }
1616
1617 nir_cf_node *cf_next = nir_cf_node_next(&block->cf_node);
1618 if (cf_next == NULL && block->cf_node.parent->type == nir_cf_node_function)
1619 return NULL;
1620
1621 if (cf_next && cf_next->type == nir_cf_node_block)
1622 return nir_cf_node_as_block(cf_next);
1623
1624 return nir_block_cf_tree_next(block);
1625 }
1626
1627 nir_block *
1628 nir_unstructured_start_block(nir_function_impl *impl)
1629 {
1630 return nir_start_block(impl);
1631 }
1632
1633 nir_block *
1634 nir_block_cf_tree_next(nir_block *block)
1635 {
1636 if (block == NULL) {
1637 /* nir_foreach_block_safe() will call this function on a NULL block
1638 * after the last iteration, but it won't use the result so just return
1639 * NULL here.
1640 */
1641 return NULL;
1642 }
1643
1644 assert(nir_cf_node_get_function(&block->cf_node)->structured);
1645
1646 nir_cf_node *cf_next = nir_cf_node_next(&block->cf_node);
1647 if (cf_next)
1648 return nir_cf_node_cf_tree_first(cf_next);
1649
1650 nir_cf_node *parent = block->cf_node.parent;
1651
1652 switch (parent->type) {
1653 case nir_cf_node_if: {
1654 /* Are we at the end of the if? Go to the beginning of the else */
1655 nir_if *if_stmt = nir_cf_node_as_if(parent);
1656 if (block == nir_if_last_then_block(if_stmt))
1657 return nir_if_first_else_block(if_stmt);
1658
1659 assert(block == nir_if_last_else_block(if_stmt));
1660 }
1661 /* fallthrough */
1662
1663 case nir_cf_node_loop:
1664 return nir_cf_node_as_block(nir_cf_node_next(parent));
1665
1666 case nir_cf_node_function:
1667 return NULL;
1668
1669 default:
1670 unreachable("unknown cf node type");
1671 }
1672 }
1673
1674 nir_block *
1675 nir_block_cf_tree_prev(nir_block *block)
1676 {
1677 if (block == NULL) {
1678 /* do this for consistency with nir_block_cf_tree_next() */
1679 return NULL;
1680 }
1681
1682 assert(nir_cf_node_get_function(&block->cf_node)->structured);
1683
1684 nir_cf_node *cf_prev = nir_cf_node_prev(&block->cf_node);
1685 if (cf_prev)
1686 return nir_cf_node_cf_tree_last(cf_prev);
1687
1688 nir_cf_node *parent = block->cf_node.parent;
1689
1690 switch (parent->type) {
1691 case nir_cf_node_if: {
1692 /* Are we at the beginning of the else? Go to the end of the if */
1693 nir_if *if_stmt = nir_cf_node_as_if(parent);
1694 if (block == nir_if_first_else_block(if_stmt))
1695 return nir_if_last_then_block(if_stmt);
1696
1697 assert(block == nir_if_first_then_block(if_stmt));
1698 }
1699 /* fallthrough */
1700
1701 case nir_cf_node_loop:
1702 return nir_cf_node_as_block(nir_cf_node_prev(parent));
1703
1704 case nir_cf_node_function:
1705 return NULL;
1706
1707 default:
1708 unreachable("unknown cf node type");
1709 }
1710 }
1711
1712 nir_block *nir_cf_node_cf_tree_first(nir_cf_node *node)
1713 {
1714 switch (node->type) {
1715 case nir_cf_node_function: {
1716 nir_function_impl *impl = nir_cf_node_as_function(node);
1717 return nir_start_block(impl);
1718 }
1719
1720 case nir_cf_node_if: {
1721 nir_if *if_stmt = nir_cf_node_as_if(node);
1722 return nir_if_first_then_block(if_stmt);
1723 }
1724
1725 case nir_cf_node_loop: {
1726 nir_loop *loop = nir_cf_node_as_loop(node);
1727 return nir_loop_first_block(loop);
1728 }
1729
1730 case nir_cf_node_block: {
1731 return nir_cf_node_as_block(node);
1732 }
1733
1734 default:
1735 unreachable("unknown node type");
1736 }
1737 }
1738
1739 nir_block *nir_cf_node_cf_tree_last(nir_cf_node *node)
1740 {
1741 switch (node->type) {
1742 case nir_cf_node_function: {
1743 nir_function_impl *impl = nir_cf_node_as_function(node);
1744 return nir_impl_last_block(impl);
1745 }
1746
1747 case nir_cf_node_if: {
1748 nir_if *if_stmt = nir_cf_node_as_if(node);
1749 return nir_if_last_else_block(if_stmt);
1750 }
1751
1752 case nir_cf_node_loop: {
1753 nir_loop *loop = nir_cf_node_as_loop(node);
1754 return nir_loop_last_block(loop);
1755 }
1756
1757 case nir_cf_node_block: {
1758 return nir_cf_node_as_block(node);
1759 }
1760
1761 default:
1762 unreachable("unknown node type");
1763 }
1764 }
1765
1766 nir_block *nir_cf_node_cf_tree_next(nir_cf_node *node)
1767 {
1768 if (node->type == nir_cf_node_block)
1769 return nir_block_cf_tree_next(nir_cf_node_as_block(node));
1770 else if (node->type == nir_cf_node_function)
1771 return NULL;
1772 else
1773 return nir_cf_node_as_block(nir_cf_node_next(node));
1774 }
1775
1776 nir_if *
1777 nir_block_get_following_if(nir_block *block)
1778 {
1779 if (exec_node_is_tail_sentinel(&block->cf_node.node))
1780 return NULL;
1781
1782 if (nir_cf_node_is_last(&block->cf_node))
1783 return NULL;
1784
1785 nir_cf_node *next_node = nir_cf_node_next(&block->cf_node);
1786
1787 if (next_node->type != nir_cf_node_if)
1788 return NULL;
1789
1790 return nir_cf_node_as_if(next_node);
1791 }
1792
1793 nir_loop *
1794 nir_block_get_following_loop(nir_block *block)
1795 {
1796 if (exec_node_is_tail_sentinel(&block->cf_node.node))
1797 return NULL;
1798
1799 if (nir_cf_node_is_last(&block->cf_node))
1800 return NULL;
1801
1802 nir_cf_node *next_node = nir_cf_node_next(&block->cf_node);
1803
1804 if (next_node->type != nir_cf_node_loop)
1805 return NULL;
1806
1807 return nir_cf_node_as_loop(next_node);
1808 }
1809
1810 void
1811 nir_index_blocks(nir_function_impl *impl)
1812 {
1813 unsigned index = 0;
1814
1815 if (impl->valid_metadata & nir_metadata_block_index)
1816 return;
1817
1818 nir_foreach_block_unstructured(block, impl) {
1819 block->index = index++;
1820 }
1821
1822 /* The end_block isn't really part of the program, which is why its index
1823 * is >= num_blocks.
1824 */
1825 impl->num_blocks = impl->end_block->index = index;
1826 }
1827
1828 static bool
1829 index_ssa_def_cb(nir_ssa_def *def, void *state)
1830 {
1831 unsigned *index = (unsigned *) state;
1832 def->index = (*index)++;
1833
1834 return true;
1835 }
1836
1837 /**
1838 * The indices are applied top-to-bottom which has the very nice property
1839 * that, if A dominates B, then A->index <= B->index.
1840 */
1841 void
1842 nir_index_ssa_defs(nir_function_impl *impl)
1843 {
1844 unsigned index = 0;
1845
1846 nir_foreach_block_unstructured(block, impl) {
1847 nir_foreach_instr(instr, block)
1848 nir_foreach_ssa_def(instr, index_ssa_def_cb, &index);
1849 }
1850
1851 impl->ssa_alloc = index;
1852 }
1853
1854 /**
1855 * The indices are applied top-to-bottom which has the very nice property
1856 * that, if A dominates B, then A->index <= B->index.
1857 */
1858 unsigned
1859 nir_index_instrs(nir_function_impl *impl)
1860 {
1861 unsigned index = 0;
1862
1863 nir_foreach_block(block, impl) {
1864 nir_foreach_instr(instr, block)
1865 instr->index = index++;
1866 }
1867
1868 return index;
1869 }
1870
1871 unsigned
1872 nir_shader_index_vars(nir_shader *shader, nir_variable_mode modes)
1873 {
1874 unsigned count = 0;
1875 nir_foreach_variable_with_modes(var, shader, modes)
1876 var->index = count++;
1877 return count;
1878 }
1879
1880 unsigned
1881 nir_function_impl_index_vars(nir_function_impl *impl)
1882 {
1883 unsigned count = 0;
1884 nir_foreach_function_temp_variable(var, impl)
1885 var->index = count++;
1886 return count;
1887 }
1888
1889 static nir_instr *
1890 cursor_next_instr(nir_cursor cursor)
1891 {
1892 switch (cursor.option) {
1893 case nir_cursor_before_block:
1894 for (nir_block *block = cursor.block; block;
1895 block = nir_block_cf_tree_next(block)) {
1896 nir_instr *instr = nir_block_first_instr(block);
1897 if (instr)
1898 return instr;
1899 }
1900 return NULL;
1901
1902 case nir_cursor_after_block:
1903 cursor.block = nir_block_cf_tree_next(cursor.block);
1904 if (cursor.block == NULL)
1905 return NULL;
1906
1907 cursor.option = nir_cursor_before_block;
1908 return cursor_next_instr(cursor);
1909
1910 case nir_cursor_before_instr:
1911 return cursor.instr;
1912
1913 case nir_cursor_after_instr:
1914 if (nir_instr_next(cursor.instr))
1915 return nir_instr_next(cursor.instr);
1916
1917 cursor.option = nir_cursor_after_block;
1918 cursor.block = cursor.instr->block;
1919 return cursor_next_instr(cursor);
1920 }
1921
1922 unreachable("Inavlid cursor option");
1923 }
1924
1925 ASSERTED static bool
1926 dest_is_ssa(nir_dest *dest, void *_state)
1927 {
1928 (void) _state;
1929 return dest->is_ssa;
1930 }
1931
1932 bool
1933 nir_function_impl_lower_instructions(nir_function_impl *impl,
1934 nir_instr_filter_cb filter,
1935 nir_lower_instr_cb lower,
1936 void *cb_data)
1937 {
1938 nir_builder b;
1939 nir_builder_init(&b, impl);
1940
1941 nir_metadata preserved = nir_metadata_block_index |
1942 nir_metadata_dominance;
1943
1944 bool progress = false;
1945 nir_cursor iter = nir_before_cf_list(&impl->body);
1946 nir_instr *instr;
1947 while ((instr = cursor_next_instr(iter)) != NULL) {
1948 if (filter && !filter(instr, cb_data)) {
1949 iter = nir_after_instr(instr);
1950 continue;
1951 }
1952
1953 assert(nir_foreach_dest(instr, dest_is_ssa, NULL));
1954 nir_ssa_def *old_def = nir_instr_ssa_def(instr);
1955 if (old_def == NULL) {
1956 iter = nir_after_instr(instr);
1957 continue;
1958 }
1959
1960 /* We're about to ask the callback to generate a replacement for instr.
1961 * Save off the uses from instr's SSA def so we know what uses to
1962 * rewrite later. If we use nir_ssa_def_rewrite_uses, it fails in the
1963 * case where the generated replacement code uses the result of instr
1964 * itself. If we use nir_ssa_def_rewrite_uses_after (which is the
1965 * normal solution to this problem), it doesn't work well if control-
1966 * flow is inserted as part of the replacement, doesn't handle cases
1967 * where the replacement is something consumed by instr, and suffers
1968 * from performance issues. This is the only way to 100% guarantee
1969 * that we rewrite the correct set efficiently.
1970 */
1971 struct list_head old_uses, old_if_uses;
1972 list_replace(&old_def->uses, &old_uses);
1973 list_inithead(&old_def->uses);
1974 list_replace(&old_def->if_uses, &old_if_uses);
1975 list_inithead(&old_def->if_uses);
1976
1977 b.cursor = nir_after_instr(instr);
1978 nir_ssa_def *new_def = lower(&b, instr, cb_data);
1979 if (new_def && new_def != NIR_LOWER_INSTR_PROGRESS) {
1980 assert(old_def != NULL);
1981 if (new_def->parent_instr->block != instr->block)
1982 preserved = nir_metadata_none;
1983
1984 nir_src new_src = nir_src_for_ssa(new_def);
1985 list_for_each_entry_safe(nir_src, use_src, &old_uses, use_link)
1986 nir_instr_rewrite_src(use_src->parent_instr, use_src, new_src);
1987
1988 list_for_each_entry_safe(nir_src, use_src, &old_if_uses, use_link)
1989 nir_if_rewrite_condition(use_src->parent_if, new_src);
1990
1991 if (list_is_empty(&old_def->uses) && list_is_empty(&old_def->if_uses)) {
1992 iter = nir_instr_remove(instr);
1993 } else {
1994 iter = nir_after_instr(instr);
1995 }
1996 progress = true;
1997 } else {
1998 /* We didn't end up lowering after all. Put the uses back */
1999 if (old_def) {
2000 list_replace(&old_uses, &old_def->uses);
2001 list_replace(&old_if_uses, &old_def->if_uses);
2002 }
2003 iter = nir_after_instr(instr);
2004
2005 if (new_def == NIR_LOWER_INSTR_PROGRESS)
2006 progress = true;
2007 }
2008 }
2009
2010 if (progress) {
2011 nir_metadata_preserve(impl, preserved);
2012 } else {
2013 nir_metadata_preserve(impl, nir_metadata_all);
2014 }
2015
2016 return progress;
2017 }
2018
2019 bool
2020 nir_shader_lower_instructions(nir_shader *shader,
2021 nir_instr_filter_cb filter,
2022 nir_lower_instr_cb lower,
2023 void *cb_data)
2024 {
2025 bool progress = false;
2026
2027 nir_foreach_function(function, shader) {
2028 if (function->impl &&
2029 nir_function_impl_lower_instructions(function->impl,
2030 filter, lower, cb_data))
2031 progress = true;
2032 }
2033
2034 return progress;
2035 }
2036
2037 nir_intrinsic_op
2038 nir_intrinsic_from_system_value(gl_system_value val)
2039 {
2040 switch (val) {
2041 case SYSTEM_VALUE_VERTEX_ID:
2042 return nir_intrinsic_load_vertex_id;
2043 case SYSTEM_VALUE_INSTANCE_ID:
2044 return nir_intrinsic_load_instance_id;
2045 case SYSTEM_VALUE_DRAW_ID:
2046 return nir_intrinsic_load_draw_id;
2047 case SYSTEM_VALUE_BASE_INSTANCE:
2048 return nir_intrinsic_load_base_instance;
2049 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
2050 return nir_intrinsic_load_vertex_id_zero_base;
2051 case SYSTEM_VALUE_IS_INDEXED_DRAW:
2052 return nir_intrinsic_load_is_indexed_draw;
2053 case SYSTEM_VALUE_FIRST_VERTEX:
2054 return nir_intrinsic_load_first_vertex;
2055 case SYSTEM_VALUE_BASE_VERTEX:
2056 return nir_intrinsic_load_base_vertex;
2057 case SYSTEM_VALUE_INVOCATION_ID:
2058 return nir_intrinsic_load_invocation_id;
2059 case SYSTEM_VALUE_FRAG_COORD:
2060 return nir_intrinsic_load_frag_coord;
2061 case SYSTEM_VALUE_POINT_COORD:
2062 return nir_intrinsic_load_point_coord;
2063 case SYSTEM_VALUE_LINE_COORD:
2064 return nir_intrinsic_load_line_coord;
2065 case SYSTEM_VALUE_FRONT_FACE:
2066 return nir_intrinsic_load_front_face;
2067 case SYSTEM_VALUE_SAMPLE_ID:
2068 return nir_intrinsic_load_sample_id;
2069 case SYSTEM_VALUE_SAMPLE_POS:
2070 return nir_intrinsic_load_sample_pos;
2071 case SYSTEM_VALUE_SAMPLE_MASK_IN:
2072 return nir_intrinsic_load_sample_mask_in;
2073 case SYSTEM_VALUE_LOCAL_INVOCATION_ID:
2074 return nir_intrinsic_load_local_invocation_id;
2075 case SYSTEM_VALUE_LOCAL_INVOCATION_INDEX:
2076 return nir_intrinsic_load_local_invocation_index;
2077 case SYSTEM_VALUE_WORK_GROUP_ID:
2078 return nir_intrinsic_load_work_group_id;
2079 case SYSTEM_VALUE_NUM_WORK_GROUPS:
2080 return nir_intrinsic_load_num_work_groups;
2081 case SYSTEM_VALUE_PRIMITIVE_ID:
2082 return nir_intrinsic_load_primitive_id;
2083 case SYSTEM_VALUE_TESS_COORD:
2084 return nir_intrinsic_load_tess_coord;
2085 case SYSTEM_VALUE_TESS_LEVEL_OUTER:
2086 return nir_intrinsic_load_tess_level_outer;
2087 case SYSTEM_VALUE_TESS_LEVEL_INNER:
2088 return nir_intrinsic_load_tess_level_inner;
2089 case SYSTEM_VALUE_TESS_LEVEL_OUTER_DEFAULT:
2090 return nir_intrinsic_load_tess_level_outer_default;
2091 case SYSTEM_VALUE_TESS_LEVEL_INNER_DEFAULT:
2092 return nir_intrinsic_load_tess_level_inner_default;
2093 case SYSTEM_VALUE_VERTICES_IN:
2094 return nir_intrinsic_load_patch_vertices_in;
2095 case SYSTEM_VALUE_HELPER_INVOCATION:
2096 return nir_intrinsic_load_helper_invocation;
2097 case SYSTEM_VALUE_COLOR0:
2098 return nir_intrinsic_load_color0;
2099 case SYSTEM_VALUE_COLOR1:
2100 return nir_intrinsic_load_color1;
2101 case SYSTEM_VALUE_VIEW_INDEX:
2102 return nir_intrinsic_load_view_index;
2103 case SYSTEM_VALUE_SUBGROUP_SIZE:
2104 return nir_intrinsic_load_subgroup_size;
2105 case SYSTEM_VALUE_SUBGROUP_INVOCATION:
2106 return nir_intrinsic_load_subgroup_invocation;
2107 case SYSTEM_VALUE_SUBGROUP_EQ_MASK:
2108 return nir_intrinsic_load_subgroup_eq_mask;
2109 case SYSTEM_VALUE_SUBGROUP_GE_MASK:
2110 return nir_intrinsic_load_subgroup_ge_mask;
2111 case SYSTEM_VALUE_SUBGROUP_GT_MASK:
2112 return nir_intrinsic_load_subgroup_gt_mask;
2113 case SYSTEM_VALUE_SUBGROUP_LE_MASK:
2114 return nir_intrinsic_load_subgroup_le_mask;
2115 case SYSTEM_VALUE_SUBGROUP_LT_MASK:
2116 return nir_intrinsic_load_subgroup_lt_mask;
2117 case SYSTEM_VALUE_NUM_SUBGROUPS:
2118 return nir_intrinsic_load_num_subgroups;
2119 case SYSTEM_VALUE_SUBGROUP_ID:
2120 return nir_intrinsic_load_subgroup_id;
2121 case SYSTEM_VALUE_LOCAL_GROUP_SIZE:
2122 return nir_intrinsic_load_local_group_size;
2123 case SYSTEM_VALUE_GLOBAL_INVOCATION_ID:
2124 return nir_intrinsic_load_global_invocation_id;
2125 case SYSTEM_VALUE_GLOBAL_INVOCATION_INDEX:
2126 return nir_intrinsic_load_global_invocation_index;
2127 case SYSTEM_VALUE_WORK_DIM:
2128 return nir_intrinsic_load_work_dim;
2129 case SYSTEM_VALUE_USER_DATA_AMD:
2130 return nir_intrinsic_load_user_data_amd;
2131 default:
2132 unreachable("system value does not directly correspond to intrinsic");
2133 }
2134 }
2135
2136 gl_system_value
2137 nir_system_value_from_intrinsic(nir_intrinsic_op intrin)
2138 {
2139 switch (intrin) {
2140 case nir_intrinsic_load_vertex_id:
2141 return SYSTEM_VALUE_VERTEX_ID;
2142 case nir_intrinsic_load_instance_id:
2143 return SYSTEM_VALUE_INSTANCE_ID;
2144 case nir_intrinsic_load_draw_id:
2145 return SYSTEM_VALUE_DRAW_ID;
2146 case nir_intrinsic_load_base_instance:
2147 return SYSTEM_VALUE_BASE_INSTANCE;
2148 case nir_intrinsic_load_vertex_id_zero_base:
2149 return SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
2150 case nir_intrinsic_load_first_vertex:
2151 return SYSTEM_VALUE_FIRST_VERTEX;
2152 case nir_intrinsic_load_is_indexed_draw:
2153 return SYSTEM_VALUE_IS_INDEXED_DRAW;
2154 case nir_intrinsic_load_base_vertex:
2155 return SYSTEM_VALUE_BASE_VERTEX;
2156 case nir_intrinsic_load_invocation_id:
2157 return SYSTEM_VALUE_INVOCATION_ID;
2158 case nir_intrinsic_load_frag_coord:
2159 return SYSTEM_VALUE_FRAG_COORD;
2160 case nir_intrinsic_load_point_coord:
2161 return SYSTEM_VALUE_POINT_COORD;
2162 case nir_intrinsic_load_line_coord:
2163 return SYSTEM_VALUE_LINE_COORD;
2164 case nir_intrinsic_load_front_face:
2165 return SYSTEM_VALUE_FRONT_FACE;
2166 case nir_intrinsic_load_sample_id:
2167 return SYSTEM_VALUE_SAMPLE_ID;
2168 case nir_intrinsic_load_sample_pos:
2169 return SYSTEM_VALUE_SAMPLE_POS;
2170 case nir_intrinsic_load_sample_mask_in:
2171 return SYSTEM_VALUE_SAMPLE_MASK_IN;
2172 case nir_intrinsic_load_local_invocation_id:
2173 return SYSTEM_VALUE_LOCAL_INVOCATION_ID;
2174 case nir_intrinsic_load_local_invocation_index:
2175 return SYSTEM_VALUE_LOCAL_INVOCATION_INDEX;
2176 case nir_intrinsic_load_num_work_groups:
2177 return SYSTEM_VALUE_NUM_WORK_GROUPS;
2178 case nir_intrinsic_load_work_group_id:
2179 return SYSTEM_VALUE_WORK_GROUP_ID;
2180 case nir_intrinsic_load_primitive_id:
2181 return SYSTEM_VALUE_PRIMITIVE_ID;
2182 case nir_intrinsic_load_tess_coord:
2183 return SYSTEM_VALUE_TESS_COORD;
2184 case nir_intrinsic_load_tess_level_outer:
2185 return SYSTEM_VALUE_TESS_LEVEL_OUTER;
2186 case nir_intrinsic_load_tess_level_inner:
2187 return SYSTEM_VALUE_TESS_LEVEL_INNER;
2188 case nir_intrinsic_load_tess_level_outer_default:
2189 return SYSTEM_VALUE_TESS_LEVEL_OUTER_DEFAULT;
2190 case nir_intrinsic_load_tess_level_inner_default:
2191 return SYSTEM_VALUE_TESS_LEVEL_INNER_DEFAULT;
2192 case nir_intrinsic_load_patch_vertices_in:
2193 return SYSTEM_VALUE_VERTICES_IN;
2194 case nir_intrinsic_load_helper_invocation:
2195 return SYSTEM_VALUE_HELPER_INVOCATION;
2196 case nir_intrinsic_load_color0:
2197 return SYSTEM_VALUE_COLOR0;
2198 case nir_intrinsic_load_color1:
2199 return SYSTEM_VALUE_COLOR1;
2200 case nir_intrinsic_load_view_index:
2201 return SYSTEM_VALUE_VIEW_INDEX;
2202 case nir_intrinsic_load_subgroup_size:
2203 return SYSTEM_VALUE_SUBGROUP_SIZE;
2204 case nir_intrinsic_load_subgroup_invocation:
2205 return SYSTEM_VALUE_SUBGROUP_INVOCATION;
2206 case nir_intrinsic_load_subgroup_eq_mask:
2207 return SYSTEM_VALUE_SUBGROUP_EQ_MASK;
2208 case nir_intrinsic_load_subgroup_ge_mask:
2209 return SYSTEM_VALUE_SUBGROUP_GE_MASK;
2210 case nir_intrinsic_load_subgroup_gt_mask:
2211 return SYSTEM_VALUE_SUBGROUP_GT_MASK;
2212 case nir_intrinsic_load_subgroup_le_mask:
2213 return SYSTEM_VALUE_SUBGROUP_LE_MASK;
2214 case nir_intrinsic_load_subgroup_lt_mask:
2215 return SYSTEM_VALUE_SUBGROUP_LT_MASK;
2216 case nir_intrinsic_load_num_subgroups:
2217 return SYSTEM_VALUE_NUM_SUBGROUPS;
2218 case nir_intrinsic_load_subgroup_id:
2219 return SYSTEM_VALUE_SUBGROUP_ID;
2220 case nir_intrinsic_load_local_group_size:
2221 return SYSTEM_VALUE_LOCAL_GROUP_SIZE;
2222 case nir_intrinsic_load_global_invocation_id:
2223 return SYSTEM_VALUE_GLOBAL_INVOCATION_ID;
2224 case nir_intrinsic_load_user_data_amd:
2225 return SYSTEM_VALUE_USER_DATA_AMD;
2226 default:
2227 unreachable("intrinsic doesn't produce a system value");
2228 }
2229 }
2230
2231 /* OpenGL utility method that remaps the location attributes if they are
2232 * doubles. Not needed for vulkan due the differences on the input location
2233 * count for doubles on vulkan vs OpenGL
2234 *
2235 * The bitfield returned in dual_slot is one bit for each double input slot in
2236 * the original OpenGL single-slot input numbering. The mapping from old
2237 * locations to new locations is as follows:
2238 *
2239 * new_loc = loc + util_bitcount(dual_slot & BITFIELD64_MASK(loc))
2240 */
2241 void
2242 nir_remap_dual_slot_attributes(nir_shader *shader, uint64_t *dual_slot)
2243 {
2244 assert(shader->info.stage == MESA_SHADER_VERTEX);
2245
2246 *dual_slot = 0;
2247 nir_foreach_shader_in_variable(var, shader) {
2248 if (glsl_type_is_dual_slot(glsl_without_array(var->type))) {
2249 unsigned slots = glsl_count_attribute_slots(var->type, true);
2250 *dual_slot |= BITFIELD64_MASK(slots) << var->data.location;
2251 }
2252 }
2253
2254 nir_foreach_shader_in_variable(var, shader) {
2255 var->data.location +=
2256 util_bitcount64(*dual_slot & BITFIELD64_MASK(var->data.location));
2257 }
2258 }
2259
2260 /* Returns an attribute mask that has been re-compacted using the given
2261 * dual_slot mask.
2262 */
2263 uint64_t
2264 nir_get_single_slot_attribs_mask(uint64_t attribs, uint64_t dual_slot)
2265 {
2266 while (dual_slot) {
2267 unsigned loc = u_bit_scan64(&dual_slot);
2268 /* mask of all bits up to and including loc */
2269 uint64_t mask = BITFIELD64_MASK(loc + 1);
2270 attribs = (attribs & mask) | ((attribs & ~mask) >> 1);
2271 }
2272 return attribs;
2273 }
2274
2275 void
2276 nir_rewrite_image_intrinsic(nir_intrinsic_instr *intrin, nir_ssa_def *src,
2277 bool bindless)
2278 {
2279 enum gl_access_qualifier access = nir_intrinsic_access(intrin);
2280
2281 switch (intrin->intrinsic) {
2282 #define CASE(op) \
2283 case nir_intrinsic_image_deref_##op: \
2284 intrin->intrinsic = bindless ? nir_intrinsic_bindless_image_##op \
2285 : nir_intrinsic_image_##op; \
2286 break;
2287 CASE(load)
2288 CASE(store)
2289 CASE(atomic_add)
2290 CASE(atomic_imin)
2291 CASE(atomic_umin)
2292 CASE(atomic_imax)
2293 CASE(atomic_umax)
2294 CASE(atomic_and)
2295 CASE(atomic_or)
2296 CASE(atomic_xor)
2297 CASE(atomic_exchange)
2298 CASE(atomic_comp_swap)
2299 CASE(atomic_fadd)
2300 CASE(atomic_inc_wrap)
2301 CASE(atomic_dec_wrap)
2302 CASE(size)
2303 CASE(samples)
2304 CASE(load_raw_intel)
2305 CASE(store_raw_intel)
2306 #undef CASE
2307 default:
2308 unreachable("Unhanded image intrinsic");
2309 }
2310
2311 nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);
2312 nir_variable *var = nir_deref_instr_get_variable(deref);
2313
2314 nir_intrinsic_set_image_dim(intrin, glsl_get_sampler_dim(deref->type));
2315 nir_intrinsic_set_image_array(intrin, glsl_sampler_type_is_array(deref->type));
2316 nir_intrinsic_set_access(intrin, access | var->data.access);
2317 nir_intrinsic_set_format(intrin, var->data.image.format);
2318
2319 nir_instr_rewrite_src(&intrin->instr, &intrin->src[0],
2320 nir_src_for_ssa(src));
2321 }
2322
2323 unsigned
2324 nir_image_intrinsic_coord_components(const nir_intrinsic_instr *instr)
2325 {
2326 enum glsl_sampler_dim dim = nir_intrinsic_image_dim(instr);
2327 int coords = glsl_get_sampler_dim_coordinate_components(dim);
2328 if (dim == GLSL_SAMPLER_DIM_CUBE)
2329 return coords;
2330 else
2331 return coords + nir_intrinsic_image_array(instr);
2332 }