src/compiler/nir/nir.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Connor Abbott (cwabbott0@gmail.com)
  25  *
  26  */
  27
  28 #include "nir.h"
  29 #include "nir_control_flow_private.h"
  30 #include "util/half_float.h"
  31 #include <limits.h>
  32 #include <assert.h>
  33 #include <math.h>
  34
  35 nir_shader *
  36 nir_shader_create(void *mem_ctx,
  37                   gl_shader_stage stage,
  38                   const nir_shader_compiler_options *options,
  39                   shader_info *si)
  40 {
  41    nir_shader *shader = rzalloc(mem_ctx, nir_shader);
  42
  43    exec_list_make_empty(&shader->uniforms);
  44    exec_list_make_empty(&shader->inputs);
  45    exec_list_make_empty(&shader->outputs);
  46    exec_list_make_empty(&shader->shared);
  47
  48    shader->options = options;
  49
  50    if (si) {
  51       assert(si->stage == stage);
  52       shader->info = *si;
  53    } else {
  54       shader->info.stage = stage;
  55    }
  56
  57    exec_list_make_empty(&shader->functions);
  58    exec_list_make_empty(&shader->registers);
  59    exec_list_make_empty(&shader->globals);
  60    exec_list_make_empty(&shader->system_values);
  61    shader->reg_alloc = 0;
  62
  63    shader->num_inputs = 0;
  64    shader->num_outputs = 0;
  65    shader->num_uniforms = 0;
  66    shader->num_shared = 0;
  67
  68    return shader;
  69 }
  70
  71 static nir_register *
  72 reg_create(void *mem_ctx, struct exec_list *list)
  73 {
  74    nir_register *reg = ralloc(mem_ctx, nir_register);
  75
  76    list_inithead(&reg->uses);
  77    list_inithead(&reg->defs);
  78    list_inithead(&reg->if_uses);
  79
  80    reg->num_components = 0;
  81    reg->bit_size = 32;
  82    reg->num_array_elems = 0;
  83    reg->is_packed = false;
  84    reg->name = NULL;
  85
  86    exec_list_push_tail(list, &reg->node);
  87
  88    return reg;
  89 }
  90
  91 nir_register *
  92 nir_global_reg_create(nir_shader *shader)
  93 {
  94    nir_register *reg = reg_create(shader, &shader->registers);
  95    reg->index = shader->reg_alloc++;
  96    reg->is_global = true;
  97
  98    return reg;
  99 }
 100
 101 nir_register *
 102 nir_local_reg_create(nir_function_impl *impl)
 103 {
 104    nir_register *reg = reg_create(ralloc_parent(impl), &impl->registers);
 105    reg->index = impl->reg_alloc++;
 106    reg->is_global = false;
 107
 108    return reg;
 109 }
 110
 111 void
 112 nir_reg_remove(nir_register *reg)
 113 {
 114    exec_node_remove(&reg->node);
 115 }
 116
 117 void
 118 nir_shader_add_variable(nir_shader *shader, nir_variable *var)
 119 {
 120    switch (var->data.mode) {
 121    case nir_var_all:
 122       assert(!"invalid mode");
 123       break;
 124
 125    case nir_var_local:
 126       assert(!"nir_shader_add_variable cannot be used for local variables");
 127       break;
 128
 129    case nir_var_global:
 130       exec_list_push_tail(&shader->globals, &var->node);
 131       break;
 132
 133    case nir_var_shader_in:
 134       exec_list_push_tail(&shader->inputs, &var->node);
 135       break;
 136
 137    case nir_var_shader_out:
 138       exec_list_push_tail(&shader->outputs, &var->node);
 139       break;
 140
 141    case nir_var_uniform:
 142    case nir_var_shader_storage:
 143       exec_list_push_tail(&shader->uniforms, &var->node);
 144       break;
 145
 146    case nir_var_shared:
 147       assert(shader->info.stage == MESA_SHADER_COMPUTE);
 148       exec_list_push_tail(&shader->shared, &var->node);
 149       break;
 150
 151    case nir_var_system_value:
 152       exec_list_push_tail(&shader->system_values, &var->node);
 153       break;
 154    }
 155 }
 156
 157 nir_variable *
 158 nir_variable_create(nir_shader *shader, nir_variable_mode mode,
 159                     const struct glsl_type *type, const char *name)
 160 {
 161    nir_variable *var = rzalloc(shader, nir_variable);
 162    var->name = ralloc_strdup(var, name);
 163    var->type = type;
 164    var->data.mode = mode;
 165
 166    if ((mode == nir_var_shader_in &&
 167         shader->info.stage != MESA_SHADER_VERTEX) ||
 168        (mode == nir_var_shader_out &&
 169         shader->info.stage != MESA_SHADER_FRAGMENT))
 170       var->data.interpolation = INTERP_MODE_SMOOTH;
 171
 172    if (mode == nir_var_shader_in || mode == nir_var_uniform)
 173       var->data.read_only = true;
 174
 175    nir_shader_add_variable(shader, var);
 176
 177    return var;
 178 }
 179
 180 nir_variable *
 181 nir_local_variable_create(nir_function_impl *impl,
 182                           const struct glsl_type *type, const char *name)
 183 {
 184    nir_variable *var = rzalloc(impl->function->shader, nir_variable);
 185    var->name = ralloc_strdup(var, name);
 186    var->type = type;
 187    var->data.mode = nir_var_local;
 188
 189    nir_function_impl_add_variable(impl, var);
 190
 191    return var;
 192 }
 193
 194 nir_function *
 195 nir_function_create(nir_shader *shader, const char *name)
 196 {
 197    nir_function *func = ralloc(shader, nir_function);
 198
 199    exec_list_push_tail(&shader->functions, &func->node);
 200
 201    func->name = ralloc_strdup(func, name);
 202    func->shader = shader;
 203    func->num_params = 0;
 204    func->params = NULL;
 205    func->impl = NULL;
 206
 207    return func;
 208 }
 209
 210 /* NOTE: if the instruction you are copying a src to is already added
 211  * to the IR, use nir_instr_rewrite_src() instead.
 212  */
 213 void nir_src_copy(nir_src *dest, const nir_src *src, void *mem_ctx)
 214 {
 215    dest->is_ssa = src->is_ssa;
 216    if (src->is_ssa) {
 217       dest->ssa = src->ssa;
 218    } else {
 219       dest->reg.base_offset = src->reg.base_offset;
 220       dest->reg.reg = src->reg.reg;
 221       if (src->reg.indirect) {
 222          dest->reg.indirect = ralloc(mem_ctx, nir_src);
 223          nir_src_copy(dest->reg.indirect, src->reg.indirect, mem_ctx);
 224       } else {
 225          dest->reg.indirect = NULL;
 226       }
 227    }
 228 }
 229
 230 void nir_dest_copy(nir_dest *dest, const nir_dest *src, nir_instr *instr)
 231 {
 232    /* Copying an SSA definition makes no sense whatsoever. */
 233    assert(!src->is_ssa);
 234
 235    dest->is_ssa = false;
 236
 237    dest->reg.base_offset = src->reg.base_offset;
 238    dest->reg.reg = src->reg.reg;
 239    if (src->reg.indirect) {
 240       dest->reg.indirect = ralloc(instr, nir_src);
 241       nir_src_copy(dest->reg.indirect, src->reg.indirect, instr);
 242    } else {
 243       dest->reg.indirect = NULL;
 244    }
 245 }
 246
 247 void
 248 nir_alu_src_copy(nir_alu_src *dest, const nir_alu_src *src,
 249                  nir_alu_instr *instr)
 250 {
 251    nir_src_copy(&dest->src, &src->src, &instr->instr);
 252    dest->abs = src->abs;
 253    dest->negate = src->negate;
 254    for (unsigned i = 0; i < 4; i++)
 255       dest->swizzle[i] = src->swizzle[i];
 256 }
 257
 258 void
 259 nir_alu_dest_copy(nir_alu_dest *dest, const nir_alu_dest *src,
 260                   nir_alu_instr *instr)
 261 {
 262    nir_dest_copy(&dest->dest, &src->dest, &instr->instr);
 263    dest->write_mask = src->write_mask;
 264    dest->saturate = src->saturate;
 265 }
 266
 267
 268 static void
 269 cf_init(nir_cf_node *node, nir_cf_node_type type)
 270 {
 271    exec_node_init(&node->node);
 272    node->parent = NULL;
 273    node->type = type;
 274 }
 275
 276 nir_function_impl *
 277 nir_function_impl_create_bare(nir_shader *shader)
 278 {
 279    nir_function_impl *impl = ralloc(shader, nir_function_impl);
 280
 281    impl->function = NULL;
 282
 283    cf_init(&impl->cf_node, nir_cf_node_function);
 284
 285    exec_list_make_empty(&impl->body);
 286    exec_list_make_empty(&impl->registers);
 287    exec_list_make_empty(&impl->locals);
 288    impl->reg_alloc = 0;
 289    impl->ssa_alloc = 0;
 290    impl->valid_metadata = nir_metadata_none;
 291
 292    /* create start & end blocks */
 293    nir_block *start_block = nir_block_create(shader);
 294    nir_block *end_block = nir_block_create(shader);
 295    start_block->cf_node.parent = &impl->cf_node;
 296    end_block->cf_node.parent = &impl->cf_node;
 297    impl->end_block = end_block;
 298
 299    exec_list_push_tail(&impl->body, &start_block->cf_node.node);
 300
 301    start_block->successors[0] = end_block;
 302    _mesa_set_add(end_block->predecessors, start_block);
 303    return impl;
 304 }
 305
 306 nir_function_impl *
 307 nir_function_impl_create(nir_function *function)
 308 {
 309    assert(function->impl == NULL);
 310
 311    nir_function_impl *impl = nir_function_impl_create_bare(function->shader);
 312
 313    function->impl = impl;
 314    impl->function = function;
 315
 316    return impl;
 317 }
 318
 319 nir_block *
 320 nir_block_create(nir_shader *shader)
 321 {
 322    nir_block *block = rzalloc(shader, nir_block);
 323
 324    cf_init(&block->cf_node, nir_cf_node_block);
 325
 326    block->successors[0] = block->successors[1] = NULL;
 327    block->predecessors = _mesa_set_create(block, _mesa_hash_pointer,
 328                                           _mesa_key_pointer_equal);
 329    block->imm_dom = NULL;
 330    /* XXX maybe it would be worth it to defer allocation?  This
 331     * way it doesn't get allocated for shader refs that never run
 332     * nir_calc_dominance?  For example, state-tracker creates an
 333     * initial IR, clones that, runs appropriate lowering pass, passes
 334     * to driver which does common lowering/opt, and then stores ref
 335     * which is later used to do state specific lowering and futher
 336     * opt.  Do any of the references not need dominance metadata?
 337     */
 338    block->dom_frontier = _mesa_set_create(block, _mesa_hash_pointer,
 339                                           _mesa_key_pointer_equal);
 340
 341    exec_list_make_empty(&block->instr_list);
 342
 343    return block;
 344 }
 345
 346 static inline void
 347 src_init(nir_src *src)
 348 {
 349    src->is_ssa = false;
 350    src->reg.reg = NULL;
 351    src->reg.indirect = NULL;
 352    src->reg.base_offset = 0;
 353 }
 354
 355 nir_if *
 356 nir_if_create(nir_shader *shader)
 357 {
 358    nir_if *if_stmt = ralloc(shader, nir_if);
 359
 360    cf_init(&if_stmt->cf_node, nir_cf_node_if);
 361    src_init(&if_stmt->condition);
 362
 363    nir_block *then = nir_block_create(shader);
 364    exec_list_make_empty(&if_stmt->then_list);
 365    exec_list_push_tail(&if_stmt->then_list, &then->cf_node.node);
 366    then->cf_node.parent = &if_stmt->cf_node;
 367
 368    nir_block *else_stmt = nir_block_create(shader);
 369    exec_list_make_empty(&if_stmt->else_list);
 370    exec_list_push_tail(&if_stmt->else_list, &else_stmt->cf_node.node);
 371    else_stmt->cf_node.parent = &if_stmt->cf_node;
 372
 373    return if_stmt;
 374 }
 375
 376 nir_loop *
 377 nir_loop_create(nir_shader *shader)
 378 {
 379    nir_loop *loop = rzalloc(shader, nir_loop);
 380
 381    cf_init(&loop->cf_node, nir_cf_node_loop);
 382
 383    nir_block *body = nir_block_create(shader);
 384    exec_list_make_empty(&loop->body);
 385    exec_list_push_tail(&loop->body, &body->cf_node.node);
 386    body->cf_node.parent = &loop->cf_node;
 387
 388    body->successors[0] = body;
 389    _mesa_set_add(body->predecessors, body);
 390
 391    return loop;
 392 }
 393
 394 static void
 395 instr_init(nir_instr *instr, nir_instr_type type)
 396 {
 397    instr->type = type;
 398    instr->block = NULL;
 399    exec_node_init(&instr->node);
 400 }
 401
 402 static void
 403 dest_init(nir_dest *dest)
 404 {
 405    dest->is_ssa = false;
 406    dest->reg.reg = NULL;
 407    dest->reg.indirect = NULL;
 408    dest->reg.base_offset = 0;
 409 }
 410
 411 static void
 412 alu_dest_init(nir_alu_dest *dest)
 413 {
 414    dest_init(&dest->dest);
 415    dest->saturate = false;
 416    dest->write_mask = 0xf;
 417 }
 418
 419 static void
 420 alu_src_init(nir_alu_src *src)
 421 {
 422    src_init(&src->src);
 423    src->abs = src->negate = false;
 424    src->swizzle[0] = 0;
 425    src->swizzle[1] = 1;
 426    src->swizzle[2] = 2;
 427    src->swizzle[3] = 3;
 428 }
 429
 430 nir_alu_instr *
 431 nir_alu_instr_create(nir_shader *shader, nir_op op)
 432 {
 433    unsigned num_srcs = nir_op_infos[op].num_inputs;
 434    /* TODO: don't use rzalloc */
 435    nir_alu_instr *instr =
 436       rzalloc_size(shader,
 437                    sizeof(nir_alu_instr) + num_srcs * sizeof(nir_alu_src));
 438
 439    instr_init(&instr->instr, nir_instr_type_alu);
 440    instr->op = op;
 441    alu_dest_init(&instr->dest);
 442    for (unsigned i = 0; i < num_srcs; i++)
 443       alu_src_init(&instr->src[i]);
 444
 445    return instr;
 446 }
 447
 448 nir_deref_instr *
 449 nir_deref_instr_create(nir_shader *shader, nir_deref_type deref_type)
 450 {
 451    nir_deref_instr *instr =
 452       rzalloc_size(shader, sizeof(nir_deref_instr));
 453
 454    instr_init(&instr->instr, nir_instr_type_deref);
 455
 456    instr->deref_type = deref_type;
 457    if (deref_type != nir_deref_type_var)
 458       src_init(&instr->parent);
 459
 460    if (deref_type == nir_deref_type_array)
 461       src_init(&instr->arr.index);
 462
 463    dest_init(&instr->dest);
 464
 465    return instr;
 466 }
 467
 468 nir_jump_instr *
 469 nir_jump_instr_create(nir_shader *shader, nir_jump_type type)
 470 {
 471    nir_jump_instr *instr = ralloc(shader, nir_jump_instr);
 472    instr_init(&instr->instr, nir_instr_type_jump);
 473    instr->type = type;
 474    return instr;
 475 }
 476
 477 nir_load_const_instr *
 478 nir_load_const_instr_create(nir_shader *shader, unsigned num_components,
 479                             unsigned bit_size)
 480 {
 481    nir_load_const_instr *instr = rzalloc(shader, nir_load_const_instr);
 482    instr_init(&instr->instr, nir_instr_type_load_const);
 483
 484    nir_ssa_def_init(&instr->instr, &instr->def, num_components, bit_size, NULL);
 485
 486    return instr;
 487 }
 488
 489 nir_intrinsic_instr *
 490 nir_intrinsic_instr_create(nir_shader *shader, nir_intrinsic_op op)
 491 {
 492    unsigned num_srcs = nir_intrinsic_infos[op].num_srcs;
 493    /* TODO: don't use rzalloc */
 494    nir_intrinsic_instr *instr =
 495       rzalloc_size(shader,
 496                   sizeof(nir_intrinsic_instr) + num_srcs * sizeof(nir_src));
 497
 498    instr_init(&instr->instr, nir_instr_type_intrinsic);
 499    instr->intrinsic = op;
 500
 501    if (nir_intrinsic_infos[op].has_dest)
 502       dest_init(&instr->dest);
 503
 504    for (unsigned i = 0; i < num_srcs; i++)
 505       src_init(&instr->src[i]);
 506
 507    return instr;
 508 }
 509
 510 nir_call_instr *
 511 nir_call_instr_create(nir_shader *shader, nir_function *callee)
 512 {
 513    const unsigned num_params = callee->num_params;
 514    nir_call_instr *instr =
 515       rzalloc_size(shader, sizeof(*instr) +
 516                    num_params * sizeof(instr->params[0]));
 517
 518    instr_init(&instr->instr, nir_instr_type_call);
 519    instr->callee = callee;
 520    instr->num_params = num_params;
 521    for (unsigned i = 0; i < num_params; i++)
 522       src_init(&instr->params[i]);
 523
 524    return instr;
 525 }
 526
 527 nir_tex_instr *
 528 nir_tex_instr_create(nir_shader *shader, unsigned num_srcs)
 529 {
 530    nir_tex_instr *instr = rzalloc(shader, nir_tex_instr);
 531    instr_init(&instr->instr, nir_instr_type_tex);
 532
 533    dest_init(&instr->dest);
 534
 535    instr->num_srcs = num_srcs;
 536    instr->src = ralloc_array(instr, nir_tex_src, num_srcs);
 537    for (unsigned i = 0; i < num_srcs; i++)
 538       src_init(&instr->src[i].src);
 539
 540    instr->texture_index = 0;
 541    instr->texture_array_size = 0;
 542    instr->sampler_index = 0;
 543
 544    return instr;
 545 }
 546
 547 void
 548 nir_tex_instr_add_src(nir_tex_instr *tex,
 549                       nir_tex_src_type src_type,
 550                       nir_src src)
 551 {
 552    nir_tex_src *new_srcs = rzalloc_array(tex, nir_tex_src,
 553                                          tex->num_srcs + 1);
 554
 555    for (unsigned i = 0; i < tex->num_srcs; i++) {
 556       new_srcs[i].src_type = tex->src[i].src_type;
 557       nir_instr_move_src(&tex->instr, &new_srcs[i].src,
 558                          &tex->src[i].src);
 559    }
 560
 561    ralloc_free(tex->src);
 562    tex->src = new_srcs;
 563
 564    tex->src[tex->num_srcs].src_type = src_type;
 565    nir_instr_rewrite_src(&tex->instr, &tex->src[tex->num_srcs].src, src);
 566    tex->num_srcs++;
 567 }
 568
 569 void
 570 nir_tex_instr_remove_src(nir_tex_instr *tex, unsigned src_idx)
 571 {
 572    assert(src_idx < tex->num_srcs);
 573
 574    /* First rewrite the source to NIR_SRC_INIT */
 575    nir_instr_rewrite_src(&tex->instr, &tex->src[src_idx].src, NIR_SRC_INIT);
 576
 577    /* Now, move all of the other sources down */
 578    for (unsigned i = src_idx + 1; i < tex->num_srcs; i++) {
 579       tex->src[i-1].src_type = tex->src[i].src_type;
 580       nir_instr_move_src(&tex->instr, &tex->src[i-1].src, &tex->src[i].src);
 581    }
 582    tex->num_srcs--;
 583 }
 584
 585 nir_phi_instr *
 586 nir_phi_instr_create(nir_shader *shader)
 587 {
 588    nir_phi_instr *instr = ralloc(shader, nir_phi_instr);
 589    instr_init(&instr->instr, nir_instr_type_phi);
 590
 591    dest_init(&instr->dest);
 592    exec_list_make_empty(&instr->srcs);
 593    return instr;
 594 }
 595
 596 nir_parallel_copy_instr *
 597 nir_parallel_copy_instr_create(nir_shader *shader)
 598 {
 599    nir_parallel_copy_instr *instr = ralloc(shader, nir_parallel_copy_instr);
 600    instr_init(&instr->instr, nir_instr_type_parallel_copy);
 601
 602    exec_list_make_empty(&instr->entries);
 603
 604    return instr;
 605 }
 606
 607 nir_ssa_undef_instr *
 608 nir_ssa_undef_instr_create(nir_shader *shader,
 609                            unsigned num_components,
 610                            unsigned bit_size)
 611 {
 612    nir_ssa_undef_instr *instr = ralloc(shader, nir_ssa_undef_instr);
 613    instr_init(&instr->instr, nir_instr_type_ssa_undef);
 614
 615    nir_ssa_def_init(&instr->instr, &instr->def, num_components, bit_size, NULL);
 616
 617    return instr;
 618 }
 619
 620 static nir_const_value
 621 const_value_float(double d, unsigned bit_size)
 622 {
 623    nir_const_value v;
 624    switch (bit_size) {
 625    case 16: v.u16[0] = _mesa_float_to_half(d);  break;
 626    case 32: v.f32[0] = d;                       break;
 627    case 64: v.f64[0] = d;                       break;
 628    default:
 629       unreachable("Invalid bit size");
 630    }
 631    return v;
 632 }
 633
 634 static nir_const_value
 635 const_value_int(int64_t i, unsigned bit_size)
 636 {
 637    nir_const_value v;
 638    switch (bit_size) {
 639    case 8:  v.i8[0]  = i;  break;
 640    case 16: v.i16[0] = i;  break;
 641    case 32: v.i32[0] = i;  break;
 642    case 64: v.i64[0] = i;  break;
 643    default:
 644       unreachable("Invalid bit size");
 645    }
 646    return v;
 647 }
 648
 649 nir_const_value
 650 nir_alu_binop_identity(nir_op binop, unsigned bit_size)
 651 {
 652    const int64_t max_int = (1ull << (bit_size - 1)) - 1;
 653    const int64_t min_int = -max_int - 1;
 654    switch (binop) {
 655    case nir_op_iadd:
 656       return const_value_int(0, bit_size);
 657    case nir_op_fadd:
 658       return const_value_float(0, bit_size);
 659    case nir_op_imul:
 660       return const_value_int(1, bit_size);
 661    case nir_op_fmul:
 662       return const_value_float(1, bit_size);
 663    case nir_op_imin:
 664       return const_value_int(max_int, bit_size);
 665    case nir_op_umin:
 666       return const_value_int(~0ull, bit_size);
 667    case nir_op_fmin:
 668       return const_value_float(INFINITY, bit_size);
 669    case nir_op_imax:
 670       return const_value_int(min_int, bit_size);
 671    case nir_op_umax:
 672       return const_value_int(0, bit_size);
 673    case nir_op_fmax:
 674       return const_value_float(-INFINITY, bit_size);
 675    case nir_op_iand:
 676       return const_value_int(~0ull, bit_size);
 677    case nir_op_ior:
 678       return const_value_int(0, bit_size);
 679    case nir_op_ixor:
 680       return const_value_int(0, bit_size);
 681    default:
 682       unreachable("Invalid reduction operation");
 683    }
 684 }
 685
 686 nir_function_impl *
 687 nir_cf_node_get_function(nir_cf_node *node)
 688 {
 689    while (node->type != nir_cf_node_function) {
 690       node = node->parent;
 691    }
 692
 693    return nir_cf_node_as_function(node);
 694 }
 695
 696 /* Reduces a cursor by trying to convert everything to after and trying to
 697  * go up to block granularity when possible.
 698  */
 699 static nir_cursor
 700 reduce_cursor(nir_cursor cursor)
 701 {
 702    switch (cursor.option) {
 703    case nir_cursor_before_block:
 704       assert(nir_cf_node_prev(&cursor.block->cf_node) == NULL ||
 705              nir_cf_node_prev(&cursor.block->cf_node)->type != nir_cf_node_block);
 706       if (exec_list_is_empty(&cursor.block->instr_list)) {
 707          /* Empty block.  After is as good as before. */
 708          cursor.option = nir_cursor_after_block;
 709       }
 710       return cursor;
 711
 712    case nir_cursor_after_block:
 713       return cursor;
 714
 715    case nir_cursor_before_instr: {
 716       nir_instr *prev_instr = nir_instr_prev(cursor.instr);
 717       if (prev_instr) {
 718          /* Before this instruction is after the previous */
 719          cursor.instr = prev_instr;
 720          cursor.option = nir_cursor_after_instr;
 721       } else {
 722          /* No previous instruction.  Switch to before block */
 723          cursor.block = cursor.instr->block;
 724          cursor.option = nir_cursor_before_block;
 725       }
 726       return reduce_cursor(cursor);
 727    }
 728
 729    case nir_cursor_after_instr:
 730       if (nir_instr_next(cursor.instr) == NULL) {
 731          /* This is the last instruction, switch to after block */
 732          cursor.option = nir_cursor_after_block;
 733          cursor.block = cursor.instr->block;
 734       }
 735       return cursor;
 736
 737    default:
 738       unreachable("Inavlid cursor option");
 739    }
 740 }
 741
 742 bool
 743 nir_cursors_equal(nir_cursor a, nir_cursor b)
 744 {
 745    /* Reduced cursors should be unique */
 746    a = reduce_cursor(a);
 747    b = reduce_cursor(b);
 748
 749    return a.block == b.block && a.option == b.option;
 750 }
 751
 752 static bool
 753 add_use_cb(nir_src *src, void *state)
 754 {
 755    nir_instr *instr = state;
 756
 757    src->parent_instr = instr;
 758    list_addtail(&src->use_link,
 759                 src->is_ssa ? &src->ssa->uses : &src->reg.reg->uses);
 760
 761    return true;
 762 }
 763
 764 static bool
 765 add_ssa_def_cb(nir_ssa_def *def, void *state)
 766 {
 767    nir_instr *instr = state;
 768
 769    if (instr->block && def->index == UINT_MAX) {
 770       nir_function_impl *impl =
 771          nir_cf_node_get_function(&instr->block->cf_node);
 772
 773       def->index = impl->ssa_alloc++;
 774    }
 775
 776    return true;
 777 }
 778
 779 static bool
 780 add_reg_def_cb(nir_dest *dest, void *state)
 781 {
 782    nir_instr *instr = state;
 783
 784    if (!dest->is_ssa) {
 785       dest->reg.parent_instr = instr;
 786       list_addtail(&dest->reg.def_link, &dest->reg.reg->defs);
 787    }
 788
 789    return true;
 790 }
 791
 792 static void
 793 add_defs_uses(nir_instr *instr)
 794 {
 795    nir_foreach_src(instr, add_use_cb, instr);
 796    nir_foreach_dest(instr, add_reg_def_cb, instr);
 797    nir_foreach_ssa_def(instr, add_ssa_def_cb, instr);
 798 }
 799
 800 void
 801 nir_instr_insert(nir_cursor cursor, nir_instr *instr)
 802 {
 803    switch (cursor.option) {
 804    case nir_cursor_before_block:
 805       /* Only allow inserting jumps into empty blocks. */
 806       if (instr->type == nir_instr_type_jump)
 807          assert(exec_list_is_empty(&cursor.block->instr_list));
 808
 809       instr->block = cursor.block;
 810       add_defs_uses(instr);
 811       exec_list_push_head(&cursor.block->instr_list, &instr->node);
 812       break;
 813    case nir_cursor_after_block: {
 814       /* Inserting instructions after a jump is illegal. */
 815       nir_instr *last = nir_block_last_instr(cursor.block);
 816       assert(last == NULL || last->type != nir_instr_type_jump);
 817       (void) last;
 818
 819       instr->block = cursor.block;
 820       add_defs_uses(instr);
 821       exec_list_push_tail(&cursor.block->instr_list, &instr->node);
 822       break;
 823    }
 824    case nir_cursor_before_instr:
 825       assert(instr->type != nir_instr_type_jump);
 826       instr->block = cursor.instr->block;
 827       add_defs_uses(instr);
 828       exec_node_insert_node_before(&cursor.instr->node, &instr->node);
 829       break;
 830    case nir_cursor_after_instr:
 831       /* Inserting instructions after a jump is illegal. */
 832       assert(cursor.instr->type != nir_instr_type_jump);
 833
 834       /* Only allow inserting jumps at the end of the block. */
 835       if (instr->type == nir_instr_type_jump)
 836          assert(cursor.instr == nir_block_last_instr(cursor.instr->block));
 837
 838       instr->block = cursor.instr->block;
 839       add_defs_uses(instr);
 840       exec_node_insert_after(&cursor.instr->node, &instr->node);
 841       break;
 842    }
 843
 844    if (instr->type == nir_instr_type_jump)
 845       nir_handle_add_jump(instr->block);
 846 }
 847
 848 static bool
 849 src_is_valid(const nir_src *src)
 850 {
 851    return src->is_ssa ? (src->ssa != NULL) : (src->reg.reg != NULL);
 852 }
 853
 854 static bool
 855 remove_use_cb(nir_src *src, void *state)
 856 {
 857    (void) state;
 858
 859    if (src_is_valid(src))
 860       list_del(&src->use_link);
 861
 862    return true;
 863 }
 864
 865 static bool
 866 remove_def_cb(nir_dest *dest, void *state)
 867 {
 868    (void) state;
 869
 870    if (!dest->is_ssa)
 871       list_del(&dest->reg.def_link);
 872
 873    return true;
 874 }
 875
 876 static void
 877 remove_defs_uses(nir_instr *instr)
 878 {
 879    nir_foreach_dest(instr, remove_def_cb, instr);
 880    nir_foreach_src(instr, remove_use_cb, instr);
 881 }
 882
 883 void nir_instr_remove_v(nir_instr *instr)
 884 {
 885    remove_defs_uses(instr);
 886    exec_node_remove(&instr->node);
 887
 888    if (instr->type == nir_instr_type_jump) {
 889       nir_jump_instr *jump_instr = nir_instr_as_jump(instr);
 890       nir_handle_remove_jump(instr->block, jump_instr->type);
 891    }
 892 }
 893
 894 /*@}*/
 895
 896 void
 897 nir_index_local_regs(nir_function_impl *impl)
 898 {
 899    unsigned index = 0;
 900    foreach_list_typed(nir_register, reg, node, &impl->registers) {
 901       reg->index = index++;
 902    }
 903    impl->reg_alloc = index;
 904 }
 905
 906 void
 907 nir_index_global_regs(nir_shader *shader)
 908 {
 909    unsigned index = 0;
 910    foreach_list_typed(nir_register, reg, node, &shader->registers) {
 911       reg->index = index++;
 912    }
 913    shader->reg_alloc = index;
 914 }
 915
 916 static bool
 917 visit_alu_dest(nir_alu_instr *instr, nir_foreach_dest_cb cb, void *state)
 918 {
 919    return cb(&instr->dest.dest, state);
 920 }
 921
 922 static bool
 923 visit_deref_dest(nir_deref_instr *instr, nir_foreach_dest_cb cb, void *state)
 924 {
 925    return cb(&instr->dest, state);
 926 }
 927
 928 static bool
 929 visit_intrinsic_dest(nir_intrinsic_instr *instr, nir_foreach_dest_cb cb,
 930                      void *state)
 931 {
 932    if (nir_intrinsic_infos[instr->intrinsic].has_dest)
 933       return cb(&instr->dest, state);
 934
 935    return true;
 936 }
 937
 938 static bool
 939 visit_texture_dest(nir_tex_instr *instr, nir_foreach_dest_cb cb,
 940                    void *state)
 941 {
 942    return cb(&instr->dest, state);
 943 }
 944
 945 static bool
 946 visit_phi_dest(nir_phi_instr *instr, nir_foreach_dest_cb cb, void *state)
 947 {
 948    return cb(&instr->dest, state);
 949 }
 950
 951 static bool
 952 visit_parallel_copy_dest(nir_parallel_copy_instr *instr,
 953                          nir_foreach_dest_cb cb, void *state)
 954 {
 955    nir_foreach_parallel_copy_entry(entry, instr) {
 956       if (!cb(&entry->dest, state))
 957          return false;
 958    }
 959
 960    return true;
 961 }
 962
 963 bool
 964 nir_foreach_dest(nir_instr *instr, nir_foreach_dest_cb cb, void *state)
 965 {
 966    switch (instr->type) {
 967    case nir_instr_type_alu:
 968       return visit_alu_dest(nir_instr_as_alu(instr), cb, state);
 969    case nir_instr_type_deref:
 970       return visit_deref_dest(nir_instr_as_deref(instr), cb, state);
 971    case nir_instr_type_intrinsic:
 972       return visit_intrinsic_dest(nir_instr_as_intrinsic(instr), cb, state);
 973    case nir_instr_type_tex:
 974       return visit_texture_dest(nir_instr_as_tex(instr), cb, state);
 975    case nir_instr_type_phi:
 976       return visit_phi_dest(nir_instr_as_phi(instr), cb, state);
 977    case nir_instr_type_parallel_copy:
 978       return visit_parallel_copy_dest(nir_instr_as_parallel_copy(instr),
 979                                       cb, state);
 980
 981    case nir_instr_type_load_const:
 982    case nir_instr_type_ssa_undef:
 983    case nir_instr_type_call:
 984    case nir_instr_type_jump:
 985       break;
 986
 987    default:
 988       unreachable("Invalid instruction type");
 989       break;
 990    }
 991
 992    return true;
 993 }
 994
 995 struct foreach_ssa_def_state {
 996    nir_foreach_ssa_def_cb cb;
 997    void *client_state;
 998 };
 999
1000 static inline bool
1001 nir_ssa_def_visitor(nir_dest *dest, void *void_state)
1002 {
1003    struct foreach_ssa_def_state *state = void_state;
1004
1005    if (dest->is_ssa)
1006       return state->cb(&dest->ssa, state->client_state);
1007    else
1008       return true;
1009 }
1010
1011 bool
1012 nir_foreach_ssa_def(nir_instr *instr, nir_foreach_ssa_def_cb cb, void *state)
1013 {
1014    switch (instr->type) {
1015    case nir_instr_type_alu:
1016    case nir_instr_type_deref:
1017    case nir_instr_type_tex:
1018    case nir_instr_type_intrinsic:
1019    case nir_instr_type_phi:
1020    case nir_instr_type_parallel_copy: {
1021       struct foreach_ssa_def_state foreach_state = {cb, state};
1022       return nir_foreach_dest(instr, nir_ssa_def_visitor, &foreach_state);
1023    }
1024
1025    case nir_instr_type_load_const:
1026       return cb(&nir_instr_as_load_const(instr)->def, state);
1027    case nir_instr_type_ssa_undef:
1028       return cb(&nir_instr_as_ssa_undef(instr)->def, state);
1029    case nir_instr_type_call:
1030    case nir_instr_type_jump:
1031       return true;
1032    default:
1033       unreachable("Invalid instruction type");
1034    }
1035 }
1036
1037 static bool
1038 visit_src(nir_src *src, nir_foreach_src_cb cb, void *state)
1039 {
1040    if (!cb(src, state))
1041       return false;
1042    if (!src->is_ssa && src->reg.indirect)
1043       return cb(src->reg.indirect, state);
1044    return true;
1045 }
1046
1047 static bool
1048 visit_alu_src(nir_alu_instr *instr, nir_foreach_src_cb cb, void *state)
1049 {
1050    for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1051       if (!visit_src(&instr->src[i].src, cb, state))
1052          return false;
1053
1054    return true;
1055 }
1056
1057 static bool
1058 visit_deref_instr_src(nir_deref_instr *instr,
1059                       nir_foreach_src_cb cb, void *state)
1060 {
1061    if (instr->deref_type != nir_deref_type_var) {
1062       if (!visit_src(&instr->parent, cb, state))
1063          return false;
1064    }
1065
1066    if (instr->deref_type == nir_deref_type_array) {
1067       if (!visit_src(&instr->arr.index, cb, state))
1068          return false;
1069    }
1070
1071    return true;
1072 }
1073
1074 static bool
1075 visit_tex_src(nir_tex_instr *instr, nir_foreach_src_cb cb, void *state)
1076 {
1077    for (unsigned i = 0; i < instr->num_srcs; i++) {
1078       if (!visit_src(&instr->src[i].src, cb, state))
1079          return false;
1080    }
1081
1082    return true;
1083 }
1084
1085 static bool
1086 visit_intrinsic_src(nir_intrinsic_instr *instr, nir_foreach_src_cb cb,
1087                     void *state)
1088 {
1089    unsigned num_srcs = nir_intrinsic_infos[instr->intrinsic].num_srcs;
1090    for (unsigned i = 0; i < num_srcs; i++) {
1091       if (!visit_src(&instr->src[i], cb, state))
1092          return false;
1093    }
1094
1095    return true;
1096 }
1097
1098 static bool
1099 visit_call_src(nir_call_instr *instr, nir_foreach_src_cb cb, void *state)
1100 {
1101    for (unsigned i = 0; i < instr->num_params; i++) {
1102       if (!visit_src(&instr->params[i], cb, state))
1103          return false;
1104    }
1105
1106    return true;
1107 }
1108
1109 static bool
1110 visit_phi_src(nir_phi_instr *instr, nir_foreach_src_cb cb, void *state)
1111 {
1112    nir_foreach_phi_src(src, instr) {
1113       if (!visit_src(&src->src, cb, state))
1114          return false;
1115    }
1116
1117    return true;
1118 }
1119
1120 static bool
1121 visit_parallel_copy_src(nir_parallel_copy_instr *instr,
1122                         nir_foreach_src_cb cb, void *state)
1123 {
1124    nir_foreach_parallel_copy_entry(entry, instr) {
1125       if (!visit_src(&entry->src, cb, state))
1126          return false;
1127    }
1128
1129    return true;
1130 }
1131
1132 typedef struct {
1133    void *state;
1134    nir_foreach_src_cb cb;
1135 } visit_dest_indirect_state;
1136
1137 static bool
1138 visit_dest_indirect(nir_dest *dest, void *_state)
1139 {
1140    visit_dest_indirect_state *state = (visit_dest_indirect_state *) _state;
1141
1142    if (!dest->is_ssa && dest->reg.indirect)
1143       return state->cb(dest->reg.indirect, state->state);
1144
1145    return true;
1146 }
1147
1148 bool
1149 nir_foreach_src(nir_instr *instr, nir_foreach_src_cb cb, void *state)
1150 {
1151    switch (instr->type) {
1152    case nir_instr_type_alu:
1153       if (!visit_alu_src(nir_instr_as_alu(instr), cb, state))
1154          return false;
1155       break;
1156    case nir_instr_type_deref:
1157       if (!visit_deref_instr_src(nir_instr_as_deref(instr), cb, state))
1158          return false;
1159       break;
1160    case nir_instr_type_intrinsic:
1161       if (!visit_intrinsic_src(nir_instr_as_intrinsic(instr), cb, state))
1162          return false;
1163       break;
1164    case nir_instr_type_tex:
1165       if (!visit_tex_src(nir_instr_as_tex(instr), cb, state))
1166          return false;
1167       break;
1168    case nir_instr_type_call:
1169       if (!visit_call_src(nir_instr_as_call(instr), cb, state))
1170          return false;
1171       break;
1172    case nir_instr_type_load_const:
1173       /* Constant load instructions have no regular sources */
1174       break;
1175    case nir_instr_type_phi:
1176       if (!visit_phi_src(nir_instr_as_phi(instr), cb, state))
1177          return false;
1178       break;
1179    case nir_instr_type_parallel_copy:
1180       if (!visit_parallel_copy_src(nir_instr_as_parallel_copy(instr),
1181                                    cb, state))
1182          return false;
1183       break;
1184    case nir_instr_type_jump:
1185    case nir_instr_type_ssa_undef:
1186       return true;
1187
1188    default:
1189       unreachable("Invalid instruction type");
1190       break;
1191    }
1192
1193    visit_dest_indirect_state dest_state;
1194    dest_state.state = state;
1195    dest_state.cb = cb;
1196    return nir_foreach_dest(instr, visit_dest_indirect, &dest_state);
1197 }
1198
1199 nir_const_value *
1200 nir_src_as_const_value(nir_src src)
1201 {
1202    if (!src.is_ssa)
1203       return NULL;
1204
1205    if (src.ssa->parent_instr->type != nir_instr_type_load_const)
1206       return NULL;
1207
1208    nir_load_const_instr *load = nir_instr_as_load_const(src.ssa->parent_instr);
1209
1210    return &load->value;
1211 }
1212
1213 /**
1214  * Returns true if the source is known to be dynamically uniform. Otherwise it
1215  * returns false which means it may or may not be dynamically uniform but it
1216  * can't be determined.
1217  */
1218 bool
1219 nir_src_is_dynamically_uniform(nir_src src)
1220 {
1221    if (!src.is_ssa)
1222       return false;
1223
1224    /* Constants are trivially dynamically uniform */
1225    if (src.ssa->parent_instr->type == nir_instr_type_load_const)
1226       return true;
1227
1228    /* As are uniform variables */
1229    if (src.ssa->parent_instr->type == nir_instr_type_intrinsic) {
1230       nir_intrinsic_instr *intr = nir_instr_as_intrinsic(src.ssa->parent_instr);
1231
1232       if (intr->intrinsic == nir_intrinsic_load_uniform)
1233          return true;
1234    }
1235
1236    /* XXX: this could have many more tests, such as when a sampler function is
1237     * called with dynamically uniform arguments.
1238     */
1239    return false;
1240 }
1241
1242 static void
1243 src_remove_all_uses(nir_src *src)
1244 {
1245    for (; src; src = src->is_ssa ? NULL : src->reg.indirect) {
1246       if (!src_is_valid(src))
1247          continue;
1248
1249       list_del(&src->use_link);
1250    }
1251 }
1252
1253 static void
1254 src_add_all_uses(nir_src *src, nir_instr *parent_instr, nir_if *parent_if)
1255 {
1256    for (; src; src = src->is_ssa ? NULL : src->reg.indirect) {
1257       if (!src_is_valid(src))
1258          continue;
1259
1260       if (parent_instr) {
1261          src->parent_instr = parent_instr;
1262          if (src->is_ssa)
1263             list_addtail(&src->use_link, &src->ssa->uses);
1264          else
1265             list_addtail(&src->use_link, &src->reg.reg->uses);
1266       } else {
1267          assert(parent_if);
1268          src->parent_if = parent_if;
1269          if (src->is_ssa)
1270             list_addtail(&src->use_link, &src->ssa->if_uses);
1271          else
1272             list_addtail(&src->use_link, &src->reg.reg->if_uses);
1273       }
1274    }
1275 }
1276
1277 void
1278 nir_instr_rewrite_src(nir_instr *instr, nir_src *src, nir_src new_src)
1279 {
1280    assert(!src_is_valid(src) || src->parent_instr == instr);
1281
1282    src_remove_all_uses(src);
1283    *src = new_src;
1284    src_add_all_uses(src, instr, NULL);
1285 }
1286
1287 void
1288 nir_instr_move_src(nir_instr *dest_instr, nir_src *dest, nir_src *src)
1289 {
1290    assert(!src_is_valid(dest) || dest->parent_instr == dest_instr);
1291
1292    src_remove_all_uses(dest);
1293    src_remove_all_uses(src);
1294    *dest = *src;
1295    *src = NIR_SRC_INIT;
1296    src_add_all_uses(dest, dest_instr, NULL);
1297 }
1298
1299 void
1300 nir_if_rewrite_condition(nir_if *if_stmt, nir_src new_src)
1301 {
1302    nir_src *src = &if_stmt->condition;
1303    assert(!src_is_valid(src) || src->parent_if == if_stmt);
1304
1305    src_remove_all_uses(src);
1306    *src = new_src;
1307    src_add_all_uses(src, NULL, if_stmt);
1308 }
1309
1310 void
1311 nir_instr_rewrite_dest(nir_instr *instr, nir_dest *dest, nir_dest new_dest)
1312 {
1313    if (dest->is_ssa) {
1314       /* We can only overwrite an SSA destination if it has no uses. */
1315       assert(list_empty(&dest->ssa.uses) && list_empty(&dest->ssa.if_uses));
1316    } else {
1317       list_del(&dest->reg.def_link);
1318       if (dest->reg.indirect)
1319          src_remove_all_uses(dest->reg.indirect);
1320    }
1321
1322    /* We can't re-write with an SSA def */
1323    assert(!new_dest.is_ssa);
1324
1325    nir_dest_copy(dest, &new_dest, instr);
1326
1327    dest->reg.parent_instr = instr;
1328    list_addtail(&dest->reg.def_link, &new_dest.reg.reg->defs);
1329
1330    if (dest->reg.indirect)
1331       src_add_all_uses(dest->reg.indirect, instr, NULL);
1332 }
1333
1334 /* note: does *not* take ownership of 'name' */
1335 void
1336 nir_ssa_def_init(nir_instr *instr, nir_ssa_def *def,
1337                  unsigned num_components,
1338                  unsigned bit_size, const char *name)
1339 {
1340    def->name = ralloc_strdup(instr, name);
1341    def->parent_instr = instr;
1342    list_inithead(&def->uses);
1343    list_inithead(&def->if_uses);
1344    def->num_components = num_components;
1345    def->bit_size = bit_size;
1346
1347    if (instr->block) {
1348       nir_function_impl *impl =
1349          nir_cf_node_get_function(&instr->block->cf_node);
1350
1351       def->index = impl->ssa_alloc++;
1352    } else {
1353       def->index = UINT_MAX;
1354    }
1355 }
1356
1357 /* note: does *not* take ownership of 'name' */
1358 void
1359 nir_ssa_dest_init(nir_instr *instr, nir_dest *dest,
1360                  unsigned num_components, unsigned bit_size,
1361                  const char *name)
1362 {
1363    dest->is_ssa = true;
1364    nir_ssa_def_init(instr, &dest->ssa, num_components, bit_size, name);
1365 }
1366
1367 void
1368 nir_ssa_def_rewrite_uses(nir_ssa_def *def, nir_src new_src)
1369 {
1370    assert(!new_src.is_ssa || def != new_src.ssa);
1371
1372    nir_foreach_use_safe(use_src, def)
1373       nir_instr_rewrite_src(use_src->parent_instr, use_src, new_src);
1374
1375    nir_foreach_if_use_safe(use_src, def)
1376       nir_if_rewrite_condition(use_src->parent_if, new_src);
1377 }
1378
1379 static bool
1380 is_instr_between(nir_instr *start, nir_instr *end, nir_instr *between)
1381 {
1382    assert(start->block == end->block);
1383
1384    if (between->block != start->block)
1385       return false;
1386
1387    /* Search backwards looking for "between" */
1388    while (start != end) {
1389       if (between == end)
1390          return true;
1391
1392       end = nir_instr_prev(end);
1393       assert(end);
1394    }
1395
1396    return false;
1397 }
1398
1399 /* Replaces all uses of the given SSA def with the given source but only if
1400  * the use comes after the after_me instruction.  This can be useful if you
1401  * are emitting code to fix up the result of some instruction: you can freely
1402  * use the result in that code and then call rewrite_uses_after and pass the
1403  * last fixup instruction as after_me and it will replace all of the uses you
1404  * want without touching the fixup code.
1405  *
1406  * This function assumes that after_me is in the same block as
1407  * def->parent_instr and that after_me comes after def->parent_instr.
1408  */
1409 void
1410 nir_ssa_def_rewrite_uses_after(nir_ssa_def *def, nir_src new_src,
1411                                nir_instr *after_me)
1412 {
1413    assert(!new_src.is_ssa || def != new_src.ssa);
1414
1415    nir_foreach_use_safe(use_src, def) {
1416       assert(use_src->parent_instr != def->parent_instr);
1417       /* Since def already dominates all of its uses, the only way a use can
1418        * not be dominated by after_me is if it is between def and after_me in
1419        * the instruction list.
1420        */
1421       if (!is_instr_between(def->parent_instr, after_me, use_src->parent_instr))
1422          nir_instr_rewrite_src(use_src->parent_instr, use_src, new_src);
1423    }
1424
1425    nir_foreach_if_use_safe(use_src, def)
1426       nir_if_rewrite_condition(use_src->parent_if, new_src);
1427 }
1428
1429 uint8_t
1430 nir_ssa_def_components_read(const nir_ssa_def *def)
1431 {
1432    uint8_t read_mask = 0;
1433    nir_foreach_use(use, def) {
1434       if (use->parent_instr->type == nir_instr_type_alu) {
1435          nir_alu_instr *alu = nir_instr_as_alu(use->parent_instr);
1436          nir_alu_src *alu_src = exec_node_data(nir_alu_src, use, src);
1437          int src_idx = alu_src - &alu->src[0];
1438          assert(src_idx >= 0 && src_idx < nir_op_infos[alu->op].num_inputs);
1439
1440          for (unsigned c = 0; c < 4; c++) {
1441             if (!nir_alu_instr_channel_used(alu, src_idx, c))
1442                continue;
1443
1444             read_mask |= (1 << alu_src->swizzle[c]);
1445          }
1446       } else {
1447          return (1 << def->num_components) - 1;
1448       }
1449    }
1450
1451    return read_mask;
1452 }
1453
1454 nir_block *
1455 nir_block_cf_tree_next(nir_block *block)
1456 {
1457    if (block == NULL) {
1458       /* nir_foreach_block_safe() will call this function on a NULL block
1459        * after the last iteration, but it won't use the result so just return
1460        * NULL here.
1461        */
1462       return NULL;
1463    }
1464
1465    nir_cf_node *cf_next = nir_cf_node_next(&block->cf_node);
1466    if (cf_next)
1467       return nir_cf_node_cf_tree_first(cf_next);
1468
1469    nir_cf_node *parent = block->cf_node.parent;
1470
1471    switch (parent->type) {
1472    case nir_cf_node_if: {
1473       /* Are we at the end of the if? Go to the beginning of the else */
1474       nir_if *if_stmt = nir_cf_node_as_if(parent);
1475       if (block == nir_if_last_then_block(if_stmt))
1476          return nir_if_first_else_block(if_stmt);
1477
1478       assert(block == nir_if_last_else_block(if_stmt));
1479       /* fall through */
1480    }
1481
1482    case nir_cf_node_loop:
1483       return nir_cf_node_as_block(nir_cf_node_next(parent));
1484
1485    case nir_cf_node_function:
1486       return NULL;
1487
1488    default:
1489       unreachable("unknown cf node type");
1490    }
1491 }
1492
1493 nir_block *
1494 nir_block_cf_tree_prev(nir_block *block)
1495 {
1496    if (block == NULL) {
1497       /* do this for consistency with nir_block_cf_tree_next() */
1498       return NULL;
1499    }
1500
1501    nir_cf_node *cf_prev = nir_cf_node_prev(&block->cf_node);
1502    if (cf_prev)
1503       return nir_cf_node_cf_tree_last(cf_prev);
1504
1505    nir_cf_node *parent = block->cf_node.parent;
1506
1507    switch (parent->type) {
1508    case nir_cf_node_if: {
1509       /* Are we at the beginning of the else? Go to the end of the if */
1510       nir_if *if_stmt = nir_cf_node_as_if(parent);
1511       if (block == nir_if_first_else_block(if_stmt))
1512          return nir_if_last_then_block(if_stmt);
1513
1514       assert(block == nir_if_first_then_block(if_stmt));
1515       /* fall through */
1516    }
1517
1518    case nir_cf_node_loop:
1519       return nir_cf_node_as_block(nir_cf_node_prev(parent));
1520
1521    case nir_cf_node_function:
1522       return NULL;
1523
1524    default:
1525       unreachable("unknown cf node type");
1526    }
1527 }
1528
1529 nir_block *nir_cf_node_cf_tree_first(nir_cf_node *node)
1530 {
1531    switch (node->type) {
1532    case nir_cf_node_function: {
1533       nir_function_impl *impl = nir_cf_node_as_function(node);
1534       return nir_start_block(impl);
1535    }
1536
1537    case nir_cf_node_if: {
1538       nir_if *if_stmt = nir_cf_node_as_if(node);
1539       return nir_if_first_then_block(if_stmt);
1540    }
1541
1542    case nir_cf_node_loop: {
1543       nir_loop *loop = nir_cf_node_as_loop(node);
1544       return nir_loop_first_block(loop);
1545    }
1546
1547    case nir_cf_node_block: {
1548       return nir_cf_node_as_block(node);
1549    }
1550
1551    default:
1552       unreachable("unknown node type");
1553    }
1554 }
1555
1556 nir_block *nir_cf_node_cf_tree_last(nir_cf_node *node)
1557 {
1558    switch (node->type) {
1559    case nir_cf_node_function: {
1560       nir_function_impl *impl = nir_cf_node_as_function(node);
1561       return nir_impl_last_block(impl);
1562    }
1563
1564    case nir_cf_node_if: {
1565       nir_if *if_stmt = nir_cf_node_as_if(node);
1566       return nir_if_last_else_block(if_stmt);
1567    }
1568
1569    case nir_cf_node_loop: {
1570       nir_loop *loop = nir_cf_node_as_loop(node);
1571       return nir_loop_last_block(loop);
1572    }
1573
1574    case nir_cf_node_block: {
1575       return nir_cf_node_as_block(node);
1576    }
1577
1578    default:
1579       unreachable("unknown node type");
1580    }
1581 }
1582
1583 nir_block *nir_cf_node_cf_tree_next(nir_cf_node *node)
1584 {
1585    if (node->type == nir_cf_node_block)
1586       return nir_block_cf_tree_next(nir_cf_node_as_block(node));
1587    else if (node->type == nir_cf_node_function)
1588       return NULL;
1589    else
1590       return nir_cf_node_as_block(nir_cf_node_next(node));
1591 }
1592
1593 nir_if *
1594 nir_block_get_following_if(nir_block *block)
1595 {
1596    if (exec_node_is_tail_sentinel(&block->cf_node.node))
1597       return NULL;
1598
1599    if (nir_cf_node_is_last(&block->cf_node))
1600       return NULL;
1601
1602    nir_cf_node *next_node = nir_cf_node_next(&block->cf_node);
1603
1604    if (next_node->type != nir_cf_node_if)
1605       return NULL;
1606
1607    return nir_cf_node_as_if(next_node);
1608 }
1609
1610 nir_loop *
1611 nir_block_get_following_loop(nir_block *block)
1612 {
1613    if (exec_node_is_tail_sentinel(&block->cf_node.node))
1614       return NULL;
1615
1616    if (nir_cf_node_is_last(&block->cf_node))
1617       return NULL;
1618
1619    nir_cf_node *next_node = nir_cf_node_next(&block->cf_node);
1620
1621    if (next_node->type != nir_cf_node_loop)
1622       return NULL;
1623
1624    return nir_cf_node_as_loop(next_node);
1625 }
1626
1627 void
1628 nir_index_blocks(nir_function_impl *impl)
1629 {
1630    unsigned index = 0;
1631
1632    if (impl->valid_metadata & nir_metadata_block_index)
1633       return;
1634
1635    nir_foreach_block(block, impl) {
1636       block->index = index++;
1637    }
1638
1639    impl->num_blocks = index;
1640 }
1641
1642 static bool
1643 index_ssa_def_cb(nir_ssa_def *def, void *state)
1644 {
1645    unsigned *index = (unsigned *) state;
1646    def->index = (*index)++;
1647
1648    return true;
1649 }
1650
1651 /**
1652  * The indices are applied top-to-bottom which has the very nice property
1653  * that, if A dominates B, then A->index <= B->index.
1654  */
1655 void
1656 nir_index_ssa_defs(nir_function_impl *impl)
1657 {
1658    unsigned index = 0;
1659
1660    nir_foreach_block(block, impl) {
1661       nir_foreach_instr(instr, block)
1662          nir_foreach_ssa_def(instr, index_ssa_def_cb, &index);
1663    }
1664
1665    impl->ssa_alloc = index;
1666 }
1667
1668 /**
1669  * The indices are applied top-to-bottom which has the very nice property
1670  * that, if A dominates B, then A->index <= B->index.
1671  */
1672 unsigned
1673 nir_index_instrs(nir_function_impl *impl)
1674 {
1675    unsigned index = 0;
1676
1677    nir_foreach_block(block, impl) {
1678       nir_foreach_instr(instr, block)
1679          instr->index = index++;
1680    }
1681
1682    return index;
1683 }
1684
1685 nir_intrinsic_op
1686 nir_intrinsic_from_system_value(gl_system_value val)
1687 {
1688    switch (val) {
1689    case SYSTEM_VALUE_VERTEX_ID:
1690       return nir_intrinsic_load_vertex_id;
1691    case SYSTEM_VALUE_INSTANCE_ID:
1692       return nir_intrinsic_load_instance_id;
1693    case SYSTEM_VALUE_DRAW_ID:
1694       return nir_intrinsic_load_draw_id;
1695    case SYSTEM_VALUE_BASE_INSTANCE:
1696       return nir_intrinsic_load_base_instance;
1697    case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
1698       return nir_intrinsic_load_vertex_id_zero_base;
1699    case SYSTEM_VALUE_IS_INDEXED_DRAW:
1700       return nir_intrinsic_load_is_indexed_draw;
1701    case SYSTEM_VALUE_FIRST_VERTEX:
1702       return nir_intrinsic_load_first_vertex;
1703    case SYSTEM_VALUE_BASE_VERTEX:
1704       return nir_intrinsic_load_base_vertex;
1705    case SYSTEM_VALUE_INVOCATION_ID:
1706       return nir_intrinsic_load_invocation_id;
1707    case SYSTEM_VALUE_FRAG_COORD:
1708       return nir_intrinsic_load_frag_coord;
1709    case SYSTEM_VALUE_FRONT_FACE:
1710       return nir_intrinsic_load_front_face;
1711    case SYSTEM_VALUE_SAMPLE_ID:
1712       return nir_intrinsic_load_sample_id;
1713    case SYSTEM_VALUE_SAMPLE_POS:
1714       return nir_intrinsic_load_sample_pos;
1715    case SYSTEM_VALUE_SAMPLE_MASK_IN:
1716       return nir_intrinsic_load_sample_mask_in;
1717    case SYSTEM_VALUE_LOCAL_INVOCATION_ID:
1718       return nir_intrinsic_load_local_invocation_id;
1719    case SYSTEM_VALUE_LOCAL_INVOCATION_INDEX:
1720       return nir_intrinsic_load_local_invocation_index;
1721    case SYSTEM_VALUE_WORK_GROUP_ID:
1722       return nir_intrinsic_load_work_group_id;
1723    case SYSTEM_VALUE_NUM_WORK_GROUPS:
1724       return nir_intrinsic_load_num_work_groups;
1725    case SYSTEM_VALUE_PRIMITIVE_ID:
1726       return nir_intrinsic_load_primitive_id;
1727    case SYSTEM_VALUE_TESS_COORD:
1728       return nir_intrinsic_load_tess_coord;
1729    case SYSTEM_VALUE_TESS_LEVEL_OUTER:
1730       return nir_intrinsic_load_tess_level_outer;
1731    case SYSTEM_VALUE_TESS_LEVEL_INNER:
1732       return nir_intrinsic_load_tess_level_inner;
1733    case SYSTEM_VALUE_VERTICES_IN:
1734       return nir_intrinsic_load_patch_vertices_in;
1735    case SYSTEM_VALUE_HELPER_INVOCATION:
1736       return nir_intrinsic_load_helper_invocation;
1737    case SYSTEM_VALUE_VIEW_INDEX:
1738       return nir_intrinsic_load_view_index;
1739    case SYSTEM_VALUE_SUBGROUP_SIZE:
1740       return nir_intrinsic_load_subgroup_size;
1741    case SYSTEM_VALUE_SUBGROUP_INVOCATION:
1742       return nir_intrinsic_load_subgroup_invocation;
1743    case SYSTEM_VALUE_SUBGROUP_EQ_MASK:
1744       return nir_intrinsic_load_subgroup_eq_mask;
1745    case SYSTEM_VALUE_SUBGROUP_GE_MASK:
1746       return nir_intrinsic_load_subgroup_ge_mask;
1747    case SYSTEM_VALUE_SUBGROUP_GT_MASK:
1748       return nir_intrinsic_load_subgroup_gt_mask;
1749    case SYSTEM_VALUE_SUBGROUP_LE_MASK:
1750       return nir_intrinsic_load_subgroup_le_mask;
1751    case SYSTEM_VALUE_SUBGROUP_LT_MASK:
1752       return nir_intrinsic_load_subgroup_lt_mask;
1753    case SYSTEM_VALUE_NUM_SUBGROUPS:
1754       return nir_intrinsic_load_num_subgroups;
1755    case SYSTEM_VALUE_SUBGROUP_ID:
1756       return nir_intrinsic_load_subgroup_id;
1757    case SYSTEM_VALUE_LOCAL_GROUP_SIZE:
1758       return nir_intrinsic_load_local_group_size;
1759    case SYSTEM_VALUE_GLOBAL_INVOCATION_ID:
1760       return nir_intrinsic_load_global_invocation_id;
1761    case SYSTEM_VALUE_WORK_DIM:
1762       return nir_intrinsic_load_work_dim;
1763    default:
1764       unreachable("system value does not directly correspond to intrinsic");
1765    }
1766 }
1767
1768 gl_system_value
1769 nir_system_value_from_intrinsic(nir_intrinsic_op intrin)
1770 {
1771    switch (intrin) {
1772    case nir_intrinsic_load_vertex_id:
1773       return SYSTEM_VALUE_VERTEX_ID;
1774    case nir_intrinsic_load_instance_id:
1775       return SYSTEM_VALUE_INSTANCE_ID;
1776    case nir_intrinsic_load_draw_id:
1777       return SYSTEM_VALUE_DRAW_ID;
1778    case nir_intrinsic_load_base_instance:
1779       return SYSTEM_VALUE_BASE_INSTANCE;
1780    case nir_intrinsic_load_vertex_id_zero_base:
1781       return SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1782    case nir_intrinsic_load_first_vertex:
1783       return SYSTEM_VALUE_FIRST_VERTEX;
1784    case nir_intrinsic_load_is_indexed_draw:
1785       return SYSTEM_VALUE_IS_INDEXED_DRAW;
1786    case nir_intrinsic_load_base_vertex:
1787       return SYSTEM_VALUE_BASE_VERTEX;
1788    case nir_intrinsic_load_invocation_id:
1789       return SYSTEM_VALUE_INVOCATION_ID;
1790    case nir_intrinsic_load_frag_coord:
1791       return SYSTEM_VALUE_FRAG_COORD;
1792    case nir_intrinsic_load_front_face:
1793       return SYSTEM_VALUE_FRONT_FACE;
1794    case nir_intrinsic_load_sample_id:
1795       return SYSTEM_VALUE_SAMPLE_ID;
1796    case nir_intrinsic_load_sample_pos:
1797       return SYSTEM_VALUE_SAMPLE_POS;
1798    case nir_intrinsic_load_sample_mask_in:
1799       return SYSTEM_VALUE_SAMPLE_MASK_IN;
1800    case nir_intrinsic_load_local_invocation_id:
1801       return SYSTEM_VALUE_LOCAL_INVOCATION_ID;
1802    case nir_intrinsic_load_local_invocation_index:
1803       return SYSTEM_VALUE_LOCAL_INVOCATION_INDEX;
1804    case nir_intrinsic_load_num_work_groups:
1805       return SYSTEM_VALUE_NUM_WORK_GROUPS;
1806    case nir_intrinsic_load_work_group_id:
1807       return SYSTEM_VALUE_WORK_GROUP_ID;
1808    case nir_intrinsic_load_primitive_id:
1809       return SYSTEM_VALUE_PRIMITIVE_ID;
1810    case nir_intrinsic_load_tess_coord:
1811       return SYSTEM_VALUE_TESS_COORD;
1812    case nir_intrinsic_load_tess_level_outer:
1813       return SYSTEM_VALUE_TESS_LEVEL_OUTER;
1814    case nir_intrinsic_load_tess_level_inner:
1815       return SYSTEM_VALUE_TESS_LEVEL_INNER;
1816    case nir_intrinsic_load_patch_vertices_in:
1817       return SYSTEM_VALUE_VERTICES_IN;
1818    case nir_intrinsic_load_helper_invocation:
1819       return SYSTEM_VALUE_HELPER_INVOCATION;
1820    case nir_intrinsic_load_view_index:
1821       return SYSTEM_VALUE_VIEW_INDEX;
1822    case nir_intrinsic_load_subgroup_size:
1823       return SYSTEM_VALUE_SUBGROUP_SIZE;
1824    case nir_intrinsic_load_subgroup_invocation:
1825       return SYSTEM_VALUE_SUBGROUP_INVOCATION;
1826    case nir_intrinsic_load_subgroup_eq_mask:
1827       return SYSTEM_VALUE_SUBGROUP_EQ_MASK;
1828    case nir_intrinsic_load_subgroup_ge_mask:
1829       return SYSTEM_VALUE_SUBGROUP_GE_MASK;
1830    case nir_intrinsic_load_subgroup_gt_mask:
1831       return SYSTEM_VALUE_SUBGROUP_GT_MASK;
1832    case nir_intrinsic_load_subgroup_le_mask:
1833       return SYSTEM_VALUE_SUBGROUP_LE_MASK;
1834    case nir_intrinsic_load_subgroup_lt_mask:
1835       return SYSTEM_VALUE_SUBGROUP_LT_MASK;
1836    case nir_intrinsic_load_num_subgroups:
1837       return SYSTEM_VALUE_NUM_SUBGROUPS;
1838    case nir_intrinsic_load_subgroup_id:
1839       return SYSTEM_VALUE_SUBGROUP_ID;
1840    case nir_intrinsic_load_local_group_size:
1841       return SYSTEM_VALUE_LOCAL_GROUP_SIZE;
1842    case nir_intrinsic_load_global_invocation_id:
1843       return SYSTEM_VALUE_GLOBAL_INVOCATION_ID;
1844    default:
1845       unreachable("intrinsic doesn't produce a system value");
1846    }
1847 }