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nir: Add a structured flag to nir_shader
[mesa.git] / src / compiler / nir / nir.c
1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Connor Abbott (cwabbott0@gmail.com)
25 *
26 */
27
28 #include "nir.h"
29 #include "nir_builder.h"
30 #include "nir_control_flow_private.h"
31 #include "util/half_float.h"
32 #include <limits.h>
33 #include <assert.h>
34 #include <math.h>
35 #include "util/u_math.h"
36
37 #include "main/menums.h" /* BITFIELD64_MASK */
38
39 nir_shader *
40 nir_shader_create(void *mem_ctx,
41 gl_shader_stage stage,
42 const nir_shader_compiler_options *options,
43 shader_info *si)
44 {
45 nir_shader *shader = rzalloc(mem_ctx, nir_shader);
46
47 exec_list_make_empty(&shader->variables);
48
49 shader->options = options;
50
51 if (si) {
52 assert(si->stage == stage);
53 shader->info = *si;
54 } else {
55 shader->info.stage = stage;
56 }
57
58 exec_list_make_empty(&shader->functions);
59
60 shader->num_inputs = 0;
61 shader->num_outputs = 0;
62 shader->num_uniforms = 0;
63 shader->num_shared = 0;
64
65 return shader;
66 }
67
68 static nir_register *
69 reg_create(void *mem_ctx, struct exec_list *list)
70 {
71 nir_register *reg = ralloc(mem_ctx, nir_register);
72
73 list_inithead(&reg->uses);
74 list_inithead(&reg->defs);
75 list_inithead(&reg->if_uses);
76
77 reg->num_components = 0;
78 reg->bit_size = 32;
79 reg->num_array_elems = 0;
80 reg->name = NULL;
81
82 exec_list_push_tail(list, &reg->node);
83
84 return reg;
85 }
86
87 nir_register *
88 nir_local_reg_create(nir_function_impl *impl)
89 {
90 nir_register *reg = reg_create(ralloc_parent(impl), &impl->registers);
91 reg->index = impl->reg_alloc++;
92
93 return reg;
94 }
95
96 void
97 nir_reg_remove(nir_register *reg)
98 {
99 exec_node_remove(&reg->node);
100 }
101
102 void
103 nir_shader_add_variable(nir_shader *shader, nir_variable *var)
104 {
105 switch (var->data.mode) {
106 case nir_var_function_temp:
107 assert(!"nir_shader_add_variable cannot be used for local variables");
108 return;
109
110 case nir_var_shader_temp:
111 case nir_var_shader_in:
112 case nir_var_shader_out:
113 case nir_var_uniform:
114 case nir_var_mem_ubo:
115 case nir_var_mem_ssbo:
116 case nir_var_mem_shared:
117 case nir_var_system_value:
118 break;
119
120 case nir_var_mem_global:
121 assert(!"nir_shader_add_variable cannot be used for global memory");
122 return;
123
124 case nir_var_mem_push_const:
125 assert(!"nir_var_push_constant is not supposed to be used for variables");
126 return;
127
128 default:
129 assert(!"invalid mode");
130 return;
131 }
132
133 exec_list_push_tail(&shader->variables, &var->node);
134 }
135
136 nir_variable *
137 nir_variable_create(nir_shader *shader, nir_variable_mode mode,
138 const struct glsl_type *type, const char *name)
139 {
140 nir_variable *var = rzalloc(shader, nir_variable);
141 var->name = ralloc_strdup(var, name);
142 var->type = type;
143 var->data.mode = mode;
144 var->data.how_declared = nir_var_declared_normally;
145
146 if ((mode == nir_var_shader_in &&
147 shader->info.stage != MESA_SHADER_VERTEX) ||
148 (mode == nir_var_shader_out &&
149 shader->info.stage != MESA_SHADER_FRAGMENT))
150 var->data.interpolation = INTERP_MODE_SMOOTH;
151
152 if (mode == nir_var_shader_in || mode == nir_var_uniform)
153 var->data.read_only = true;
154
155 nir_shader_add_variable(shader, var);
156
157 return var;
158 }
159
160 nir_variable *
161 nir_local_variable_create(nir_function_impl *impl,
162 const struct glsl_type *type, const char *name)
163 {
164 nir_variable *var = rzalloc(impl->function->shader, nir_variable);
165 var->name = ralloc_strdup(var, name);
166 var->type = type;
167 var->data.mode = nir_var_function_temp;
168
169 nir_function_impl_add_variable(impl, var);
170
171 return var;
172 }
173
174 nir_variable *
175 nir_find_variable_with_location(nir_shader *shader,
176 nir_variable_mode mode,
177 unsigned location)
178 {
179 assert(util_bitcount(mode) == 1 && mode != nir_var_function_temp);
180 nir_foreach_variable_with_modes(var, shader, mode) {
181 if (var->data.location == location)
182 return var;
183 }
184 return NULL;
185 }
186
187 nir_variable *
188 nir_find_variable_with_driver_location(nir_shader *shader,
189 nir_variable_mode mode,
190 unsigned location)
191 {
192 assert(util_bitcount(mode) == 1 && mode != nir_var_function_temp);
193 nir_foreach_variable_with_modes(var, shader, mode) {
194 if (var->data.driver_location == location)
195 return var;
196 }
197 return NULL;
198 }
199
200 nir_function *
201 nir_function_create(nir_shader *shader, const char *name)
202 {
203 nir_function *func = ralloc(shader, nir_function);
204
205 exec_list_push_tail(&shader->functions, &func->node);
206
207 func->name = ralloc_strdup(func, name);
208 func->shader = shader;
209 func->num_params = 0;
210 func->params = NULL;
211 func->impl = NULL;
212 func->is_entrypoint = false;
213
214 return func;
215 }
216
217 /* NOTE: if the instruction you are copying a src to is already added
218 * to the IR, use nir_instr_rewrite_src() instead.
219 */
220 void nir_src_copy(nir_src *dest, const nir_src *src, void *mem_ctx)
221 {
222 dest->is_ssa = src->is_ssa;
223 if (src->is_ssa) {
224 dest->ssa = src->ssa;
225 } else {
226 dest->reg.base_offset = src->reg.base_offset;
227 dest->reg.reg = src->reg.reg;
228 if (src->reg.indirect) {
229 dest->reg.indirect = ralloc(mem_ctx, nir_src);
230 nir_src_copy(dest->reg.indirect, src->reg.indirect, mem_ctx);
231 } else {
232 dest->reg.indirect = NULL;
233 }
234 }
235 }
236
237 void nir_dest_copy(nir_dest *dest, const nir_dest *src, nir_instr *instr)
238 {
239 /* Copying an SSA definition makes no sense whatsoever. */
240 assert(!src->is_ssa);
241
242 dest->is_ssa = false;
243
244 dest->reg.base_offset = src->reg.base_offset;
245 dest->reg.reg = src->reg.reg;
246 if (src->reg.indirect) {
247 dest->reg.indirect = ralloc(instr, nir_src);
248 nir_src_copy(dest->reg.indirect, src->reg.indirect, instr);
249 } else {
250 dest->reg.indirect = NULL;
251 }
252 }
253
254 void
255 nir_alu_src_copy(nir_alu_src *dest, const nir_alu_src *src,
256 nir_alu_instr *instr)
257 {
258 nir_src_copy(&dest->src, &src->src, &instr->instr);
259 dest->abs = src->abs;
260 dest->negate = src->negate;
261 for (unsigned i = 0; i < NIR_MAX_VEC_COMPONENTS; i++)
262 dest->swizzle[i] = src->swizzle[i];
263 }
264
265 void
266 nir_alu_dest_copy(nir_alu_dest *dest, const nir_alu_dest *src,
267 nir_alu_instr *instr)
268 {
269 nir_dest_copy(&dest->dest, &src->dest, &instr->instr);
270 dest->write_mask = src->write_mask;
271 dest->saturate = src->saturate;
272 }
273
274
275 static void
276 cf_init(nir_cf_node *node, nir_cf_node_type type)
277 {
278 exec_node_init(&node->node);
279 node->parent = NULL;
280 node->type = type;
281 }
282
283 nir_function_impl *
284 nir_function_impl_create_bare(nir_shader *shader)
285 {
286 nir_function_impl *impl = ralloc(shader, nir_function_impl);
287
288 impl->function = NULL;
289
290 cf_init(&impl->cf_node, nir_cf_node_function);
291
292 exec_list_make_empty(&impl->body);
293 exec_list_make_empty(&impl->registers);
294 exec_list_make_empty(&impl->locals);
295 impl->reg_alloc = 0;
296 impl->ssa_alloc = 0;
297 impl->valid_metadata = nir_metadata_none;
298 impl->structured = true;
299
300 /* create start & end blocks */
301 nir_block *start_block = nir_block_create(shader);
302 nir_block *end_block = nir_block_create(shader);
303 start_block->cf_node.parent = &impl->cf_node;
304 end_block->cf_node.parent = &impl->cf_node;
305 impl->end_block = end_block;
306
307 exec_list_push_tail(&impl->body, &start_block->cf_node.node);
308
309 start_block->successors[0] = end_block;
310 _mesa_set_add(end_block->predecessors, start_block);
311 return impl;
312 }
313
314 nir_function_impl *
315 nir_function_impl_create(nir_function *function)
316 {
317 assert(function->impl == NULL);
318
319 nir_function_impl *impl = nir_function_impl_create_bare(function->shader);
320
321 function->impl = impl;
322 impl->function = function;
323
324 return impl;
325 }
326
327 nir_block *
328 nir_block_create(nir_shader *shader)
329 {
330 nir_block *block = rzalloc(shader, nir_block);
331
332 cf_init(&block->cf_node, nir_cf_node_block);
333
334 block->successors[0] = block->successors[1] = NULL;
335 block->predecessors = _mesa_pointer_set_create(block);
336 block->imm_dom = NULL;
337 /* XXX maybe it would be worth it to defer allocation? This
338 * way it doesn't get allocated for shader refs that never run
339 * nir_calc_dominance? For example, state-tracker creates an
340 * initial IR, clones that, runs appropriate lowering pass, passes
341 * to driver which does common lowering/opt, and then stores ref
342 * which is later used to do state specific lowering and futher
343 * opt. Do any of the references not need dominance metadata?
344 */
345 block->dom_frontier = _mesa_pointer_set_create(block);
346
347 exec_list_make_empty(&block->instr_list);
348
349 return block;
350 }
351
352 static inline void
353 src_init(nir_src *src)
354 {
355 src->is_ssa = false;
356 src->reg.reg = NULL;
357 src->reg.indirect = NULL;
358 src->reg.base_offset = 0;
359 }
360
361 nir_if *
362 nir_if_create(nir_shader *shader)
363 {
364 nir_if *if_stmt = ralloc(shader, nir_if);
365
366 if_stmt->control = nir_selection_control_none;
367
368 cf_init(&if_stmt->cf_node, nir_cf_node_if);
369 src_init(&if_stmt->condition);
370
371 nir_block *then = nir_block_create(shader);
372 exec_list_make_empty(&if_stmt->then_list);
373 exec_list_push_tail(&if_stmt->then_list, &then->cf_node.node);
374 then->cf_node.parent = &if_stmt->cf_node;
375
376 nir_block *else_stmt = nir_block_create(shader);
377 exec_list_make_empty(&if_stmt->else_list);
378 exec_list_push_tail(&if_stmt->else_list, &else_stmt->cf_node.node);
379 else_stmt->cf_node.parent = &if_stmt->cf_node;
380
381 return if_stmt;
382 }
383
384 nir_loop *
385 nir_loop_create(nir_shader *shader)
386 {
387 nir_loop *loop = rzalloc(shader, nir_loop);
388
389 cf_init(&loop->cf_node, nir_cf_node_loop);
390
391 nir_block *body = nir_block_create(shader);
392 exec_list_make_empty(&loop->body);
393 exec_list_push_tail(&loop->body, &body->cf_node.node);
394 body->cf_node.parent = &loop->cf_node;
395
396 body->successors[0] = body;
397 _mesa_set_add(body->predecessors, body);
398
399 return loop;
400 }
401
402 static void
403 instr_init(nir_instr *instr, nir_instr_type type)
404 {
405 instr->type = type;
406 instr->block = NULL;
407 exec_node_init(&instr->node);
408 }
409
410 static void
411 dest_init(nir_dest *dest)
412 {
413 dest->is_ssa = false;
414 dest->reg.reg = NULL;
415 dest->reg.indirect = NULL;
416 dest->reg.base_offset = 0;
417 }
418
419 static void
420 alu_dest_init(nir_alu_dest *dest)
421 {
422 dest_init(&dest->dest);
423 dest->saturate = false;
424 dest->write_mask = 0xf;
425 }
426
427 static void
428 alu_src_init(nir_alu_src *src)
429 {
430 src_init(&src->src);
431 src->abs = src->negate = false;
432 for (int i = 0; i < NIR_MAX_VEC_COMPONENTS; ++i)
433 src->swizzle[i] = i;
434 }
435
436 nir_alu_instr *
437 nir_alu_instr_create(nir_shader *shader, nir_op op)
438 {
439 unsigned num_srcs = nir_op_infos[op].num_inputs;
440 /* TODO: don't use rzalloc */
441 nir_alu_instr *instr =
442 rzalloc_size(shader,
443 sizeof(nir_alu_instr) + num_srcs * sizeof(nir_alu_src));
444
445 instr_init(&instr->instr, nir_instr_type_alu);
446 instr->op = op;
447 alu_dest_init(&instr->dest);
448 for (unsigned i = 0; i < num_srcs; i++)
449 alu_src_init(&instr->src[i]);
450
451 return instr;
452 }
453
454 nir_deref_instr *
455 nir_deref_instr_create(nir_shader *shader, nir_deref_type deref_type)
456 {
457 nir_deref_instr *instr =
458 rzalloc_size(shader, sizeof(nir_deref_instr));
459
460 instr_init(&instr->instr, nir_instr_type_deref);
461
462 instr->deref_type = deref_type;
463 if (deref_type != nir_deref_type_var)
464 src_init(&instr->parent);
465
466 if (deref_type == nir_deref_type_array ||
467 deref_type == nir_deref_type_ptr_as_array)
468 src_init(&instr->arr.index);
469
470 dest_init(&instr->dest);
471
472 return instr;
473 }
474
475 nir_jump_instr *
476 nir_jump_instr_create(nir_shader *shader, nir_jump_type type)
477 {
478 nir_jump_instr *instr = ralloc(shader, nir_jump_instr);
479 instr_init(&instr->instr, nir_instr_type_jump);
480 instr->type = type;
481 return instr;
482 }
483
484 nir_load_const_instr *
485 nir_load_const_instr_create(nir_shader *shader, unsigned num_components,
486 unsigned bit_size)
487 {
488 nir_load_const_instr *instr =
489 rzalloc_size(shader, sizeof(*instr) + num_components * sizeof(*instr->value));
490 instr_init(&instr->instr, nir_instr_type_load_const);
491
492 nir_ssa_def_init(&instr->instr, &instr->def, num_components, bit_size, NULL);
493
494 return instr;
495 }
496
497 nir_intrinsic_instr *
498 nir_intrinsic_instr_create(nir_shader *shader, nir_intrinsic_op op)
499 {
500 unsigned num_srcs = nir_intrinsic_infos[op].num_srcs;
501 /* TODO: don't use rzalloc */
502 nir_intrinsic_instr *instr =
503 rzalloc_size(shader,
504 sizeof(nir_intrinsic_instr) + num_srcs * sizeof(nir_src));
505
506 instr_init(&instr->instr, nir_instr_type_intrinsic);
507 instr->intrinsic = op;
508
509 if (nir_intrinsic_infos[op].has_dest)
510 dest_init(&instr->dest);
511
512 for (unsigned i = 0; i < num_srcs; i++)
513 src_init(&instr->src[i]);
514
515 return instr;
516 }
517
518 nir_call_instr *
519 nir_call_instr_create(nir_shader *shader, nir_function *callee)
520 {
521 const unsigned num_params = callee->num_params;
522 nir_call_instr *instr =
523 rzalloc_size(shader, sizeof(*instr) +
524 num_params * sizeof(instr->params[0]));
525
526 instr_init(&instr->instr, nir_instr_type_call);
527 instr->callee = callee;
528 instr->num_params = num_params;
529 for (unsigned i = 0; i < num_params; i++)
530 src_init(&instr->params[i]);
531
532 return instr;
533 }
534
535 static int8_t default_tg4_offsets[4][2] =
536 {
537 { 0, 1 },
538 { 1, 1 },
539 { 1, 0 },
540 { 0, 0 },
541 };
542
543 nir_tex_instr *
544 nir_tex_instr_create(nir_shader *shader, unsigned num_srcs)
545 {
546 nir_tex_instr *instr = rzalloc(shader, nir_tex_instr);
547 instr_init(&instr->instr, nir_instr_type_tex);
548
549 dest_init(&instr->dest);
550
551 instr->num_srcs = num_srcs;
552 instr->src = ralloc_array(instr, nir_tex_src, num_srcs);
553 for (unsigned i = 0; i < num_srcs; i++)
554 src_init(&instr->src[i].src);
555
556 instr->texture_index = 0;
557 instr->sampler_index = 0;
558 memcpy(instr->tg4_offsets, default_tg4_offsets, sizeof(instr->tg4_offsets));
559
560 return instr;
561 }
562
563 void
564 nir_tex_instr_add_src(nir_tex_instr *tex,
565 nir_tex_src_type src_type,
566 nir_src src)
567 {
568 nir_tex_src *new_srcs = rzalloc_array(tex, nir_tex_src,
569 tex->num_srcs + 1);
570
571 for (unsigned i = 0; i < tex->num_srcs; i++) {
572 new_srcs[i].src_type = tex->src[i].src_type;
573 nir_instr_move_src(&tex->instr, &new_srcs[i].src,
574 &tex->src[i].src);
575 }
576
577 ralloc_free(tex->src);
578 tex->src = new_srcs;
579
580 tex->src[tex->num_srcs].src_type = src_type;
581 nir_instr_rewrite_src(&tex->instr, &tex->src[tex->num_srcs].src, src);
582 tex->num_srcs++;
583 }
584
585 void
586 nir_tex_instr_remove_src(nir_tex_instr *tex, unsigned src_idx)
587 {
588 assert(src_idx < tex->num_srcs);
589
590 /* First rewrite the source to NIR_SRC_INIT */
591 nir_instr_rewrite_src(&tex->instr, &tex->src[src_idx].src, NIR_SRC_INIT);
592
593 /* Now, move all of the other sources down */
594 for (unsigned i = src_idx + 1; i < tex->num_srcs; i++) {
595 tex->src[i-1].src_type = tex->src[i].src_type;
596 nir_instr_move_src(&tex->instr, &tex->src[i-1].src, &tex->src[i].src);
597 }
598 tex->num_srcs--;
599 }
600
601 bool
602 nir_tex_instr_has_explicit_tg4_offsets(nir_tex_instr *tex)
603 {
604 if (tex->op != nir_texop_tg4)
605 return false;
606 return memcmp(tex->tg4_offsets, default_tg4_offsets,
607 sizeof(tex->tg4_offsets)) != 0;
608 }
609
610 nir_phi_instr *
611 nir_phi_instr_create(nir_shader *shader)
612 {
613 nir_phi_instr *instr = ralloc(shader, nir_phi_instr);
614 instr_init(&instr->instr, nir_instr_type_phi);
615
616 dest_init(&instr->dest);
617 exec_list_make_empty(&instr->srcs);
618 return instr;
619 }
620
621 nir_parallel_copy_instr *
622 nir_parallel_copy_instr_create(nir_shader *shader)
623 {
624 nir_parallel_copy_instr *instr = ralloc(shader, nir_parallel_copy_instr);
625 instr_init(&instr->instr, nir_instr_type_parallel_copy);
626
627 exec_list_make_empty(&instr->entries);
628
629 return instr;
630 }
631
632 nir_ssa_undef_instr *
633 nir_ssa_undef_instr_create(nir_shader *shader,
634 unsigned num_components,
635 unsigned bit_size)
636 {
637 nir_ssa_undef_instr *instr = ralloc(shader, nir_ssa_undef_instr);
638 instr_init(&instr->instr, nir_instr_type_ssa_undef);
639
640 nir_ssa_def_init(&instr->instr, &instr->def, num_components, bit_size, NULL);
641
642 return instr;
643 }
644
645 static nir_const_value
646 const_value_float(double d, unsigned bit_size)
647 {
648 nir_const_value v;
649 memset(&v, 0, sizeof(v));
650 switch (bit_size) {
651 case 16: v.u16 = _mesa_float_to_half(d); break;
652 case 32: v.f32 = d; break;
653 case 64: v.f64 = d; break;
654 default:
655 unreachable("Invalid bit size");
656 }
657 return v;
658 }
659
660 static nir_const_value
661 const_value_int(int64_t i, unsigned bit_size)
662 {
663 nir_const_value v;
664 memset(&v, 0, sizeof(v));
665 switch (bit_size) {
666 case 1: v.b = i & 1; break;
667 case 8: v.i8 = i; break;
668 case 16: v.i16 = i; break;
669 case 32: v.i32 = i; break;
670 case 64: v.i64 = i; break;
671 default:
672 unreachable("Invalid bit size");
673 }
674 return v;
675 }
676
677 nir_const_value
678 nir_alu_binop_identity(nir_op binop, unsigned bit_size)
679 {
680 const int64_t max_int = (1ull << (bit_size - 1)) - 1;
681 const int64_t min_int = -max_int - 1;
682 switch (binop) {
683 case nir_op_iadd:
684 return const_value_int(0, bit_size);
685 case nir_op_fadd:
686 return const_value_float(0, bit_size);
687 case nir_op_imul:
688 return const_value_int(1, bit_size);
689 case nir_op_fmul:
690 return const_value_float(1, bit_size);
691 case nir_op_imin:
692 return const_value_int(max_int, bit_size);
693 case nir_op_umin:
694 return const_value_int(~0ull, bit_size);
695 case nir_op_fmin:
696 return const_value_float(INFINITY, bit_size);
697 case nir_op_imax:
698 return const_value_int(min_int, bit_size);
699 case nir_op_umax:
700 return const_value_int(0, bit_size);
701 case nir_op_fmax:
702 return const_value_float(-INFINITY, bit_size);
703 case nir_op_iand:
704 return const_value_int(~0ull, bit_size);
705 case nir_op_ior:
706 return const_value_int(0, bit_size);
707 case nir_op_ixor:
708 return const_value_int(0, bit_size);
709 default:
710 unreachable("Invalid reduction operation");
711 }
712 }
713
714 nir_function_impl *
715 nir_cf_node_get_function(nir_cf_node *node)
716 {
717 while (node->type != nir_cf_node_function) {
718 node = node->parent;
719 }
720
721 return nir_cf_node_as_function(node);
722 }
723
724 /* Reduces a cursor by trying to convert everything to after and trying to
725 * go up to block granularity when possible.
726 */
727 static nir_cursor
728 reduce_cursor(nir_cursor cursor)
729 {
730 switch (cursor.option) {
731 case nir_cursor_before_block:
732 assert(nir_cf_node_prev(&cursor.block->cf_node) == NULL ||
733 nir_cf_node_prev(&cursor.block->cf_node)->type != nir_cf_node_block);
734 if (exec_list_is_empty(&cursor.block->instr_list)) {
735 /* Empty block. After is as good as before. */
736 cursor.option = nir_cursor_after_block;
737 }
738 return cursor;
739
740 case nir_cursor_after_block:
741 return cursor;
742
743 case nir_cursor_before_instr: {
744 nir_instr *prev_instr = nir_instr_prev(cursor.instr);
745 if (prev_instr) {
746 /* Before this instruction is after the previous */
747 cursor.instr = prev_instr;
748 cursor.option = nir_cursor_after_instr;
749 } else {
750 /* No previous instruction. Switch to before block */
751 cursor.block = cursor.instr->block;
752 cursor.option = nir_cursor_before_block;
753 }
754 return reduce_cursor(cursor);
755 }
756
757 case nir_cursor_after_instr:
758 if (nir_instr_next(cursor.instr) == NULL) {
759 /* This is the last instruction, switch to after block */
760 cursor.option = nir_cursor_after_block;
761 cursor.block = cursor.instr->block;
762 }
763 return cursor;
764
765 default:
766 unreachable("Inavlid cursor option");
767 }
768 }
769
770 bool
771 nir_cursors_equal(nir_cursor a, nir_cursor b)
772 {
773 /* Reduced cursors should be unique */
774 a = reduce_cursor(a);
775 b = reduce_cursor(b);
776
777 return a.block == b.block && a.option == b.option;
778 }
779
780 static bool
781 add_use_cb(nir_src *src, void *state)
782 {
783 nir_instr *instr = state;
784
785 src->parent_instr = instr;
786 list_addtail(&src->use_link,
787 src->is_ssa ? &src->ssa->uses : &src->reg.reg->uses);
788
789 return true;
790 }
791
792 static bool
793 add_ssa_def_cb(nir_ssa_def *def, void *state)
794 {
795 nir_instr *instr = state;
796
797 if (instr->block && def->index == UINT_MAX) {
798 nir_function_impl *impl =
799 nir_cf_node_get_function(&instr->block->cf_node);
800
801 def->index = impl->ssa_alloc++;
802 }
803
804 return true;
805 }
806
807 static bool
808 add_reg_def_cb(nir_dest *dest, void *state)
809 {
810 nir_instr *instr = state;
811
812 if (!dest->is_ssa) {
813 dest->reg.parent_instr = instr;
814 list_addtail(&dest->reg.def_link, &dest->reg.reg->defs);
815 }
816
817 return true;
818 }
819
820 static void
821 add_defs_uses(nir_instr *instr)
822 {
823 nir_foreach_src(instr, add_use_cb, instr);
824 nir_foreach_dest(instr, add_reg_def_cb, instr);
825 nir_foreach_ssa_def(instr, add_ssa_def_cb, instr);
826 }
827
828 void
829 nir_instr_insert(nir_cursor cursor, nir_instr *instr)
830 {
831 switch (cursor.option) {
832 case nir_cursor_before_block:
833 /* Only allow inserting jumps into empty blocks. */
834 if (instr->type == nir_instr_type_jump)
835 assert(exec_list_is_empty(&cursor.block->instr_list));
836
837 instr->block = cursor.block;
838 add_defs_uses(instr);
839 exec_list_push_head(&cursor.block->instr_list, &instr->node);
840 break;
841 case nir_cursor_after_block: {
842 /* Inserting instructions after a jump is illegal. */
843 nir_instr *last = nir_block_last_instr(cursor.block);
844 assert(last == NULL || last->type != nir_instr_type_jump);
845 (void) last;
846
847 instr->block = cursor.block;
848 add_defs_uses(instr);
849 exec_list_push_tail(&cursor.block->instr_list, &instr->node);
850 break;
851 }
852 case nir_cursor_before_instr:
853 assert(instr->type != nir_instr_type_jump);
854 instr->block = cursor.instr->block;
855 add_defs_uses(instr);
856 exec_node_insert_node_before(&cursor.instr->node, &instr->node);
857 break;
858 case nir_cursor_after_instr:
859 /* Inserting instructions after a jump is illegal. */
860 assert(cursor.instr->type != nir_instr_type_jump);
861
862 /* Only allow inserting jumps at the end of the block. */
863 if (instr->type == nir_instr_type_jump)
864 assert(cursor.instr == nir_block_last_instr(cursor.instr->block));
865
866 instr->block = cursor.instr->block;
867 add_defs_uses(instr);
868 exec_node_insert_after(&cursor.instr->node, &instr->node);
869 break;
870 }
871
872 if (instr->type == nir_instr_type_jump)
873 nir_handle_add_jump(instr->block);
874 }
875
876 static bool
877 src_is_valid(const nir_src *src)
878 {
879 return src->is_ssa ? (src->ssa != NULL) : (src->reg.reg != NULL);
880 }
881
882 static bool
883 remove_use_cb(nir_src *src, void *state)
884 {
885 (void) state;
886
887 if (src_is_valid(src))
888 list_del(&src->use_link);
889
890 return true;
891 }
892
893 static bool
894 remove_def_cb(nir_dest *dest, void *state)
895 {
896 (void) state;
897
898 if (!dest->is_ssa)
899 list_del(&dest->reg.def_link);
900
901 return true;
902 }
903
904 static void
905 remove_defs_uses(nir_instr *instr)
906 {
907 nir_foreach_dest(instr, remove_def_cb, instr);
908 nir_foreach_src(instr, remove_use_cb, instr);
909 }
910
911 void nir_instr_remove_v(nir_instr *instr)
912 {
913 remove_defs_uses(instr);
914 exec_node_remove(&instr->node);
915
916 if (instr->type == nir_instr_type_jump) {
917 nir_jump_instr *jump_instr = nir_instr_as_jump(instr);
918 nir_handle_remove_jump(instr->block, jump_instr->type);
919 }
920 }
921
922 /*@}*/
923
924 void
925 nir_index_local_regs(nir_function_impl *impl)
926 {
927 unsigned index = 0;
928 foreach_list_typed(nir_register, reg, node, &impl->registers) {
929 reg->index = index++;
930 }
931 impl->reg_alloc = index;
932 }
933
934 static bool
935 visit_alu_dest(nir_alu_instr *instr, nir_foreach_dest_cb cb, void *state)
936 {
937 return cb(&instr->dest.dest, state);
938 }
939
940 static bool
941 visit_deref_dest(nir_deref_instr *instr, nir_foreach_dest_cb cb, void *state)
942 {
943 return cb(&instr->dest, state);
944 }
945
946 static bool
947 visit_intrinsic_dest(nir_intrinsic_instr *instr, nir_foreach_dest_cb cb,
948 void *state)
949 {
950 if (nir_intrinsic_infos[instr->intrinsic].has_dest)
951 return cb(&instr->dest, state);
952
953 return true;
954 }
955
956 static bool
957 visit_texture_dest(nir_tex_instr *instr, nir_foreach_dest_cb cb,
958 void *state)
959 {
960 return cb(&instr->dest, state);
961 }
962
963 static bool
964 visit_phi_dest(nir_phi_instr *instr, nir_foreach_dest_cb cb, void *state)
965 {
966 return cb(&instr->dest, state);
967 }
968
969 static bool
970 visit_parallel_copy_dest(nir_parallel_copy_instr *instr,
971 nir_foreach_dest_cb cb, void *state)
972 {
973 nir_foreach_parallel_copy_entry(entry, instr) {
974 if (!cb(&entry->dest, state))
975 return false;
976 }
977
978 return true;
979 }
980
981 bool
982 nir_foreach_dest(nir_instr *instr, nir_foreach_dest_cb cb, void *state)
983 {
984 switch (instr->type) {
985 case nir_instr_type_alu:
986 return visit_alu_dest(nir_instr_as_alu(instr), cb, state);
987 case nir_instr_type_deref:
988 return visit_deref_dest(nir_instr_as_deref(instr), cb, state);
989 case nir_instr_type_intrinsic:
990 return visit_intrinsic_dest(nir_instr_as_intrinsic(instr), cb, state);
991 case nir_instr_type_tex:
992 return visit_texture_dest(nir_instr_as_tex(instr), cb, state);
993 case nir_instr_type_phi:
994 return visit_phi_dest(nir_instr_as_phi(instr), cb, state);
995 case nir_instr_type_parallel_copy:
996 return visit_parallel_copy_dest(nir_instr_as_parallel_copy(instr),
997 cb, state);
998
999 case nir_instr_type_load_const:
1000 case nir_instr_type_ssa_undef:
1001 case nir_instr_type_call:
1002 case nir_instr_type_jump:
1003 break;
1004
1005 default:
1006 unreachable("Invalid instruction type");
1007 break;
1008 }
1009
1010 return true;
1011 }
1012
1013 struct foreach_ssa_def_state {
1014 nir_foreach_ssa_def_cb cb;
1015 void *client_state;
1016 };
1017
1018 static inline bool
1019 nir_ssa_def_visitor(nir_dest *dest, void *void_state)
1020 {
1021 struct foreach_ssa_def_state *state = void_state;
1022
1023 if (dest->is_ssa)
1024 return state->cb(&dest->ssa, state->client_state);
1025 else
1026 return true;
1027 }
1028
1029 bool
1030 nir_foreach_ssa_def(nir_instr *instr, nir_foreach_ssa_def_cb cb, void *state)
1031 {
1032 switch (instr->type) {
1033 case nir_instr_type_alu:
1034 case nir_instr_type_deref:
1035 case nir_instr_type_tex:
1036 case nir_instr_type_intrinsic:
1037 case nir_instr_type_phi:
1038 case nir_instr_type_parallel_copy: {
1039 struct foreach_ssa_def_state foreach_state = {cb, state};
1040 return nir_foreach_dest(instr, nir_ssa_def_visitor, &foreach_state);
1041 }
1042
1043 case nir_instr_type_load_const:
1044 return cb(&nir_instr_as_load_const(instr)->def, state);
1045 case nir_instr_type_ssa_undef:
1046 return cb(&nir_instr_as_ssa_undef(instr)->def, state);
1047 case nir_instr_type_call:
1048 case nir_instr_type_jump:
1049 return true;
1050 default:
1051 unreachable("Invalid instruction type");
1052 }
1053 }
1054
1055 nir_ssa_def *
1056 nir_instr_ssa_def(nir_instr *instr)
1057 {
1058 switch (instr->type) {
1059 case nir_instr_type_alu:
1060 assert(nir_instr_as_alu(instr)->dest.dest.is_ssa);
1061 return &nir_instr_as_alu(instr)->dest.dest.ssa;
1062
1063 case nir_instr_type_deref:
1064 assert(nir_instr_as_deref(instr)->dest.is_ssa);
1065 return &nir_instr_as_deref(instr)->dest.ssa;
1066
1067 case nir_instr_type_tex:
1068 assert(nir_instr_as_tex(instr)->dest.is_ssa);
1069 return &nir_instr_as_tex(instr)->dest.ssa;
1070
1071 case nir_instr_type_intrinsic: {
1072 nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
1073 if (nir_intrinsic_infos[intrin->intrinsic].has_dest) {
1074 assert(intrin->dest.is_ssa);
1075 return &intrin->dest.ssa;
1076 } else {
1077 return NULL;
1078 }
1079 }
1080
1081 case nir_instr_type_phi:
1082 assert(nir_instr_as_phi(instr)->dest.is_ssa);
1083 return &nir_instr_as_phi(instr)->dest.ssa;
1084
1085 case nir_instr_type_parallel_copy:
1086 unreachable("Parallel copies are unsupported by this function");
1087
1088 case nir_instr_type_load_const:
1089 return &nir_instr_as_load_const(instr)->def;
1090
1091 case nir_instr_type_ssa_undef:
1092 return &nir_instr_as_ssa_undef(instr)->def;
1093
1094 case nir_instr_type_call:
1095 case nir_instr_type_jump:
1096 return NULL;
1097 }
1098
1099 unreachable("Invalid instruction type");
1100 }
1101
1102 static bool
1103 visit_src(nir_src *src, nir_foreach_src_cb cb, void *state)
1104 {
1105 if (!cb(src, state))
1106 return false;
1107 if (!src->is_ssa && src->reg.indirect)
1108 return cb(src->reg.indirect, state);
1109 return true;
1110 }
1111
1112 static bool
1113 visit_alu_src(nir_alu_instr *instr, nir_foreach_src_cb cb, void *state)
1114 {
1115 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1116 if (!visit_src(&instr->src[i].src, cb, state))
1117 return false;
1118
1119 return true;
1120 }
1121
1122 static bool
1123 visit_deref_instr_src(nir_deref_instr *instr,
1124 nir_foreach_src_cb cb, void *state)
1125 {
1126 if (instr->deref_type != nir_deref_type_var) {
1127 if (!visit_src(&instr->parent, cb, state))
1128 return false;
1129 }
1130
1131 if (instr->deref_type == nir_deref_type_array ||
1132 instr->deref_type == nir_deref_type_ptr_as_array) {
1133 if (!visit_src(&instr->arr.index, cb, state))
1134 return false;
1135 }
1136
1137 return true;
1138 }
1139
1140 static bool
1141 visit_tex_src(nir_tex_instr *instr, nir_foreach_src_cb cb, void *state)
1142 {
1143 for (unsigned i = 0; i < instr->num_srcs; i++) {
1144 if (!visit_src(&instr->src[i].src, cb, state))
1145 return false;
1146 }
1147
1148 return true;
1149 }
1150
1151 static bool
1152 visit_intrinsic_src(nir_intrinsic_instr *instr, nir_foreach_src_cb cb,
1153 void *state)
1154 {
1155 unsigned num_srcs = nir_intrinsic_infos[instr->intrinsic].num_srcs;
1156 for (unsigned i = 0; i < num_srcs; i++) {
1157 if (!visit_src(&instr->src[i], cb, state))
1158 return false;
1159 }
1160
1161 return true;
1162 }
1163
1164 static bool
1165 visit_call_src(nir_call_instr *instr, nir_foreach_src_cb cb, void *state)
1166 {
1167 for (unsigned i = 0; i < instr->num_params; i++) {
1168 if (!visit_src(&instr->params[i], cb, state))
1169 return false;
1170 }
1171
1172 return true;
1173 }
1174
1175 static bool
1176 visit_phi_src(nir_phi_instr *instr, nir_foreach_src_cb cb, void *state)
1177 {
1178 nir_foreach_phi_src(src, instr) {
1179 if (!visit_src(&src->src, cb, state))
1180 return false;
1181 }
1182
1183 return true;
1184 }
1185
1186 static bool
1187 visit_parallel_copy_src(nir_parallel_copy_instr *instr,
1188 nir_foreach_src_cb cb, void *state)
1189 {
1190 nir_foreach_parallel_copy_entry(entry, instr) {
1191 if (!visit_src(&entry->src, cb, state))
1192 return false;
1193 }
1194
1195 return true;
1196 }
1197
1198 typedef struct {
1199 void *state;
1200 nir_foreach_src_cb cb;
1201 } visit_dest_indirect_state;
1202
1203 static bool
1204 visit_dest_indirect(nir_dest *dest, void *_state)
1205 {
1206 visit_dest_indirect_state *state = (visit_dest_indirect_state *) _state;
1207
1208 if (!dest->is_ssa && dest->reg.indirect)
1209 return state->cb(dest->reg.indirect, state->state);
1210
1211 return true;
1212 }
1213
1214 bool
1215 nir_foreach_src(nir_instr *instr, nir_foreach_src_cb cb, void *state)
1216 {
1217 switch (instr->type) {
1218 case nir_instr_type_alu:
1219 if (!visit_alu_src(nir_instr_as_alu(instr), cb, state))
1220 return false;
1221 break;
1222 case nir_instr_type_deref:
1223 if (!visit_deref_instr_src(nir_instr_as_deref(instr), cb, state))
1224 return false;
1225 break;
1226 case nir_instr_type_intrinsic:
1227 if (!visit_intrinsic_src(nir_instr_as_intrinsic(instr), cb, state))
1228 return false;
1229 break;
1230 case nir_instr_type_tex:
1231 if (!visit_tex_src(nir_instr_as_tex(instr), cb, state))
1232 return false;
1233 break;
1234 case nir_instr_type_call:
1235 if (!visit_call_src(nir_instr_as_call(instr), cb, state))
1236 return false;
1237 break;
1238 case nir_instr_type_load_const:
1239 /* Constant load instructions have no regular sources */
1240 break;
1241 case nir_instr_type_phi:
1242 if (!visit_phi_src(nir_instr_as_phi(instr), cb, state))
1243 return false;
1244 break;
1245 case nir_instr_type_parallel_copy:
1246 if (!visit_parallel_copy_src(nir_instr_as_parallel_copy(instr),
1247 cb, state))
1248 return false;
1249 break;
1250 case nir_instr_type_jump:
1251 case nir_instr_type_ssa_undef:
1252 return true;
1253
1254 default:
1255 unreachable("Invalid instruction type");
1256 break;
1257 }
1258
1259 visit_dest_indirect_state dest_state;
1260 dest_state.state = state;
1261 dest_state.cb = cb;
1262 return nir_foreach_dest(instr, visit_dest_indirect, &dest_state);
1263 }
1264
1265 bool
1266 nir_foreach_phi_src_leaving_block(nir_block *block,
1267 nir_foreach_src_cb cb,
1268 void *state)
1269 {
1270 for (unsigned i = 0; i < ARRAY_SIZE(block->successors); i++) {
1271 if (block->successors[i] == NULL)
1272 continue;
1273
1274 nir_foreach_instr(instr, block->successors[i]) {
1275 if (instr->type != nir_instr_type_phi)
1276 break;
1277
1278 nir_phi_instr *phi = nir_instr_as_phi(instr);
1279 nir_foreach_phi_src(phi_src, phi) {
1280 if (phi_src->pred == block) {
1281 if (!cb(&phi_src->src, state))
1282 return false;
1283 }
1284 }
1285 }
1286 }
1287
1288 return true;
1289 }
1290
1291 nir_const_value
1292 nir_const_value_for_float(double f, unsigned bit_size)
1293 {
1294 nir_const_value v;
1295 memset(&v, 0, sizeof(v));
1296
1297 switch (bit_size) {
1298 case 16:
1299 v.u16 = _mesa_float_to_half(f);
1300 break;
1301 case 32:
1302 v.f32 = f;
1303 break;
1304 case 64:
1305 v.f64 = f;
1306 break;
1307 default:
1308 unreachable("Invalid bit size");
1309 }
1310
1311 return v;
1312 }
1313
1314 double
1315 nir_const_value_as_float(nir_const_value value, unsigned bit_size)
1316 {
1317 switch (bit_size) {
1318 case 16: return _mesa_half_to_float(value.u16);
1319 case 32: return value.f32;
1320 case 64: return value.f64;
1321 default:
1322 unreachable("Invalid bit size");
1323 }
1324 }
1325
1326 nir_const_value *
1327 nir_src_as_const_value(nir_src src)
1328 {
1329 if (!src.is_ssa)
1330 return NULL;
1331
1332 if (src.ssa->parent_instr->type != nir_instr_type_load_const)
1333 return NULL;
1334
1335 nir_load_const_instr *load = nir_instr_as_load_const(src.ssa->parent_instr);
1336
1337 return load->value;
1338 }
1339
1340 /**
1341 * Returns true if the source is known to be dynamically uniform. Otherwise it
1342 * returns false which means it may or may not be dynamically uniform but it
1343 * can't be determined.
1344 */
1345 bool
1346 nir_src_is_dynamically_uniform(nir_src src)
1347 {
1348 if (!src.is_ssa)
1349 return false;
1350
1351 /* Constants are trivially dynamically uniform */
1352 if (src.ssa->parent_instr->type == nir_instr_type_load_const)
1353 return true;
1354
1355 /* As are uniform variables */
1356 if (src.ssa->parent_instr->type == nir_instr_type_intrinsic) {
1357 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(src.ssa->parent_instr);
1358 if (intr->intrinsic == nir_intrinsic_load_uniform &&
1359 nir_src_is_dynamically_uniform(intr->src[0]))
1360 return true;
1361 }
1362
1363 /* Operating together dynamically uniform expressions produces a
1364 * dynamically uniform result
1365 */
1366 if (src.ssa->parent_instr->type == nir_instr_type_alu) {
1367 nir_alu_instr *alu = nir_instr_as_alu(src.ssa->parent_instr);
1368 for (int i = 0; i < nir_op_infos[alu->op].num_inputs; i++) {
1369 if (!nir_src_is_dynamically_uniform(alu->src[i].src))
1370 return false;
1371 }
1372
1373 return true;
1374 }
1375
1376 /* XXX: this could have many more tests, such as when a sampler function is
1377 * called with dynamically uniform arguments.
1378 */
1379 return false;
1380 }
1381
1382 static void
1383 src_remove_all_uses(nir_src *src)
1384 {
1385 for (; src; src = src->is_ssa ? NULL : src->reg.indirect) {
1386 if (!src_is_valid(src))
1387 continue;
1388
1389 list_del(&src->use_link);
1390 }
1391 }
1392
1393 static void
1394 src_add_all_uses(nir_src *src, nir_instr *parent_instr, nir_if *parent_if)
1395 {
1396 for (; src; src = src->is_ssa ? NULL : src->reg.indirect) {
1397 if (!src_is_valid(src))
1398 continue;
1399
1400 if (parent_instr) {
1401 src->parent_instr = parent_instr;
1402 if (src->is_ssa)
1403 list_addtail(&src->use_link, &src->ssa->uses);
1404 else
1405 list_addtail(&src->use_link, &src->reg.reg->uses);
1406 } else {
1407 assert(parent_if);
1408 src->parent_if = parent_if;
1409 if (src->is_ssa)
1410 list_addtail(&src->use_link, &src->ssa->if_uses);
1411 else
1412 list_addtail(&src->use_link, &src->reg.reg->if_uses);
1413 }
1414 }
1415 }
1416
1417 void
1418 nir_instr_rewrite_src(nir_instr *instr, nir_src *src, nir_src new_src)
1419 {
1420 assert(!src_is_valid(src) || src->parent_instr == instr);
1421
1422 src_remove_all_uses(src);
1423 *src = new_src;
1424 src_add_all_uses(src, instr, NULL);
1425 }
1426
1427 void
1428 nir_instr_move_src(nir_instr *dest_instr, nir_src *dest, nir_src *src)
1429 {
1430 assert(!src_is_valid(dest) || dest->parent_instr == dest_instr);
1431
1432 src_remove_all_uses(dest);
1433 src_remove_all_uses(src);
1434 *dest = *src;
1435 *src = NIR_SRC_INIT;
1436 src_add_all_uses(dest, dest_instr, NULL);
1437 }
1438
1439 void
1440 nir_if_rewrite_condition(nir_if *if_stmt, nir_src new_src)
1441 {
1442 nir_src *src = &if_stmt->condition;
1443 assert(!src_is_valid(src) || src->parent_if == if_stmt);
1444
1445 src_remove_all_uses(src);
1446 *src = new_src;
1447 src_add_all_uses(src, NULL, if_stmt);
1448 }
1449
1450 void
1451 nir_instr_rewrite_dest(nir_instr *instr, nir_dest *dest, nir_dest new_dest)
1452 {
1453 if (dest->is_ssa) {
1454 /* We can only overwrite an SSA destination if it has no uses. */
1455 assert(list_is_empty(&dest->ssa.uses) && list_is_empty(&dest->ssa.if_uses));
1456 } else {
1457 list_del(&dest->reg.def_link);
1458 if (dest->reg.indirect)
1459 src_remove_all_uses(dest->reg.indirect);
1460 }
1461
1462 /* We can't re-write with an SSA def */
1463 assert(!new_dest.is_ssa);
1464
1465 nir_dest_copy(dest, &new_dest, instr);
1466
1467 dest->reg.parent_instr = instr;
1468 list_addtail(&dest->reg.def_link, &new_dest.reg.reg->defs);
1469
1470 if (dest->reg.indirect)
1471 src_add_all_uses(dest->reg.indirect, instr, NULL);
1472 }
1473
1474 /* note: does *not* take ownership of 'name' */
1475 void
1476 nir_ssa_def_init(nir_instr *instr, nir_ssa_def *def,
1477 unsigned num_components,
1478 unsigned bit_size, const char *name)
1479 {
1480 def->name = ralloc_strdup(instr, name);
1481 def->parent_instr = instr;
1482 list_inithead(&def->uses);
1483 list_inithead(&def->if_uses);
1484 def->num_components = num_components;
1485 def->bit_size = bit_size;
1486 def->divergent = true; /* This is the safer default */
1487
1488 if (instr->block) {
1489 nir_function_impl *impl =
1490 nir_cf_node_get_function(&instr->block->cf_node);
1491
1492 def->index = impl->ssa_alloc++;
1493 } else {
1494 def->index = UINT_MAX;
1495 }
1496 }
1497
1498 /* note: does *not* take ownership of 'name' */
1499 void
1500 nir_ssa_dest_init(nir_instr *instr, nir_dest *dest,
1501 unsigned num_components, unsigned bit_size,
1502 const char *name)
1503 {
1504 dest->is_ssa = true;
1505 nir_ssa_def_init(instr, &dest->ssa, num_components, bit_size, name);
1506 }
1507
1508 void
1509 nir_ssa_def_rewrite_uses(nir_ssa_def *def, nir_src new_src)
1510 {
1511 assert(!new_src.is_ssa || def != new_src.ssa);
1512
1513 nir_foreach_use_safe(use_src, def)
1514 nir_instr_rewrite_src(use_src->parent_instr, use_src, new_src);
1515
1516 nir_foreach_if_use_safe(use_src, def)
1517 nir_if_rewrite_condition(use_src->parent_if, new_src);
1518 }
1519
1520 static bool
1521 is_instr_between(nir_instr *start, nir_instr *end, nir_instr *between)
1522 {
1523 assert(start->block == end->block);
1524
1525 if (between->block != start->block)
1526 return false;
1527
1528 /* Search backwards looking for "between" */
1529 while (start != end) {
1530 if (between == end)
1531 return true;
1532
1533 end = nir_instr_prev(end);
1534 assert(end);
1535 }
1536
1537 return false;
1538 }
1539
1540 /* Replaces all uses of the given SSA def with the given source but only if
1541 * the use comes after the after_me instruction. This can be useful if you
1542 * are emitting code to fix up the result of some instruction: you can freely
1543 * use the result in that code and then call rewrite_uses_after and pass the
1544 * last fixup instruction as after_me and it will replace all of the uses you
1545 * want without touching the fixup code.
1546 *
1547 * This function assumes that after_me is in the same block as
1548 * def->parent_instr and that after_me comes after def->parent_instr.
1549 */
1550 void
1551 nir_ssa_def_rewrite_uses_after(nir_ssa_def *def, nir_src new_src,
1552 nir_instr *after_me)
1553 {
1554 if (new_src.is_ssa && def == new_src.ssa)
1555 return;
1556
1557 nir_foreach_use_safe(use_src, def) {
1558 assert(use_src->parent_instr != def->parent_instr);
1559 /* Since def already dominates all of its uses, the only way a use can
1560 * not be dominated by after_me is if it is between def and after_me in
1561 * the instruction list.
1562 */
1563 if (!is_instr_between(def->parent_instr, after_me, use_src->parent_instr))
1564 nir_instr_rewrite_src(use_src->parent_instr, use_src, new_src);
1565 }
1566
1567 nir_foreach_if_use_safe(use_src, def)
1568 nir_if_rewrite_condition(use_src->parent_if, new_src);
1569 }
1570
1571 nir_component_mask_t
1572 nir_ssa_def_components_read(const nir_ssa_def *def)
1573 {
1574 nir_component_mask_t read_mask = 0;
1575 nir_foreach_use(use, def) {
1576 if (use->parent_instr->type == nir_instr_type_alu) {
1577 nir_alu_instr *alu = nir_instr_as_alu(use->parent_instr);
1578 nir_alu_src *alu_src = exec_node_data(nir_alu_src, use, src);
1579 int src_idx = alu_src - &alu->src[0];
1580 assert(src_idx >= 0 && src_idx < nir_op_infos[alu->op].num_inputs);
1581 read_mask |= nir_alu_instr_src_read_mask(alu, src_idx);
1582 } else {
1583 return (1 << def->num_components) - 1;
1584 }
1585 }
1586
1587 if (!list_is_empty(&def->if_uses))
1588 read_mask |= 1;
1589
1590 return read_mask;
1591 }
1592
1593 nir_block *
1594 nir_block_cf_tree_next(nir_block *block)
1595 {
1596 if (block == NULL) {
1597 /* nir_foreach_block_safe() will call this function on a NULL block
1598 * after the last iteration, but it won't use the result so just return
1599 * NULL here.
1600 */
1601 return NULL;
1602 }
1603
1604 assert(nir_cf_node_get_function(&block->cf_node)->structured);
1605
1606 nir_cf_node *cf_next = nir_cf_node_next(&block->cf_node);
1607 if (cf_next)
1608 return nir_cf_node_cf_tree_first(cf_next);
1609
1610 nir_cf_node *parent = block->cf_node.parent;
1611
1612 switch (parent->type) {
1613 case nir_cf_node_if: {
1614 /* Are we at the end of the if? Go to the beginning of the else */
1615 nir_if *if_stmt = nir_cf_node_as_if(parent);
1616 if (block == nir_if_last_then_block(if_stmt))
1617 return nir_if_first_else_block(if_stmt);
1618
1619 assert(block == nir_if_last_else_block(if_stmt));
1620 }
1621 /* fallthrough */
1622
1623 case nir_cf_node_loop:
1624 return nir_cf_node_as_block(nir_cf_node_next(parent));
1625
1626 case nir_cf_node_function:
1627 return NULL;
1628
1629 default:
1630 unreachable("unknown cf node type");
1631 }
1632 }
1633
1634 nir_block *
1635 nir_block_cf_tree_prev(nir_block *block)
1636 {
1637 if (block == NULL) {
1638 /* do this for consistency with nir_block_cf_tree_next() */
1639 return NULL;
1640 }
1641
1642 assert(nir_cf_node_get_function(&block->cf_node)->structured);
1643
1644 nir_cf_node *cf_prev = nir_cf_node_prev(&block->cf_node);
1645 if (cf_prev)
1646 return nir_cf_node_cf_tree_last(cf_prev);
1647
1648 nir_cf_node *parent = block->cf_node.parent;
1649
1650 switch (parent->type) {
1651 case nir_cf_node_if: {
1652 /* Are we at the beginning of the else? Go to the end of the if */
1653 nir_if *if_stmt = nir_cf_node_as_if(parent);
1654 if (block == nir_if_first_else_block(if_stmt))
1655 return nir_if_last_then_block(if_stmt);
1656
1657 assert(block == nir_if_first_then_block(if_stmt));
1658 }
1659 /* fallthrough */
1660
1661 case nir_cf_node_loop:
1662 return nir_cf_node_as_block(nir_cf_node_prev(parent));
1663
1664 case nir_cf_node_function:
1665 return NULL;
1666
1667 default:
1668 unreachable("unknown cf node type");
1669 }
1670 }
1671
1672 nir_block *nir_cf_node_cf_tree_first(nir_cf_node *node)
1673 {
1674 switch (node->type) {
1675 case nir_cf_node_function: {
1676 nir_function_impl *impl = nir_cf_node_as_function(node);
1677 return nir_start_block(impl);
1678 }
1679
1680 case nir_cf_node_if: {
1681 nir_if *if_stmt = nir_cf_node_as_if(node);
1682 return nir_if_first_then_block(if_stmt);
1683 }
1684
1685 case nir_cf_node_loop: {
1686 nir_loop *loop = nir_cf_node_as_loop(node);
1687 return nir_loop_first_block(loop);
1688 }
1689
1690 case nir_cf_node_block: {
1691 return nir_cf_node_as_block(node);
1692 }
1693
1694 default:
1695 unreachable("unknown node type");
1696 }
1697 }
1698
1699 nir_block *nir_cf_node_cf_tree_last(nir_cf_node *node)
1700 {
1701 switch (node->type) {
1702 case nir_cf_node_function: {
1703 nir_function_impl *impl = nir_cf_node_as_function(node);
1704 return nir_impl_last_block(impl);
1705 }
1706
1707 case nir_cf_node_if: {
1708 nir_if *if_stmt = nir_cf_node_as_if(node);
1709 return nir_if_last_else_block(if_stmt);
1710 }
1711
1712 case nir_cf_node_loop: {
1713 nir_loop *loop = nir_cf_node_as_loop(node);
1714 return nir_loop_last_block(loop);
1715 }
1716
1717 case nir_cf_node_block: {
1718 return nir_cf_node_as_block(node);
1719 }
1720
1721 default:
1722 unreachable("unknown node type");
1723 }
1724 }
1725
1726 nir_block *nir_cf_node_cf_tree_next(nir_cf_node *node)
1727 {
1728 if (node->type == nir_cf_node_block)
1729 return nir_block_cf_tree_next(nir_cf_node_as_block(node));
1730 else if (node->type == nir_cf_node_function)
1731 return NULL;
1732 else
1733 return nir_cf_node_as_block(nir_cf_node_next(node));
1734 }
1735
1736 nir_if *
1737 nir_block_get_following_if(nir_block *block)
1738 {
1739 if (exec_node_is_tail_sentinel(&block->cf_node.node))
1740 return NULL;
1741
1742 if (nir_cf_node_is_last(&block->cf_node))
1743 return NULL;
1744
1745 nir_cf_node *next_node = nir_cf_node_next(&block->cf_node);
1746
1747 if (next_node->type != nir_cf_node_if)
1748 return NULL;
1749
1750 return nir_cf_node_as_if(next_node);
1751 }
1752
1753 nir_loop *
1754 nir_block_get_following_loop(nir_block *block)
1755 {
1756 if (exec_node_is_tail_sentinel(&block->cf_node.node))
1757 return NULL;
1758
1759 if (nir_cf_node_is_last(&block->cf_node))
1760 return NULL;
1761
1762 nir_cf_node *next_node = nir_cf_node_next(&block->cf_node);
1763
1764 if (next_node->type != nir_cf_node_loop)
1765 return NULL;
1766
1767 return nir_cf_node_as_loop(next_node);
1768 }
1769
1770 void
1771 nir_index_blocks(nir_function_impl *impl)
1772 {
1773 unsigned index = 0;
1774
1775 if (impl->valid_metadata & nir_metadata_block_index)
1776 return;
1777
1778 nir_foreach_block(block, impl) {
1779 block->index = index++;
1780 }
1781
1782 /* The end_block isn't really part of the program, which is why its index
1783 * is >= num_blocks.
1784 */
1785 impl->num_blocks = impl->end_block->index = index;
1786 }
1787
1788 static bool
1789 index_ssa_def_cb(nir_ssa_def *def, void *state)
1790 {
1791 unsigned *index = (unsigned *) state;
1792 def->index = (*index)++;
1793
1794 return true;
1795 }
1796
1797 /**
1798 * The indices are applied top-to-bottom which has the very nice property
1799 * that, if A dominates B, then A->index <= B->index.
1800 */
1801 void
1802 nir_index_ssa_defs(nir_function_impl *impl)
1803 {
1804 unsigned index = 0;
1805
1806 nir_foreach_block(block, impl) {
1807 nir_foreach_instr(instr, block)
1808 nir_foreach_ssa_def(instr, index_ssa_def_cb, &index);
1809 }
1810
1811 impl->ssa_alloc = index;
1812 }
1813
1814 /**
1815 * The indices are applied top-to-bottom which has the very nice property
1816 * that, if A dominates B, then A->index <= B->index.
1817 */
1818 unsigned
1819 nir_index_instrs(nir_function_impl *impl)
1820 {
1821 unsigned index = 0;
1822
1823 nir_foreach_block(block, impl) {
1824 nir_foreach_instr(instr, block)
1825 instr->index = index++;
1826 }
1827
1828 return index;
1829 }
1830
1831 unsigned
1832 nir_shader_index_vars(nir_shader *shader, nir_variable_mode modes)
1833 {
1834 unsigned count = 0;
1835 nir_foreach_variable_with_modes(var, shader, modes)
1836 var->index = count++;
1837 return count;
1838 }
1839
1840 unsigned
1841 nir_function_impl_index_vars(nir_function_impl *impl)
1842 {
1843 unsigned count = 0;
1844 nir_foreach_function_temp_variable(var, impl)
1845 var->index = count++;
1846 return count;
1847 }
1848
1849 static nir_instr *
1850 cursor_next_instr(nir_cursor cursor)
1851 {
1852 switch (cursor.option) {
1853 case nir_cursor_before_block:
1854 for (nir_block *block = cursor.block; block;
1855 block = nir_block_cf_tree_next(block)) {
1856 nir_instr *instr = nir_block_first_instr(block);
1857 if (instr)
1858 return instr;
1859 }
1860 return NULL;
1861
1862 case nir_cursor_after_block:
1863 cursor.block = nir_block_cf_tree_next(cursor.block);
1864 if (cursor.block == NULL)
1865 return NULL;
1866
1867 cursor.option = nir_cursor_before_block;
1868 return cursor_next_instr(cursor);
1869
1870 case nir_cursor_before_instr:
1871 return cursor.instr;
1872
1873 case nir_cursor_after_instr:
1874 if (nir_instr_next(cursor.instr))
1875 return nir_instr_next(cursor.instr);
1876
1877 cursor.option = nir_cursor_after_block;
1878 cursor.block = cursor.instr->block;
1879 return cursor_next_instr(cursor);
1880 }
1881
1882 unreachable("Inavlid cursor option");
1883 }
1884
1885 ASSERTED static bool
1886 dest_is_ssa(nir_dest *dest, void *_state)
1887 {
1888 (void) _state;
1889 return dest->is_ssa;
1890 }
1891
1892 bool
1893 nir_function_impl_lower_instructions(nir_function_impl *impl,
1894 nir_instr_filter_cb filter,
1895 nir_lower_instr_cb lower,
1896 void *cb_data)
1897 {
1898 nir_builder b;
1899 nir_builder_init(&b, impl);
1900
1901 nir_metadata preserved = nir_metadata_block_index |
1902 nir_metadata_dominance;
1903
1904 bool progress = false;
1905 nir_cursor iter = nir_before_cf_list(&impl->body);
1906 nir_instr *instr;
1907 while ((instr = cursor_next_instr(iter)) != NULL) {
1908 if (filter && !filter(instr, cb_data)) {
1909 iter = nir_after_instr(instr);
1910 continue;
1911 }
1912
1913 assert(nir_foreach_dest(instr, dest_is_ssa, NULL));
1914 nir_ssa_def *old_def = nir_instr_ssa_def(instr);
1915 if (old_def == NULL) {
1916 iter = nir_after_instr(instr);
1917 continue;
1918 }
1919
1920 /* We're about to ask the callback to generate a replacement for instr.
1921 * Save off the uses from instr's SSA def so we know what uses to
1922 * rewrite later. If we use nir_ssa_def_rewrite_uses, it fails in the
1923 * case where the generated replacement code uses the result of instr
1924 * itself. If we use nir_ssa_def_rewrite_uses_after (which is the
1925 * normal solution to this problem), it doesn't work well if control-
1926 * flow is inserted as part of the replacement, doesn't handle cases
1927 * where the replacement is something consumed by instr, and suffers
1928 * from performance issues. This is the only way to 100% guarantee
1929 * that we rewrite the correct set efficiently.
1930 */
1931 struct list_head old_uses, old_if_uses;
1932 list_replace(&old_def->uses, &old_uses);
1933 list_inithead(&old_def->uses);
1934 list_replace(&old_def->if_uses, &old_if_uses);
1935 list_inithead(&old_def->if_uses);
1936
1937 b.cursor = nir_after_instr(instr);
1938 nir_ssa_def *new_def = lower(&b, instr, cb_data);
1939 if (new_def && new_def != NIR_LOWER_INSTR_PROGRESS) {
1940 assert(old_def != NULL);
1941 if (new_def->parent_instr->block != instr->block)
1942 preserved = nir_metadata_none;
1943
1944 nir_src new_src = nir_src_for_ssa(new_def);
1945 list_for_each_entry_safe(nir_src, use_src, &old_uses, use_link)
1946 nir_instr_rewrite_src(use_src->parent_instr, use_src, new_src);
1947
1948 list_for_each_entry_safe(nir_src, use_src, &old_if_uses, use_link)
1949 nir_if_rewrite_condition(use_src->parent_if, new_src);
1950
1951 if (list_is_empty(&old_def->uses) && list_is_empty(&old_def->if_uses)) {
1952 iter = nir_instr_remove(instr);
1953 } else {
1954 iter = nir_after_instr(instr);
1955 }
1956 progress = true;
1957 } else {
1958 /* We didn't end up lowering after all. Put the uses back */
1959 if (old_def) {
1960 list_replace(&old_uses, &old_def->uses);
1961 list_replace(&old_if_uses, &old_def->if_uses);
1962 }
1963 iter = nir_after_instr(instr);
1964
1965 if (new_def == NIR_LOWER_INSTR_PROGRESS)
1966 progress = true;
1967 }
1968 }
1969
1970 if (progress) {
1971 nir_metadata_preserve(impl, preserved);
1972 } else {
1973 nir_metadata_preserve(impl, nir_metadata_all);
1974 }
1975
1976 return progress;
1977 }
1978
1979 bool
1980 nir_shader_lower_instructions(nir_shader *shader,
1981 nir_instr_filter_cb filter,
1982 nir_lower_instr_cb lower,
1983 void *cb_data)
1984 {
1985 bool progress = false;
1986
1987 nir_foreach_function(function, shader) {
1988 if (function->impl &&
1989 nir_function_impl_lower_instructions(function->impl,
1990 filter, lower, cb_data))
1991 progress = true;
1992 }
1993
1994 return progress;
1995 }
1996
1997 nir_intrinsic_op
1998 nir_intrinsic_from_system_value(gl_system_value val)
1999 {
2000 switch (val) {
2001 case SYSTEM_VALUE_VERTEX_ID:
2002 return nir_intrinsic_load_vertex_id;
2003 case SYSTEM_VALUE_INSTANCE_ID:
2004 return nir_intrinsic_load_instance_id;
2005 case SYSTEM_VALUE_DRAW_ID:
2006 return nir_intrinsic_load_draw_id;
2007 case SYSTEM_VALUE_BASE_INSTANCE:
2008 return nir_intrinsic_load_base_instance;
2009 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
2010 return nir_intrinsic_load_vertex_id_zero_base;
2011 case SYSTEM_VALUE_IS_INDEXED_DRAW:
2012 return nir_intrinsic_load_is_indexed_draw;
2013 case SYSTEM_VALUE_FIRST_VERTEX:
2014 return nir_intrinsic_load_first_vertex;
2015 case SYSTEM_VALUE_BASE_VERTEX:
2016 return nir_intrinsic_load_base_vertex;
2017 case SYSTEM_VALUE_INVOCATION_ID:
2018 return nir_intrinsic_load_invocation_id;
2019 case SYSTEM_VALUE_FRAG_COORD:
2020 return nir_intrinsic_load_frag_coord;
2021 case SYSTEM_VALUE_POINT_COORD:
2022 return nir_intrinsic_load_point_coord;
2023 case SYSTEM_VALUE_LINE_COORD:
2024 return nir_intrinsic_load_line_coord;
2025 case SYSTEM_VALUE_FRONT_FACE:
2026 return nir_intrinsic_load_front_face;
2027 case SYSTEM_VALUE_SAMPLE_ID:
2028 return nir_intrinsic_load_sample_id;
2029 case SYSTEM_VALUE_SAMPLE_POS:
2030 return nir_intrinsic_load_sample_pos;
2031 case SYSTEM_VALUE_SAMPLE_MASK_IN:
2032 return nir_intrinsic_load_sample_mask_in;
2033 case SYSTEM_VALUE_LOCAL_INVOCATION_ID:
2034 return nir_intrinsic_load_local_invocation_id;
2035 case SYSTEM_VALUE_LOCAL_INVOCATION_INDEX:
2036 return nir_intrinsic_load_local_invocation_index;
2037 case SYSTEM_VALUE_WORK_GROUP_ID:
2038 return nir_intrinsic_load_work_group_id;
2039 case SYSTEM_VALUE_NUM_WORK_GROUPS:
2040 return nir_intrinsic_load_num_work_groups;
2041 case SYSTEM_VALUE_PRIMITIVE_ID:
2042 return nir_intrinsic_load_primitive_id;
2043 case SYSTEM_VALUE_TESS_COORD:
2044 return nir_intrinsic_load_tess_coord;
2045 case SYSTEM_VALUE_TESS_LEVEL_OUTER:
2046 return nir_intrinsic_load_tess_level_outer;
2047 case SYSTEM_VALUE_TESS_LEVEL_INNER:
2048 return nir_intrinsic_load_tess_level_inner;
2049 case SYSTEM_VALUE_TESS_LEVEL_OUTER_DEFAULT:
2050 return nir_intrinsic_load_tess_level_outer_default;
2051 case SYSTEM_VALUE_TESS_LEVEL_INNER_DEFAULT:
2052 return nir_intrinsic_load_tess_level_inner_default;
2053 case SYSTEM_VALUE_VERTICES_IN:
2054 return nir_intrinsic_load_patch_vertices_in;
2055 case SYSTEM_VALUE_HELPER_INVOCATION:
2056 return nir_intrinsic_load_helper_invocation;
2057 case SYSTEM_VALUE_COLOR0:
2058 return nir_intrinsic_load_color0;
2059 case SYSTEM_VALUE_COLOR1:
2060 return nir_intrinsic_load_color1;
2061 case SYSTEM_VALUE_VIEW_INDEX:
2062 return nir_intrinsic_load_view_index;
2063 case SYSTEM_VALUE_SUBGROUP_SIZE:
2064 return nir_intrinsic_load_subgroup_size;
2065 case SYSTEM_VALUE_SUBGROUP_INVOCATION:
2066 return nir_intrinsic_load_subgroup_invocation;
2067 case SYSTEM_VALUE_SUBGROUP_EQ_MASK:
2068 return nir_intrinsic_load_subgroup_eq_mask;
2069 case SYSTEM_VALUE_SUBGROUP_GE_MASK:
2070 return nir_intrinsic_load_subgroup_ge_mask;
2071 case SYSTEM_VALUE_SUBGROUP_GT_MASK:
2072 return nir_intrinsic_load_subgroup_gt_mask;
2073 case SYSTEM_VALUE_SUBGROUP_LE_MASK:
2074 return nir_intrinsic_load_subgroup_le_mask;
2075 case SYSTEM_VALUE_SUBGROUP_LT_MASK:
2076 return nir_intrinsic_load_subgroup_lt_mask;
2077 case SYSTEM_VALUE_NUM_SUBGROUPS:
2078 return nir_intrinsic_load_num_subgroups;
2079 case SYSTEM_VALUE_SUBGROUP_ID:
2080 return nir_intrinsic_load_subgroup_id;
2081 case SYSTEM_VALUE_LOCAL_GROUP_SIZE:
2082 return nir_intrinsic_load_local_group_size;
2083 case SYSTEM_VALUE_GLOBAL_INVOCATION_ID:
2084 return nir_intrinsic_load_global_invocation_id;
2085 case SYSTEM_VALUE_GLOBAL_INVOCATION_INDEX:
2086 return nir_intrinsic_load_global_invocation_index;
2087 case SYSTEM_VALUE_WORK_DIM:
2088 return nir_intrinsic_load_work_dim;
2089 case SYSTEM_VALUE_USER_DATA_AMD:
2090 return nir_intrinsic_load_user_data_amd;
2091 default:
2092 unreachable("system value does not directly correspond to intrinsic");
2093 }
2094 }
2095
2096 gl_system_value
2097 nir_system_value_from_intrinsic(nir_intrinsic_op intrin)
2098 {
2099 switch (intrin) {
2100 case nir_intrinsic_load_vertex_id:
2101 return SYSTEM_VALUE_VERTEX_ID;
2102 case nir_intrinsic_load_instance_id:
2103 return SYSTEM_VALUE_INSTANCE_ID;
2104 case nir_intrinsic_load_draw_id:
2105 return SYSTEM_VALUE_DRAW_ID;
2106 case nir_intrinsic_load_base_instance:
2107 return SYSTEM_VALUE_BASE_INSTANCE;
2108 case nir_intrinsic_load_vertex_id_zero_base:
2109 return SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
2110 case nir_intrinsic_load_first_vertex:
2111 return SYSTEM_VALUE_FIRST_VERTEX;
2112 case nir_intrinsic_load_is_indexed_draw:
2113 return SYSTEM_VALUE_IS_INDEXED_DRAW;
2114 case nir_intrinsic_load_base_vertex:
2115 return SYSTEM_VALUE_BASE_VERTEX;
2116 case nir_intrinsic_load_invocation_id:
2117 return SYSTEM_VALUE_INVOCATION_ID;
2118 case nir_intrinsic_load_frag_coord:
2119 return SYSTEM_VALUE_FRAG_COORD;
2120 case nir_intrinsic_load_point_coord:
2121 return SYSTEM_VALUE_POINT_COORD;
2122 case nir_intrinsic_load_line_coord:
2123 return SYSTEM_VALUE_LINE_COORD;
2124 case nir_intrinsic_load_front_face:
2125 return SYSTEM_VALUE_FRONT_FACE;
2126 case nir_intrinsic_load_sample_id:
2127 return SYSTEM_VALUE_SAMPLE_ID;
2128 case nir_intrinsic_load_sample_pos:
2129 return SYSTEM_VALUE_SAMPLE_POS;
2130 case nir_intrinsic_load_sample_mask_in:
2131 return SYSTEM_VALUE_SAMPLE_MASK_IN;
2132 case nir_intrinsic_load_local_invocation_id:
2133 return SYSTEM_VALUE_LOCAL_INVOCATION_ID;
2134 case nir_intrinsic_load_local_invocation_index:
2135 return SYSTEM_VALUE_LOCAL_INVOCATION_INDEX;
2136 case nir_intrinsic_load_num_work_groups:
2137 return SYSTEM_VALUE_NUM_WORK_GROUPS;
2138 case nir_intrinsic_load_work_group_id:
2139 return SYSTEM_VALUE_WORK_GROUP_ID;
2140 case nir_intrinsic_load_primitive_id:
2141 return SYSTEM_VALUE_PRIMITIVE_ID;
2142 case nir_intrinsic_load_tess_coord:
2143 return SYSTEM_VALUE_TESS_COORD;
2144 case nir_intrinsic_load_tess_level_outer:
2145 return SYSTEM_VALUE_TESS_LEVEL_OUTER;
2146 case nir_intrinsic_load_tess_level_inner:
2147 return SYSTEM_VALUE_TESS_LEVEL_INNER;
2148 case nir_intrinsic_load_tess_level_outer_default:
2149 return SYSTEM_VALUE_TESS_LEVEL_OUTER_DEFAULT;
2150 case nir_intrinsic_load_tess_level_inner_default:
2151 return SYSTEM_VALUE_TESS_LEVEL_INNER_DEFAULT;
2152 case nir_intrinsic_load_patch_vertices_in:
2153 return SYSTEM_VALUE_VERTICES_IN;
2154 case nir_intrinsic_load_helper_invocation:
2155 return SYSTEM_VALUE_HELPER_INVOCATION;
2156 case nir_intrinsic_load_color0:
2157 return SYSTEM_VALUE_COLOR0;
2158 case nir_intrinsic_load_color1:
2159 return SYSTEM_VALUE_COLOR1;
2160 case nir_intrinsic_load_view_index:
2161 return SYSTEM_VALUE_VIEW_INDEX;
2162 case nir_intrinsic_load_subgroup_size:
2163 return SYSTEM_VALUE_SUBGROUP_SIZE;
2164 case nir_intrinsic_load_subgroup_invocation:
2165 return SYSTEM_VALUE_SUBGROUP_INVOCATION;
2166 case nir_intrinsic_load_subgroup_eq_mask:
2167 return SYSTEM_VALUE_SUBGROUP_EQ_MASK;
2168 case nir_intrinsic_load_subgroup_ge_mask:
2169 return SYSTEM_VALUE_SUBGROUP_GE_MASK;
2170 case nir_intrinsic_load_subgroup_gt_mask:
2171 return SYSTEM_VALUE_SUBGROUP_GT_MASK;
2172 case nir_intrinsic_load_subgroup_le_mask:
2173 return SYSTEM_VALUE_SUBGROUP_LE_MASK;
2174 case nir_intrinsic_load_subgroup_lt_mask:
2175 return SYSTEM_VALUE_SUBGROUP_LT_MASK;
2176 case nir_intrinsic_load_num_subgroups:
2177 return SYSTEM_VALUE_NUM_SUBGROUPS;
2178 case nir_intrinsic_load_subgroup_id:
2179 return SYSTEM_VALUE_SUBGROUP_ID;
2180 case nir_intrinsic_load_local_group_size:
2181 return SYSTEM_VALUE_LOCAL_GROUP_SIZE;
2182 case nir_intrinsic_load_global_invocation_id:
2183 return SYSTEM_VALUE_GLOBAL_INVOCATION_ID;
2184 case nir_intrinsic_load_user_data_amd:
2185 return SYSTEM_VALUE_USER_DATA_AMD;
2186 default:
2187 unreachable("intrinsic doesn't produce a system value");
2188 }
2189 }
2190
2191 /* OpenGL utility method that remaps the location attributes if they are
2192 * doubles. Not needed for vulkan due the differences on the input location
2193 * count for doubles on vulkan vs OpenGL
2194 *
2195 * The bitfield returned in dual_slot is one bit for each double input slot in
2196 * the original OpenGL single-slot input numbering. The mapping from old
2197 * locations to new locations is as follows:
2198 *
2199 * new_loc = loc + util_bitcount(dual_slot & BITFIELD64_MASK(loc))
2200 */
2201 void
2202 nir_remap_dual_slot_attributes(nir_shader *shader, uint64_t *dual_slot)
2203 {
2204 assert(shader->info.stage == MESA_SHADER_VERTEX);
2205
2206 *dual_slot = 0;
2207 nir_foreach_shader_in_variable(var, shader) {
2208 if (glsl_type_is_dual_slot(glsl_without_array(var->type))) {
2209 unsigned slots = glsl_count_attribute_slots(var->type, true);
2210 *dual_slot |= BITFIELD64_MASK(slots) << var->data.location;
2211 }
2212 }
2213
2214 nir_foreach_shader_in_variable(var, shader) {
2215 var->data.location +=
2216 util_bitcount64(*dual_slot & BITFIELD64_MASK(var->data.location));
2217 }
2218 }
2219
2220 /* Returns an attribute mask that has been re-compacted using the given
2221 * dual_slot mask.
2222 */
2223 uint64_t
2224 nir_get_single_slot_attribs_mask(uint64_t attribs, uint64_t dual_slot)
2225 {
2226 while (dual_slot) {
2227 unsigned loc = u_bit_scan64(&dual_slot);
2228 /* mask of all bits up to and including loc */
2229 uint64_t mask = BITFIELD64_MASK(loc + 1);
2230 attribs = (attribs & mask) | ((attribs & ~mask) >> 1);
2231 }
2232 return attribs;
2233 }
2234
2235 void
2236 nir_rewrite_image_intrinsic(nir_intrinsic_instr *intrin, nir_ssa_def *src,
2237 bool bindless)
2238 {
2239 enum gl_access_qualifier access = nir_intrinsic_access(intrin);
2240
2241 switch (intrin->intrinsic) {
2242 #define CASE(op) \
2243 case nir_intrinsic_image_deref_##op: \
2244 intrin->intrinsic = bindless ? nir_intrinsic_bindless_image_##op \
2245 : nir_intrinsic_image_##op; \
2246 break;
2247 CASE(load)
2248 CASE(store)
2249 CASE(atomic_add)
2250 CASE(atomic_imin)
2251 CASE(atomic_umin)
2252 CASE(atomic_imax)
2253 CASE(atomic_umax)
2254 CASE(atomic_and)
2255 CASE(atomic_or)
2256 CASE(atomic_xor)
2257 CASE(atomic_exchange)
2258 CASE(atomic_comp_swap)
2259 CASE(atomic_fadd)
2260 CASE(atomic_inc_wrap)
2261 CASE(atomic_dec_wrap)
2262 CASE(size)
2263 CASE(samples)
2264 CASE(load_raw_intel)
2265 CASE(store_raw_intel)
2266 #undef CASE
2267 default:
2268 unreachable("Unhanded image intrinsic");
2269 }
2270
2271 nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);
2272 nir_variable *var = nir_deref_instr_get_variable(deref);
2273
2274 nir_intrinsic_set_image_dim(intrin, glsl_get_sampler_dim(deref->type));
2275 nir_intrinsic_set_image_array(intrin, glsl_sampler_type_is_array(deref->type));
2276 nir_intrinsic_set_access(intrin, access | var->data.access);
2277 nir_intrinsic_set_format(intrin, var->data.image.format);
2278
2279 nir_instr_rewrite_src(&intrin->instr, &intrin->src[0],
2280 nir_src_for_ssa(src));
2281 }
2282
2283 unsigned
2284 nir_image_intrinsic_coord_components(const nir_intrinsic_instr *instr)
2285 {
2286 enum glsl_sampler_dim dim = nir_intrinsic_image_dim(instr);
2287 int coords = glsl_get_sampler_dim_coordinate_components(dim);
2288 if (dim == GLSL_SAMPLER_DIM_CUBE)
2289 return coords;
2290 else
2291 return coords + nir_intrinsic_image_array(instr);
2292 }