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nir: Add and use a nir_variable_list_for_mode helper
[mesa.git] / src / compiler / nir / nir.c
1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Connor Abbott (cwabbott0@gmail.com)
25 *
26 */
27
28 #include "nir.h"
29 #include "nir_builder.h"
30 #include "nir_control_flow_private.h"
31 #include "util/half_float.h"
32 #include <limits.h>
33 #include <assert.h>
34 #include <math.h>
35 #include "util/u_math.h"
36
37 #include "main/menums.h" /* BITFIELD64_MASK */
38
39 nir_shader *
40 nir_shader_create(void *mem_ctx,
41 gl_shader_stage stage,
42 const nir_shader_compiler_options *options,
43 shader_info *si)
44 {
45 nir_shader *shader = rzalloc(mem_ctx, nir_shader);
46
47 exec_list_make_empty(&shader->uniforms);
48 exec_list_make_empty(&shader->inputs);
49 exec_list_make_empty(&shader->outputs);
50 exec_list_make_empty(&shader->shared);
51
52 shader->options = options;
53
54 if (si) {
55 assert(si->stage == stage);
56 shader->info = *si;
57 } else {
58 shader->info.stage = stage;
59 }
60
61 exec_list_make_empty(&shader->functions);
62 exec_list_make_empty(&shader->globals);
63 exec_list_make_empty(&shader->system_values);
64
65 shader->num_inputs = 0;
66 shader->num_outputs = 0;
67 shader->num_uniforms = 0;
68 shader->num_shared = 0;
69
70 return shader;
71 }
72
73 static nir_register *
74 reg_create(void *mem_ctx, struct exec_list *list)
75 {
76 nir_register *reg = ralloc(mem_ctx, nir_register);
77
78 list_inithead(&reg->uses);
79 list_inithead(&reg->defs);
80 list_inithead(&reg->if_uses);
81
82 reg->num_components = 0;
83 reg->bit_size = 32;
84 reg->num_array_elems = 0;
85 reg->name = NULL;
86
87 exec_list_push_tail(list, &reg->node);
88
89 return reg;
90 }
91
92 nir_register *
93 nir_local_reg_create(nir_function_impl *impl)
94 {
95 nir_register *reg = reg_create(ralloc_parent(impl), &impl->registers);
96 reg->index = impl->reg_alloc++;
97
98 return reg;
99 }
100
101 void
102 nir_reg_remove(nir_register *reg)
103 {
104 exec_node_remove(&reg->node);
105 }
106
107 struct exec_list *
108 nir_variable_list_for_mode(nir_shader *shader, nir_variable_mode mode)
109 {
110 switch (mode) {
111 case nir_var_function_temp:
112 assert(!"nir_shader_add_variable cannot be used for local variables");
113 return NULL;
114
115 case nir_var_shader_temp:
116 return &shader->globals;
117
118 case nir_var_shader_in:
119 return &shader->inputs;
120
121 case nir_var_shader_out:
122 return &shader->outputs;
123
124 case nir_var_uniform:
125 case nir_var_mem_ubo:
126 case nir_var_mem_ssbo:
127 return &shader->uniforms;
128
129 case nir_var_mem_shared:
130 assert(gl_shader_stage_is_compute(shader->info.stage));
131 return &shader->shared;
132
133 case nir_var_mem_global:
134 assert(!"nir_shader_add_variable cannot be used for global memory");
135 return NULL;
136
137 case nir_var_system_value:
138 return &shader->system_values;
139
140 case nir_var_mem_push_const:
141 assert(!"nir_var_push_constant is not supposed to be used for variables");
142 return NULL;
143
144 default:
145 assert(!"invalid mode");
146 return NULL;
147 }
148 }
149
150 void
151 nir_shader_add_variable(nir_shader *shader, nir_variable *var)
152 {
153 struct exec_list *var_list =
154 nir_variable_list_for_mode(shader, var->data.mode);
155 if (var_list)
156 exec_list_push_tail(var_list, &var->node);
157 }
158
159 nir_variable *
160 nir_variable_create(nir_shader *shader, nir_variable_mode mode,
161 const struct glsl_type *type, const char *name)
162 {
163 nir_variable *var = rzalloc(shader, nir_variable);
164 var->name = ralloc_strdup(var, name);
165 var->type = type;
166 var->data.mode = mode;
167 var->data.how_declared = nir_var_declared_normally;
168
169 if ((mode == nir_var_shader_in &&
170 shader->info.stage != MESA_SHADER_VERTEX) ||
171 (mode == nir_var_shader_out &&
172 shader->info.stage != MESA_SHADER_FRAGMENT))
173 var->data.interpolation = INTERP_MODE_SMOOTH;
174
175 if (mode == nir_var_shader_in || mode == nir_var_uniform)
176 var->data.read_only = true;
177
178 nir_shader_add_variable(shader, var);
179
180 return var;
181 }
182
183 nir_variable *
184 nir_local_variable_create(nir_function_impl *impl,
185 const struct glsl_type *type, const char *name)
186 {
187 nir_variable *var = rzalloc(impl->function->shader, nir_variable);
188 var->name = ralloc_strdup(var, name);
189 var->type = type;
190 var->data.mode = nir_var_function_temp;
191
192 nir_function_impl_add_variable(impl, var);
193
194 return var;
195 }
196
197 nir_function *
198 nir_function_create(nir_shader *shader, const char *name)
199 {
200 nir_function *func = ralloc(shader, nir_function);
201
202 exec_list_push_tail(&shader->functions, &func->node);
203
204 func->name = ralloc_strdup(func, name);
205 func->shader = shader;
206 func->num_params = 0;
207 func->params = NULL;
208 func->impl = NULL;
209 func->is_entrypoint = false;
210
211 return func;
212 }
213
214 /* NOTE: if the instruction you are copying a src to is already added
215 * to the IR, use nir_instr_rewrite_src() instead.
216 */
217 void nir_src_copy(nir_src *dest, const nir_src *src, void *mem_ctx)
218 {
219 dest->is_ssa = src->is_ssa;
220 if (src->is_ssa) {
221 dest->ssa = src->ssa;
222 } else {
223 dest->reg.base_offset = src->reg.base_offset;
224 dest->reg.reg = src->reg.reg;
225 if (src->reg.indirect) {
226 dest->reg.indirect = ralloc(mem_ctx, nir_src);
227 nir_src_copy(dest->reg.indirect, src->reg.indirect, mem_ctx);
228 } else {
229 dest->reg.indirect = NULL;
230 }
231 }
232 }
233
234 void nir_dest_copy(nir_dest *dest, const nir_dest *src, nir_instr *instr)
235 {
236 /* Copying an SSA definition makes no sense whatsoever. */
237 assert(!src->is_ssa);
238
239 dest->is_ssa = false;
240
241 dest->reg.base_offset = src->reg.base_offset;
242 dest->reg.reg = src->reg.reg;
243 if (src->reg.indirect) {
244 dest->reg.indirect = ralloc(instr, nir_src);
245 nir_src_copy(dest->reg.indirect, src->reg.indirect, instr);
246 } else {
247 dest->reg.indirect = NULL;
248 }
249 }
250
251 void
252 nir_alu_src_copy(nir_alu_src *dest, const nir_alu_src *src,
253 nir_alu_instr *instr)
254 {
255 nir_src_copy(&dest->src, &src->src, &instr->instr);
256 dest->abs = src->abs;
257 dest->negate = src->negate;
258 for (unsigned i = 0; i < NIR_MAX_VEC_COMPONENTS; i++)
259 dest->swizzle[i] = src->swizzle[i];
260 }
261
262 void
263 nir_alu_dest_copy(nir_alu_dest *dest, const nir_alu_dest *src,
264 nir_alu_instr *instr)
265 {
266 nir_dest_copy(&dest->dest, &src->dest, &instr->instr);
267 dest->write_mask = src->write_mask;
268 dest->saturate = src->saturate;
269 }
270
271
272 static void
273 cf_init(nir_cf_node *node, nir_cf_node_type type)
274 {
275 exec_node_init(&node->node);
276 node->parent = NULL;
277 node->type = type;
278 }
279
280 nir_function_impl *
281 nir_function_impl_create_bare(nir_shader *shader)
282 {
283 nir_function_impl *impl = ralloc(shader, nir_function_impl);
284
285 impl->function = NULL;
286
287 cf_init(&impl->cf_node, nir_cf_node_function);
288
289 exec_list_make_empty(&impl->body);
290 exec_list_make_empty(&impl->registers);
291 exec_list_make_empty(&impl->locals);
292 impl->reg_alloc = 0;
293 impl->ssa_alloc = 0;
294 impl->valid_metadata = nir_metadata_none;
295
296 /* create start & end blocks */
297 nir_block *start_block = nir_block_create(shader);
298 nir_block *end_block = nir_block_create(shader);
299 start_block->cf_node.parent = &impl->cf_node;
300 end_block->cf_node.parent = &impl->cf_node;
301 impl->end_block = end_block;
302
303 exec_list_push_tail(&impl->body, &start_block->cf_node.node);
304
305 start_block->successors[0] = end_block;
306 _mesa_set_add(end_block->predecessors, start_block);
307 return impl;
308 }
309
310 nir_function_impl *
311 nir_function_impl_create(nir_function *function)
312 {
313 assert(function->impl == NULL);
314
315 nir_function_impl *impl = nir_function_impl_create_bare(function->shader);
316
317 function->impl = impl;
318 impl->function = function;
319
320 return impl;
321 }
322
323 nir_block *
324 nir_block_create(nir_shader *shader)
325 {
326 nir_block *block = rzalloc(shader, nir_block);
327
328 cf_init(&block->cf_node, nir_cf_node_block);
329
330 block->successors[0] = block->successors[1] = NULL;
331 block->predecessors = _mesa_pointer_set_create(block);
332 block->imm_dom = NULL;
333 /* XXX maybe it would be worth it to defer allocation? This
334 * way it doesn't get allocated for shader refs that never run
335 * nir_calc_dominance? For example, state-tracker creates an
336 * initial IR, clones that, runs appropriate lowering pass, passes
337 * to driver which does common lowering/opt, and then stores ref
338 * which is later used to do state specific lowering and futher
339 * opt. Do any of the references not need dominance metadata?
340 */
341 block->dom_frontier = _mesa_pointer_set_create(block);
342
343 exec_list_make_empty(&block->instr_list);
344
345 return block;
346 }
347
348 static inline void
349 src_init(nir_src *src)
350 {
351 src->is_ssa = false;
352 src->reg.reg = NULL;
353 src->reg.indirect = NULL;
354 src->reg.base_offset = 0;
355 }
356
357 nir_if *
358 nir_if_create(nir_shader *shader)
359 {
360 nir_if *if_stmt = ralloc(shader, nir_if);
361
362 if_stmt->control = nir_selection_control_none;
363
364 cf_init(&if_stmt->cf_node, nir_cf_node_if);
365 src_init(&if_stmt->condition);
366
367 nir_block *then = nir_block_create(shader);
368 exec_list_make_empty(&if_stmt->then_list);
369 exec_list_push_tail(&if_stmt->then_list, &then->cf_node.node);
370 then->cf_node.parent = &if_stmt->cf_node;
371
372 nir_block *else_stmt = nir_block_create(shader);
373 exec_list_make_empty(&if_stmt->else_list);
374 exec_list_push_tail(&if_stmt->else_list, &else_stmt->cf_node.node);
375 else_stmt->cf_node.parent = &if_stmt->cf_node;
376
377 return if_stmt;
378 }
379
380 nir_loop *
381 nir_loop_create(nir_shader *shader)
382 {
383 nir_loop *loop = rzalloc(shader, nir_loop);
384
385 cf_init(&loop->cf_node, nir_cf_node_loop);
386
387 nir_block *body = nir_block_create(shader);
388 exec_list_make_empty(&loop->body);
389 exec_list_push_tail(&loop->body, &body->cf_node.node);
390 body->cf_node.parent = &loop->cf_node;
391
392 body->successors[0] = body;
393 _mesa_set_add(body->predecessors, body);
394
395 return loop;
396 }
397
398 static void
399 instr_init(nir_instr *instr, nir_instr_type type)
400 {
401 instr->type = type;
402 instr->block = NULL;
403 exec_node_init(&instr->node);
404 }
405
406 static void
407 dest_init(nir_dest *dest)
408 {
409 dest->is_ssa = false;
410 dest->reg.reg = NULL;
411 dest->reg.indirect = NULL;
412 dest->reg.base_offset = 0;
413 }
414
415 static void
416 alu_dest_init(nir_alu_dest *dest)
417 {
418 dest_init(&dest->dest);
419 dest->saturate = false;
420 dest->write_mask = 0xf;
421 }
422
423 static void
424 alu_src_init(nir_alu_src *src)
425 {
426 src_init(&src->src);
427 src->abs = src->negate = false;
428 for (int i = 0; i < NIR_MAX_VEC_COMPONENTS; ++i)
429 src->swizzle[i] = i;
430 }
431
432 nir_alu_instr *
433 nir_alu_instr_create(nir_shader *shader, nir_op op)
434 {
435 unsigned num_srcs = nir_op_infos[op].num_inputs;
436 /* TODO: don't use rzalloc */
437 nir_alu_instr *instr =
438 rzalloc_size(shader,
439 sizeof(nir_alu_instr) + num_srcs * sizeof(nir_alu_src));
440
441 instr_init(&instr->instr, nir_instr_type_alu);
442 instr->op = op;
443 alu_dest_init(&instr->dest);
444 for (unsigned i = 0; i < num_srcs; i++)
445 alu_src_init(&instr->src[i]);
446
447 return instr;
448 }
449
450 nir_deref_instr *
451 nir_deref_instr_create(nir_shader *shader, nir_deref_type deref_type)
452 {
453 nir_deref_instr *instr =
454 rzalloc_size(shader, sizeof(nir_deref_instr));
455
456 instr_init(&instr->instr, nir_instr_type_deref);
457
458 instr->deref_type = deref_type;
459 if (deref_type != nir_deref_type_var)
460 src_init(&instr->parent);
461
462 if (deref_type == nir_deref_type_array ||
463 deref_type == nir_deref_type_ptr_as_array)
464 src_init(&instr->arr.index);
465
466 dest_init(&instr->dest);
467
468 return instr;
469 }
470
471 nir_jump_instr *
472 nir_jump_instr_create(nir_shader *shader, nir_jump_type type)
473 {
474 nir_jump_instr *instr = ralloc(shader, nir_jump_instr);
475 instr_init(&instr->instr, nir_instr_type_jump);
476 instr->type = type;
477 return instr;
478 }
479
480 nir_load_const_instr *
481 nir_load_const_instr_create(nir_shader *shader, unsigned num_components,
482 unsigned bit_size)
483 {
484 nir_load_const_instr *instr =
485 rzalloc_size(shader, sizeof(*instr) + num_components * sizeof(*instr->value));
486 instr_init(&instr->instr, nir_instr_type_load_const);
487
488 nir_ssa_def_init(&instr->instr, &instr->def, num_components, bit_size, NULL);
489
490 return instr;
491 }
492
493 nir_intrinsic_instr *
494 nir_intrinsic_instr_create(nir_shader *shader, nir_intrinsic_op op)
495 {
496 unsigned num_srcs = nir_intrinsic_infos[op].num_srcs;
497 /* TODO: don't use rzalloc */
498 nir_intrinsic_instr *instr =
499 rzalloc_size(shader,
500 sizeof(nir_intrinsic_instr) + num_srcs * sizeof(nir_src));
501
502 instr_init(&instr->instr, nir_instr_type_intrinsic);
503 instr->intrinsic = op;
504
505 if (nir_intrinsic_infos[op].has_dest)
506 dest_init(&instr->dest);
507
508 for (unsigned i = 0; i < num_srcs; i++)
509 src_init(&instr->src[i]);
510
511 return instr;
512 }
513
514 nir_call_instr *
515 nir_call_instr_create(nir_shader *shader, nir_function *callee)
516 {
517 const unsigned num_params = callee->num_params;
518 nir_call_instr *instr =
519 rzalloc_size(shader, sizeof(*instr) +
520 num_params * sizeof(instr->params[0]));
521
522 instr_init(&instr->instr, nir_instr_type_call);
523 instr->callee = callee;
524 instr->num_params = num_params;
525 for (unsigned i = 0; i < num_params; i++)
526 src_init(&instr->params[i]);
527
528 return instr;
529 }
530
531 static int8_t default_tg4_offsets[4][2] =
532 {
533 { 0, 1 },
534 { 1, 1 },
535 { 1, 0 },
536 { 0, 0 },
537 };
538
539 nir_tex_instr *
540 nir_tex_instr_create(nir_shader *shader, unsigned num_srcs)
541 {
542 nir_tex_instr *instr = rzalloc(shader, nir_tex_instr);
543 instr_init(&instr->instr, nir_instr_type_tex);
544
545 dest_init(&instr->dest);
546
547 instr->num_srcs = num_srcs;
548 instr->src = ralloc_array(instr, nir_tex_src, num_srcs);
549 for (unsigned i = 0; i < num_srcs; i++)
550 src_init(&instr->src[i].src);
551
552 instr->texture_index = 0;
553 instr->sampler_index = 0;
554 memcpy(instr->tg4_offsets, default_tg4_offsets, sizeof(instr->tg4_offsets));
555
556 return instr;
557 }
558
559 void
560 nir_tex_instr_add_src(nir_tex_instr *tex,
561 nir_tex_src_type src_type,
562 nir_src src)
563 {
564 nir_tex_src *new_srcs = rzalloc_array(tex, nir_tex_src,
565 tex->num_srcs + 1);
566
567 for (unsigned i = 0; i < tex->num_srcs; i++) {
568 new_srcs[i].src_type = tex->src[i].src_type;
569 nir_instr_move_src(&tex->instr, &new_srcs[i].src,
570 &tex->src[i].src);
571 }
572
573 ralloc_free(tex->src);
574 tex->src = new_srcs;
575
576 tex->src[tex->num_srcs].src_type = src_type;
577 nir_instr_rewrite_src(&tex->instr, &tex->src[tex->num_srcs].src, src);
578 tex->num_srcs++;
579 }
580
581 void
582 nir_tex_instr_remove_src(nir_tex_instr *tex, unsigned src_idx)
583 {
584 assert(src_idx < tex->num_srcs);
585
586 /* First rewrite the source to NIR_SRC_INIT */
587 nir_instr_rewrite_src(&tex->instr, &tex->src[src_idx].src, NIR_SRC_INIT);
588
589 /* Now, move all of the other sources down */
590 for (unsigned i = src_idx + 1; i < tex->num_srcs; i++) {
591 tex->src[i-1].src_type = tex->src[i].src_type;
592 nir_instr_move_src(&tex->instr, &tex->src[i-1].src, &tex->src[i].src);
593 }
594 tex->num_srcs--;
595 }
596
597 bool
598 nir_tex_instr_has_explicit_tg4_offsets(nir_tex_instr *tex)
599 {
600 if (tex->op != nir_texop_tg4)
601 return false;
602 return memcmp(tex->tg4_offsets, default_tg4_offsets,
603 sizeof(tex->tg4_offsets)) != 0;
604 }
605
606 nir_phi_instr *
607 nir_phi_instr_create(nir_shader *shader)
608 {
609 nir_phi_instr *instr = ralloc(shader, nir_phi_instr);
610 instr_init(&instr->instr, nir_instr_type_phi);
611
612 dest_init(&instr->dest);
613 exec_list_make_empty(&instr->srcs);
614 return instr;
615 }
616
617 nir_parallel_copy_instr *
618 nir_parallel_copy_instr_create(nir_shader *shader)
619 {
620 nir_parallel_copy_instr *instr = ralloc(shader, nir_parallel_copy_instr);
621 instr_init(&instr->instr, nir_instr_type_parallel_copy);
622
623 exec_list_make_empty(&instr->entries);
624
625 return instr;
626 }
627
628 nir_ssa_undef_instr *
629 nir_ssa_undef_instr_create(nir_shader *shader,
630 unsigned num_components,
631 unsigned bit_size)
632 {
633 nir_ssa_undef_instr *instr = ralloc(shader, nir_ssa_undef_instr);
634 instr_init(&instr->instr, nir_instr_type_ssa_undef);
635
636 nir_ssa_def_init(&instr->instr, &instr->def, num_components, bit_size, NULL);
637
638 return instr;
639 }
640
641 static nir_const_value
642 const_value_float(double d, unsigned bit_size)
643 {
644 nir_const_value v;
645 memset(&v, 0, sizeof(v));
646 switch (bit_size) {
647 case 16: v.u16 = _mesa_float_to_half(d); break;
648 case 32: v.f32 = d; break;
649 case 64: v.f64 = d; break;
650 default:
651 unreachable("Invalid bit size");
652 }
653 return v;
654 }
655
656 static nir_const_value
657 const_value_int(int64_t i, unsigned bit_size)
658 {
659 nir_const_value v;
660 memset(&v, 0, sizeof(v));
661 switch (bit_size) {
662 case 1: v.b = i & 1; break;
663 case 8: v.i8 = i; break;
664 case 16: v.i16 = i; break;
665 case 32: v.i32 = i; break;
666 case 64: v.i64 = i; break;
667 default:
668 unreachable("Invalid bit size");
669 }
670 return v;
671 }
672
673 nir_const_value
674 nir_alu_binop_identity(nir_op binop, unsigned bit_size)
675 {
676 const int64_t max_int = (1ull << (bit_size - 1)) - 1;
677 const int64_t min_int = -max_int - 1;
678 switch (binop) {
679 case nir_op_iadd:
680 return const_value_int(0, bit_size);
681 case nir_op_fadd:
682 return const_value_float(0, bit_size);
683 case nir_op_imul:
684 return const_value_int(1, bit_size);
685 case nir_op_fmul:
686 return const_value_float(1, bit_size);
687 case nir_op_imin:
688 return const_value_int(max_int, bit_size);
689 case nir_op_umin:
690 return const_value_int(~0ull, bit_size);
691 case nir_op_fmin:
692 return const_value_float(INFINITY, bit_size);
693 case nir_op_imax:
694 return const_value_int(min_int, bit_size);
695 case nir_op_umax:
696 return const_value_int(0, bit_size);
697 case nir_op_fmax:
698 return const_value_float(-INFINITY, bit_size);
699 case nir_op_iand:
700 return const_value_int(~0ull, bit_size);
701 case nir_op_ior:
702 return const_value_int(0, bit_size);
703 case nir_op_ixor:
704 return const_value_int(0, bit_size);
705 default:
706 unreachable("Invalid reduction operation");
707 }
708 }
709
710 nir_function_impl *
711 nir_cf_node_get_function(nir_cf_node *node)
712 {
713 while (node->type != nir_cf_node_function) {
714 node = node->parent;
715 }
716
717 return nir_cf_node_as_function(node);
718 }
719
720 /* Reduces a cursor by trying to convert everything to after and trying to
721 * go up to block granularity when possible.
722 */
723 static nir_cursor
724 reduce_cursor(nir_cursor cursor)
725 {
726 switch (cursor.option) {
727 case nir_cursor_before_block:
728 assert(nir_cf_node_prev(&cursor.block->cf_node) == NULL ||
729 nir_cf_node_prev(&cursor.block->cf_node)->type != nir_cf_node_block);
730 if (exec_list_is_empty(&cursor.block->instr_list)) {
731 /* Empty block. After is as good as before. */
732 cursor.option = nir_cursor_after_block;
733 }
734 return cursor;
735
736 case nir_cursor_after_block:
737 return cursor;
738
739 case nir_cursor_before_instr: {
740 nir_instr *prev_instr = nir_instr_prev(cursor.instr);
741 if (prev_instr) {
742 /* Before this instruction is after the previous */
743 cursor.instr = prev_instr;
744 cursor.option = nir_cursor_after_instr;
745 } else {
746 /* No previous instruction. Switch to before block */
747 cursor.block = cursor.instr->block;
748 cursor.option = nir_cursor_before_block;
749 }
750 return reduce_cursor(cursor);
751 }
752
753 case nir_cursor_after_instr:
754 if (nir_instr_next(cursor.instr) == NULL) {
755 /* This is the last instruction, switch to after block */
756 cursor.option = nir_cursor_after_block;
757 cursor.block = cursor.instr->block;
758 }
759 return cursor;
760
761 default:
762 unreachable("Inavlid cursor option");
763 }
764 }
765
766 bool
767 nir_cursors_equal(nir_cursor a, nir_cursor b)
768 {
769 /* Reduced cursors should be unique */
770 a = reduce_cursor(a);
771 b = reduce_cursor(b);
772
773 return a.block == b.block && a.option == b.option;
774 }
775
776 static bool
777 add_use_cb(nir_src *src, void *state)
778 {
779 nir_instr *instr = state;
780
781 src->parent_instr = instr;
782 list_addtail(&src->use_link,
783 src->is_ssa ? &src->ssa->uses : &src->reg.reg->uses);
784
785 return true;
786 }
787
788 static bool
789 add_ssa_def_cb(nir_ssa_def *def, void *state)
790 {
791 nir_instr *instr = state;
792
793 if (instr->block && def->index == UINT_MAX) {
794 nir_function_impl *impl =
795 nir_cf_node_get_function(&instr->block->cf_node);
796
797 def->index = impl->ssa_alloc++;
798 }
799
800 return true;
801 }
802
803 static bool
804 add_reg_def_cb(nir_dest *dest, void *state)
805 {
806 nir_instr *instr = state;
807
808 if (!dest->is_ssa) {
809 dest->reg.parent_instr = instr;
810 list_addtail(&dest->reg.def_link, &dest->reg.reg->defs);
811 }
812
813 return true;
814 }
815
816 static void
817 add_defs_uses(nir_instr *instr)
818 {
819 nir_foreach_src(instr, add_use_cb, instr);
820 nir_foreach_dest(instr, add_reg_def_cb, instr);
821 nir_foreach_ssa_def(instr, add_ssa_def_cb, instr);
822 }
823
824 void
825 nir_instr_insert(nir_cursor cursor, nir_instr *instr)
826 {
827 switch (cursor.option) {
828 case nir_cursor_before_block:
829 /* Only allow inserting jumps into empty blocks. */
830 if (instr->type == nir_instr_type_jump)
831 assert(exec_list_is_empty(&cursor.block->instr_list));
832
833 instr->block = cursor.block;
834 add_defs_uses(instr);
835 exec_list_push_head(&cursor.block->instr_list, &instr->node);
836 break;
837 case nir_cursor_after_block: {
838 /* Inserting instructions after a jump is illegal. */
839 nir_instr *last = nir_block_last_instr(cursor.block);
840 assert(last == NULL || last->type != nir_instr_type_jump);
841 (void) last;
842
843 instr->block = cursor.block;
844 add_defs_uses(instr);
845 exec_list_push_tail(&cursor.block->instr_list, &instr->node);
846 break;
847 }
848 case nir_cursor_before_instr:
849 assert(instr->type != nir_instr_type_jump);
850 instr->block = cursor.instr->block;
851 add_defs_uses(instr);
852 exec_node_insert_node_before(&cursor.instr->node, &instr->node);
853 break;
854 case nir_cursor_after_instr:
855 /* Inserting instructions after a jump is illegal. */
856 assert(cursor.instr->type != nir_instr_type_jump);
857
858 /* Only allow inserting jumps at the end of the block. */
859 if (instr->type == nir_instr_type_jump)
860 assert(cursor.instr == nir_block_last_instr(cursor.instr->block));
861
862 instr->block = cursor.instr->block;
863 add_defs_uses(instr);
864 exec_node_insert_after(&cursor.instr->node, &instr->node);
865 break;
866 }
867
868 if (instr->type == nir_instr_type_jump)
869 nir_handle_add_jump(instr->block);
870 }
871
872 static bool
873 src_is_valid(const nir_src *src)
874 {
875 return src->is_ssa ? (src->ssa != NULL) : (src->reg.reg != NULL);
876 }
877
878 static bool
879 remove_use_cb(nir_src *src, void *state)
880 {
881 (void) state;
882
883 if (src_is_valid(src))
884 list_del(&src->use_link);
885
886 return true;
887 }
888
889 static bool
890 remove_def_cb(nir_dest *dest, void *state)
891 {
892 (void) state;
893
894 if (!dest->is_ssa)
895 list_del(&dest->reg.def_link);
896
897 return true;
898 }
899
900 static void
901 remove_defs_uses(nir_instr *instr)
902 {
903 nir_foreach_dest(instr, remove_def_cb, instr);
904 nir_foreach_src(instr, remove_use_cb, instr);
905 }
906
907 void nir_instr_remove_v(nir_instr *instr)
908 {
909 remove_defs_uses(instr);
910 exec_node_remove(&instr->node);
911
912 if (instr->type == nir_instr_type_jump) {
913 nir_jump_instr *jump_instr = nir_instr_as_jump(instr);
914 nir_handle_remove_jump(instr->block, jump_instr->type);
915 }
916 }
917
918 /*@}*/
919
920 void
921 nir_index_local_regs(nir_function_impl *impl)
922 {
923 unsigned index = 0;
924 foreach_list_typed(nir_register, reg, node, &impl->registers) {
925 reg->index = index++;
926 }
927 impl->reg_alloc = index;
928 }
929
930 static bool
931 visit_alu_dest(nir_alu_instr *instr, nir_foreach_dest_cb cb, void *state)
932 {
933 return cb(&instr->dest.dest, state);
934 }
935
936 static bool
937 visit_deref_dest(nir_deref_instr *instr, nir_foreach_dest_cb cb, void *state)
938 {
939 return cb(&instr->dest, state);
940 }
941
942 static bool
943 visit_intrinsic_dest(nir_intrinsic_instr *instr, nir_foreach_dest_cb cb,
944 void *state)
945 {
946 if (nir_intrinsic_infos[instr->intrinsic].has_dest)
947 return cb(&instr->dest, state);
948
949 return true;
950 }
951
952 static bool
953 visit_texture_dest(nir_tex_instr *instr, nir_foreach_dest_cb cb,
954 void *state)
955 {
956 return cb(&instr->dest, state);
957 }
958
959 static bool
960 visit_phi_dest(nir_phi_instr *instr, nir_foreach_dest_cb cb, void *state)
961 {
962 return cb(&instr->dest, state);
963 }
964
965 static bool
966 visit_parallel_copy_dest(nir_parallel_copy_instr *instr,
967 nir_foreach_dest_cb cb, void *state)
968 {
969 nir_foreach_parallel_copy_entry(entry, instr) {
970 if (!cb(&entry->dest, state))
971 return false;
972 }
973
974 return true;
975 }
976
977 bool
978 nir_foreach_dest(nir_instr *instr, nir_foreach_dest_cb cb, void *state)
979 {
980 switch (instr->type) {
981 case nir_instr_type_alu:
982 return visit_alu_dest(nir_instr_as_alu(instr), cb, state);
983 case nir_instr_type_deref:
984 return visit_deref_dest(nir_instr_as_deref(instr), cb, state);
985 case nir_instr_type_intrinsic:
986 return visit_intrinsic_dest(nir_instr_as_intrinsic(instr), cb, state);
987 case nir_instr_type_tex:
988 return visit_texture_dest(nir_instr_as_tex(instr), cb, state);
989 case nir_instr_type_phi:
990 return visit_phi_dest(nir_instr_as_phi(instr), cb, state);
991 case nir_instr_type_parallel_copy:
992 return visit_parallel_copy_dest(nir_instr_as_parallel_copy(instr),
993 cb, state);
994
995 case nir_instr_type_load_const:
996 case nir_instr_type_ssa_undef:
997 case nir_instr_type_call:
998 case nir_instr_type_jump:
999 break;
1000
1001 default:
1002 unreachable("Invalid instruction type");
1003 break;
1004 }
1005
1006 return true;
1007 }
1008
1009 struct foreach_ssa_def_state {
1010 nir_foreach_ssa_def_cb cb;
1011 void *client_state;
1012 };
1013
1014 static inline bool
1015 nir_ssa_def_visitor(nir_dest *dest, void *void_state)
1016 {
1017 struct foreach_ssa_def_state *state = void_state;
1018
1019 if (dest->is_ssa)
1020 return state->cb(&dest->ssa, state->client_state);
1021 else
1022 return true;
1023 }
1024
1025 bool
1026 nir_foreach_ssa_def(nir_instr *instr, nir_foreach_ssa_def_cb cb, void *state)
1027 {
1028 switch (instr->type) {
1029 case nir_instr_type_alu:
1030 case nir_instr_type_deref:
1031 case nir_instr_type_tex:
1032 case nir_instr_type_intrinsic:
1033 case nir_instr_type_phi:
1034 case nir_instr_type_parallel_copy: {
1035 struct foreach_ssa_def_state foreach_state = {cb, state};
1036 return nir_foreach_dest(instr, nir_ssa_def_visitor, &foreach_state);
1037 }
1038
1039 case nir_instr_type_load_const:
1040 return cb(&nir_instr_as_load_const(instr)->def, state);
1041 case nir_instr_type_ssa_undef:
1042 return cb(&nir_instr_as_ssa_undef(instr)->def, state);
1043 case nir_instr_type_call:
1044 case nir_instr_type_jump:
1045 return true;
1046 default:
1047 unreachable("Invalid instruction type");
1048 }
1049 }
1050
1051 nir_ssa_def *
1052 nir_instr_ssa_def(nir_instr *instr)
1053 {
1054 switch (instr->type) {
1055 case nir_instr_type_alu:
1056 assert(nir_instr_as_alu(instr)->dest.dest.is_ssa);
1057 return &nir_instr_as_alu(instr)->dest.dest.ssa;
1058
1059 case nir_instr_type_deref:
1060 assert(nir_instr_as_deref(instr)->dest.is_ssa);
1061 return &nir_instr_as_deref(instr)->dest.ssa;
1062
1063 case nir_instr_type_tex:
1064 assert(nir_instr_as_tex(instr)->dest.is_ssa);
1065 return &nir_instr_as_tex(instr)->dest.ssa;
1066
1067 case nir_instr_type_intrinsic: {
1068 nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
1069 if (nir_intrinsic_infos[intrin->intrinsic].has_dest) {
1070 assert(intrin->dest.is_ssa);
1071 return &intrin->dest.ssa;
1072 } else {
1073 return NULL;
1074 }
1075 }
1076
1077 case nir_instr_type_phi:
1078 assert(nir_instr_as_phi(instr)->dest.is_ssa);
1079 return &nir_instr_as_phi(instr)->dest.ssa;
1080
1081 case nir_instr_type_parallel_copy:
1082 unreachable("Parallel copies are unsupported by this function");
1083
1084 case nir_instr_type_load_const:
1085 return &nir_instr_as_load_const(instr)->def;
1086
1087 case nir_instr_type_ssa_undef:
1088 return &nir_instr_as_ssa_undef(instr)->def;
1089
1090 case nir_instr_type_call:
1091 case nir_instr_type_jump:
1092 return NULL;
1093 }
1094
1095 unreachable("Invalid instruction type");
1096 }
1097
1098 static bool
1099 visit_src(nir_src *src, nir_foreach_src_cb cb, void *state)
1100 {
1101 if (!cb(src, state))
1102 return false;
1103 if (!src->is_ssa && src->reg.indirect)
1104 return cb(src->reg.indirect, state);
1105 return true;
1106 }
1107
1108 static bool
1109 visit_alu_src(nir_alu_instr *instr, nir_foreach_src_cb cb, void *state)
1110 {
1111 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1112 if (!visit_src(&instr->src[i].src, cb, state))
1113 return false;
1114
1115 return true;
1116 }
1117
1118 static bool
1119 visit_deref_instr_src(nir_deref_instr *instr,
1120 nir_foreach_src_cb cb, void *state)
1121 {
1122 if (instr->deref_type != nir_deref_type_var) {
1123 if (!visit_src(&instr->parent, cb, state))
1124 return false;
1125 }
1126
1127 if (instr->deref_type == nir_deref_type_array ||
1128 instr->deref_type == nir_deref_type_ptr_as_array) {
1129 if (!visit_src(&instr->arr.index, cb, state))
1130 return false;
1131 }
1132
1133 return true;
1134 }
1135
1136 static bool
1137 visit_tex_src(nir_tex_instr *instr, nir_foreach_src_cb cb, void *state)
1138 {
1139 for (unsigned i = 0; i < instr->num_srcs; i++) {
1140 if (!visit_src(&instr->src[i].src, cb, state))
1141 return false;
1142 }
1143
1144 return true;
1145 }
1146
1147 static bool
1148 visit_intrinsic_src(nir_intrinsic_instr *instr, nir_foreach_src_cb cb,
1149 void *state)
1150 {
1151 unsigned num_srcs = nir_intrinsic_infos[instr->intrinsic].num_srcs;
1152 for (unsigned i = 0; i < num_srcs; i++) {
1153 if (!visit_src(&instr->src[i], cb, state))
1154 return false;
1155 }
1156
1157 return true;
1158 }
1159
1160 static bool
1161 visit_call_src(nir_call_instr *instr, nir_foreach_src_cb cb, void *state)
1162 {
1163 for (unsigned i = 0; i < instr->num_params; i++) {
1164 if (!visit_src(&instr->params[i], cb, state))
1165 return false;
1166 }
1167
1168 return true;
1169 }
1170
1171 static bool
1172 visit_phi_src(nir_phi_instr *instr, nir_foreach_src_cb cb, void *state)
1173 {
1174 nir_foreach_phi_src(src, instr) {
1175 if (!visit_src(&src->src, cb, state))
1176 return false;
1177 }
1178
1179 return true;
1180 }
1181
1182 static bool
1183 visit_parallel_copy_src(nir_parallel_copy_instr *instr,
1184 nir_foreach_src_cb cb, void *state)
1185 {
1186 nir_foreach_parallel_copy_entry(entry, instr) {
1187 if (!visit_src(&entry->src, cb, state))
1188 return false;
1189 }
1190
1191 return true;
1192 }
1193
1194 typedef struct {
1195 void *state;
1196 nir_foreach_src_cb cb;
1197 } visit_dest_indirect_state;
1198
1199 static bool
1200 visit_dest_indirect(nir_dest *dest, void *_state)
1201 {
1202 visit_dest_indirect_state *state = (visit_dest_indirect_state *) _state;
1203
1204 if (!dest->is_ssa && dest->reg.indirect)
1205 return state->cb(dest->reg.indirect, state->state);
1206
1207 return true;
1208 }
1209
1210 bool
1211 nir_foreach_src(nir_instr *instr, nir_foreach_src_cb cb, void *state)
1212 {
1213 switch (instr->type) {
1214 case nir_instr_type_alu:
1215 if (!visit_alu_src(nir_instr_as_alu(instr), cb, state))
1216 return false;
1217 break;
1218 case nir_instr_type_deref:
1219 if (!visit_deref_instr_src(nir_instr_as_deref(instr), cb, state))
1220 return false;
1221 break;
1222 case nir_instr_type_intrinsic:
1223 if (!visit_intrinsic_src(nir_instr_as_intrinsic(instr), cb, state))
1224 return false;
1225 break;
1226 case nir_instr_type_tex:
1227 if (!visit_tex_src(nir_instr_as_tex(instr), cb, state))
1228 return false;
1229 break;
1230 case nir_instr_type_call:
1231 if (!visit_call_src(nir_instr_as_call(instr), cb, state))
1232 return false;
1233 break;
1234 case nir_instr_type_load_const:
1235 /* Constant load instructions have no regular sources */
1236 break;
1237 case nir_instr_type_phi:
1238 if (!visit_phi_src(nir_instr_as_phi(instr), cb, state))
1239 return false;
1240 break;
1241 case nir_instr_type_parallel_copy:
1242 if (!visit_parallel_copy_src(nir_instr_as_parallel_copy(instr),
1243 cb, state))
1244 return false;
1245 break;
1246 case nir_instr_type_jump:
1247 case nir_instr_type_ssa_undef:
1248 return true;
1249
1250 default:
1251 unreachable("Invalid instruction type");
1252 break;
1253 }
1254
1255 visit_dest_indirect_state dest_state;
1256 dest_state.state = state;
1257 dest_state.cb = cb;
1258 return nir_foreach_dest(instr, visit_dest_indirect, &dest_state);
1259 }
1260
1261 bool
1262 nir_foreach_phi_src_leaving_block(nir_block *block,
1263 nir_foreach_src_cb cb,
1264 void *state)
1265 {
1266 for (unsigned i = 0; i < ARRAY_SIZE(block->successors); i++) {
1267 if (block->successors[i] == NULL)
1268 continue;
1269
1270 nir_foreach_instr(instr, block->successors[i]) {
1271 if (instr->type != nir_instr_type_phi)
1272 break;
1273
1274 nir_phi_instr *phi = nir_instr_as_phi(instr);
1275 nir_foreach_phi_src(phi_src, phi) {
1276 if (phi_src->pred == block) {
1277 if (!cb(&phi_src->src, state))
1278 return false;
1279 }
1280 }
1281 }
1282 }
1283
1284 return true;
1285 }
1286
1287 nir_const_value
1288 nir_const_value_for_float(double f, unsigned bit_size)
1289 {
1290 nir_const_value v;
1291 memset(&v, 0, sizeof(v));
1292
1293 switch (bit_size) {
1294 case 16:
1295 v.u16 = _mesa_float_to_half(f);
1296 break;
1297 case 32:
1298 v.f32 = f;
1299 break;
1300 case 64:
1301 v.f64 = f;
1302 break;
1303 default:
1304 unreachable("Invalid bit size");
1305 }
1306
1307 return v;
1308 }
1309
1310 double
1311 nir_const_value_as_float(nir_const_value value, unsigned bit_size)
1312 {
1313 switch (bit_size) {
1314 case 16: return _mesa_half_to_float(value.u16);
1315 case 32: return value.f32;
1316 case 64: return value.f64;
1317 default:
1318 unreachable("Invalid bit size");
1319 }
1320 }
1321
1322 nir_const_value *
1323 nir_src_as_const_value(nir_src src)
1324 {
1325 if (!src.is_ssa)
1326 return NULL;
1327
1328 if (src.ssa->parent_instr->type != nir_instr_type_load_const)
1329 return NULL;
1330
1331 nir_load_const_instr *load = nir_instr_as_load_const(src.ssa->parent_instr);
1332
1333 return load->value;
1334 }
1335
1336 /**
1337 * Returns true if the source is known to be dynamically uniform. Otherwise it
1338 * returns false which means it may or may not be dynamically uniform but it
1339 * can't be determined.
1340 */
1341 bool
1342 nir_src_is_dynamically_uniform(nir_src src)
1343 {
1344 if (!src.is_ssa)
1345 return false;
1346
1347 /* Constants are trivially dynamically uniform */
1348 if (src.ssa->parent_instr->type == nir_instr_type_load_const)
1349 return true;
1350
1351 /* As are uniform variables */
1352 if (src.ssa->parent_instr->type == nir_instr_type_intrinsic) {
1353 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(src.ssa->parent_instr);
1354 if (intr->intrinsic == nir_intrinsic_load_uniform &&
1355 nir_src_is_dynamically_uniform(intr->src[0]))
1356 return true;
1357 }
1358
1359 /* Operating together dynamically uniform expressions produces a
1360 * dynamically uniform result
1361 */
1362 if (src.ssa->parent_instr->type == nir_instr_type_alu) {
1363 nir_alu_instr *alu = nir_instr_as_alu(src.ssa->parent_instr);
1364 for (int i = 0; i < nir_op_infos[alu->op].num_inputs; i++) {
1365 if (!nir_src_is_dynamically_uniform(alu->src[i].src))
1366 return false;
1367 }
1368
1369 return true;
1370 }
1371
1372 /* XXX: this could have many more tests, such as when a sampler function is
1373 * called with dynamically uniform arguments.
1374 */
1375 return false;
1376 }
1377
1378 static void
1379 src_remove_all_uses(nir_src *src)
1380 {
1381 for (; src; src = src->is_ssa ? NULL : src->reg.indirect) {
1382 if (!src_is_valid(src))
1383 continue;
1384
1385 list_del(&src->use_link);
1386 }
1387 }
1388
1389 static void
1390 src_add_all_uses(nir_src *src, nir_instr *parent_instr, nir_if *parent_if)
1391 {
1392 for (; src; src = src->is_ssa ? NULL : src->reg.indirect) {
1393 if (!src_is_valid(src))
1394 continue;
1395
1396 if (parent_instr) {
1397 src->parent_instr = parent_instr;
1398 if (src->is_ssa)
1399 list_addtail(&src->use_link, &src->ssa->uses);
1400 else
1401 list_addtail(&src->use_link, &src->reg.reg->uses);
1402 } else {
1403 assert(parent_if);
1404 src->parent_if = parent_if;
1405 if (src->is_ssa)
1406 list_addtail(&src->use_link, &src->ssa->if_uses);
1407 else
1408 list_addtail(&src->use_link, &src->reg.reg->if_uses);
1409 }
1410 }
1411 }
1412
1413 void
1414 nir_instr_rewrite_src(nir_instr *instr, nir_src *src, nir_src new_src)
1415 {
1416 assert(!src_is_valid(src) || src->parent_instr == instr);
1417
1418 src_remove_all_uses(src);
1419 *src = new_src;
1420 src_add_all_uses(src, instr, NULL);
1421 }
1422
1423 void
1424 nir_instr_move_src(nir_instr *dest_instr, nir_src *dest, nir_src *src)
1425 {
1426 assert(!src_is_valid(dest) || dest->parent_instr == dest_instr);
1427
1428 src_remove_all_uses(dest);
1429 src_remove_all_uses(src);
1430 *dest = *src;
1431 *src = NIR_SRC_INIT;
1432 src_add_all_uses(dest, dest_instr, NULL);
1433 }
1434
1435 void
1436 nir_if_rewrite_condition(nir_if *if_stmt, nir_src new_src)
1437 {
1438 nir_src *src = &if_stmt->condition;
1439 assert(!src_is_valid(src) || src->parent_if == if_stmt);
1440
1441 src_remove_all_uses(src);
1442 *src = new_src;
1443 src_add_all_uses(src, NULL, if_stmt);
1444 }
1445
1446 void
1447 nir_instr_rewrite_dest(nir_instr *instr, nir_dest *dest, nir_dest new_dest)
1448 {
1449 if (dest->is_ssa) {
1450 /* We can only overwrite an SSA destination if it has no uses. */
1451 assert(list_is_empty(&dest->ssa.uses) && list_is_empty(&dest->ssa.if_uses));
1452 } else {
1453 list_del(&dest->reg.def_link);
1454 if (dest->reg.indirect)
1455 src_remove_all_uses(dest->reg.indirect);
1456 }
1457
1458 /* We can't re-write with an SSA def */
1459 assert(!new_dest.is_ssa);
1460
1461 nir_dest_copy(dest, &new_dest, instr);
1462
1463 dest->reg.parent_instr = instr;
1464 list_addtail(&dest->reg.def_link, &new_dest.reg.reg->defs);
1465
1466 if (dest->reg.indirect)
1467 src_add_all_uses(dest->reg.indirect, instr, NULL);
1468 }
1469
1470 /* note: does *not* take ownership of 'name' */
1471 void
1472 nir_ssa_def_init(nir_instr *instr, nir_ssa_def *def,
1473 unsigned num_components,
1474 unsigned bit_size, const char *name)
1475 {
1476 def->name = ralloc_strdup(instr, name);
1477 def->parent_instr = instr;
1478 list_inithead(&def->uses);
1479 list_inithead(&def->if_uses);
1480 def->num_components = num_components;
1481 def->bit_size = bit_size;
1482 def->divergent = true; /* This is the safer default */
1483
1484 if (instr->block) {
1485 nir_function_impl *impl =
1486 nir_cf_node_get_function(&instr->block->cf_node);
1487
1488 def->index = impl->ssa_alloc++;
1489 } else {
1490 def->index = UINT_MAX;
1491 }
1492 }
1493
1494 /* note: does *not* take ownership of 'name' */
1495 void
1496 nir_ssa_dest_init(nir_instr *instr, nir_dest *dest,
1497 unsigned num_components, unsigned bit_size,
1498 const char *name)
1499 {
1500 dest->is_ssa = true;
1501 nir_ssa_def_init(instr, &dest->ssa, num_components, bit_size, name);
1502 }
1503
1504 void
1505 nir_ssa_def_rewrite_uses(nir_ssa_def *def, nir_src new_src)
1506 {
1507 assert(!new_src.is_ssa || def != new_src.ssa);
1508
1509 nir_foreach_use_safe(use_src, def)
1510 nir_instr_rewrite_src(use_src->parent_instr, use_src, new_src);
1511
1512 nir_foreach_if_use_safe(use_src, def)
1513 nir_if_rewrite_condition(use_src->parent_if, new_src);
1514 }
1515
1516 static bool
1517 is_instr_between(nir_instr *start, nir_instr *end, nir_instr *between)
1518 {
1519 assert(start->block == end->block);
1520
1521 if (between->block != start->block)
1522 return false;
1523
1524 /* Search backwards looking for "between" */
1525 while (start != end) {
1526 if (between == end)
1527 return true;
1528
1529 end = nir_instr_prev(end);
1530 assert(end);
1531 }
1532
1533 return false;
1534 }
1535
1536 /* Replaces all uses of the given SSA def with the given source but only if
1537 * the use comes after the after_me instruction. This can be useful if you
1538 * are emitting code to fix up the result of some instruction: you can freely
1539 * use the result in that code and then call rewrite_uses_after and pass the
1540 * last fixup instruction as after_me and it will replace all of the uses you
1541 * want without touching the fixup code.
1542 *
1543 * This function assumes that after_me is in the same block as
1544 * def->parent_instr and that after_me comes after def->parent_instr.
1545 */
1546 void
1547 nir_ssa_def_rewrite_uses_after(nir_ssa_def *def, nir_src new_src,
1548 nir_instr *after_me)
1549 {
1550 if (new_src.is_ssa && def == new_src.ssa)
1551 return;
1552
1553 nir_foreach_use_safe(use_src, def) {
1554 assert(use_src->parent_instr != def->parent_instr);
1555 /* Since def already dominates all of its uses, the only way a use can
1556 * not be dominated by after_me is if it is between def and after_me in
1557 * the instruction list.
1558 */
1559 if (!is_instr_between(def->parent_instr, after_me, use_src->parent_instr))
1560 nir_instr_rewrite_src(use_src->parent_instr, use_src, new_src);
1561 }
1562
1563 nir_foreach_if_use_safe(use_src, def)
1564 nir_if_rewrite_condition(use_src->parent_if, new_src);
1565 }
1566
1567 nir_component_mask_t
1568 nir_ssa_def_components_read(const nir_ssa_def *def)
1569 {
1570 nir_component_mask_t read_mask = 0;
1571 nir_foreach_use(use, def) {
1572 if (use->parent_instr->type == nir_instr_type_alu) {
1573 nir_alu_instr *alu = nir_instr_as_alu(use->parent_instr);
1574 nir_alu_src *alu_src = exec_node_data(nir_alu_src, use, src);
1575 int src_idx = alu_src - &alu->src[0];
1576 assert(src_idx >= 0 && src_idx < nir_op_infos[alu->op].num_inputs);
1577 read_mask |= nir_alu_instr_src_read_mask(alu, src_idx);
1578 } else {
1579 return (1 << def->num_components) - 1;
1580 }
1581 }
1582
1583 if (!list_is_empty(&def->if_uses))
1584 read_mask |= 1;
1585
1586 return read_mask;
1587 }
1588
1589 nir_block *
1590 nir_block_cf_tree_next(nir_block *block)
1591 {
1592 if (block == NULL) {
1593 /* nir_foreach_block_safe() will call this function on a NULL block
1594 * after the last iteration, but it won't use the result so just return
1595 * NULL here.
1596 */
1597 return NULL;
1598 }
1599
1600 nir_cf_node *cf_next = nir_cf_node_next(&block->cf_node);
1601 if (cf_next)
1602 return nir_cf_node_cf_tree_first(cf_next);
1603
1604 nir_cf_node *parent = block->cf_node.parent;
1605
1606 switch (parent->type) {
1607 case nir_cf_node_if: {
1608 /* Are we at the end of the if? Go to the beginning of the else */
1609 nir_if *if_stmt = nir_cf_node_as_if(parent);
1610 if (block == nir_if_last_then_block(if_stmt))
1611 return nir_if_first_else_block(if_stmt);
1612
1613 assert(block == nir_if_last_else_block(if_stmt));
1614 }
1615 /* fallthrough */
1616
1617 case nir_cf_node_loop:
1618 return nir_cf_node_as_block(nir_cf_node_next(parent));
1619
1620 case nir_cf_node_function:
1621 return NULL;
1622
1623 default:
1624 unreachable("unknown cf node type");
1625 }
1626 }
1627
1628 nir_block *
1629 nir_block_cf_tree_prev(nir_block *block)
1630 {
1631 if (block == NULL) {
1632 /* do this for consistency with nir_block_cf_tree_next() */
1633 return NULL;
1634 }
1635
1636 nir_cf_node *cf_prev = nir_cf_node_prev(&block->cf_node);
1637 if (cf_prev)
1638 return nir_cf_node_cf_tree_last(cf_prev);
1639
1640 nir_cf_node *parent = block->cf_node.parent;
1641
1642 switch (parent->type) {
1643 case nir_cf_node_if: {
1644 /* Are we at the beginning of the else? Go to the end of the if */
1645 nir_if *if_stmt = nir_cf_node_as_if(parent);
1646 if (block == nir_if_first_else_block(if_stmt))
1647 return nir_if_last_then_block(if_stmt);
1648
1649 assert(block == nir_if_first_then_block(if_stmt));
1650 }
1651 /* fallthrough */
1652
1653 case nir_cf_node_loop:
1654 return nir_cf_node_as_block(nir_cf_node_prev(parent));
1655
1656 case nir_cf_node_function:
1657 return NULL;
1658
1659 default:
1660 unreachable("unknown cf node type");
1661 }
1662 }
1663
1664 nir_block *nir_cf_node_cf_tree_first(nir_cf_node *node)
1665 {
1666 switch (node->type) {
1667 case nir_cf_node_function: {
1668 nir_function_impl *impl = nir_cf_node_as_function(node);
1669 return nir_start_block(impl);
1670 }
1671
1672 case nir_cf_node_if: {
1673 nir_if *if_stmt = nir_cf_node_as_if(node);
1674 return nir_if_first_then_block(if_stmt);
1675 }
1676
1677 case nir_cf_node_loop: {
1678 nir_loop *loop = nir_cf_node_as_loop(node);
1679 return nir_loop_first_block(loop);
1680 }
1681
1682 case nir_cf_node_block: {
1683 return nir_cf_node_as_block(node);
1684 }
1685
1686 default:
1687 unreachable("unknown node type");
1688 }
1689 }
1690
1691 nir_block *nir_cf_node_cf_tree_last(nir_cf_node *node)
1692 {
1693 switch (node->type) {
1694 case nir_cf_node_function: {
1695 nir_function_impl *impl = nir_cf_node_as_function(node);
1696 return nir_impl_last_block(impl);
1697 }
1698
1699 case nir_cf_node_if: {
1700 nir_if *if_stmt = nir_cf_node_as_if(node);
1701 return nir_if_last_else_block(if_stmt);
1702 }
1703
1704 case nir_cf_node_loop: {
1705 nir_loop *loop = nir_cf_node_as_loop(node);
1706 return nir_loop_last_block(loop);
1707 }
1708
1709 case nir_cf_node_block: {
1710 return nir_cf_node_as_block(node);
1711 }
1712
1713 default:
1714 unreachable("unknown node type");
1715 }
1716 }
1717
1718 nir_block *nir_cf_node_cf_tree_next(nir_cf_node *node)
1719 {
1720 if (node->type == nir_cf_node_block)
1721 return nir_block_cf_tree_next(nir_cf_node_as_block(node));
1722 else if (node->type == nir_cf_node_function)
1723 return NULL;
1724 else
1725 return nir_cf_node_as_block(nir_cf_node_next(node));
1726 }
1727
1728 nir_if *
1729 nir_block_get_following_if(nir_block *block)
1730 {
1731 if (exec_node_is_tail_sentinel(&block->cf_node.node))
1732 return NULL;
1733
1734 if (nir_cf_node_is_last(&block->cf_node))
1735 return NULL;
1736
1737 nir_cf_node *next_node = nir_cf_node_next(&block->cf_node);
1738
1739 if (next_node->type != nir_cf_node_if)
1740 return NULL;
1741
1742 return nir_cf_node_as_if(next_node);
1743 }
1744
1745 nir_loop *
1746 nir_block_get_following_loop(nir_block *block)
1747 {
1748 if (exec_node_is_tail_sentinel(&block->cf_node.node))
1749 return NULL;
1750
1751 if (nir_cf_node_is_last(&block->cf_node))
1752 return NULL;
1753
1754 nir_cf_node *next_node = nir_cf_node_next(&block->cf_node);
1755
1756 if (next_node->type != nir_cf_node_loop)
1757 return NULL;
1758
1759 return nir_cf_node_as_loop(next_node);
1760 }
1761
1762 void
1763 nir_index_blocks(nir_function_impl *impl)
1764 {
1765 unsigned index = 0;
1766
1767 if (impl->valid_metadata & nir_metadata_block_index)
1768 return;
1769
1770 nir_foreach_block(block, impl) {
1771 block->index = index++;
1772 }
1773
1774 /* The end_block isn't really part of the program, which is why its index
1775 * is >= num_blocks.
1776 */
1777 impl->num_blocks = impl->end_block->index = index;
1778 }
1779
1780 static bool
1781 index_ssa_def_cb(nir_ssa_def *def, void *state)
1782 {
1783 unsigned *index = (unsigned *) state;
1784 def->index = (*index)++;
1785
1786 return true;
1787 }
1788
1789 /**
1790 * The indices are applied top-to-bottom which has the very nice property
1791 * that, if A dominates B, then A->index <= B->index.
1792 */
1793 void
1794 nir_index_ssa_defs(nir_function_impl *impl)
1795 {
1796 unsigned index = 0;
1797
1798 nir_foreach_block(block, impl) {
1799 nir_foreach_instr(instr, block)
1800 nir_foreach_ssa_def(instr, index_ssa_def_cb, &index);
1801 }
1802
1803 impl->ssa_alloc = index;
1804 }
1805
1806 /**
1807 * The indices are applied top-to-bottom which has the very nice property
1808 * that, if A dominates B, then A->index <= B->index.
1809 */
1810 unsigned
1811 nir_index_instrs(nir_function_impl *impl)
1812 {
1813 unsigned index = 0;
1814
1815 nir_foreach_block(block, impl) {
1816 nir_foreach_instr(instr, block)
1817 instr->index = index++;
1818 }
1819
1820 return index;
1821 }
1822
1823 static void
1824 index_var_list(struct exec_list *list)
1825 {
1826 unsigned next_index = 0;
1827 nir_foreach_variable(var, list)
1828 var->index = next_index++;
1829 }
1830
1831 void
1832 nir_index_vars(nir_shader *shader, nir_function_impl *impl, nir_variable_mode modes)
1833 {
1834 if ((modes & nir_var_function_temp) && impl)
1835 index_var_list(&impl->locals);
1836
1837 if (modes & nir_var_shader_temp)
1838 index_var_list(&shader->globals);
1839
1840 if (modes & nir_var_shader_in)
1841 index_var_list(&shader->inputs);
1842
1843 if (modes & nir_var_shader_out)
1844 index_var_list(&shader->outputs);
1845
1846 if (modes & (nir_var_uniform | nir_var_mem_ubo | nir_var_mem_ssbo))
1847 index_var_list(&shader->uniforms);
1848
1849 if (modes & nir_var_mem_shared)
1850 index_var_list(&shader->shared);
1851
1852 if (modes & nir_var_system_value)
1853 index_var_list(&shader->system_values);
1854 }
1855
1856 static nir_instr *
1857 cursor_next_instr(nir_cursor cursor)
1858 {
1859 switch (cursor.option) {
1860 case nir_cursor_before_block:
1861 for (nir_block *block = cursor.block; block;
1862 block = nir_block_cf_tree_next(block)) {
1863 nir_instr *instr = nir_block_first_instr(block);
1864 if (instr)
1865 return instr;
1866 }
1867 return NULL;
1868
1869 case nir_cursor_after_block:
1870 cursor.block = nir_block_cf_tree_next(cursor.block);
1871 if (cursor.block == NULL)
1872 return NULL;
1873
1874 cursor.option = nir_cursor_before_block;
1875 return cursor_next_instr(cursor);
1876
1877 case nir_cursor_before_instr:
1878 return cursor.instr;
1879
1880 case nir_cursor_after_instr:
1881 if (nir_instr_next(cursor.instr))
1882 return nir_instr_next(cursor.instr);
1883
1884 cursor.option = nir_cursor_after_block;
1885 cursor.block = cursor.instr->block;
1886 return cursor_next_instr(cursor);
1887 }
1888
1889 unreachable("Inavlid cursor option");
1890 }
1891
1892 ASSERTED static bool
1893 dest_is_ssa(nir_dest *dest, void *_state)
1894 {
1895 (void) _state;
1896 return dest->is_ssa;
1897 }
1898
1899 bool
1900 nir_function_impl_lower_instructions(nir_function_impl *impl,
1901 nir_instr_filter_cb filter,
1902 nir_lower_instr_cb lower,
1903 void *cb_data)
1904 {
1905 nir_builder b;
1906 nir_builder_init(&b, impl);
1907
1908 nir_metadata preserved = nir_metadata_block_index |
1909 nir_metadata_dominance;
1910
1911 bool progress = false;
1912 nir_cursor iter = nir_before_cf_list(&impl->body);
1913 nir_instr *instr;
1914 while ((instr = cursor_next_instr(iter)) != NULL) {
1915 if (filter && !filter(instr, cb_data)) {
1916 iter = nir_after_instr(instr);
1917 continue;
1918 }
1919
1920 assert(nir_foreach_dest(instr, dest_is_ssa, NULL));
1921 nir_ssa_def *old_def = nir_instr_ssa_def(instr);
1922 if (old_def == NULL) {
1923 iter = nir_after_instr(instr);
1924 continue;
1925 }
1926
1927 /* We're about to ask the callback to generate a replacement for instr.
1928 * Save off the uses from instr's SSA def so we know what uses to
1929 * rewrite later. If we use nir_ssa_def_rewrite_uses, it fails in the
1930 * case where the generated replacement code uses the result of instr
1931 * itself. If we use nir_ssa_def_rewrite_uses_after (which is the
1932 * normal solution to this problem), it doesn't work well if control-
1933 * flow is inserted as part of the replacement, doesn't handle cases
1934 * where the replacement is something consumed by instr, and suffers
1935 * from performance issues. This is the only way to 100% guarantee
1936 * that we rewrite the correct set efficiently.
1937 */
1938 struct list_head old_uses, old_if_uses;
1939 list_replace(&old_def->uses, &old_uses);
1940 list_inithead(&old_def->uses);
1941 list_replace(&old_def->if_uses, &old_if_uses);
1942 list_inithead(&old_def->if_uses);
1943
1944 b.cursor = nir_after_instr(instr);
1945 nir_ssa_def *new_def = lower(&b, instr, cb_data);
1946 if (new_def && new_def != NIR_LOWER_INSTR_PROGRESS) {
1947 assert(old_def != NULL);
1948 if (new_def->parent_instr->block != instr->block)
1949 preserved = nir_metadata_none;
1950
1951 nir_src new_src = nir_src_for_ssa(new_def);
1952 list_for_each_entry_safe(nir_src, use_src, &old_uses, use_link)
1953 nir_instr_rewrite_src(use_src->parent_instr, use_src, new_src);
1954
1955 list_for_each_entry_safe(nir_src, use_src, &old_if_uses, use_link)
1956 nir_if_rewrite_condition(use_src->parent_if, new_src);
1957
1958 if (list_is_empty(&old_def->uses) && list_is_empty(&old_def->if_uses)) {
1959 iter = nir_instr_remove(instr);
1960 } else {
1961 iter = nir_after_instr(instr);
1962 }
1963 progress = true;
1964 } else {
1965 /* We didn't end up lowering after all. Put the uses back */
1966 if (old_def) {
1967 list_replace(&old_uses, &old_def->uses);
1968 list_replace(&old_if_uses, &old_def->if_uses);
1969 }
1970 iter = nir_after_instr(instr);
1971
1972 if (new_def == NIR_LOWER_INSTR_PROGRESS)
1973 progress = true;
1974 }
1975 }
1976
1977 if (progress) {
1978 nir_metadata_preserve(impl, preserved);
1979 } else {
1980 nir_metadata_preserve(impl, nir_metadata_all);
1981 }
1982
1983 return progress;
1984 }
1985
1986 bool
1987 nir_shader_lower_instructions(nir_shader *shader,
1988 nir_instr_filter_cb filter,
1989 nir_lower_instr_cb lower,
1990 void *cb_data)
1991 {
1992 bool progress = false;
1993
1994 nir_foreach_function(function, shader) {
1995 if (function->impl &&
1996 nir_function_impl_lower_instructions(function->impl,
1997 filter, lower, cb_data))
1998 progress = true;
1999 }
2000
2001 return progress;
2002 }
2003
2004 nir_intrinsic_op
2005 nir_intrinsic_from_system_value(gl_system_value val)
2006 {
2007 switch (val) {
2008 case SYSTEM_VALUE_VERTEX_ID:
2009 return nir_intrinsic_load_vertex_id;
2010 case SYSTEM_VALUE_INSTANCE_ID:
2011 return nir_intrinsic_load_instance_id;
2012 case SYSTEM_VALUE_DRAW_ID:
2013 return nir_intrinsic_load_draw_id;
2014 case SYSTEM_VALUE_BASE_INSTANCE:
2015 return nir_intrinsic_load_base_instance;
2016 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
2017 return nir_intrinsic_load_vertex_id_zero_base;
2018 case SYSTEM_VALUE_IS_INDEXED_DRAW:
2019 return nir_intrinsic_load_is_indexed_draw;
2020 case SYSTEM_VALUE_FIRST_VERTEX:
2021 return nir_intrinsic_load_first_vertex;
2022 case SYSTEM_VALUE_BASE_VERTEX:
2023 return nir_intrinsic_load_base_vertex;
2024 case SYSTEM_VALUE_INVOCATION_ID:
2025 return nir_intrinsic_load_invocation_id;
2026 case SYSTEM_VALUE_FRAG_COORD:
2027 return nir_intrinsic_load_frag_coord;
2028 case SYSTEM_VALUE_POINT_COORD:
2029 return nir_intrinsic_load_point_coord;
2030 case SYSTEM_VALUE_LINE_COORD:
2031 return nir_intrinsic_load_line_coord;
2032 case SYSTEM_VALUE_FRONT_FACE:
2033 return nir_intrinsic_load_front_face;
2034 case SYSTEM_VALUE_SAMPLE_ID:
2035 return nir_intrinsic_load_sample_id;
2036 case SYSTEM_VALUE_SAMPLE_POS:
2037 return nir_intrinsic_load_sample_pos;
2038 case SYSTEM_VALUE_SAMPLE_MASK_IN:
2039 return nir_intrinsic_load_sample_mask_in;
2040 case SYSTEM_VALUE_LOCAL_INVOCATION_ID:
2041 return nir_intrinsic_load_local_invocation_id;
2042 case SYSTEM_VALUE_LOCAL_INVOCATION_INDEX:
2043 return nir_intrinsic_load_local_invocation_index;
2044 case SYSTEM_VALUE_WORK_GROUP_ID:
2045 return nir_intrinsic_load_work_group_id;
2046 case SYSTEM_VALUE_NUM_WORK_GROUPS:
2047 return nir_intrinsic_load_num_work_groups;
2048 case SYSTEM_VALUE_PRIMITIVE_ID:
2049 return nir_intrinsic_load_primitive_id;
2050 case SYSTEM_VALUE_TESS_COORD:
2051 return nir_intrinsic_load_tess_coord;
2052 case SYSTEM_VALUE_TESS_LEVEL_OUTER:
2053 return nir_intrinsic_load_tess_level_outer;
2054 case SYSTEM_VALUE_TESS_LEVEL_INNER:
2055 return nir_intrinsic_load_tess_level_inner;
2056 case SYSTEM_VALUE_TESS_LEVEL_OUTER_DEFAULT:
2057 return nir_intrinsic_load_tess_level_outer_default;
2058 case SYSTEM_VALUE_TESS_LEVEL_INNER_DEFAULT:
2059 return nir_intrinsic_load_tess_level_inner_default;
2060 case SYSTEM_VALUE_VERTICES_IN:
2061 return nir_intrinsic_load_patch_vertices_in;
2062 case SYSTEM_VALUE_HELPER_INVOCATION:
2063 return nir_intrinsic_load_helper_invocation;
2064 case SYSTEM_VALUE_COLOR0:
2065 return nir_intrinsic_load_color0;
2066 case SYSTEM_VALUE_COLOR1:
2067 return nir_intrinsic_load_color1;
2068 case SYSTEM_VALUE_VIEW_INDEX:
2069 return nir_intrinsic_load_view_index;
2070 case SYSTEM_VALUE_SUBGROUP_SIZE:
2071 return nir_intrinsic_load_subgroup_size;
2072 case SYSTEM_VALUE_SUBGROUP_INVOCATION:
2073 return nir_intrinsic_load_subgroup_invocation;
2074 case SYSTEM_VALUE_SUBGROUP_EQ_MASK:
2075 return nir_intrinsic_load_subgroup_eq_mask;
2076 case SYSTEM_VALUE_SUBGROUP_GE_MASK:
2077 return nir_intrinsic_load_subgroup_ge_mask;
2078 case SYSTEM_VALUE_SUBGROUP_GT_MASK:
2079 return nir_intrinsic_load_subgroup_gt_mask;
2080 case SYSTEM_VALUE_SUBGROUP_LE_MASK:
2081 return nir_intrinsic_load_subgroup_le_mask;
2082 case SYSTEM_VALUE_SUBGROUP_LT_MASK:
2083 return nir_intrinsic_load_subgroup_lt_mask;
2084 case SYSTEM_VALUE_NUM_SUBGROUPS:
2085 return nir_intrinsic_load_num_subgroups;
2086 case SYSTEM_VALUE_SUBGROUP_ID:
2087 return nir_intrinsic_load_subgroup_id;
2088 case SYSTEM_VALUE_LOCAL_GROUP_SIZE:
2089 return nir_intrinsic_load_local_group_size;
2090 case SYSTEM_VALUE_GLOBAL_INVOCATION_ID:
2091 return nir_intrinsic_load_global_invocation_id;
2092 case SYSTEM_VALUE_GLOBAL_INVOCATION_INDEX:
2093 return nir_intrinsic_load_global_invocation_index;
2094 case SYSTEM_VALUE_WORK_DIM:
2095 return nir_intrinsic_load_work_dim;
2096 case SYSTEM_VALUE_USER_DATA_AMD:
2097 return nir_intrinsic_load_user_data_amd;
2098 default:
2099 unreachable("system value does not directly correspond to intrinsic");
2100 }
2101 }
2102
2103 gl_system_value
2104 nir_system_value_from_intrinsic(nir_intrinsic_op intrin)
2105 {
2106 switch (intrin) {
2107 case nir_intrinsic_load_vertex_id:
2108 return SYSTEM_VALUE_VERTEX_ID;
2109 case nir_intrinsic_load_instance_id:
2110 return SYSTEM_VALUE_INSTANCE_ID;
2111 case nir_intrinsic_load_draw_id:
2112 return SYSTEM_VALUE_DRAW_ID;
2113 case nir_intrinsic_load_base_instance:
2114 return SYSTEM_VALUE_BASE_INSTANCE;
2115 case nir_intrinsic_load_vertex_id_zero_base:
2116 return SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
2117 case nir_intrinsic_load_first_vertex:
2118 return SYSTEM_VALUE_FIRST_VERTEX;
2119 case nir_intrinsic_load_is_indexed_draw:
2120 return SYSTEM_VALUE_IS_INDEXED_DRAW;
2121 case nir_intrinsic_load_base_vertex:
2122 return SYSTEM_VALUE_BASE_VERTEX;
2123 case nir_intrinsic_load_invocation_id:
2124 return SYSTEM_VALUE_INVOCATION_ID;
2125 case nir_intrinsic_load_frag_coord:
2126 return SYSTEM_VALUE_FRAG_COORD;
2127 case nir_intrinsic_load_point_coord:
2128 return SYSTEM_VALUE_POINT_COORD;
2129 case nir_intrinsic_load_line_coord:
2130 return SYSTEM_VALUE_LINE_COORD;
2131 case nir_intrinsic_load_front_face:
2132 return SYSTEM_VALUE_FRONT_FACE;
2133 case nir_intrinsic_load_sample_id:
2134 return SYSTEM_VALUE_SAMPLE_ID;
2135 case nir_intrinsic_load_sample_pos:
2136 return SYSTEM_VALUE_SAMPLE_POS;
2137 case nir_intrinsic_load_sample_mask_in:
2138 return SYSTEM_VALUE_SAMPLE_MASK_IN;
2139 case nir_intrinsic_load_local_invocation_id:
2140 return SYSTEM_VALUE_LOCAL_INVOCATION_ID;
2141 case nir_intrinsic_load_local_invocation_index:
2142 return SYSTEM_VALUE_LOCAL_INVOCATION_INDEX;
2143 case nir_intrinsic_load_num_work_groups:
2144 return SYSTEM_VALUE_NUM_WORK_GROUPS;
2145 case nir_intrinsic_load_work_group_id:
2146 return SYSTEM_VALUE_WORK_GROUP_ID;
2147 case nir_intrinsic_load_primitive_id:
2148 return SYSTEM_VALUE_PRIMITIVE_ID;
2149 case nir_intrinsic_load_tess_coord:
2150 return SYSTEM_VALUE_TESS_COORD;
2151 case nir_intrinsic_load_tess_level_outer:
2152 return SYSTEM_VALUE_TESS_LEVEL_OUTER;
2153 case nir_intrinsic_load_tess_level_inner:
2154 return SYSTEM_VALUE_TESS_LEVEL_INNER;
2155 case nir_intrinsic_load_tess_level_outer_default:
2156 return SYSTEM_VALUE_TESS_LEVEL_OUTER_DEFAULT;
2157 case nir_intrinsic_load_tess_level_inner_default:
2158 return SYSTEM_VALUE_TESS_LEVEL_INNER_DEFAULT;
2159 case nir_intrinsic_load_patch_vertices_in:
2160 return SYSTEM_VALUE_VERTICES_IN;
2161 case nir_intrinsic_load_helper_invocation:
2162 return SYSTEM_VALUE_HELPER_INVOCATION;
2163 case nir_intrinsic_load_color0:
2164 return SYSTEM_VALUE_COLOR0;
2165 case nir_intrinsic_load_color1:
2166 return SYSTEM_VALUE_COLOR1;
2167 case nir_intrinsic_load_view_index:
2168 return SYSTEM_VALUE_VIEW_INDEX;
2169 case nir_intrinsic_load_subgroup_size:
2170 return SYSTEM_VALUE_SUBGROUP_SIZE;
2171 case nir_intrinsic_load_subgroup_invocation:
2172 return SYSTEM_VALUE_SUBGROUP_INVOCATION;
2173 case nir_intrinsic_load_subgroup_eq_mask:
2174 return SYSTEM_VALUE_SUBGROUP_EQ_MASK;
2175 case nir_intrinsic_load_subgroup_ge_mask:
2176 return SYSTEM_VALUE_SUBGROUP_GE_MASK;
2177 case nir_intrinsic_load_subgroup_gt_mask:
2178 return SYSTEM_VALUE_SUBGROUP_GT_MASK;
2179 case nir_intrinsic_load_subgroup_le_mask:
2180 return SYSTEM_VALUE_SUBGROUP_LE_MASK;
2181 case nir_intrinsic_load_subgroup_lt_mask:
2182 return SYSTEM_VALUE_SUBGROUP_LT_MASK;
2183 case nir_intrinsic_load_num_subgroups:
2184 return SYSTEM_VALUE_NUM_SUBGROUPS;
2185 case nir_intrinsic_load_subgroup_id:
2186 return SYSTEM_VALUE_SUBGROUP_ID;
2187 case nir_intrinsic_load_local_group_size:
2188 return SYSTEM_VALUE_LOCAL_GROUP_SIZE;
2189 case nir_intrinsic_load_global_invocation_id:
2190 return SYSTEM_VALUE_GLOBAL_INVOCATION_ID;
2191 case nir_intrinsic_load_user_data_amd:
2192 return SYSTEM_VALUE_USER_DATA_AMD;
2193 default:
2194 unreachable("intrinsic doesn't produce a system value");
2195 }
2196 }
2197
2198 /* OpenGL utility method that remaps the location attributes if they are
2199 * doubles. Not needed for vulkan due the differences on the input location
2200 * count for doubles on vulkan vs OpenGL
2201 *
2202 * The bitfield returned in dual_slot is one bit for each double input slot in
2203 * the original OpenGL single-slot input numbering. The mapping from old
2204 * locations to new locations is as follows:
2205 *
2206 * new_loc = loc + util_bitcount(dual_slot & BITFIELD64_MASK(loc))
2207 */
2208 void
2209 nir_remap_dual_slot_attributes(nir_shader *shader, uint64_t *dual_slot)
2210 {
2211 assert(shader->info.stage == MESA_SHADER_VERTEX);
2212
2213 *dual_slot = 0;
2214 nir_foreach_shader_in_variable(var, shader) {
2215 if (glsl_type_is_dual_slot(glsl_without_array(var->type))) {
2216 unsigned slots = glsl_count_attribute_slots(var->type, true);
2217 *dual_slot |= BITFIELD64_MASK(slots) << var->data.location;
2218 }
2219 }
2220
2221 nir_foreach_shader_in_variable(var, shader) {
2222 var->data.location +=
2223 util_bitcount64(*dual_slot & BITFIELD64_MASK(var->data.location));
2224 }
2225 }
2226
2227 /* Returns an attribute mask that has been re-compacted using the given
2228 * dual_slot mask.
2229 */
2230 uint64_t
2231 nir_get_single_slot_attribs_mask(uint64_t attribs, uint64_t dual_slot)
2232 {
2233 while (dual_slot) {
2234 unsigned loc = u_bit_scan64(&dual_slot);
2235 /* mask of all bits up to and including loc */
2236 uint64_t mask = BITFIELD64_MASK(loc + 1);
2237 attribs = (attribs & mask) | ((attribs & ~mask) >> 1);
2238 }
2239 return attribs;
2240 }
2241
2242 void
2243 nir_rewrite_image_intrinsic(nir_intrinsic_instr *intrin, nir_ssa_def *src,
2244 bool bindless)
2245 {
2246 enum gl_access_qualifier access = nir_intrinsic_access(intrin);
2247
2248 switch (intrin->intrinsic) {
2249 #define CASE(op) \
2250 case nir_intrinsic_image_deref_##op: \
2251 intrin->intrinsic = bindless ? nir_intrinsic_bindless_image_##op \
2252 : nir_intrinsic_image_##op; \
2253 break;
2254 CASE(load)
2255 CASE(store)
2256 CASE(atomic_add)
2257 CASE(atomic_imin)
2258 CASE(atomic_umin)
2259 CASE(atomic_imax)
2260 CASE(atomic_umax)
2261 CASE(atomic_and)
2262 CASE(atomic_or)
2263 CASE(atomic_xor)
2264 CASE(atomic_exchange)
2265 CASE(atomic_comp_swap)
2266 CASE(atomic_fadd)
2267 CASE(atomic_inc_wrap)
2268 CASE(atomic_dec_wrap)
2269 CASE(size)
2270 CASE(samples)
2271 CASE(load_raw_intel)
2272 CASE(store_raw_intel)
2273 #undef CASE
2274 default:
2275 unreachable("Unhanded image intrinsic");
2276 }
2277
2278 nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);
2279 nir_variable *var = nir_deref_instr_get_variable(deref);
2280
2281 nir_intrinsic_set_image_dim(intrin, glsl_get_sampler_dim(deref->type));
2282 nir_intrinsic_set_image_array(intrin, glsl_sampler_type_is_array(deref->type));
2283 nir_intrinsic_set_access(intrin, access | var->data.access);
2284 nir_intrinsic_set_format(intrin, var->data.image.format);
2285
2286 nir_instr_rewrite_src(&intrin->instr, &intrin->src[0],
2287 nir_src_for_ssa(src));
2288 }
2289
2290 unsigned
2291 nir_image_intrinsic_coord_components(const nir_intrinsic_instr *instr)
2292 {
2293 enum glsl_sampler_dim dim = nir_intrinsic_image_dim(instr);
2294 int coords = glsl_get_sampler_dim_coordinate_components(dim);
2295 if (dim == GLSL_SAMPLER_DIM_CUBE)
2296 return coords;
2297 else
2298 return coords + nir_intrinsic_image_array(instr);
2299 }