nir: Add nir_imm_vec4_16
[mesa.git] / src / compiler / nir / nir_builder.h
1 /*
2 * Copyright © 2014-2015 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef NIR_BUILDER_H
25 #define NIR_BUILDER_H
26
27 #include "nir_control_flow.h"
28 #include "util/bitscan.h"
29 #include "util/half_float.h"
30
31 struct exec_list;
32
33 typedef struct nir_builder {
34 nir_cursor cursor;
35
36 /* Whether new ALU instructions will be marked "exact" */
37 bool exact;
38
39 nir_shader *shader;
40 nir_function_impl *impl;
41 } nir_builder;
42
43 static inline void
44 nir_builder_init(nir_builder *build, nir_function_impl *impl)
45 {
46 memset(build, 0, sizeof(*build));
47 build->exact = false;
48 build->impl = impl;
49 build->shader = impl->function->shader;
50 }
51
52 static inline void
53 nir_builder_init_simple_shader(nir_builder *build, void *mem_ctx,
54 gl_shader_stage stage,
55 const nir_shader_compiler_options *options)
56 {
57 build->shader = nir_shader_create(mem_ctx, stage, options, NULL);
58 nir_function *func = nir_function_create(build->shader, "main");
59 func->is_entrypoint = true;
60 build->exact = false;
61 build->impl = nir_function_impl_create(func);
62 build->cursor = nir_after_cf_list(&build->impl->body);
63 }
64
65 static inline void
66 nir_builder_instr_insert(nir_builder *build, nir_instr *instr)
67 {
68 nir_instr_insert(build->cursor, instr);
69
70 /* Move the cursor forward. */
71 build->cursor = nir_after_instr(instr);
72 }
73
74 static inline nir_instr *
75 nir_builder_last_instr(nir_builder *build)
76 {
77 assert(build->cursor.option == nir_cursor_after_instr);
78 return build->cursor.instr;
79 }
80
81 static inline void
82 nir_builder_cf_insert(nir_builder *build, nir_cf_node *cf)
83 {
84 nir_cf_node_insert(build->cursor, cf);
85 }
86
87 static inline bool
88 nir_builder_is_inside_cf(nir_builder *build, nir_cf_node *cf_node)
89 {
90 nir_block *block = nir_cursor_current_block(build->cursor);
91 for (nir_cf_node *n = &block->cf_node; n; n = n->parent) {
92 if (n == cf_node)
93 return true;
94 }
95 return false;
96 }
97
98 static inline nir_if *
99 nir_push_if(nir_builder *build, nir_ssa_def *condition)
100 {
101 nir_if *nif = nir_if_create(build->shader);
102 nif->condition = nir_src_for_ssa(condition);
103 nir_builder_cf_insert(build, &nif->cf_node);
104 build->cursor = nir_before_cf_list(&nif->then_list);
105 return nif;
106 }
107
108 static inline nir_if *
109 nir_push_else(nir_builder *build, nir_if *nif)
110 {
111 if (nif) {
112 assert(nir_builder_is_inside_cf(build, &nif->cf_node));
113 } else {
114 nir_block *block = nir_cursor_current_block(build->cursor);
115 nif = nir_cf_node_as_if(block->cf_node.parent);
116 }
117 build->cursor = nir_before_cf_list(&nif->else_list);
118 return nif;
119 }
120
121 static inline void
122 nir_pop_if(nir_builder *build, nir_if *nif)
123 {
124 if (nif) {
125 assert(nir_builder_is_inside_cf(build, &nif->cf_node));
126 } else {
127 nir_block *block = nir_cursor_current_block(build->cursor);
128 nif = nir_cf_node_as_if(block->cf_node.parent);
129 }
130 build->cursor = nir_after_cf_node(&nif->cf_node);
131 }
132
133 static inline nir_ssa_def *
134 nir_if_phi(nir_builder *build, nir_ssa_def *then_def, nir_ssa_def *else_def)
135 {
136 nir_block *block = nir_cursor_current_block(build->cursor);
137 nir_if *nif = nir_cf_node_as_if(nir_cf_node_prev(&block->cf_node));
138
139 nir_phi_instr *phi = nir_phi_instr_create(build->shader);
140
141 nir_phi_src *src = ralloc(phi, nir_phi_src);
142 src->pred = nir_if_last_then_block(nif);
143 src->src = nir_src_for_ssa(then_def);
144 exec_list_push_tail(&phi->srcs, &src->node);
145
146 src = ralloc(phi, nir_phi_src);
147 src->pred = nir_if_last_else_block(nif);
148 src->src = nir_src_for_ssa(else_def);
149 exec_list_push_tail(&phi->srcs, &src->node);
150
151 assert(then_def->num_components == else_def->num_components);
152 assert(then_def->bit_size == else_def->bit_size);
153 nir_ssa_dest_init(&phi->instr, &phi->dest,
154 then_def->num_components, then_def->bit_size, NULL);
155
156 nir_builder_instr_insert(build, &phi->instr);
157
158 return &phi->dest.ssa;
159 }
160
161 static inline nir_loop *
162 nir_push_loop(nir_builder *build)
163 {
164 nir_loop *loop = nir_loop_create(build->shader);
165 nir_builder_cf_insert(build, &loop->cf_node);
166 build->cursor = nir_before_cf_list(&loop->body);
167 return loop;
168 }
169
170 static inline void
171 nir_pop_loop(nir_builder *build, nir_loop *loop)
172 {
173 if (loop) {
174 assert(nir_builder_is_inside_cf(build, &loop->cf_node));
175 } else {
176 nir_block *block = nir_cursor_current_block(build->cursor);
177 loop = nir_cf_node_as_loop(block->cf_node.parent);
178 }
179 build->cursor = nir_after_cf_node(&loop->cf_node);
180 }
181
182 static inline nir_ssa_def *
183 nir_ssa_undef(nir_builder *build, unsigned num_components, unsigned bit_size)
184 {
185 nir_ssa_undef_instr *undef =
186 nir_ssa_undef_instr_create(build->shader, num_components, bit_size);
187 if (!undef)
188 return NULL;
189
190 nir_instr_insert(nir_before_cf_list(&build->impl->body), &undef->instr);
191
192 return &undef->def;
193 }
194
195 static inline nir_ssa_def *
196 nir_build_imm(nir_builder *build, unsigned num_components,
197 unsigned bit_size, const nir_const_value *value)
198 {
199 nir_load_const_instr *load_const =
200 nir_load_const_instr_create(build->shader, num_components, bit_size);
201 if (!load_const)
202 return NULL;
203
204 memcpy(load_const->value, value, sizeof(nir_const_value) * num_components);
205
206 nir_builder_instr_insert(build, &load_const->instr);
207
208 return &load_const->def;
209 }
210
211 static inline nir_ssa_def *
212 nir_imm_zero(nir_builder *build, unsigned num_components, unsigned bit_size)
213 {
214 nir_load_const_instr *load_const =
215 nir_load_const_instr_create(build->shader, num_components, bit_size);
216
217 /* nir_load_const_instr_create uses rzalloc so it's already zero */
218
219 nir_builder_instr_insert(build, &load_const->instr);
220
221 return &load_const->def;
222 }
223
224 static inline nir_ssa_def *
225 nir_imm_bool(nir_builder *build, bool x)
226 {
227 nir_const_value v;
228
229 memset(&v, 0, sizeof(v));
230 v.b = x;
231
232 return nir_build_imm(build, 1, 1, &v);
233 }
234
235 static inline nir_ssa_def *
236 nir_imm_true(nir_builder *build)
237 {
238 return nir_imm_bool(build, true);
239 }
240
241 static inline nir_ssa_def *
242 nir_imm_false(nir_builder *build)
243 {
244 return nir_imm_bool(build, false);
245 }
246
247 static inline nir_ssa_def *
248 nir_imm_float16(nir_builder *build, float x)
249 {
250 nir_const_value v;
251
252 memset(&v, 0, sizeof(v));
253 v.u16 = _mesa_float_to_half(x);
254
255 return nir_build_imm(build, 1, 16, &v);
256 }
257
258 static inline nir_ssa_def *
259 nir_imm_float(nir_builder *build, float x)
260 {
261 nir_const_value v;
262
263 memset(&v, 0, sizeof(v));
264 v.f32 = x;
265
266 return nir_build_imm(build, 1, 32, &v);
267 }
268
269 static inline nir_ssa_def *
270 nir_imm_double(nir_builder *build, double x)
271 {
272 nir_const_value v;
273
274 memset(&v, 0, sizeof(v));
275 v.f64 = x;
276
277 return nir_build_imm(build, 1, 64, &v);
278 }
279
280 static inline nir_ssa_def *
281 nir_imm_floatN_t(nir_builder *build, double x, unsigned bit_size)
282 {
283 switch (bit_size) {
284 case 16:
285 return nir_imm_float16(build, x);
286 case 32:
287 return nir_imm_float(build, x);
288 case 64:
289 return nir_imm_double(build, x);
290 }
291
292 unreachable("unknown float immediate bit size");
293 }
294
295 static inline nir_ssa_def *
296 nir_imm_vec2(nir_builder *build, float x, float y)
297 {
298 nir_const_value v[2];
299
300 memset(v, 0, sizeof(v));
301 v[0].f32 = x;
302 v[1].f32 = y;
303
304 return nir_build_imm(build, 2, 32, v);
305 }
306
307 static inline nir_ssa_def *
308 nir_imm_vec4(nir_builder *build, float x, float y, float z, float w)
309 {
310 nir_const_value v[4];
311
312 memset(v, 0, sizeof(v));
313 v[0].f32 = x;
314 v[1].f32 = y;
315 v[2].f32 = z;
316 v[3].f32 = w;
317
318 return nir_build_imm(build, 4, 32, v);
319 }
320
321 static inline nir_ssa_def *
322 nir_imm_vec4_16(nir_builder *build, float x, float y, float z, float w)
323 {
324 nir_const_value v[4];
325
326 memset(v, 0, sizeof(v));
327 v[0].u16 = _mesa_float_to_half(x);
328 v[1].u16 = _mesa_float_to_half(y);
329 v[2].u16 = _mesa_float_to_half(z);
330 v[3].u16 = _mesa_float_to_half(w);
331
332 return nir_build_imm(build, 4, 16, v);
333 }
334
335 static inline nir_ssa_def *
336 nir_imm_ivec2(nir_builder *build, int x, int y)
337 {
338 nir_const_value v[2];
339
340 memset(v, 0, sizeof(v));
341 v[0].i32 = x;
342 v[1].i32 = y;
343
344 return nir_build_imm(build, 2, 32, v);
345 }
346
347 static inline nir_ssa_def *
348 nir_imm_int(nir_builder *build, int x)
349 {
350 nir_const_value v;
351
352 memset(&v, 0, sizeof(v));
353 v.i32 = x;
354
355 return nir_build_imm(build, 1, 32, &v);
356 }
357
358 static inline nir_ssa_def *
359 nir_imm_int64(nir_builder *build, int64_t x)
360 {
361 nir_const_value v;
362
363 memset(&v, 0, sizeof(v));
364 v.i64 = x;
365
366 return nir_build_imm(build, 1, 64, &v);
367 }
368
369 static inline nir_ssa_def *
370 nir_imm_intN_t(nir_builder *build, uint64_t x, unsigned bit_size)
371 {
372 nir_const_value v;
373
374 memset(&v, 0, sizeof(v));
375 assert(bit_size <= 64);
376 if (bit_size == 1)
377 v.b = x & 1;
378 else
379 v.i64 = x & (~0ull >> (64 - bit_size));
380
381 return nir_build_imm(build, 1, bit_size, &v);
382 }
383
384 static inline nir_ssa_def *
385 nir_imm_ivec4(nir_builder *build, int x, int y, int z, int w)
386 {
387 nir_const_value v[4];
388
389 memset(v, 0, sizeof(v));
390 v[0].i32 = x;
391 v[1].i32 = y;
392 v[2].i32 = z;
393 v[3].i32 = w;
394
395 return nir_build_imm(build, 4, 32, v);
396 }
397
398 static inline nir_ssa_def *
399 nir_imm_boolN_t(nir_builder *build, bool x, unsigned bit_size)
400 {
401 /* We use a 0/-1 convention for all booleans regardless of size */
402 return nir_imm_intN_t(build, -(int)x, bit_size);
403 }
404
405 static inline nir_ssa_def *
406 nir_builder_alu_instr_finish_and_insert(nir_builder *build, nir_alu_instr *instr)
407 {
408 const nir_op_info *op_info = &nir_op_infos[instr->op];
409
410 instr->exact = build->exact;
411
412 /* Guess the number of components the destination temporary should have
413 * based on our input sizes, if it's not fixed for the op.
414 */
415 unsigned num_components = op_info->output_size;
416 if (num_components == 0) {
417 for (unsigned i = 0; i < op_info->num_inputs; i++) {
418 if (op_info->input_sizes[i] == 0)
419 num_components = MAX2(num_components,
420 instr->src[i].src.ssa->num_components);
421 }
422 }
423 assert(num_components != 0);
424
425 /* Figure out the bitwidth based on the source bitwidth if the instruction
426 * is variable-width.
427 */
428 unsigned bit_size = nir_alu_type_get_type_size(op_info->output_type);
429 if (bit_size == 0) {
430 for (unsigned i = 0; i < op_info->num_inputs; i++) {
431 unsigned src_bit_size = instr->src[i].src.ssa->bit_size;
432 if (nir_alu_type_get_type_size(op_info->input_types[i]) == 0) {
433 if (bit_size)
434 assert(src_bit_size == bit_size);
435 else
436 bit_size = src_bit_size;
437 } else {
438 assert(src_bit_size ==
439 nir_alu_type_get_type_size(op_info->input_types[i]));
440 }
441 }
442 }
443
444 /* When in doubt, assume 32. */
445 if (bit_size == 0)
446 bit_size = 32;
447
448 /* Make sure we don't swizzle from outside of our source vector (like if a
449 * scalar value was passed into a multiply with a vector).
450 */
451 for (unsigned i = 0; i < op_info->num_inputs; i++) {
452 for (unsigned j = instr->src[i].src.ssa->num_components;
453 j < NIR_MAX_VEC_COMPONENTS; j++) {
454 instr->src[i].swizzle[j] = instr->src[i].src.ssa->num_components - 1;
455 }
456 }
457
458 nir_ssa_dest_init(&instr->instr, &instr->dest.dest, num_components,
459 bit_size, NULL);
460 instr->dest.write_mask = (1 << num_components) - 1;
461
462 nir_builder_instr_insert(build, &instr->instr);
463
464 return &instr->dest.dest.ssa;
465 }
466
467 static inline nir_ssa_def *
468 nir_build_alu(nir_builder *build, nir_op op, nir_ssa_def *src0,
469 nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3)
470 {
471 nir_alu_instr *instr = nir_alu_instr_create(build->shader, op);
472 if (!instr)
473 return NULL;
474
475 instr->src[0].src = nir_src_for_ssa(src0);
476 if (src1)
477 instr->src[1].src = nir_src_for_ssa(src1);
478 if (src2)
479 instr->src[2].src = nir_src_for_ssa(src2);
480 if (src3)
481 instr->src[3].src = nir_src_for_ssa(src3);
482
483 return nir_builder_alu_instr_finish_and_insert(build, instr);
484 }
485
486 /* for the couple special cases with more than 4 src args: */
487 static inline nir_ssa_def *
488 nir_build_alu_src_arr(nir_builder *build, nir_op op, nir_ssa_def **srcs)
489 {
490 const nir_op_info *op_info = &nir_op_infos[op];
491 nir_alu_instr *instr = nir_alu_instr_create(build->shader, op);
492 if (!instr)
493 return NULL;
494
495 for (unsigned i = 0; i < op_info->num_inputs; i++)
496 instr->src[i].src = nir_src_for_ssa(srcs[i]);
497
498 return nir_builder_alu_instr_finish_and_insert(build, instr);
499 }
500
501 #include "nir_builder_opcodes.h"
502
503 static inline nir_ssa_def *
504 nir_vec(nir_builder *build, nir_ssa_def **comp, unsigned num_components)
505 {
506 return nir_build_alu_src_arr(build, nir_op_vec(num_components), comp);
507 }
508
509 static inline nir_ssa_def *
510 nir_mov_alu(nir_builder *build, nir_alu_src src, unsigned num_components)
511 {
512 assert(!src.abs && !src.negate);
513 nir_alu_instr *mov = nir_alu_instr_create(build->shader, nir_op_mov);
514 nir_ssa_dest_init(&mov->instr, &mov->dest.dest, num_components,
515 nir_src_bit_size(src.src), NULL);
516 mov->exact = build->exact;
517 mov->dest.write_mask = (1 << num_components) - 1;
518 mov->src[0] = src;
519 nir_builder_instr_insert(build, &mov->instr);
520
521 return &mov->dest.dest.ssa;
522 }
523
524 /**
525 * Construct an fmov or imov that reswizzles the source's components.
526 */
527 static inline nir_ssa_def *
528 nir_swizzle(nir_builder *build, nir_ssa_def *src, const unsigned *swiz,
529 unsigned num_components)
530 {
531 assert(num_components <= NIR_MAX_VEC_COMPONENTS);
532 nir_alu_src alu_src = { NIR_SRC_INIT };
533 alu_src.src = nir_src_for_ssa(src);
534
535 bool is_identity_swizzle = true;
536 for (unsigned i = 0; i < num_components && i < NIR_MAX_VEC_COMPONENTS; i++) {
537 if (swiz[i] != i)
538 is_identity_swizzle = false;
539 alu_src.swizzle[i] = swiz[i];
540 }
541
542 if (num_components == src->num_components && is_identity_swizzle)
543 return src;
544
545 return nir_mov_alu(build, alu_src, num_components);
546 }
547
548 /* Selects the right fdot given the number of components in each source. */
549 static inline nir_ssa_def *
550 nir_fdot(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
551 {
552 assert(src0->num_components == src1->num_components);
553 switch (src0->num_components) {
554 case 1: return nir_fmul(build, src0, src1);
555 case 2: return nir_fdot2(build, src0, src1);
556 case 3: return nir_fdot3(build, src0, src1);
557 case 4: return nir_fdot4(build, src0, src1);
558 default:
559 unreachable("bad component size");
560 }
561
562 return NULL;
563 }
564
565 static inline nir_ssa_def *
566 nir_ball_iequal(nir_builder *b, nir_ssa_def *src0, nir_ssa_def *src1)
567 {
568 switch (src0->num_components) {
569 case 1: return nir_ieq(b, src0, src1);
570 case 2: return nir_ball_iequal2(b, src0, src1);
571 case 3: return nir_ball_iequal3(b, src0, src1);
572 case 4: return nir_ball_iequal4(b, src0, src1);
573 default:
574 unreachable("bad component size");
575 }
576 }
577
578 static inline nir_ssa_def *
579 nir_bany_inequal(nir_builder *b, nir_ssa_def *src0, nir_ssa_def *src1)
580 {
581 switch (src0->num_components) {
582 case 1: return nir_ine(b, src0, src1);
583 case 2: return nir_bany_inequal2(b, src0, src1);
584 case 3: return nir_bany_inequal3(b, src0, src1);
585 case 4: return nir_bany_inequal4(b, src0, src1);
586 default:
587 unreachable("bad component size");
588 }
589 }
590
591 static inline nir_ssa_def *
592 nir_bany(nir_builder *b, nir_ssa_def *src)
593 {
594 return nir_bany_inequal(b, src, nir_imm_false(b));
595 }
596
597 static inline nir_ssa_def *
598 nir_channel(nir_builder *b, nir_ssa_def *def, unsigned c)
599 {
600 return nir_swizzle(b, def, &c, 1);
601 }
602
603 static inline nir_ssa_def *
604 nir_channels(nir_builder *b, nir_ssa_def *def, nir_component_mask_t mask)
605 {
606 unsigned num_channels = 0, swizzle[NIR_MAX_VEC_COMPONENTS] = { 0 };
607
608 for (unsigned i = 0; i < NIR_MAX_VEC_COMPONENTS; i++) {
609 if ((mask & (1 << i)) == 0)
610 continue;
611 swizzle[num_channels++] = i;
612 }
613
614 return nir_swizzle(b, def, swizzle, num_channels);
615 }
616
617 static inline nir_ssa_def *
618 _nir_vector_extract_helper(nir_builder *b, nir_ssa_def *vec, nir_ssa_def *c,
619 unsigned start, unsigned end)
620 {
621 if (start == end - 1) {
622 return nir_channel(b, vec, start);
623 } else {
624 unsigned mid = start + (end - start) / 2;
625 return nir_bcsel(b, nir_ilt(b, c, nir_imm_int(b, mid)),
626 _nir_vector_extract_helper(b, vec, c, start, mid),
627 _nir_vector_extract_helper(b, vec, c, mid, end));
628 }
629 }
630
631 static inline nir_ssa_def *
632 nir_vector_extract(nir_builder *b, nir_ssa_def *vec, nir_ssa_def *c)
633 {
634 nir_src c_src = nir_src_for_ssa(c);
635 if (nir_src_is_const(c_src)) {
636 unsigned c_const = nir_src_as_uint(c_src);
637 if (c_const < vec->num_components)
638 return nir_channel(b, vec, c_const);
639 else
640 return nir_ssa_undef(b, 1, vec->bit_size);
641 } else {
642 return _nir_vector_extract_helper(b, vec, c, 0, vec->num_components);
643 }
644 }
645
646 static inline nir_ssa_def *
647 nir_i2i(nir_builder *build, nir_ssa_def *x, unsigned dest_bit_size)
648 {
649 if (x->bit_size == dest_bit_size)
650 return x;
651
652 switch (dest_bit_size) {
653 case 64: return nir_i2i64(build, x);
654 case 32: return nir_i2i32(build, x);
655 case 16: return nir_i2i16(build, x);
656 case 8: return nir_i2i8(build, x);
657 default: unreachable("Invalid bit size");
658 }
659 }
660
661 static inline nir_ssa_def *
662 nir_u2u(nir_builder *build, nir_ssa_def *x, unsigned dest_bit_size)
663 {
664 if (x->bit_size == dest_bit_size)
665 return x;
666
667 switch (dest_bit_size) {
668 case 64: return nir_u2u64(build, x);
669 case 32: return nir_u2u32(build, x);
670 case 16: return nir_u2u16(build, x);
671 case 8: return nir_u2u8(build, x);
672 default: unreachable("Invalid bit size");
673 }
674 }
675
676 static inline nir_ssa_def *
677 nir_iadd_imm(nir_builder *build, nir_ssa_def *x, uint64_t y)
678 {
679 assert(x->bit_size <= 64);
680 if (x->bit_size < 64)
681 y &= (1ull << x->bit_size) - 1;
682
683 if (y == 0) {
684 return x;
685 } else {
686 return nir_iadd(build, x, nir_imm_intN_t(build, y, x->bit_size));
687 }
688 }
689
690 static inline nir_ssa_def *
691 nir_imul_imm(nir_builder *build, nir_ssa_def *x, uint64_t y)
692 {
693 assert(x->bit_size <= 64);
694 if (x->bit_size < 64)
695 y &= (1ull << x->bit_size) - 1;
696
697 if (y == 0) {
698 return nir_imm_intN_t(build, 0, x->bit_size);
699 } else if (y == 1) {
700 return x;
701 } else if (util_is_power_of_two_or_zero64(y)) {
702 return nir_ishl(build, x, nir_imm_int(build, ffsll(y) - 1));
703 } else {
704 return nir_imul(build, x, nir_imm_intN_t(build, y, x->bit_size));
705 }
706 }
707
708 static inline nir_ssa_def *
709 nir_fadd_imm(nir_builder *build, nir_ssa_def *x, double y)
710 {
711 return nir_fadd(build, x, nir_imm_floatN_t(build, y, x->bit_size));
712 }
713
714 static inline nir_ssa_def *
715 nir_fmul_imm(nir_builder *build, nir_ssa_def *x, double y)
716 {
717 return nir_fmul(build, x, nir_imm_floatN_t(build, y, x->bit_size));
718 }
719
720 static inline nir_ssa_def *
721 nir_pack_bits(nir_builder *b, nir_ssa_def *src, unsigned dest_bit_size)
722 {
723 assert(src->num_components * src->bit_size == dest_bit_size);
724
725 switch (dest_bit_size) {
726 case 64:
727 switch (src->bit_size) {
728 case 32: return nir_pack_64_2x32(b, src);
729 case 16: return nir_pack_64_4x16(b, src);
730 default: break;
731 }
732 break;
733
734 case 32:
735 if (src->bit_size == 16)
736 return nir_pack_32_2x16(b, src);
737 break;
738
739 default:
740 break;
741 }
742
743 /* If we got here, we have no dedicated unpack opcode. */
744 nir_ssa_def *dest = nir_imm_intN_t(b, 0, dest_bit_size);
745 for (unsigned i = 0; i < src->num_components; i++) {
746 nir_ssa_def *val = nir_u2u(b, nir_channel(b, src, i), dest_bit_size);
747 val = nir_ishl(b, val, nir_imm_int(b, i * src->bit_size));
748 dest = nir_ior(b, dest, val);
749 }
750 return dest;
751 }
752
753 static inline nir_ssa_def *
754 nir_unpack_bits(nir_builder *b, nir_ssa_def *src, unsigned dest_bit_size)
755 {
756 assert(src->num_components == 1);
757 assert(src->bit_size > dest_bit_size);
758 const unsigned dest_num_components = src->bit_size / dest_bit_size;
759 assert(dest_num_components <= NIR_MAX_VEC_COMPONENTS);
760
761 switch (src->bit_size) {
762 case 64:
763 switch (dest_bit_size) {
764 case 32: return nir_unpack_64_2x32(b, src);
765 case 16: return nir_unpack_64_4x16(b, src);
766 default: break;
767 }
768 break;
769
770 case 32:
771 if (dest_bit_size == 16)
772 return nir_unpack_32_2x16(b, src);
773 break;
774
775 default:
776 break;
777 }
778
779 /* If we got here, we have no dedicated unpack opcode. */
780 nir_ssa_def *dest_comps[NIR_MAX_VEC_COMPONENTS];
781 for (unsigned i = 0; i < dest_num_components; i++) {
782 nir_ssa_def *val = nir_ushr(b, src, nir_imm_int(b, i * dest_bit_size));
783 dest_comps[i] = nir_u2u(b, val, dest_bit_size);
784 }
785 return nir_vec(b, dest_comps, dest_num_components);
786 }
787
788 static inline nir_ssa_def *
789 nir_bitcast_vector(nir_builder *b, nir_ssa_def *src, unsigned dest_bit_size)
790 {
791 assert((src->bit_size * src->num_components) % dest_bit_size == 0);
792 const unsigned dest_num_components =
793 (src->bit_size * src->num_components) / dest_bit_size;
794 assert(dest_num_components <= NIR_MAX_VEC_COMPONENTS);
795
796 if (src->bit_size > dest_bit_size) {
797 assert(src->bit_size % dest_bit_size == 0);
798 if (src->num_components == 1) {
799 return nir_unpack_bits(b, src, dest_bit_size);
800 } else {
801 const unsigned divisor = src->bit_size / dest_bit_size;
802 assert(src->num_components * divisor == dest_num_components);
803 nir_ssa_def *dest[NIR_MAX_VEC_COMPONENTS];
804 for (unsigned i = 0; i < src->num_components; i++) {
805 nir_ssa_def *unpacked =
806 nir_unpack_bits(b, nir_channel(b, src, i), dest_bit_size);
807 assert(unpacked->num_components == divisor);
808 for (unsigned j = 0; j < divisor; j++)
809 dest[i * divisor + j] = nir_channel(b, unpacked, j);
810 }
811 return nir_vec(b, dest, dest_num_components);
812 }
813 } else if (src->bit_size < dest_bit_size) {
814 assert(dest_bit_size % src->bit_size == 0);
815 if (dest_num_components == 1) {
816 return nir_pack_bits(b, src, dest_bit_size);
817 } else {
818 const unsigned divisor = dest_bit_size / src->bit_size;
819 assert(src->num_components == dest_num_components * divisor);
820 nir_ssa_def *dest[NIR_MAX_VEC_COMPONENTS];
821 for (unsigned i = 0; i < dest_num_components; i++) {
822 nir_component_mask_t src_mask =
823 ((1 << divisor) - 1) << (i * divisor);
824 dest[i] = nir_pack_bits(b, nir_channels(b, src, src_mask),
825 dest_bit_size);
826 }
827 return nir_vec(b, dest, dest_num_components);
828 }
829 } else {
830 assert(src->bit_size == dest_bit_size);
831 return src;
832 }
833 }
834
835 /**
836 * Turns a nir_src into a nir_ssa_def * so it can be passed to
837 * nir_build_alu()-based builder calls.
838 *
839 * See nir_ssa_for_alu_src() for alu instructions.
840 */
841 static inline nir_ssa_def *
842 nir_ssa_for_src(nir_builder *build, nir_src src, int num_components)
843 {
844 if (src.is_ssa && src.ssa->num_components == num_components)
845 return src.ssa;
846
847 nir_alu_src alu = { NIR_SRC_INIT };
848 alu.src = src;
849 for (int j = 0; j < 4; j++)
850 alu.swizzle[j] = j;
851
852 return nir_mov_alu(build, alu, num_components);
853 }
854
855 /**
856 * Similar to nir_ssa_for_src(), but for alu srcs, respecting the
857 * nir_alu_src's swizzle.
858 */
859 static inline nir_ssa_def *
860 nir_ssa_for_alu_src(nir_builder *build, nir_alu_instr *instr, unsigned srcn)
861 {
862 static uint8_t trivial_swizzle[NIR_MAX_VEC_COMPONENTS];
863 for (int i = 0; i < NIR_MAX_VEC_COMPONENTS; ++i)
864 trivial_swizzle[i] = i;
865 nir_alu_src *src = &instr->src[srcn];
866 unsigned num_components = nir_ssa_alu_instr_src_components(instr, srcn);
867
868 if (src->src.is_ssa && (src->src.ssa->num_components == num_components) &&
869 !src->abs && !src->negate &&
870 (memcmp(src->swizzle, trivial_swizzle, num_components) == 0))
871 return src->src.ssa;
872
873 return nir_mov_alu(build, *src, num_components);
874 }
875
876 static inline unsigned
877 nir_get_ptr_bitsize(nir_builder *build)
878 {
879 if (build->shader->info.stage == MESA_SHADER_KERNEL)
880 return build->shader->info.cs.ptr_size;
881 return 32;
882 }
883
884 static inline nir_deref_instr *
885 nir_build_deref_var(nir_builder *build, nir_variable *var)
886 {
887 nir_deref_instr *deref =
888 nir_deref_instr_create(build->shader, nir_deref_type_var);
889
890 deref->mode = var->data.mode;
891 deref->type = var->type;
892 deref->var = var;
893
894 nir_ssa_dest_init(&deref->instr, &deref->dest, 1,
895 nir_get_ptr_bitsize(build), NULL);
896
897 nir_builder_instr_insert(build, &deref->instr);
898
899 return deref;
900 }
901
902 static inline nir_deref_instr *
903 nir_build_deref_array(nir_builder *build, nir_deref_instr *parent,
904 nir_ssa_def *index)
905 {
906 assert(glsl_type_is_array(parent->type) ||
907 glsl_type_is_matrix(parent->type) ||
908 glsl_type_is_vector(parent->type));
909
910 assert(index->bit_size == parent->dest.ssa.bit_size);
911
912 nir_deref_instr *deref =
913 nir_deref_instr_create(build->shader, nir_deref_type_array);
914
915 deref->mode = parent->mode;
916 deref->type = glsl_get_array_element(parent->type);
917 deref->parent = nir_src_for_ssa(&parent->dest.ssa);
918 deref->arr.index = nir_src_for_ssa(index);
919
920 nir_ssa_dest_init(&deref->instr, &deref->dest,
921 parent->dest.ssa.num_components,
922 parent->dest.ssa.bit_size, NULL);
923
924 nir_builder_instr_insert(build, &deref->instr);
925
926 return deref;
927 }
928
929 static inline nir_deref_instr *
930 nir_build_deref_array_imm(nir_builder *build, nir_deref_instr *parent,
931 int64_t index)
932 {
933 assert(parent->dest.is_ssa);
934 nir_ssa_def *idx_ssa = nir_imm_intN_t(build, index,
935 parent->dest.ssa.bit_size);
936
937 return nir_build_deref_array(build, parent, idx_ssa);
938 }
939
940 static inline nir_deref_instr *
941 nir_build_deref_ptr_as_array(nir_builder *build, nir_deref_instr *parent,
942 nir_ssa_def *index)
943 {
944 assert(parent->deref_type == nir_deref_type_array ||
945 parent->deref_type == nir_deref_type_ptr_as_array ||
946 parent->deref_type == nir_deref_type_cast);
947
948 assert(index->bit_size == parent->dest.ssa.bit_size);
949
950 nir_deref_instr *deref =
951 nir_deref_instr_create(build->shader, nir_deref_type_ptr_as_array);
952
953 deref->mode = parent->mode;
954 deref->type = parent->type;
955 deref->parent = nir_src_for_ssa(&parent->dest.ssa);
956 deref->arr.index = nir_src_for_ssa(index);
957
958 nir_ssa_dest_init(&deref->instr, &deref->dest,
959 parent->dest.ssa.num_components,
960 parent->dest.ssa.bit_size, NULL);
961
962 nir_builder_instr_insert(build, &deref->instr);
963
964 return deref;
965 }
966
967 static inline nir_deref_instr *
968 nir_build_deref_array_wildcard(nir_builder *build, nir_deref_instr *parent)
969 {
970 assert(glsl_type_is_array(parent->type) ||
971 glsl_type_is_matrix(parent->type));
972
973 nir_deref_instr *deref =
974 nir_deref_instr_create(build->shader, nir_deref_type_array_wildcard);
975
976 deref->mode = parent->mode;
977 deref->type = glsl_get_array_element(parent->type);
978 deref->parent = nir_src_for_ssa(&parent->dest.ssa);
979
980 nir_ssa_dest_init(&deref->instr, &deref->dest,
981 parent->dest.ssa.num_components,
982 parent->dest.ssa.bit_size, NULL);
983
984 nir_builder_instr_insert(build, &deref->instr);
985
986 return deref;
987 }
988
989 static inline nir_deref_instr *
990 nir_build_deref_struct(nir_builder *build, nir_deref_instr *parent,
991 unsigned index)
992 {
993 assert(glsl_type_is_struct_or_ifc(parent->type));
994
995 nir_deref_instr *deref =
996 nir_deref_instr_create(build->shader, nir_deref_type_struct);
997
998 deref->mode = parent->mode;
999 deref->type = glsl_get_struct_field(parent->type, index);
1000 deref->parent = nir_src_for_ssa(&parent->dest.ssa);
1001 deref->strct.index = index;
1002
1003 nir_ssa_dest_init(&deref->instr, &deref->dest,
1004 parent->dest.ssa.num_components,
1005 parent->dest.ssa.bit_size, NULL);
1006
1007 nir_builder_instr_insert(build, &deref->instr);
1008
1009 return deref;
1010 }
1011
1012 static inline nir_deref_instr *
1013 nir_build_deref_cast(nir_builder *build, nir_ssa_def *parent,
1014 nir_variable_mode mode, const struct glsl_type *type,
1015 unsigned ptr_stride)
1016 {
1017 nir_deref_instr *deref =
1018 nir_deref_instr_create(build->shader, nir_deref_type_cast);
1019
1020 deref->mode = mode;
1021 deref->type = type;
1022 deref->parent = nir_src_for_ssa(parent);
1023 deref->cast.ptr_stride = ptr_stride;
1024
1025 nir_ssa_dest_init(&deref->instr, &deref->dest,
1026 parent->num_components, parent->bit_size, NULL);
1027
1028 nir_builder_instr_insert(build, &deref->instr);
1029
1030 return deref;
1031 }
1032
1033 /** Returns a deref that follows another but starting from the given parent
1034 *
1035 * The new deref will be the same type and take the same array or struct index
1036 * as the leader deref but it may have a different parent. This is very
1037 * useful for walking deref paths.
1038 */
1039 static inline nir_deref_instr *
1040 nir_build_deref_follower(nir_builder *b, nir_deref_instr *parent,
1041 nir_deref_instr *leader)
1042 {
1043 /* If the derefs would have the same parent, don't make a new one */
1044 assert(leader->parent.is_ssa);
1045 if (leader->parent.ssa == &parent->dest.ssa)
1046 return leader;
1047
1048 UNUSED nir_deref_instr *leader_parent = nir_src_as_deref(leader->parent);
1049
1050 switch (leader->deref_type) {
1051 case nir_deref_type_var:
1052 unreachable("A var dereference cannot have a parent");
1053 break;
1054
1055 case nir_deref_type_array:
1056 case nir_deref_type_array_wildcard:
1057 assert(glsl_type_is_matrix(parent->type) ||
1058 glsl_type_is_array(parent->type) ||
1059 (leader->deref_type == nir_deref_type_array &&
1060 glsl_type_is_vector(parent->type)));
1061 assert(glsl_get_length(parent->type) ==
1062 glsl_get_length(leader_parent->type));
1063
1064 if (leader->deref_type == nir_deref_type_array) {
1065 assert(leader->arr.index.is_ssa);
1066 nir_ssa_def *index = nir_i2i(b, leader->arr.index.ssa,
1067 parent->dest.ssa.bit_size);
1068 return nir_build_deref_array(b, parent, index);
1069 } else {
1070 return nir_build_deref_array_wildcard(b, parent);
1071 }
1072
1073 case nir_deref_type_struct:
1074 assert(glsl_type_is_struct_or_ifc(parent->type));
1075 assert(glsl_get_length(parent->type) ==
1076 glsl_get_length(leader_parent->type));
1077
1078 return nir_build_deref_struct(b, parent, leader->strct.index);
1079
1080 default:
1081 unreachable("Invalid deref instruction type");
1082 }
1083 }
1084
1085 static inline nir_ssa_def *
1086 nir_load_reg(nir_builder *build, nir_register *reg)
1087 {
1088 return nir_ssa_for_src(build, nir_src_for_reg(reg), reg->num_components);
1089 }
1090
1091 static inline nir_ssa_def *
1092 nir_load_deref_with_access(nir_builder *build, nir_deref_instr *deref,
1093 enum gl_access_qualifier access)
1094 {
1095 nir_intrinsic_instr *load =
1096 nir_intrinsic_instr_create(build->shader, nir_intrinsic_load_deref);
1097 load->num_components = glsl_get_vector_elements(deref->type);
1098 load->src[0] = nir_src_for_ssa(&deref->dest.ssa);
1099 nir_ssa_dest_init(&load->instr, &load->dest, load->num_components,
1100 glsl_get_bit_size(deref->type), NULL);
1101 nir_intrinsic_set_access(load, access);
1102 nir_builder_instr_insert(build, &load->instr);
1103 return &load->dest.ssa;
1104 }
1105
1106 static inline nir_ssa_def *
1107 nir_load_deref(nir_builder *build, nir_deref_instr *deref)
1108 {
1109 return nir_load_deref_with_access(build, deref, (enum gl_access_qualifier)0);
1110 }
1111
1112 static inline void
1113 nir_store_deref_with_access(nir_builder *build, nir_deref_instr *deref,
1114 nir_ssa_def *value, unsigned writemask,
1115 enum gl_access_qualifier access)
1116 {
1117 nir_intrinsic_instr *store =
1118 nir_intrinsic_instr_create(build->shader, nir_intrinsic_store_deref);
1119 store->num_components = glsl_get_vector_elements(deref->type);
1120 store->src[0] = nir_src_for_ssa(&deref->dest.ssa);
1121 store->src[1] = nir_src_for_ssa(value);
1122 nir_intrinsic_set_write_mask(store,
1123 writemask & ((1 << store->num_components) - 1));
1124 nir_intrinsic_set_access(store, access);
1125 nir_builder_instr_insert(build, &store->instr);
1126 }
1127
1128 static inline void
1129 nir_store_deref(nir_builder *build, nir_deref_instr *deref,
1130 nir_ssa_def *value, unsigned writemask)
1131 {
1132 nir_store_deref_with_access(build, deref, value, writemask,
1133 (enum gl_access_qualifier)0);
1134 }
1135
1136 static inline void
1137 nir_copy_deref_with_access(nir_builder *build, nir_deref_instr *dest,
1138 nir_deref_instr *src,
1139 enum gl_access_qualifier dest_access,
1140 enum gl_access_qualifier src_access)
1141 {
1142 nir_intrinsic_instr *copy =
1143 nir_intrinsic_instr_create(build->shader, nir_intrinsic_copy_deref);
1144 copy->src[0] = nir_src_for_ssa(&dest->dest.ssa);
1145 copy->src[1] = nir_src_for_ssa(&src->dest.ssa);
1146 nir_intrinsic_set_dst_access(copy, dest_access);
1147 nir_intrinsic_set_src_access(copy, src_access);
1148 nir_builder_instr_insert(build, &copy->instr);
1149 }
1150
1151 static inline void
1152 nir_copy_deref(nir_builder *build, nir_deref_instr *dest, nir_deref_instr *src)
1153 {
1154 nir_copy_deref_with_access(build, dest, src,
1155 (enum gl_access_qualifier) 0,
1156 (enum gl_access_qualifier) 0);
1157 }
1158
1159 static inline nir_ssa_def *
1160 nir_load_var(nir_builder *build, nir_variable *var)
1161 {
1162 return nir_load_deref(build, nir_build_deref_var(build, var));
1163 }
1164
1165 static inline void
1166 nir_store_var(nir_builder *build, nir_variable *var, nir_ssa_def *value,
1167 unsigned writemask)
1168 {
1169 nir_store_deref(build, nir_build_deref_var(build, var), value, writemask);
1170 }
1171
1172 static inline void
1173 nir_copy_var(nir_builder *build, nir_variable *dest, nir_variable *src)
1174 {
1175 nir_copy_deref(build, nir_build_deref_var(build, dest),
1176 nir_build_deref_var(build, src));
1177 }
1178
1179 static inline nir_ssa_def *
1180 nir_load_param(nir_builder *build, uint32_t param_idx)
1181 {
1182 assert(param_idx < build->impl->function->num_params);
1183 nir_parameter *param = &build->impl->function->params[param_idx];
1184
1185 nir_intrinsic_instr *load =
1186 nir_intrinsic_instr_create(build->shader, nir_intrinsic_load_param);
1187 nir_intrinsic_set_param_idx(load, param_idx);
1188 load->num_components = param->num_components;
1189 nir_ssa_dest_init(&load->instr, &load->dest,
1190 param->num_components, param->bit_size, NULL);
1191 nir_builder_instr_insert(build, &load->instr);
1192 return &load->dest.ssa;
1193 }
1194
1195 #include "nir_builder_opcodes.h"
1196
1197 static inline nir_ssa_def *
1198 nir_f2b(nir_builder *build, nir_ssa_def *f)
1199 {
1200 return nir_f2b1(build, f);
1201 }
1202
1203 static inline nir_ssa_def *
1204 nir_i2b(nir_builder *build, nir_ssa_def *i)
1205 {
1206 return nir_i2b1(build, i);
1207 }
1208
1209 static inline nir_ssa_def *
1210 nir_b2f(nir_builder *build, nir_ssa_def *b, uint32_t bit_size)
1211 {
1212 switch (bit_size) {
1213 case 64: return nir_b2f64(build, b);
1214 case 32: return nir_b2f32(build, b);
1215 case 16: return nir_b2f16(build, b);
1216 default:
1217 unreachable("Invalid bit-size");
1218 };
1219 }
1220
1221 static inline nir_ssa_def *
1222 nir_load_barycentric(nir_builder *build, nir_intrinsic_op op,
1223 unsigned interp_mode)
1224 {
1225 nir_intrinsic_instr *bary = nir_intrinsic_instr_create(build->shader, op);
1226 nir_ssa_dest_init(&bary->instr, &bary->dest, 2, 32, NULL);
1227 nir_intrinsic_set_interp_mode(bary, interp_mode);
1228 nir_builder_instr_insert(build, &bary->instr);
1229 return &bary->dest.ssa;
1230 }
1231
1232 static inline void
1233 nir_jump(nir_builder *build, nir_jump_type jump_type)
1234 {
1235 nir_jump_instr *jump = nir_jump_instr_create(build->shader, jump_type);
1236 nir_builder_instr_insert(build, &jump->instr);
1237 }
1238
1239 static inline nir_ssa_def *
1240 nir_compare_func(nir_builder *b, enum compare_func func,
1241 nir_ssa_def *src0, nir_ssa_def *src1)
1242 {
1243 switch (func) {
1244 case COMPARE_FUNC_NEVER:
1245 return nir_imm_int(b, 0);
1246 case COMPARE_FUNC_ALWAYS:
1247 return nir_imm_int(b, ~0);
1248 case COMPARE_FUNC_EQUAL:
1249 return nir_feq(b, src0, src1);
1250 case COMPARE_FUNC_NOTEQUAL:
1251 return nir_fne(b, src0, src1);
1252 case COMPARE_FUNC_GREATER:
1253 return nir_flt(b, src1, src0);
1254 case COMPARE_FUNC_GEQUAL:
1255 return nir_fge(b, src0, src1);
1256 case COMPARE_FUNC_LESS:
1257 return nir_flt(b, src0, src1);
1258 case COMPARE_FUNC_LEQUAL:
1259 return nir_fge(b, src1, src0);
1260 }
1261 unreachable("bad compare func");
1262 }
1263
1264 #endif /* NIR_BUILDER_H */