src/compiler/nir/nir_lower_bool_to_float.c

   1 /*
   2  * Copyright © 2018 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "nir.h"
  25 #include "nir_builder.h"
  26
  27 static bool
  28 assert_ssa_def_is_not_1bit(nir_ssa_def *def, UNUSED void *unused)
  29 {
  30    assert(def->bit_size > 1);
  31    return true;
  32 }
  33
  34 static bool
  35 rewrite_1bit_ssa_def_to_32bit(nir_ssa_def *def, void *_progress)
  36 {
  37    bool *progress = _progress;
  38    if (def->bit_size == 1) {
  39       def->bit_size = 32;
  40       *progress = true;
  41    }
  42    return true;
  43 }
  44
  45 static bool
  46 lower_alu_instr(nir_builder *b, nir_alu_instr *alu)
  47 {
  48    const nir_op_info *op_info = &nir_op_infos[alu->op];
  49
  50    b->cursor = nir_before_instr(&alu->instr);
  51
  52    /* Replacement SSA value */
  53    nir_ssa_def *rep = NULL;
  54    switch (alu->op) {
  55    case nir_op_mov:
  56    case nir_op_vec2:
  57    case nir_op_vec3:
  58    case nir_op_vec4:
  59    case nir_op_vec8:
  60    case nir_op_vec16:
  61       if (alu->dest.dest.ssa.bit_size != 1)
  62          return false;
  63       /* These we expect to have booleans but the opcode doesn't change */
  64       break;
  65
  66    case nir_op_b2f32: alu->op = nir_op_mov; break;
  67    case nir_op_b2i32: alu->op = nir_op_mov; break;
  68    case nir_op_f2b1:
  69    case nir_op_i2b1:
  70       rep = nir_sne(b, nir_ssa_for_alu_src(b, alu, 0),
  71                        nir_imm_float(b, 0));
  72       break;
  73    case nir_op_b2b1: alu->op = nir_op_mov; break;
  74
  75    case nir_op_flt: alu->op = nir_op_slt; break;
  76    case nir_op_fge: alu->op = nir_op_sge; break;
  77    case nir_op_feq: alu->op = nir_op_seq; break;
  78    case nir_op_fneu: alu->op = nir_op_sne; break;
  79    case nir_op_ilt: alu->op = nir_op_slt; break;
  80    case nir_op_ige: alu->op = nir_op_sge; break;
  81    case nir_op_ieq: alu->op = nir_op_seq; break;
  82    case nir_op_ine: alu->op = nir_op_sne; break;
  83    case nir_op_ult: alu->op = nir_op_slt; break;
  84    case nir_op_uge: alu->op = nir_op_sge; break;
  85
  86    case nir_op_ball_fequal2:  alu->op = nir_op_fall_equal2; break;
  87    case nir_op_ball_fequal3:  alu->op = nir_op_fall_equal3; break;
  88    case nir_op_ball_fequal4:  alu->op = nir_op_fall_equal4; break;
  89    case nir_op_bany_fnequal2: alu->op = nir_op_fany_nequal2; break;
  90    case nir_op_bany_fnequal3: alu->op = nir_op_fany_nequal3; break;
  91    case nir_op_bany_fnequal4: alu->op = nir_op_fany_nequal4; break;
  92    case nir_op_ball_iequal2:  alu->op = nir_op_fall_equal2; break;
  93    case nir_op_ball_iequal3:  alu->op = nir_op_fall_equal3; break;
  94    case nir_op_ball_iequal4:  alu->op = nir_op_fall_equal4; break;
  95    case nir_op_bany_inequal2: alu->op = nir_op_fany_nequal2; break;
  96    case nir_op_bany_inequal3: alu->op = nir_op_fany_nequal3; break;
  97    case nir_op_bany_inequal4: alu->op = nir_op_fany_nequal4; break;
  98
  99    case nir_op_bcsel: alu->op = nir_op_fcsel; break;
 100
 101    case nir_op_iand: alu->op = nir_op_fmul; break;
 102    case nir_op_ixor: alu->op = nir_op_sne; break;
 103    case nir_op_ior: alu->op = nir_op_fmax; break;
 104
 105    case nir_op_inot:
 106       rep = nir_seq(b, nir_ssa_for_alu_src(b, alu, 0),
 107                        nir_imm_float(b, 0));
 108       break;
 109
 110    default:
 111       assert(alu->dest.dest.ssa.bit_size > 1);
 112       for (unsigned i = 0; i < op_info->num_inputs; i++)
 113          assert(alu->src[i].src.ssa->bit_size > 1);
 114       return false;
 115    }
 116
 117    if (rep) {
 118       /* We've emitted a replacement instruction */
 119       nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(rep));
 120       nir_instr_remove(&alu->instr);
 121    } else {
 122       if (alu->dest.dest.ssa.bit_size == 1)
 123          alu->dest.dest.ssa.bit_size = 32;
 124    }
 125
 126    return true;
 127 }
 128
 129 static bool
 130 nir_lower_bool_to_float_impl(nir_function_impl *impl)
 131 {
 132    bool progress = false;
 133
 134    nir_builder b;
 135    nir_builder_init(&b, impl);
 136
 137    nir_foreach_block(block, impl) {
 138       nir_foreach_instr_safe(instr, block) {
 139          switch (instr->type) {
 140          case nir_instr_type_alu:
 141             progress |= lower_alu_instr(&b, nir_instr_as_alu(instr));
 142             break;
 143
 144          case nir_instr_type_load_const: {
 145             nir_load_const_instr *load = nir_instr_as_load_const(instr);
 146             if (load->def.bit_size == 1) {
 147                nir_const_value *value = load->value;
 148                for (unsigned i = 0; i < load->def.num_components; i++)
 149                   load->value[i].f32 = value[i].b ? 1.0 : 0.0;
 150                load->def.bit_size = 32;
 151                progress = true;
 152             }
 153             break;
 154          }
 155
 156          case nir_instr_type_intrinsic:
 157          case nir_instr_type_ssa_undef:
 158          case nir_instr_type_phi:
 159          case nir_instr_type_tex:
 160             nir_foreach_ssa_def(instr, rewrite_1bit_ssa_def_to_32bit,
 161                                 &progress);
 162             break;
 163
 164          default:
 165             nir_foreach_ssa_def(instr, assert_ssa_def_is_not_1bit, NULL);
 166          }
 167       }
 168    }
 169
 170    if (progress) {
 171       nir_metadata_preserve(impl, nir_metadata_block_index |
 172                                   nir_metadata_dominance);
 173    }
 174
 175    return progress;
 176 }
 177
 178 bool
 179 nir_lower_bool_to_float(nir_shader *shader)
 180 {
 181    bool progress = false;
 182
 183    nir_foreach_function(function, shader) {
 184       if (function->impl && nir_lower_bool_to_float_impl(function->impl))
 185          progress = true;
 186    }
 187
 188    return progress;
 189 }