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24 #include "nir_schedule.h"
26 #include "util/u_dynarray.h"
30 * Implements basic-block-level prepass instruction scheduling in NIR to
31 * manage register pressure.
33 * This is based on the Goodman/Hsu paper (1988, cached copy at
34 * https://people.freedesktop.org/~anholt/scheduling-goodman-hsu.pdf). We
35 * make up the DDG for NIR (which can be mostly done using the NIR def/use
36 * chains for SSA instructions, plus some edges for ordering register writes
37 * vs reads, and some more for ordering intrinsics). Then we pick heads off
38 * of the DDG using their heuristic to emit the NIR instructions back into the
39 * block in their new order.
41 * The hard case for prepass scheduling on GPUs seems to always be consuming
42 * texture/ubo results. The register pressure heuristic doesn't want to pick
43 * an instr that starts consuming texture results because it usually won't be
44 * the only usage, so that instruction will increase pressure.
46 * If you try to force consumption of tex results always, then in a case where
47 * single sample is used for many outputs, you'll end up picking every other
48 * user and expanding register pressure. The partially_evaluated_path flag
49 * helps tremendously, in that if you happen for whatever reason to pick a
50 * texture sample's output, then you'll try to finish off that sample. Future
51 * work may include doing some local search before locking in a choice, to try
52 * to more reliably find the case where just a few choices going against the
53 * heuristic can manage to free the whole vector.
59 * Represents a node in the DDG for a NIR instruction.
62 struct dag_node dag
; /* must be first for our u_dynarray_foreach */
64 bool partially_evaluated_path
;
66 /* Approximate estimate of the delay between starting this instruction and
67 * its results being available.
69 * Accuracy is not too important, given that we're prepass scheduling here
70 * and just trying to reduce excess dependencies introduced by a register
71 * allocator by stretching out the live intervals of expensive
76 /* Cost of the maximum-delay path from this node to the leaves. */
79 /* scoreboard->time value when this instruction can be scheduled without
80 * any stalls expected.
90 /* Mapping from nir_register * or nir_ssa_def * to a struct set of
91 * instructions remaining to be scheduled using the register.
93 struct hash_table
*remaining_uses
;
95 /* Map from nir_instr to nir_schedule_node * */
96 struct hash_table
*instr_map
;
98 /* Set of nir_register * or nir_ssa_def * that have had any instruction
101 struct set
*live_values
;
103 /* An abstract approximation of the number of nir_scheduler_node->delay
104 * units since the start of the shader.
108 /* Number of channels currently used by the NIR instructions that have been
113 /* Number of channels that may be in use before we switch to the
114 * pressure-prioritizing scheduling heuristic.
118 /* Mask of stages that share memory for inputs and outputs */
119 unsigned stages_with_shared_io_memory
;
120 } nir_schedule_scoreboard
;
122 /* When walking the instructions in reverse, we use this flag to swap
123 * before/after in add_dep().
125 enum direction
{ F
, R
};
128 nir_schedule_scoreboard
*scoreboard
;
130 /* Map from nir_register to nir_schedule_node * */
131 struct hash_table
*reg_map
;
133 /* Scheduler nodes for last instruction involved in some class of dependency.
135 nir_schedule_node
*load_input
;
136 nir_schedule_node
*store_shared
;
137 nir_schedule_node
*unknown_intrinsic
;
138 nir_schedule_node
*discard
;
139 nir_schedule_node
*jump
;
145 _mesa_hash_table_search_data(struct hash_table
*ht
, void *key
)
147 struct hash_entry
*entry
= _mesa_hash_table_search(ht
, key
);
153 static nir_schedule_node
*
154 nir_schedule_get_node(struct hash_table
*instr_map
, nir_instr
*instr
)
156 return _mesa_hash_table_search_data(instr_map
, instr
);
160 nir_schedule_scoreboard_get_src(nir_schedule_scoreboard
*scoreboard
, nir_src
*src
)
163 return _mesa_hash_table_search_data(scoreboard
->remaining_uses
, src
->ssa
);
165 return _mesa_hash_table_search_data(scoreboard
->remaining_uses
,
171 nir_schedule_def_pressure(nir_ssa_def
*def
)
173 return def
->num_components
;
177 nir_schedule_src_pressure(nir_src
*src
)
180 return nir_schedule_def_pressure(src
->ssa
);
182 return src
->reg
.reg
->num_components
;
186 nir_schedule_dest_pressure(nir_dest
*dest
)
189 return nir_schedule_def_pressure(&dest
->ssa
);
191 return dest
->reg
.reg
->num_components
;
195 * Adds a dependency such that @after must appear in the final program after
198 * We add @before as a child of @after, so that DAG heads are the outputs of
199 * the program and we make our scheduling decisions bottom to top.
202 add_dep(nir_deps_state
*state
,
203 nir_schedule_node
*before
,
204 nir_schedule_node
*after
)
206 if (!before
|| !after
)
209 assert(before
!= after
);
212 dag_add_edge(&before
->dag
, &after
->dag
, NULL
);
214 dag_add_edge(&after
->dag
, &before
->dag
, NULL
);
219 add_read_dep(nir_deps_state
*state
,
220 nir_schedule_node
*before
,
221 nir_schedule_node
*after
)
223 add_dep(state
, before
, after
);
227 add_write_dep(nir_deps_state
*state
,
228 nir_schedule_node
**before
,
229 nir_schedule_node
*after
)
231 add_dep(state
, *before
, after
);
236 nir_schedule_reg_src_deps(nir_src
*src
, void *in_state
)
238 nir_deps_state
*state
= in_state
;
243 struct hash_entry
*entry
= _mesa_hash_table_search(state
->reg_map
,
247 nir_schedule_node
*dst_n
= entry
->data
;
249 nir_schedule_node
*src_n
=
250 nir_schedule_get_node(state
->scoreboard
->instr_map
,
253 add_dep(state
, dst_n
, src_n
);
259 nir_schedule_reg_dest_deps(nir_dest
*dest
, void *in_state
)
261 nir_deps_state
*state
= in_state
;
266 nir_schedule_node
*dest_n
=
267 nir_schedule_get_node(state
->scoreboard
->instr_map
,
268 dest
->reg
.parent_instr
);
270 struct hash_entry
*entry
= _mesa_hash_table_search(state
->reg_map
,
273 _mesa_hash_table_insert(state
->reg_map
, dest
->reg
.reg
, dest_n
);
276 nir_schedule_node
**before
= (nir_schedule_node
**)&entry
->data
;
278 add_write_dep(state
, before
, dest_n
);
284 nir_schedule_ssa_deps(nir_ssa_def
*def
, void *in_state
)
286 nir_deps_state
*state
= in_state
;
287 struct hash_table
*instr_map
= state
->scoreboard
->instr_map
;
288 nir_schedule_node
*def_n
= nir_schedule_get_node(instr_map
, def
->parent_instr
);
290 nir_foreach_use(src
, def
) {
291 nir_schedule_node
*use_n
= nir_schedule_get_node(instr_map
,
294 add_read_dep(state
, def_n
, use_n
);
301 nir_schedule_intrinsic_deps(nir_deps_state
*state
,
302 nir_intrinsic_instr
*instr
)
304 nir_schedule_node
*n
= nir_schedule_get_node(state
->scoreboard
->instr_map
,
307 switch (instr
->intrinsic
) {
308 case nir_intrinsic_load_uniform
:
309 case nir_intrinsic_load_ubo
:
310 case nir_intrinsic_load_front_face
:
313 case nir_intrinsic_discard
:
314 case nir_intrinsic_discard_if
:
315 /* We are adding two dependencies:
317 * * A individual one that we could use to add a read_dep while handling
320 * * Include it on the unknown intrinsic set, as we want discard to be
321 * serialized in in the same order relative to intervening stores or
322 * atomic accesses to SSBOs and images
324 add_write_dep(state
, &state
->discard
, n
);
325 add_write_dep(state
, &state
->unknown_intrinsic
, n
);
328 case nir_intrinsic_store_output
:
329 /* For some hardware and stages, output stores affect the same shared
330 * memory as input loads.
332 if ((state
->scoreboard
->stages_with_shared_io_memory
&
333 (1 << state
->scoreboard
->shader
->info
.stage
)))
334 add_write_dep(state
, &state
->load_input
, n
);
336 /* Make sure that preceding discards stay before the store_output */
337 add_read_dep(state
, state
->discard
, n
);
341 case nir_intrinsic_load_input
:
342 case nir_intrinsic_load_per_vertex_input
:
343 add_read_dep(state
, state
->load_input
, n
);
346 case nir_intrinsic_load_shared
:
347 /* Don't move load_shared beyond a following store_shared, as it could
350 add_read_dep(state
, state
->store_shared
, n
);
353 case nir_intrinsic_store_shared
:
354 add_write_dep(state
, &state
->store_shared
, n
);
357 case nir_intrinsic_control_barrier
:
358 case nir_intrinsic_memory_barrier_shared
:
359 add_write_dep(state
, &state
->store_shared
, n
);
361 /* Serialize against ssbos/atomics/etc. */
362 add_write_dep(state
, &state
->unknown_intrinsic
, n
);
366 /* Attempt to handle other intrinsics that we haven't individually
367 * categorized by serializing them in the same order relative to each
370 add_write_dep(state
, &state
->unknown_intrinsic
, n
);
376 * Common code for dependencies that need to be tracked both forward and
379 * This is for things like "all reads of r4 have to happen between the r4
380 * writes that surround them".
383 nir_schedule_calculate_deps(nir_deps_state
*state
, nir_schedule_node
*n
)
385 nir_instr
*instr
= n
->instr
;
387 /* For NIR SSA defs, we only need to do a single pass of making the uses
391 nir_foreach_ssa_def(instr
, nir_schedule_ssa_deps
, state
);
393 /* For NIR regs, track the last writer in the scheduler state so that we
394 * can keep the writes in order and let reads get reordered only between
397 nir_foreach_src(instr
, nir_schedule_reg_src_deps
, state
);
399 nir_foreach_dest(instr
, nir_schedule_reg_dest_deps
, state
);
401 /* Make sure any other instructions keep their positions relative to
404 if (instr
->type
!= nir_instr_type_jump
)
405 add_read_dep(state
, state
->jump
, n
);
407 switch (instr
->type
) {
408 case nir_instr_type_ssa_undef
:
409 case nir_instr_type_load_const
:
410 case nir_instr_type_alu
:
411 case nir_instr_type_deref
:
414 case nir_instr_type_tex
:
415 /* Don't move texture ops before a discard, as that could increase
416 * memory bandwidth for reading the discarded samples.
418 add_read_dep(state
, state
->discard
, n
);
421 case nir_instr_type_jump
:
422 add_write_dep(state
, &state
->jump
, n
);
425 case nir_instr_type_call
:
426 unreachable("Calls should have been lowered");
429 case nir_instr_type_parallel_copy
:
430 unreachable("Parallel copies should have been lowered");
433 case nir_instr_type_phi
:
434 unreachable("nir_schedule() should be called after lowering from SSA");
437 case nir_instr_type_intrinsic
:
438 nir_schedule_intrinsic_deps(state
, nir_instr_as_intrinsic(instr
));
444 calculate_forward_deps(nir_schedule_scoreboard
*scoreboard
, nir_block
*block
)
446 nir_deps_state state
= {
447 .scoreboard
= scoreboard
,
449 .reg_map
= _mesa_pointer_hash_table_create(NULL
),
452 nir_foreach_instr(instr
, block
) {
453 nir_schedule_node
*node
= nir_schedule_get_node(scoreboard
->instr_map
,
455 nir_schedule_calculate_deps(&state
, node
);
458 ralloc_free(state
.reg_map
);
462 calculate_reverse_deps(nir_schedule_scoreboard
*scoreboard
, nir_block
*block
)
464 nir_deps_state state
= {
465 .scoreboard
= scoreboard
,
467 .reg_map
= _mesa_pointer_hash_table_create(NULL
),
470 nir_foreach_instr_reverse(instr
, block
) {
471 nir_schedule_node
*node
= nir_schedule_get_node(scoreboard
->instr_map
,
473 nir_schedule_calculate_deps(&state
, node
);
476 ralloc_free(state
.reg_map
);
480 nir_schedule_scoreboard
*scoreboard
;
482 } nir_schedule_regs_freed_state
;
485 nir_schedule_regs_freed_src_cb(nir_src
*src
, void *in_state
)
487 nir_schedule_regs_freed_state
*state
= in_state
;
488 nir_schedule_scoreboard
*scoreboard
= state
->scoreboard
;
489 struct set
*remaining_uses
= nir_schedule_scoreboard_get_src(scoreboard
, src
);
491 if (remaining_uses
->entries
== 1 &&
492 _mesa_set_search(remaining_uses
, src
->parent_instr
)) {
493 state
->regs_freed
+= nir_schedule_src_pressure(src
);
500 nir_schedule_regs_freed_def_cb(nir_ssa_def
*def
, void *in_state
)
502 nir_schedule_regs_freed_state
*state
= in_state
;
504 state
->regs_freed
-= nir_schedule_def_pressure(def
);
510 nir_schedule_regs_freed_dest_cb(nir_dest
*dest
, void *in_state
)
512 nir_schedule_regs_freed_state
*state
= in_state
;
513 nir_schedule_scoreboard
*scoreboard
= state
->scoreboard
;
518 nir_register
*reg
= dest
->reg
.reg
;
520 /* Only the first def of a reg counts against register pressure. */
521 if (!_mesa_set_search(scoreboard
->live_values
, reg
))
522 state
->regs_freed
-= nir_schedule_dest_pressure(dest
);
528 nir_schedule_regs_freed(nir_schedule_scoreboard
*scoreboard
, nir_schedule_node
*n
)
530 nir_schedule_regs_freed_state state
= {
531 .scoreboard
= scoreboard
,
534 nir_foreach_src(n
->instr
, nir_schedule_regs_freed_src_cb
, &state
);
536 nir_foreach_ssa_def(n
->instr
, nir_schedule_regs_freed_def_cb
, &state
);
538 nir_foreach_dest(n
->instr
, nir_schedule_regs_freed_dest_cb
, &state
);
540 return state
.regs_freed
;
544 * Chooses an instruction to schedule using the Goodman/Hsu (1988) CSP (Code
545 * Scheduling for Parallelism) heuristic.
547 * Picks an instruction on the critical that's ready to execute without
548 * stalls, if possible, otherwise picks the instruction on the critical path.
550 static nir_schedule_node
*
551 nir_schedule_choose_instruction_csp(nir_schedule_scoreboard
*scoreboard
)
553 nir_schedule_node
*chosen
= NULL
;
555 /* Find the leader in the ready (shouldn't-stall) set with the maximum
558 list_for_each_entry(nir_schedule_node
, n
, &scoreboard
->dag
->heads
, dag
.link
) {
559 if (scoreboard
->time
< n
->ready_time
)
562 if (!chosen
|| chosen
->max_delay
< n
->max_delay
)
567 fprintf(stderr
, "chose (ready): ");
568 nir_print_instr(chosen
->instr
, stderr
);
569 fprintf(stderr
, "\n");
575 /* Otherwise, choose the leader with the maximum cost. */
576 list_for_each_entry(nir_schedule_node
, n
, &scoreboard
->dag
->heads
, dag
.link
) {
577 if (!chosen
|| chosen
->max_delay
< n
->max_delay
)
581 fprintf(stderr
, "chose (leader): ");
582 nir_print_instr(chosen
->instr
, stderr
);
583 fprintf(stderr
, "\n");
590 * Chooses an instruction to schedule using the Goodman/Hsu (1988) CSR (Code
591 * Scheduling for Register pressure) heuristic.
593 static nir_schedule_node
*
594 nir_schedule_choose_instruction_csr(nir_schedule_scoreboard
*scoreboard
)
596 nir_schedule_node
*chosen
= NULL
;
598 /* Find a ready inst with regs freed and pick the one with max cost. */
599 list_for_each_entry(nir_schedule_node
, n
, &scoreboard
->dag
->heads
, dag
.link
) {
600 if (n
->ready_time
> scoreboard
->time
)
603 int regs_freed
= nir_schedule_regs_freed(scoreboard
, n
);
605 if (regs_freed
> 0 && (!chosen
|| chosen
->max_delay
< n
->max_delay
)) {
611 fprintf(stderr
, "chose (freed+ready): ");
612 nir_print_instr(chosen
->instr
, stderr
);
613 fprintf(stderr
, "\n");
619 /* Find a leader with regs freed and pick the one with max cost. */
620 list_for_each_entry(nir_schedule_node
, n
, &scoreboard
->dag
->heads
, dag
.link
) {
621 int regs_freed
= nir_schedule_regs_freed(scoreboard
, n
);
623 if (regs_freed
> 0 && (!chosen
|| chosen
->max_delay
< n
->max_delay
)) {
629 fprintf(stderr
, "chose (regs freed): ");
630 nir_print_instr(chosen
->instr
, stderr
);
631 fprintf(stderr
, "\n");
637 /* Find a partially evaluated path and try to finish it off */
638 list_for_each_entry(nir_schedule_node
, n
, &scoreboard
->dag
->heads
, dag
.link
) {
639 if (n
->partially_evaluated_path
&&
640 (!chosen
|| chosen
->max_delay
< n
->max_delay
)) {
646 fprintf(stderr
, "chose (partial path): ");
647 nir_print_instr(chosen
->instr
, stderr
);
648 fprintf(stderr
, "\n");
654 /* Contra the paper, pick a leader with no effect on used regs. This may
655 * open up new opportunities, as otherwise a single-operand instr consuming
656 * a value will tend to block finding freeing that value. This had a
657 * massive effect on reducing spilling on V3D.
659 * XXX: Should this prioritize ready?
661 list_for_each_entry(nir_schedule_node
, n
, &scoreboard
->dag
->heads
, dag
.link
) {
662 if (nir_schedule_regs_freed(scoreboard
, n
) != 0)
665 if (!chosen
|| chosen
->max_delay
< n
->max_delay
)
670 fprintf(stderr
, "chose (regs no-op): ");
671 nir_print_instr(chosen
->instr
, stderr
);
672 fprintf(stderr
, "\n");
678 /* Pick the max delay of the remaining ready set. */
679 list_for_each_entry(nir_schedule_node
, n
, &scoreboard
->dag
->heads
, dag
.link
) {
680 if (n
->ready_time
> scoreboard
->time
)
682 if (!chosen
|| chosen
->max_delay
< n
->max_delay
)
687 fprintf(stderr
, "chose (ready max delay): ");
688 nir_print_instr(chosen
->instr
, stderr
);
689 fprintf(stderr
, "\n");
694 /* Pick the max delay of the remaining leaders. */
695 list_for_each_entry(nir_schedule_node
, n
, &scoreboard
->dag
->heads
, dag
.link
) {
696 if (!chosen
|| chosen
->max_delay
< n
->max_delay
)
701 fprintf(stderr
, "chose (max delay): ");
702 nir_print_instr(chosen
->instr
, stderr
);
703 fprintf(stderr
, "\n");
710 dump_state(nir_schedule_scoreboard
*scoreboard
)
712 list_for_each_entry(nir_schedule_node
, n
, &scoreboard
->dag
->heads
, dag
.link
) {
713 fprintf(stderr
, "maxdel %5d ", n
->max_delay
);
714 nir_print_instr(n
->instr
, stderr
);
715 fprintf(stderr
, "\n");
717 util_dynarray_foreach(&n
->dag
.edges
, struct dag_edge
, edge
) {
718 nir_schedule_node
*child
= (nir_schedule_node
*)edge
->child
;
720 fprintf(stderr
, " -> (%d parents) ", child
->dag
.parent_count
);
721 nir_print_instr(child
->instr
, stderr
);
722 fprintf(stderr
, "\n");
728 nir_schedule_mark_use(nir_schedule_scoreboard
*scoreboard
,
730 nir_instr
*reg_or_def_parent
,
733 /* Make the value live if it's the first time it's been used. */
734 if (!_mesa_set_search(scoreboard
->live_values
, reg_or_def
)) {
735 _mesa_set_add(scoreboard
->live_values
, reg_or_def
);
736 scoreboard
->pressure
+= pressure
;
739 /* Make the value dead if it's the last remaining use. Be careful when one
740 * instruction uses a value twice to not decrement pressure twice.
742 struct set
*remaining_uses
=
743 _mesa_hash_table_search_data(scoreboard
->remaining_uses
, reg_or_def
);
744 struct set_entry
*entry
= _mesa_set_search(remaining_uses
, reg_or_def_parent
);
746 _mesa_set_remove(remaining_uses
, entry
);
748 if (remaining_uses
->entries
== 0)
749 scoreboard
->pressure
-= pressure
;
754 nir_schedule_mark_src_scheduled(nir_src
*src
, void *state
)
756 nir_schedule_scoreboard
*scoreboard
= state
;
757 struct set
*remaining_uses
= nir_schedule_scoreboard_get_src(scoreboard
, src
);
759 struct set_entry
*entry
= _mesa_set_search(remaining_uses
,
762 /* Once we've used an SSA value in one instruction, bump the priority of
763 * the other uses so the SSA value can get fully consumed.
765 * We don't do this for registers, and it's would be a hassle and it's
766 * unclear if that would help or not. Also, skip it for constants, as
767 * they're often folded as immediates into backend instructions and have
768 * many unrelated instructions all referencing the same value (0).
771 src
->ssa
->parent_instr
->type
!= nir_instr_type_load_const
) {
772 nir_foreach_use(other_src
, src
->ssa
) {
773 if (other_src
->parent_instr
== src
->parent_instr
)
776 nir_schedule_node
*n
=
777 nir_schedule_get_node(scoreboard
->instr_map
,
778 other_src
->parent_instr
);
780 if (n
&& !n
->partially_evaluated_path
) {
782 fprintf(stderr
, " New partially evaluated path: ");
783 nir_print_instr(n
->instr
, stderr
);
784 fprintf(stderr
, "\n");
787 n
->partially_evaluated_path
= true;
793 nir_schedule_mark_use(scoreboard
,
794 src
->is_ssa
? (void *)src
->ssa
: (void *)src
->reg
.reg
,
796 nir_schedule_src_pressure(src
));
802 nir_schedule_mark_def_scheduled(nir_ssa_def
*def
, void *state
)
804 nir_schedule_scoreboard
*scoreboard
= state
;
806 nir_schedule_mark_use(scoreboard
, def
, def
->parent_instr
,
807 nir_schedule_def_pressure(def
));
813 nir_schedule_mark_dest_scheduled(nir_dest
*dest
, void *state
)
815 nir_schedule_scoreboard
*scoreboard
= state
;
817 /* SSA defs were handled in nir_schedule_mark_def_scheduled()
822 /* XXX: This is not actually accurate for regs -- the last use of a reg may
823 * have a live interval that extends across control flow. We should
824 * calculate the live ranges of regs, and have scheduler nodes for the CF
825 * nodes that also "use" the reg.
827 nir_schedule_mark_use(scoreboard
, dest
->reg
.reg
,
828 dest
->reg
.parent_instr
,
829 nir_schedule_dest_pressure(dest
));
835 nir_schedule_mark_node_scheduled(nir_schedule_scoreboard
*scoreboard
,
836 nir_schedule_node
*n
)
838 nir_foreach_src(n
->instr
, nir_schedule_mark_src_scheduled
, scoreboard
);
839 nir_foreach_ssa_def(n
->instr
, nir_schedule_mark_def_scheduled
, scoreboard
);
840 nir_foreach_dest(n
->instr
, nir_schedule_mark_dest_scheduled
, scoreboard
);
842 util_dynarray_foreach(&n
->dag
.edges
, struct dag_edge
, edge
) {
843 nir_schedule_node
*child
= (nir_schedule_node
*)edge
->child
;
845 child
->ready_time
= MAX2(child
->ready_time
,
846 scoreboard
->time
+ n
->delay
);
848 if (child
->dag
.parent_count
== 1) {
850 fprintf(stderr
, " New DAG head: ");
851 nir_print_instr(child
->instr
, stderr
);
852 fprintf(stderr
, "\n");
857 dag_prune_head(scoreboard
->dag
, &n
->dag
);
859 scoreboard
->time
= MAX2(n
->ready_time
, scoreboard
->time
);
864 nir_schedule_instructions(nir_schedule_scoreboard
*scoreboard
, nir_block
*block
)
866 while (!list_is_empty(&scoreboard
->dag
->heads
)) {
868 fprintf(stderr
, "current list:\n");
869 dump_state(scoreboard
);
872 nir_schedule_node
*chosen
;
873 if (scoreboard
->pressure
< scoreboard
->threshold
)
874 chosen
= nir_schedule_choose_instruction_csp(scoreboard
);
876 chosen
= nir_schedule_choose_instruction_csr(scoreboard
);
878 /* Now that we've scheduled a new instruction, some of its children may
879 * be promoted to the list of instructions ready to be scheduled.
881 nir_schedule_mark_node_scheduled(scoreboard
, chosen
);
883 /* Move the instruction to the end (so our first chosen instructions are
884 * the start of the program).
886 exec_node_remove(&chosen
->instr
->node
);
887 exec_list_push_tail(&block
->instr_list
, &chosen
->instr
->node
);
890 fprintf(stderr
, "\n");
895 nir_schedule_get_delay(nir_instr
*instr
)
897 switch (instr
->type
) {
898 case nir_instr_type_ssa_undef
:
899 case nir_instr_type_load_const
:
900 case nir_instr_type_alu
:
901 case nir_instr_type_deref
:
902 case nir_instr_type_jump
:
903 case nir_instr_type_parallel_copy
:
904 case nir_instr_type_call
:
905 case nir_instr_type_phi
:
908 case nir_instr_type_intrinsic
:
909 /* XXX: Pick a large number for UBO/SSBO/image/shared loads */
912 case nir_instr_type_tex
:
913 /* Pick some large number to try to fetch textures early and sample them
923 nir_schedule_dag_max_delay_cb(struct dag_node
*node
, void *state
)
925 nir_schedule_node
*n
= (nir_schedule_node
*)node
;
926 uint32_t max_delay
= 0;
928 util_dynarray_foreach(&n
->dag
.edges
, struct dag_edge
, edge
) {
929 nir_schedule_node
*child
= (nir_schedule_node
*)edge
->child
;
930 max_delay
= MAX2(child
->max_delay
, max_delay
);
933 n
->max_delay
= MAX2(n
->max_delay
, max_delay
+ n
->delay
);
937 nir_schedule_block(nir_schedule_scoreboard
*scoreboard
, nir_block
*block
)
939 void *mem_ctx
= ralloc_context(NULL
);
940 scoreboard
->instr_map
= _mesa_pointer_hash_table_create(mem_ctx
);
942 scoreboard
->dag
= dag_create(mem_ctx
);
944 nir_foreach_instr(instr
, block
) {
945 nir_schedule_node
*n
=
946 rzalloc(mem_ctx
, nir_schedule_node
);
949 n
->delay
= nir_schedule_get_delay(instr
);
950 dag_init_node(scoreboard
->dag
, &n
->dag
);
952 _mesa_hash_table_insert(scoreboard
->instr_map
, instr
, n
);
955 calculate_forward_deps(scoreboard
, block
);
956 calculate_reverse_deps(scoreboard
, block
);
958 dag_traverse_bottom_up(scoreboard
->dag
, nir_schedule_dag_max_delay_cb
, NULL
);
960 nir_schedule_instructions(scoreboard
, block
);
962 ralloc_free(mem_ctx
);
963 scoreboard
->instr_map
= NULL
;
967 nir_schedule_ssa_def_init_scoreboard(nir_ssa_def
*def
, void *state
)
969 nir_schedule_scoreboard
*scoreboard
= state
;
970 struct set
*def_uses
= _mesa_pointer_set_create(scoreboard
);
972 _mesa_hash_table_insert(scoreboard
->remaining_uses
, def
, def_uses
);
974 _mesa_set_add(def_uses
, def
->parent_instr
);
976 nir_foreach_use(src
, def
) {
977 _mesa_set_add(def_uses
, src
->parent_instr
);
980 /* XXX: Handle if uses */
985 static nir_schedule_scoreboard
*
986 nir_schedule_get_scoreboard(nir_shader
*shader
,
987 const nir_schedule_options
*options
)
989 nir_schedule_scoreboard
*scoreboard
= rzalloc(NULL
, nir_schedule_scoreboard
);
991 scoreboard
->shader
= shader
;
992 scoreboard
->live_values
= _mesa_pointer_set_create(scoreboard
);
993 scoreboard
->remaining_uses
= _mesa_pointer_hash_table_create(scoreboard
);
994 scoreboard
->threshold
= options
->threshold
;
995 scoreboard
->stages_with_shared_io_memory
=
996 options
->stages_with_shared_io_memory
;
997 scoreboard
->pressure
= 0;
999 nir_foreach_function(function
, shader
) {
1000 nir_foreach_register(reg
, &function
->impl
->registers
) {
1001 struct set
*register_uses
=
1002 _mesa_pointer_set_create(scoreboard
);
1004 _mesa_hash_table_insert(scoreboard
->remaining_uses
, reg
, register_uses
);
1006 nir_foreach_use(src
, reg
) {
1007 _mesa_set_add(register_uses
, src
->parent_instr
);
1010 /* XXX: Handle if uses */
1012 nir_foreach_def(dest
, reg
) {
1013 _mesa_set_add(register_uses
, dest
->reg
.parent_instr
);
1017 nir_foreach_block(block
, function
->impl
) {
1018 nir_foreach_instr(instr
, block
) {
1019 nir_foreach_ssa_def(instr
, nir_schedule_ssa_def_init_scoreboard
,
1023 /* XXX: We're ignoring if uses, which may prioritize scheduling other
1024 * uses of the if src even when it doesn't help. That's not many
1025 * values, though, so meh.
1034 nir_schedule_validate_uses(nir_schedule_scoreboard
*scoreboard
)
1040 bool any_uses
= false;
1042 hash_table_foreach(scoreboard
->remaining_uses
, entry
) {
1043 struct set
*remaining_uses
= entry
->data
;
1045 set_foreach(remaining_uses
, instr_entry
) {
1047 fprintf(stderr
, "Tracked uses remain after scheduling. "
1048 "Affected instructions: \n");
1051 nir_print_instr(instr_entry
->key
, stderr
);
1052 fprintf(stderr
, "\n");
1060 * Schedules the NIR instructions to try to decrease stalls (for example,
1061 * delaying texture reads) while managing register pressure.
1063 * The threshold represents "number of NIR register/SSA def channels live
1064 * before switching the scheduling heuristic to reduce register pressure",
1065 * since most of our GPU architectures are scalar (extending to vector with a
1066 * flag wouldn't be hard). This number should be a bit below the number of
1067 * registers available (counting any that may be occupied by system value
1068 * payload values, for example), since the heuristic may not always be able to
1069 * free a register immediately. The amount below the limit is up to you to
1073 nir_schedule(nir_shader
*shader
,
1074 const nir_schedule_options
*options
)
1076 nir_schedule_scoreboard
*scoreboard
= nir_schedule_get_scoreboard(shader
,
1080 fprintf(stderr
, "NIR shader before scheduling:\n");
1081 nir_print_shader(shader
, stderr
);
1084 nir_foreach_function(function
, shader
) {
1085 if (!function
->impl
)
1088 nir_foreach_block(block
, function
->impl
) {
1089 nir_schedule_block(scoreboard
, block
);
1093 nir_schedule_validate_uses(scoreboard
);
1095 ralloc_free(scoreboard
);