src/etnaviv/drm/etnaviv_drmif.h

   1 /*
   2  * Copyright (C) 2014-2015 Etnaviv Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Christian Gmeiner <christian.gmeiner@gmail.com>
  25  */
  26
  27 #ifndef ETNAVIV_DRMIF_H_
  28 #define ETNAVIV_DRMIF_H_
  29
  30 #include <xf86drm.h>
  31 #include <stdint.h>
  32
  33 struct etna_bo;
  34 struct etna_pipe;
  35 struct etna_gpu;
  36 struct etna_device;
  37 struct etna_cmd_stream;
  38 struct etna_perfmon;
  39 struct etna_perfmon_domain;
  40 struct etna_perfmon_signal;
  41
  42 enum etna_pipe_id {
  43         ETNA_PIPE_3D = 0,
  44         ETNA_PIPE_2D = 1,
  45         ETNA_PIPE_VG = 2,
  46         ETNA_PIPE_MAX
  47 };
  48
  49 enum etna_param_id {
  50         ETNA_GPU_MODEL                     = 0x1,
  51         ETNA_GPU_REVISION                  = 0x2,
  52         ETNA_GPU_FEATURES_0                = 0x3,
  53         ETNA_GPU_FEATURES_1                = 0x4,
  54         ETNA_GPU_FEATURES_2                = 0x5,
  55         ETNA_GPU_FEATURES_3                = 0x6,
  56         ETNA_GPU_FEATURES_4                = 0x7,
  57         ETNA_GPU_FEATURES_5                = 0x8,
  58         ETNA_GPU_FEATURES_6                = 0x9,
  59         ETNA_GPU_FEATURES_7                = 0xa,
  60
  61         ETNA_GPU_STREAM_COUNT              = 0x10,
  62         ETNA_GPU_REGISTER_MAX              = 0x11,
  63         ETNA_GPU_THREAD_COUNT              = 0x12,
  64         ETNA_GPU_VERTEX_CACHE_SIZE         = 0x13,
  65         ETNA_GPU_SHADER_CORE_COUNT         = 0x14,
  66         ETNA_GPU_PIXEL_PIPES               = 0x15,
  67         ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE = 0x16,
  68         ETNA_GPU_BUFFER_SIZE               = 0x17,
  69         ETNA_GPU_INSTRUCTION_COUNT         = 0x18,
  70         ETNA_GPU_NUM_CONSTANTS             = 0x19,
  71         ETNA_GPU_NUM_VARYINGS              = 0x1a
  72 };
  73
  74 /* bo flags: */
  75 #define DRM_ETNA_GEM_CACHE_CACHED       0x00010000
  76 #define DRM_ETNA_GEM_CACHE_WC           0x00020000
  77 #define DRM_ETNA_GEM_CACHE_UNCACHED     0x00040000
  78 #define DRM_ETNA_GEM_CACHE_MASK         0x000f0000
  79 /* map flags */
  80 #define DRM_ETNA_GEM_FORCE_MMU          0x00100000
  81
  82 /* bo access flags: (keep aligned to ETNA_PREP_x) */
  83 #define DRM_ETNA_PREP_READ              0x01
  84 #define DRM_ETNA_PREP_WRITE             0x02
  85 #define DRM_ETNA_PREP_NOSYNC            0x04
  86
  87 /* device functions:
  88  */
  89
  90 struct etna_device *etna_device_new(int fd);
  91 struct etna_device *etna_device_new_dup(int fd);
  92 struct etna_device *etna_device_ref(struct etna_device *dev);
  93 void etna_device_del(struct etna_device *dev);
  94 int etna_device_fd(struct etna_device *dev);
  95
  96 /* gpu functions:
  97  */
  98
  99 struct etna_gpu *etna_gpu_new(struct etna_device *dev, unsigned int core);
 100 void etna_gpu_del(struct etna_gpu *gpu);
 101 int etna_gpu_get_param(struct etna_gpu *gpu, enum etna_param_id param,
 102                 uint64_t *value);
 103
 104
 105 /* pipe functions:
 106  */
 107
 108 struct etna_pipe *etna_pipe_new(struct etna_gpu *gpu, enum etna_pipe_id id);
 109 void etna_pipe_del(struct etna_pipe *pipe);
 110 int etna_pipe_wait(struct etna_pipe *pipe, uint32_t timestamp, uint32_t ms);
 111 int etna_pipe_wait_ns(struct etna_pipe *pipe, uint32_t timestamp, uint64_t ns);
 112
 113
 114 /* buffer-object functions:
 115  */
 116
 117 struct etna_bo *etna_bo_new(struct etna_device *dev,
 118                 uint32_t size, uint32_t flags);
 119 struct etna_bo *etna_bo_from_name(struct etna_device *dev, uint32_t name);
 120 struct etna_bo *etna_bo_from_dmabuf(struct etna_device *dev, int fd);
 121 struct etna_bo *etna_bo_ref(struct etna_bo *bo);
 122 void etna_bo_del(struct etna_bo *bo);
 123 int etna_bo_get_name(struct etna_bo *bo, uint32_t *name);
 124 uint32_t etna_bo_handle(struct etna_bo *bo);
 125 int etna_bo_dmabuf(struct etna_bo *bo);
 126 uint32_t etna_bo_size(struct etna_bo *bo);
 127 void * etna_bo_map(struct etna_bo *bo);
 128 int etna_bo_cpu_prep(struct etna_bo *bo, uint32_t op);
 129 void etna_bo_cpu_fini(struct etna_bo *bo);
 130
 131
 132 /* cmd stream functions:
 133  */
 134
 135 struct etna_cmd_stream {
 136         uint32_t *buffer;
 137         uint32_t offset;        /* in 32-bit words */
 138         uint32_t size;          /* in 32-bit words */
 139 };
 140
 141 struct etna_cmd_stream *etna_cmd_stream_new(struct etna_pipe *pipe, uint32_t size,
 142                 void (*reset_notify)(struct etna_cmd_stream *stream, void *priv),
 143                 void *priv);
 144 void etna_cmd_stream_del(struct etna_cmd_stream *stream);
 145 uint32_t etna_cmd_stream_timestamp(struct etna_cmd_stream *stream);
 146 void etna_cmd_stream_flush(struct etna_cmd_stream *stream);
 147 void etna_cmd_stream_flush2(struct etna_cmd_stream *stream, int in_fence_fd,
 148                             int *out_fence_fd);
 149 void etna_cmd_stream_finish(struct etna_cmd_stream *stream);
 150
 151 static inline uint32_t etna_cmd_stream_avail(struct etna_cmd_stream *stream)
 152 {
 153         static const uint32_t END_CLEARANCE = 2; /* LINK op code */
 154
 155         return stream->size - stream->offset - END_CLEARANCE;
 156 }
 157
 158 static inline void etna_cmd_stream_reserve(struct etna_cmd_stream *stream, size_t n)
 159 {
 160         if (etna_cmd_stream_avail(stream) < n)
 161                 etna_cmd_stream_flush(stream);
 162 }
 163
 164 static inline void etna_cmd_stream_emit(struct etna_cmd_stream *stream, uint32_t data)
 165 {
 166         stream->buffer[stream->offset++] = data;
 167 }
 168
 169 static inline uint32_t etna_cmd_stream_get(struct etna_cmd_stream *stream, uint32_t offset)
 170 {
 171         return stream->buffer[offset];
 172 }
 173
 174 static inline void etna_cmd_stream_set(struct etna_cmd_stream *stream, uint32_t offset,
 175                 uint32_t data)
 176 {
 177         stream->buffer[offset] = data;
 178 }
 179
 180 static inline uint32_t etna_cmd_stream_offset(struct etna_cmd_stream *stream)
 181 {
 182         return stream->offset;
 183 }
 184
 185 struct etna_reloc {
 186         struct etna_bo *bo;
 187 #define ETNA_RELOC_READ             0x0001
 188 #define ETNA_RELOC_WRITE            0x0002
 189         uint32_t flags;
 190         uint32_t offset;
 191 };
 192
 193 void etna_cmd_stream_reloc(struct etna_cmd_stream *stream, const struct etna_reloc *r);
 194
 195 /* performance monitoring functions:
 196  */
 197
 198 struct etna_perfmon *etna_perfmon_create(struct etna_pipe *pipe);
 199 void etna_perfmon_del(struct etna_perfmon *perfmon);
 200 struct etna_perfmon_domain *etna_perfmon_get_dom_by_name(struct etna_perfmon *pm, const char *name);
 201 struct etna_perfmon_signal *etna_perfmon_get_sig_by_name(struct etna_perfmon_domain *dom, const char *name);
 202
 203 struct etna_perf {
 204 #define ETNA_PM_PROCESS_PRE             0x0001
 205 #define ETNA_PM_PROCESS_POST            0x0002
 206         uint32_t flags;
 207         uint32_t sequence;
 208         struct etna_perfmon_signal *signal;
 209         struct etna_bo *bo;
 210         uint32_t offset;
 211 };
 212
 213 void etna_cmd_stream_perf(struct etna_cmd_stream *stream, const struct etna_perf *p);
 214
 215 #endif /* ETNAVIV_DRMIF_H_ */