src/freedreno/.gitlab-ci/reference/afuc_test.asm

   1 ; a6xx microcode
   2 ; Disassembling microcode: src/freedreno/.gitlab-ci/reference/afuc_test.fw
   3 ; Version: 01000001
   4
   5         [01000001]  ; nop
   6         [01000060]  ; nop
   7         mov $02, 0x0883 ; CP_SCRATCH[0].REG
   8         mov $03, 0xbeef
   9         mov $04, 0xdead << 16
  10         or $03, $03, $04
  11         cwrite $02, [$00 + @REG_WRITE_ADDR], 0x0
  12         cwrite $03, [$00 + @REG_WRITE], 0x0
  13         waitin
  14         mov $01, $data
  15
  16 CP_ME_INIT:
  17         mov $02, 0x0002
  18         waitin
  19         mov $01, $data
  20
  21 CP_MEM_WRITE:
  22         mov $addr, 0x00a0 << 24
  23         mov $02, 0x0004
  24         (xmov1)add $data, $02, $data
  25         mov $addr, 0xa204 << 16
  26         (rep)(xmov3)mov $data, $data
  27         waitin
  28         mov $01, $data
  29
  30 CP_SCRATCH_WRITE:
  31         mov $02, 0x00ff
  32         (rep)cwrite $data, [$02 + 0x001], 0x4
  33         waitin
  34         mov $01, $data
  35
  36 CP_SET_SECURE_MODE:
  37         mov $02, $data
  38         setsecure $02, #l000
  39  l001:  jump #l001
  40         nop
  41  l000:  waitin
  42         mov $01, $data
  43 fxn00:
  44  l004:  cmp $04, $02, $03
  45         breq $04, b0, #l002
  46         brne $04, b1, #l003
  47         breq $04, b2, #l004
  48         sub $03, $03, $02
  49  l003:  jump #l004
  50         sub $02, $02, $03
  51  l002:  ret
  52         nop
  53
  54 CP_REG_RMW:
  55         cwrite $data, [$00 + @REG_READ_ADDR], 0x0
  56         add $02, $addr2, 0x0042
  57         addhi $03, $00, $addr2
  58         sub $02, $02, $addr2
  59         call #fxn00
  60         subhi $03, $03, $addr2
  61         and $02, $02, $addr2
  62         or $02, $02, 0x0001
  63         xor $02, $02, 0x0001
  64         not $02, $02
  65         shl $02, $02, $addr2
  66         ushr $02, $02, $addr2
  67         ishr $02, $02, $addr2
  68         rot $02, $02, $addr2
  69         min $02, $02, $addr2
  70         max $02, $02, $addr2
  71         mul8 $02, $02, $addr2
  72         msb $02, $02
  73         mov $addr2, $data
  74         mov $data, $02
  75         waitin
  76         mov $01, $data
  77
  78 CP_MEMCPY:
  79         mov $02, $data
  80         mov $03, $data
  81         mov $04, $data
  82         mov $05, $data
  83         mov $06, $data
  84  l006:  breq $06, 0x0, #l005
  85         cwrite $03, [$00 + @LOAD_STORE_HI], 0x0
  86         load $07, [$02 + 0x004], 0x4
  87         cwrite $05, [$00 + @LOAD_STORE_HI], 0x0
  88         jump #l006
  89         store $07, [$04 + 0x004], 0x4
  90  l005:  waitin
  91         mov $01, $data
  92
  93 CP_MEM_TO_MEM:
  94         cwrite $data, [$00 + @MEM_READ_ADDR], 0x0
  95         cwrite $data, [$00 + @MEM_READ_ADDR+0x1], 0x0
  96         mov $02, $data
  97         cwrite $data, [$00 + @LOAD_STORE_HI], 0x0
  98         mov $rem, $data
  99         cwrite $rem, [$00 + @MEM_READ_DWORDS], 0x0
 100         (rep)store $addr, [$02 + 0x004], 0x4
 101         waitin
 102         mov $01, $data
 103
 104 UNKN15:
 105         cread $02, [$00 + 0x101], 0x0
 106         brne $02, 0x1, #l007
 107         nop
 108         preemptleave #l001
 109         nop
 110         nop
 111         nop
 112         waitin
 113         mov $01, $data
 114  l007:  iret
 115         nop
 116
 117 UNKN0:
 118 UNKN1:
 119 UNKN2:
 120 UNKN3:
 121 PKT4:
 122 UNKN5:
 123 UNKN6:
 124 UNKN7:
 125 UNKN8:
 126 UNKN9:
 127 UNKN10:
 128 UNKN11:
 129 UNKN12:
 130 UNKN13:
 131 UNKN14:
 132 CP_NOP:
 133 CP_RECORD_PFP_TIMESTAMP:
 134 CP_WAIT_MEM_WRITES:
 135 CP_WAIT_FOR_ME:
 136 CP_WAIT_MEM_GTE:
 137 UNKN21:
 138 UNKN22:
 139 UNKN23:
 140 UNKN24:
 141 CP_DRAW_PRED_ENABLE_GLOBAL:
 142 CP_DRAW_PRED_ENABLE_LOCAL:
 143 UNKN27:
 144 CP_PREEMPT_ENABLE:
 145 CP_SKIP_IB2_ENABLE_GLOBAL:
 146 CP_PREEMPT_TOKEN:
 147 UNKN31:
 148 UNKN32:
 149 CP_DRAW_INDX:
 150 CP_SKIP_IB2_ENABLE_LOCAL:
 151 CP_DRAW_AUTO:
 152 CP_SET_STATE:
 153 CP_WAIT_FOR_IDLE:
 154 CP_IM_LOAD:
 155 CP_DRAW_INDIRECT:
 156 CP_DRAW_INDX_INDIRECT:
 157 CP_DRAW_INDIRECT_MULTI:
 158 CP_IM_LOAD_IMMEDIATE:
 159 CP_BLIT:
 160 CP_SET_CONSTANT:
 161 CP_SET_BIN_DATA5_OFFSET:
 162 CP_SET_BIN_DATA5:
 163 UNKN48:
 164 CP_RUN_OPENCL:
 165 CP_LOAD_STATE6_GEOM:
 166 CP_EXEC_CS:
 167 CP_LOAD_STATE6_FRAG:
 168 CP_SET_SUBDRAW_SIZE:
 169 CP_LOAD_STATE6:
 170 CP_INDIRECT_BUFFER_PFD:
 171 CP_DRAW_INDX_OFFSET:
 172 CP_REG_TEST:
 173 CP_COND_INDIRECT_BUFFER_PFE:
 174 CP_INVALIDATE_STATE:
 175 CP_WAIT_REG_MEM:
 176 CP_REG_TO_MEM:
 177 CP_INDIRECT_BUFFER:
 178 CP_INTERRUPT:
 179 CP_EXEC_CS_INDIRECT:
 180 CP_MEM_TO_REG:
 181 CP_SET_DRAW_STATE:
 182 CP_COND_EXEC:
 183 CP_COND_WRITE5:
 184 CP_EVENT_WRITE:
 185 CP_COND_REG_EXEC:
 186 UNKN73:
 187 CP_REG_TO_SCRATCH:
 188 CP_SET_DRAW_INIT_FLAGS:
 189 CP_SCRATCH_TO_REG:
 190 CP_DRAW_PRED_SET:
 191 CP_MEM_WRITE_CNTR:
 192 UNKN80:
 193 CP_SET_BIN_SELECT:
 194 CP_WAIT_REG_EQ:
 195 CP_SMMU_TABLE_UPDATE:
 196 UNKN84:
 197 CP_SET_CTXSWITCH_IB:
 198 CP_SET_PSEUDO_REG:
 199 CP_INDIRECT_BUFFER_CHAIN:
 200 CP_EVENT_WRITE_SHD:
 201 CP_EVENT_WRITE_CFL:
 202 UNKN90:
 203 CP_EVENT_WRITE_ZPD:
 204 CP_CONTEXT_REG_BUNCH:
 205 CP_WAIT_IB_PFD_COMPLETE:
 206 CP_CONTEXT_UPDATE:
 207 CP_SET_PROTECTED_MODE:
 208 UNKN96:
 209 UNKN97:
 210 UNKN98:
 211 CP_SET_MODE:
 212 CP_SET_VISIBILITY_OVERRIDE:
 213 CP_SET_MARKER:
 214 UNKN103:
 215 UNKN104:
 216 UNKN105:
 217 UNKN106:
 218 UNKN107:
 219 UNKN108:
 220 CP_REG_WRITE:
 221 UNKN110:
 222 CP_BOOTSTRAP_UCODE:
 223 CP_WAIT_TWO_REGS:
 224 CP_TEST_TWO_MEMS:
 225 CP_REG_TO_MEM_OFFSET_REG:
 226 CP_REG_TO_MEM_OFFSET_MEM:
 227 UNKN118:
 228 UNKN119:
 229 CP_REG_WR_NO_CTXT:
 230 UNKN121:
 231 UNKN122:
 232 UNKN123:
 233 UNKN124:
 234 UNKN125:
 235 UNKN126:
 236 UNKN127:
 237         waitin
 238         mov $01, $data