projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
freedreno/a6xx: Document the bit for the magic 32bit-uniforms-as-16b mode.
[mesa.git] / src / freedreno / .gitlab-ci / reference / dEQP-GLES2.functional.texture.specification.basic_teximage2d.rgba16f_2d.log
1 Reading src/freedreno/.gitlab-ci/traces/dEQP-GLES2.functional.texture.specification.basic_teximage2d.rgba16f_2d.rd.gz...
2 gpu_id: 201
3 cmd: deqp-gles2/185: fence=1250
4 ############################################################
5 cmdstream: 124 dwords
6 t0 write RB_BC_CONTROL (0f01)
7 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
8 0122d000: 0000: 00000f01 1c004046
9 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
10 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
11 0122d008: 0000: c0012d00 00040293 00000020
12 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
13 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
14 0122d014: 0000: c0012d00 00040316 00000002
15 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
16 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
17 0122d020: 0000: c0012d00 00040317 00000002
18 t0 write CP_PERFMON_CNTL (0444)
19 CP_PERFMON_CNTL: 0
20 0122d02c: 0000: 00000444 00000000
21 t0 write RBBM_PM_OVERRIDE1 (039c)
22 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
23 RBBM_PM_OVERRIDE2: 0xfff
24 0122d034: 0000: 0001039c ffffffff 00000fff
25 t0 write TP0_CHICKEN (0e1e)
26 TP0_CHICKEN: 0x2
27 0122d040: 0000: 00000e1e 00000002
28 t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
29 0122d048: 0000: c0003b00 00007fff
30 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
31 SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
32 0122d050: 0000: c0012d00 00040307 00100020
33 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
34 SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
35 0122d05c: 0000: c0012d00 00040308 000e0120
36 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
37 VGT_MAX_VTX_INDX: 0xffffffff
38 VGT_MIN_VTX_INDX: 0
39 0122d068: 0000: c0022d00 00040100 ffffffff 00000000
40 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
41 VGT_INDX_OFFSET: 0
42 0122d078: 0000: c0012d00 00040102 00000000
43 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
44 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
45 0122d084: 0000: c0012d00 00040181 00000004
46 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
47 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
48 0122d090: 0000: c0012d00 00040182 ffffffff
49 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
50 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
51 0122d09c: 0000: c0012d00 00040301 00000000
52 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
53 PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
54 0122d0a8: 0000: c0012d00 00040300 00000000
55 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
56 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
57 0122d0b4: 0000: c0012d00 00040080 00000000
58 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
59 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
60 0122d0c0: 0000: c0012d00 00040208 00000004
61 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
62 RB_SAMPLE_POS: 0x88888888
63 0122d0cc: 0000: c0012d00 0004020a 88888888
64 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
65 RB_COLOR_DEST_MASK: 0xffffffff
66 0122d0d8: 0000: c0012d00 00040326 ffffffff
67 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
68 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
69 0122d0e4: 0000: c0012d00 0004031b 0003c000
70 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
71 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
72 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
73 0122d0f0: 0000: c0022d00 00040183 00000000 00000000
74 t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
75 0122d100: 0000: c0004b00 00000000
76 t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords)
77 0122d108: 0000: c0035200 000005d0 00000000 5f601000 00000001
78 t0 write SQ_INST_STORE_MANAGMENT (0d02)
79 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
80 0122d11c: 0000: 00000d02 00000180
81 t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
82 0122d124: 0000: c0003b00 00000300
83 t3 opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
84 0122d12c: 0000: c0004a00 80000180
85 t3 opcode: CP_SET_CONSTANT (2d) (14 dwords)
86 0122d13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
87 0122d15c: 2.000000 0.750000 0.375000 0.250000
88 0122d134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
89 0122d154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
90 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
91 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
92 0122d16c: 0000: c0012d00 00040104 0000000f
93 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
94 RB_BLEND_RED: 0
95 RB_BLEND_GREEN: 0
96 RB_BLEND_BLUE: 0
97 RB_BLEND_ALPHA: 0xff
98 0122d178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
99 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
100 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
101 0122d190: 0000: c0012d00 00040206 0000043f
102 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
103 RB_SURFACE_INFO: { SURFACE_PITCH = 64 | MSAA_SAMPLES = 0 }
104 0122d19c: 0000: c0012d00 00040000 00000040
105 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
106 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x110d000 }
107 0122d1a8: 0000: c0012d00 00040001 0110d009
108 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
109 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
110 PA_SC_SCREEN_SCISSOR_BR: { X = 64 | Y = 128 }
111 0122d1b4: 0000: c0022d00 0004000e 80000000 00800040
112 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
113 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
114 0122d1c4: 0000: c0012d00 00040080 00000000
115 t0 write CP_SCRATCH_REG6 (057e)
116 CP_SCRATCH_REG6: 9
117 :0,0,9,0
118 0122d1d0: 0000: 0000057e 00000009
119 t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
120 ibaddr:0122e000
121 ibsize:000000b6
122 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
123 set shader const 0078
124 0122e000: 0000: c0042d00 00010078 0112d003 00100000 0112d003 00100000
125 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
126 PA_SC_AA_MASK: 0xffff
127 0122e018: 0000: c0012d00 00040312 0000ffff
128 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
129 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
130 0122e024: 0000: c0012d00 00040200 00000000
131 t3 opcode: CP_SET_CONSTANT (2d) (5 dwords)
132 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
133 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
134 RB_ALPHA_REF: 0
135 0122e030: 0000: c0032d00 0004010c 00000000 00000000 00000000
136 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
137 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
138 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
139 0122e044: 0000: c0022d00 00040204 00000000 00090244
140 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
141 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
142 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
143 PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
144 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
145 0122e054: 0000: c0042d00 00040280 00000000 00000000 00000000 00000000
146 t3 opcode: CP_SET_CONSTANT (2d) (7 dwords)
147 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
148 PA_CL_GB_VERT_CLIP_ADJ: 1.000000
149 PA_CL_GB_VERT_DISC_ADJ: 1.000000
150 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
151 PA_CL_GB_HORZ_DISC_ADJ: 1.000000
152 0122e06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
153 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
154 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
155 PA_SC_WINDOW_SCISSOR_BR: { X = 64 | Y = 128 }
156 0122e088: 0000: c0022d00 00040081 00000000 00800040
157 t3 opcode: CP_SET_CONSTANT (2d) (8 dwords)
158 PA_CL_VPORT_XSCALE: 32.000000
159 PA_CL_VPORT_XOFFSET: 32.000000
160 PA_CL_VPORT_YSCALE: 64.000000
161 PA_CL_VPORT_YOFFSET: 64.000000
162 PA_CL_VPORT_ZSCALE: 0.000000
163 PA_CL_VPORT_ZOFFSET: 0.000000
164 0122e098: 0000: c0062d00 0004010f 42000000 42000000 42800000 42800000 00000000 00000000
165 t3 opcode: CP_SET_CONSTANT (2d) (10 dwords)
166 0122e0c0: 32.000000 64.000000 0.000000 0.000000 32.000000 64.000000 0.000000 0.000000
167 0122e0b8: 0000: c0082d00 00000184 42000000 42800000 00000000 00000000 42000000 42800000
168 *
169 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
170 vertex shader, start=0000, size=0015
171 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2)
172 03: 19481000 00262688 00000020 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0)
173 04: 13480000 40262688 00001020 FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1)
174 0000 0000 c200 ALLOC POSITION SIZE(0x0)
175 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1)
176 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position
177 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
178 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1)
179 06: 000f8000 00000000 c2000000 ALU: MAXv export0 = R0, R0
180 0000 0000 0000 NOP
181 0122e0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
182 0122e100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000
183 0122e120: 0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000
184 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
185 fragment shader, start=0000, size=000c
186 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1)
187 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
188 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
189 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1)
190 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor
191 0000 0000 0000 NOP
192 0122e140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
193 0122e160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
194 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
195 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
196 0122e17c: 0000: c0012d00 00040181 00000106
197 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
198 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
199 0122e188: 0000: c0012d00 00040180 10030002
200 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
201 0122e19c: 0.000000 0.000000 0.000000 0.000000
202 0122e194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000
203 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
204 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
205 0122e1ac: 0000: c0012d00 00040202 00000c20
206 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
207 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
208 0122e1b8: 0000: c0012d00 00040201 00000000
209 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
210 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
211 0122e1c4: 0000: c0012d00 00040104 0000000f
212 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
213 RB_BLEND_RED: 0
214 RB_BLEND_GREEN: 0
215 RB_BLEND_BLUE: 0
216 RB_BLEND_ALPHA: 0
217 0122e1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000
218 t3 opcode: CP_SET_CONSTANT (2d) (8 dwords)
219 set texture const 0000
220 clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel
221 filter min/mag: point/point
222 swizzle: xyzw
223 addr=0111d000 (flags=820), size=64x128, pitch=64, format=FMT_1_REVERSE
224 mipaddr=00000000 (flags=200)
225 0122e1e8: 0000: c0062d00 00010000 00824800 0111d820 000fe03f 00000d11 00000000 00000200
226 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
227 VGT_INDX_OFFSET: 0
228 0122e208: 0000: c0012d00 00040102 00000000
229 t0 write TC_CNTL_STATUS (0e00)
230 TC_CNTL_STATUS: { L2_INVALIDATE }
231 0122e214: 0000: 00000e00 00000001
232 t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords)
233 0122e21c: 0000: c0035200 000005d0 00000000 00001000 00000001
234 t3 opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
235 0122e230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
236 t0 write CP_SCRATCH_REG7 (057f)
237 CP_SCRATCH_REG7: 5
238 :0,0,9,5
239 0122e24c: 0000: 0000057f 00000005
240 t3 opcode: CP_NOP (10) (2 dwords)
241 0122e254: 0000: c0001000 00000000
242 t3 opcode: CP_DRAW_INDX (22) (3 dwords)
243 { VIZ_QUERY = 0 }
244 { PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 }
245 draw: 0
246 prim_type: DI_PT_TRIFAN (5)
247 source_select: DI_SRC_SEL_AUTO_INDEX (2)
248 num_indices: 1407
249 draw[0] register values
250 !+ ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
251 !+ 00000fff RBBM_PM_OVERRIDE2: 0xfff
252 + 00000000 CP_PERFMON_CNTL: 0
253 !+ 00000009 CP_SCRATCH_REG6: 9
254 :0,0,9,5
255 !+ 00000005 CP_SCRATCH_REG7: 5
256 :0,0,9,5
257 !+ 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
258 !+ 00000001 TC_CNTL_STATUS: { L2_INVALIDATE }
259 !+ 00000002 TP0_CHICKEN: 0x2
260 !+ 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
261 !+ 00000040 RB_SURFACE_INFO: { SURFACE_PITCH = 64 | MSAA_SAMPLES = 0 }
262 !+ 0110d009 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x110d000 }
263 !+ 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
264 !+ 00800040 PA_SC_SCREEN_SCISSOR_BR: { X = 64 | Y = 128 }
265 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
266 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
267 !+ 00800040 PA_SC_WINDOW_SCISSOR_BR: { X = 64 | Y = 128 }
268 !+ ffffffff VGT_MAX_VTX_INDX: 0xffffffff
269 + 00000000 VGT_MIN_VTX_INDX: 0
270 + 00000000 VGT_INDX_OFFSET: 0
271 !+ 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
272 + 00000000 RB_BLEND_RED: 0
273 + 00000000 RB_BLEND_GREEN: 0
274 + 00000000 RB_BLEND_BLUE: 0
275 + 00000000 RB_BLEND_ALPHA: 0
276 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
277 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
278 + 00000000 RB_ALPHA_REF: 0
279 !+ 42000000 PA_CL_VPORT_XSCALE: 32.000000
280 !+ 42000000 PA_CL_VPORT_XOFFSET: 32.000000
281 !+ 42800000 PA_CL_VPORT_YSCALE: 64.000000
282 !+ 42800000 PA_CL_VPORT_YOFFSET: 64.000000
283 + 00000000 PA_CL_VPORT_ZSCALE: 0.000000
284 + 00000000 PA_CL_VPORT_ZOFFSET: 0.000000
285 !+ 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
286 !+ 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
287 !+ ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
288 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
289 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
290 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
291 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
292 !+ 00000c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
293 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
294 !+ 00090244 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
295 !+ 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
296 !+ 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
297 !+ 88888888 RB_SAMPLE_POS: 0x88888888
298 + 00000000 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
299 + 00000000 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
300 + 00000000 PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
301 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
302 !+ 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
303 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
304 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
305 !+ 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
306 !+ 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000
307 !+ 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000
308 !+ 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
309 !+ 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000
310 !+ 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
311 !+ 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
312 !+ 0000ffff PA_SC_AA_MASK: 0xffff
313 !+ 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
314 !+ 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
315 !+ 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
316 !+ ffffffff RB_COLOR_DEST_MASK: 0xffffffff
317 0122e25c: 0000: c0012200 00000000 00040085
318 t0 write CP_SCRATCH_REG7 (057f)
319 NEEDS WFI: CP_SCRATCH_REG7 (57f)
320 CP_SCRATCH_REG7: 6
321 :0,0,9,6
322 0122e268: 0000: 0000057f 00000006
323 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
324 0122e270: 0000: c0002600 00000000
325 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
326 { EVENT = CACHE_FLUSH }
327 event CACHE_FLUSH
328 0122e278: 0000: c0004600 00000006
329 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
330 { EVENT = CACHE_FLUSH }
331 event CACHE_FLUSH
332 0122e280: 0000: c0004600 00000006
333 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
334 { EVENT = CACHE_FLUSH }
335 event CACHE_FLUSH
336 0122e288: 0000: c0004600 00000006
337 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
338 { EVENT = CACHE_FLUSH }
339 event CACHE_FLUSH
340 0122e290: 0000: c0004600 00000006
341 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
342 { EVENT = CACHE_FLUSH }
343 event CACHE_FLUSH
344 0122e298: 0000: c0004600 00000006
345 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
346 { EVENT = CACHE_FLUSH }
347 event CACHE_FLUSH
348 0122e2a0: 0000: c0004600 00000006
349 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
350 { EVENT = CACHE_FLUSH }
351 event CACHE_FLUSH
352 0122e2a8: 0000: c0004600 00000006
353 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
354 { EVENT = CACHE_FLUSH }
355 event CACHE_FLUSH
356 0122e2b0: 0000: c0004600 00000006
357 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
358 { EVENT = CACHE_FLUSH }
359 event CACHE_FLUSH
360 0122e2b8: 0000: c0004600 00000006
361 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
362 { EVENT = CACHE_FLUSH }
363 event CACHE_FLUSH
364 0122e2c0: 0000: c0004600 00000006
365 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
366 { EVENT = CACHE_FLUSH }
367 event CACHE_FLUSH
368 0122e2c8: 0000: c0004600 00000006
369 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
370 { EVENT = CACHE_FLUSH }
371 event CACHE_FLUSH
372 0122e2d0: 0000: c0004600 00000006
373 0122d1d8: 0000: c0013700 0122e000 000000b6
374 t2 nop
375 ############################################################
376 vertices: 0
377 cmd: deqp-gles2/185: fence=1251
378 ############################################################
379 cmdstream: 124 dwords
380 t0 write RB_BC_CONTROL (0f01)
381 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
382 0122f000: 0000: 00000f01 1c004046
383 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
384 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
385 0122f008: 0000: c0012d00 00040293 00000020
386 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
387 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
388 0122f014: 0000: c0012d00 00040316 00000002
389 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
390 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
391 0122f020: 0000: c0012d00 00040317 00000002
392 t0 write CP_PERFMON_CNTL (0444)
393 CP_PERFMON_CNTL: 0
394 0122f02c: 0000: 00000444 00000000
395 t0 write RBBM_PM_OVERRIDE1 (039c)
396 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
397 RBBM_PM_OVERRIDE2: 0xfff
398 0122f034: 0000: 0001039c ffffffff 00000fff
399 t0 write TP0_CHICKEN (0e1e)
400 TP0_CHICKEN: 0x2
401 0122f040: 0000: 00000e1e 00000002
402 t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
403 0122f048: 0000: c0003b00 00007fff
404 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
405 SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
406 0122f050: 0000: c0012d00 00040307 00100020
407 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
408 SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
409 0122f05c: 0000: c0012d00 00040308 000e0120
410 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
411 VGT_MAX_VTX_INDX: 0xffffffff
412 VGT_MIN_VTX_INDX: 0
413 0122f068: 0000: c0022d00 00040100 ffffffff 00000000
414 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
415 VGT_INDX_OFFSET: 0
416 0122f078: 0000: c0012d00 00040102 00000000
417 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
418 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
419 0122f084: 0000: c0012d00 00040181 00000004
420 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
421 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
422 0122f090: 0000: c0012d00 00040182 ffffffff
423 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
424 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
425 0122f09c: 0000: c0012d00 00040301 00000000
426 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
427 PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
428 0122f0a8: 0000: c0012d00 00040300 00000000
429 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
430 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
431 0122f0b4: 0000: c0012d00 00040080 00000000
432 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
433 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
434 0122f0c0: 0000: c0012d00 00040208 00000004
435 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
436 RB_SAMPLE_POS: 0x88888888
437 0122f0cc: 0000: c0012d00 0004020a 88888888
438 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
439 RB_COLOR_DEST_MASK: 0xffffffff
440 0122f0d8: 0000: c0012d00 00040326 ffffffff
441 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
442 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
443 0122f0e4: 0000: c0012d00 0004031b 0003c000
444 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
445 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
446 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
447 0122f0f0: 0000: c0022d00 00040183 00000000 00000000
448 t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
449 0122f100: 0000: c0004b00 00000000
450 t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords)
451 0122f108: 0000: c0035200 000005d0 00000000 5f601000 00000001
452 t0 write SQ_INST_STORE_MANAGMENT (0d02)
453 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
454 0122f11c: 0000: 00000d02 00000180
455 t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
456 0122f124: 0000: c0003b00 00000300
457 t3 opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
458 0122f12c: 0000: c0004a00 80000180
459 t3 opcode: CP_SET_CONSTANT (2d) (14 dwords)
460 0122f13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
461 0122f15c: 2.000000 0.750000 0.375000 0.250000
462 0122f134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
463 0122f154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
464 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
465 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
466 0122f16c: 0000: c0012d00 00040104 0000000f
467 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
468 RB_BLEND_RED: 0
469 RB_BLEND_GREEN: 0
470 RB_BLEND_BLUE: 0
471 RB_BLEND_ALPHA: 0xff
472 0122f178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
473 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
474 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
475 0122f190: 0000: c0012d00 00040206 0000043f
476 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
477 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
478 0122f19c: 0000: c0012d00 00040000 00000020
479 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
480 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1240000 }
481 0122f1a8: 0000: c0012d00 00040001 01240009
482 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
483 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
484 PA_SC_SCREEN_SCISSOR_BR: { X = 32 | Y = 64 }
485 0122f1b4: 0000: c0022d00 0004000e 80000000 00400020
486 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
487 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
488 0122f1c4: 0000: c0012d00 00040080 00000000
489 t0 write CP_SCRATCH_REG6 (057e)
490 CP_SCRATCH_REG6: 15
491 :0,0,15,6
492 0122f1d0: 0000: 0000057e 0000000f
493 t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
494 ibaddr:0122e000
495 ibsize:000000b6
496 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
497 set shader const 0078
498 0122e000: 0000: c0042d00 00010078 0112d083 00100000 0112d083 00100000
499 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
500 PA_SC_AA_MASK: 0xffff
501 0122e018: 0000: c0012d00 00040312 0000ffff
502 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
503 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
504 0122e024: 0000: c0012d00 00040200 00000000
505 t3 opcode: CP_SET_CONSTANT (2d) (5 dwords)
506 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
507 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
508 RB_ALPHA_REF: 0
509 0122e030: 0000: c0032d00 0004010c 00000000 00000000 00000000
510 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
511 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
512 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
513 0122e044: 0000: c0022d00 00040204 00000000 00090244
514 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
515 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
516 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
517 PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
518 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
519 0122e054: 0000: c0042d00 00040280 00000000 00000000 00000000 00000000
520 t3 opcode: CP_SET_CONSTANT (2d) (7 dwords)
521 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
522 PA_CL_GB_VERT_CLIP_ADJ: 1.000000
523 PA_CL_GB_VERT_DISC_ADJ: 1.000000
524 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
525 PA_CL_GB_HORZ_DISC_ADJ: 1.000000
526 0122e06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
527 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
528 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
529 PA_SC_WINDOW_SCISSOR_BR: { X = 32 | Y = 64 }
530 0122e088: 0000: c0022d00 00040081 00000000 00400020
531 t3 opcode: CP_SET_CONSTANT (2d) (8 dwords)
532 PA_CL_VPORT_XSCALE: 16.000000
533 PA_CL_VPORT_XOFFSET: 16.000000
534 PA_CL_VPORT_YSCALE: 32.000000
535 PA_CL_VPORT_YOFFSET: 32.000000
536 PA_CL_VPORT_ZSCALE: 0.000000
537 PA_CL_VPORT_ZOFFSET: 0.000000
538 0122e098: 0000: c0062d00 0004010f 41800000 41800000 42000000 42000000 00000000 00000000
539 t3 opcode: CP_SET_CONSTANT (2d) (10 dwords)
540 0122e0c0: 16.000000 32.000000 0.000000 0.000000 16.000000 32.000000 0.000000 0.000000
541 0122e0b8: 0000: c0082d00 00000184 41800000 42000000 00000000 00000000 41800000 42000000
542 *
543 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
544 vertex shader, start=0000, size=0015
545 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2)
546 03: 19481000 00262688 00000020 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0)
547 04: 13480000 40262688 00001020 FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1)
548 0000 0000 c200 ALLOC POSITION SIZE(0x0)
549 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1)
550 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position
551 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
552 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1)
553 06: 000f8000 00000000 c2000000 ALU: MAXv export0 = R0, R0
554 0000 0000 0000 NOP
555 0122e0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
556 0122e100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000
557 0122e120: 0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000
558 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
559 fragment shader, start=0000, size=000c
560 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1)
561 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
562 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
563 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1)
564 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor
565 0000 0000 0000 NOP
566 0122e140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
567 0122e160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
568 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
569 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
570 0122e17c: 0000: c0012d00 00040181 00000106
571 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
572 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
573 0122e188: 0000: c0012d00 00040180 10030002
574 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
575 0122e19c: 0.000000 0.000000 0.000000 0.000000
576 0122e194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000
577 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
578 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
579 0122e1ac: 0000: c0012d00 00040202 00000c20
580 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
581 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
582 0122e1b8: 0000: c0012d00 00040201 00000000
583 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
584 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
585 0122e1c4: 0000: c0012d00 00040104 0000000f
586 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
587 RB_BLEND_RED: 0
588 RB_BLEND_GREEN: 0
589 RB_BLEND_BLUE: 0
590 RB_BLEND_ALPHA: 0
591 0122e1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000
592 t3 opcode: CP_SET_CONSTANT (2d) (8 dwords)
593 set texture const 0000
594 clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel
595 filter min/mag: point/point
596 swizzle: xyzw
597 addr=01250000 (flags=820), size=32x64, pitch=32, format=FMT_1_REVERSE
598 mipaddr=00000000 (flags=200)
599 0122e1e8: 0000: c0062d00 00010000 00424800 01250820 0007e01f 00000d11 00000000 00000200
600 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
601 VGT_INDX_OFFSET: 0
602 0122e208: 0000: c0012d00 00040102 00000000
603 t0 write TC_CNTL_STATUS (0e00)
604 TC_CNTL_STATUS: { L2_INVALIDATE }
605 0122e214: 0000: 00000e00 00000001
606 t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords)
607 0122e21c: 0000: c0035200 000005d0 00000000 00001000 00000001
608 t3 opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
609 0122e230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
610 t0 write CP_SCRATCH_REG7 (057f)
611 CP_SCRATCH_REG7: 11
612 :0,0,15,11
613 0122e24c: 0000: 0000057f 0000000b
614 t3 opcode: CP_NOP (10) (2 dwords)
615 0122e254: 0000: c0001000 00000000
616 t3 opcode: CP_DRAW_INDX (22) (3 dwords)
617 { VIZ_QUERY = 0 }
618 { PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 }
619 draw: 0
620 prim_type: DI_PT_TRIFAN (5)
621 source_select: DI_SRC_SEL_AUTO_INDEX (2)
622 num_indices: 1407
623 draw[1] register values
624 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
625 + 00000fff RBBM_PM_OVERRIDE2: 0xfff
626 + 00000000 CP_PERFMON_CNTL: 0
627 !+ 0000000f CP_SCRATCH_REG6: 15
628 :0,0,15,11
629 !+ 0000000b CP_SCRATCH_REG7: 11
630 :0,0,15,11
631 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
632 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE }
633 + 00000002 TP0_CHICKEN: 0x2
634 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
635 !+ 00000020 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
636 !+ 01240009 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1240000 }
637 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
638 !+ 00400020 PA_SC_SCREEN_SCISSOR_BR: { X = 32 | Y = 64 }
639 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
640 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
641 !+ 00400020 PA_SC_WINDOW_SCISSOR_BR: { X = 32 | Y = 64 }
642 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff
643 + 00000000 VGT_MIN_VTX_INDX: 0
644 + 00000000 VGT_INDX_OFFSET: 0
645 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
646 + 00000000 RB_BLEND_RED: 0
647 + 00000000 RB_BLEND_GREEN: 0
648 + 00000000 RB_BLEND_BLUE: 0
649 + 00000000 RB_BLEND_ALPHA: 0
650 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
651 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
652 + 00000000 RB_ALPHA_REF: 0
653 !+ 41800000 PA_CL_VPORT_XSCALE: 16.000000
654 !+ 41800000 PA_CL_VPORT_XOFFSET: 16.000000
655 !+ 42000000 PA_CL_VPORT_YSCALE: 32.000000
656 !+ 42000000 PA_CL_VPORT_YOFFSET: 32.000000
657 + 00000000 PA_CL_VPORT_ZSCALE: 0.000000
658 + 00000000 PA_CL_VPORT_ZOFFSET: 0.000000
659 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
660 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
661 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
662 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
663 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
664 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
665 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
666 + 00000c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
667 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
668 + 00090244 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
669 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
670 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
671 + 88888888 RB_SAMPLE_POS: 0x88888888
672 + 00000000 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
673 + 00000000 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
674 + 00000000 PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
675 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
676 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
677 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
678 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
679 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
680 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000
681 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000
682 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
683 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000
684 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
685 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
686 + 0000ffff PA_SC_AA_MASK: 0xffff
687 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
688 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
689 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
690 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff
691 0122e25c: 0000: c0012200 00000000 00040085
692 t0 write CP_SCRATCH_REG7 (057f)
693 NEEDS WFI: CP_SCRATCH_REG7 (57f)
694 CP_SCRATCH_REG7: 12
695 :0,0,15,12
696 0122e268: 0000: 0000057f 0000000c
697 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
698 0122e270: 0000: c0002600 00000000
699 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
700 { EVENT = CACHE_FLUSH }
701 event CACHE_FLUSH
702 0122e278: 0000: c0004600 00000006
703 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
704 { EVENT = CACHE_FLUSH }
705 event CACHE_FLUSH
706 0122e280: 0000: c0004600 00000006
707 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
708 { EVENT = CACHE_FLUSH }
709 event CACHE_FLUSH
710 0122e288: 0000: c0004600 00000006
711 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
712 { EVENT = CACHE_FLUSH }
713 event CACHE_FLUSH
714 0122e290: 0000: c0004600 00000006
715 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
716 { EVENT = CACHE_FLUSH }
717 event CACHE_FLUSH
718 0122e298: 0000: c0004600 00000006
719 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
720 { EVENT = CACHE_FLUSH }
721 event CACHE_FLUSH
722 0122e2a0: 0000: c0004600 00000006
723 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
724 { EVENT = CACHE_FLUSH }
725 event CACHE_FLUSH
726 0122e2a8: 0000: c0004600 00000006
727 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
728 { EVENT = CACHE_FLUSH }
729 event CACHE_FLUSH
730 0122e2b0: 0000: c0004600 00000006
731 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
732 { EVENT = CACHE_FLUSH }
733 event CACHE_FLUSH
734 0122e2b8: 0000: c0004600 00000006
735 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
736 { EVENT = CACHE_FLUSH }
737 event CACHE_FLUSH
738 0122e2c0: 0000: c0004600 00000006
739 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
740 { EVENT = CACHE_FLUSH }
741 event CACHE_FLUSH
742 0122e2c8: 0000: c0004600 00000006
743 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
744 { EVENT = CACHE_FLUSH }
745 event CACHE_FLUSH
746 0122e2d0: 0000: c0004600 00000006
747 0122f1d8: 0000: c0013700 0122e000 000000b6
748 t2 nop
749 ############################################################
750 vertices: 0
751 cmd: deqp-gles2/185: fence=1252
752 ############################################################
753 cmdstream: 124 dwords
754 t0 write RB_BC_CONTROL (0f01)
755 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
756 0122d000: 0000: 00000f01 1c004046
757 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
758 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
759 0122d008: 0000: c0012d00 00040293 00000020
760 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
761 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
762 0122d014: 0000: c0012d00 00040316 00000002
763 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
764 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
765 0122d020: 0000: c0012d00 00040317 00000002
766 t0 write CP_PERFMON_CNTL (0444)
767 CP_PERFMON_CNTL: 0
768 0122d02c: 0000: 00000444 00000000
769 t0 write RBBM_PM_OVERRIDE1 (039c)
770 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
771 RBBM_PM_OVERRIDE2: 0xfff
772 0122d034: 0000: 0001039c ffffffff 00000fff
773 t0 write TP0_CHICKEN (0e1e)
774 TP0_CHICKEN: 0x2
775 0122d040: 0000: 00000e1e 00000002
776 t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
777 0122d048: 0000: c0003b00 00007fff
778 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
779 SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
780 0122d050: 0000: c0012d00 00040307 00100020
781 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
782 SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
783 0122d05c: 0000: c0012d00 00040308 000e0120
784 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
785 VGT_MAX_VTX_INDX: 0xffffffff
786 VGT_MIN_VTX_INDX: 0
787 0122d068: 0000: c0022d00 00040100 ffffffff 00000000
788 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
789 VGT_INDX_OFFSET: 0
790 0122d078: 0000: c0012d00 00040102 00000000
791 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
792 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
793 0122d084: 0000: c0012d00 00040181 00000004
794 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
795 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
796 0122d090: 0000: c0012d00 00040182 ffffffff
797 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
798 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
799 0122d09c: 0000: c0012d00 00040301 00000000
800 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
801 PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
802 0122d0a8: 0000: c0012d00 00040300 00000000
803 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
804 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
805 0122d0b4: 0000: c0012d00 00040080 00000000
806 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
807 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
808 0122d0c0: 0000: c0012d00 00040208 00000004
809 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
810 RB_SAMPLE_POS: 0x88888888
811 0122d0cc: 0000: c0012d00 0004020a 88888888
812 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
813 RB_COLOR_DEST_MASK: 0xffffffff
814 0122d0d8: 0000: c0012d00 00040326 ffffffff
815 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
816 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
817 0122d0e4: 0000: c0012d00 0004031b 0003c000
818 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
819 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
820 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
821 0122d0f0: 0000: c0022d00 00040183 00000000 00000000
822 t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
823 0122d100: 0000: c0004b00 00000000
824 t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords)
825 0122d108: 0000: c0035200 000005d0 00000000 5f601000 00000001
826 t0 write SQ_INST_STORE_MANAGMENT (0d02)
827 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
828 0122d11c: 0000: 00000d02 00000180
829 t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
830 0122d124: 0000: c0003b00 00000300
831 t3 opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
832 0122d12c: 0000: c0004a00 80000180
833 t3 opcode: CP_SET_CONSTANT (2d) (14 dwords)
834 0122d13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
835 0122d15c: 2.000000 0.750000 0.375000 0.250000
836 0122d134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
837 0122d154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
838 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
839 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
840 0122d16c: 0000: c0012d00 00040104 0000000f
841 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
842 RB_BLEND_RED: 0
843 RB_BLEND_GREEN: 0
844 RB_BLEND_BLUE: 0
845 RB_BLEND_ALPHA: 0xff
846 0122d178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
847 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
848 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
849 0122d190: 0000: c0012d00 00040206 0000043f
850 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
851 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
852 0122d19c: 0000: c0012d00 00040000 00000020
853 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
854 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1244000 }
855 0122d1a8: 0000: c0012d00 00040001 01244009
856 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
857 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
858 PA_SC_SCREEN_SCISSOR_BR: { X = 16 | Y = 32 }
859 0122d1b4: 0000: c0022d00 0004000e 80000000 00200010
860 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
861 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
862 0122d1c4: 0000: c0012d00 00040080 00000000
863 t0 write CP_SCRATCH_REG6 (057e)
864 CP_SCRATCH_REG6: 21
865 :0,0,21,12
866 0122d1d0: 0000: 0000057e 00000015
867 t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
868 ibaddr:0122e000
869 ibsize:000000b6
870 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
871 set shader const 0078
872 0122e000: 0000: c0042d00 00010078 0112d103 00100000 0112d103 00100000
873 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
874 PA_SC_AA_MASK: 0xffff
875 0122e018: 0000: c0012d00 00040312 0000ffff
876 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
877 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
878 0122e024: 0000: c0012d00 00040200 00000000
879 t3 opcode: CP_SET_CONSTANT (2d) (5 dwords)
880 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
881 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
882 RB_ALPHA_REF: 0
883 0122e030: 0000: c0032d00 0004010c 00000000 00000000 00000000
884 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
885 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
886 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
887 0122e044: 0000: c0022d00 00040204 00000000 00090244
888 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
889 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
890 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
891 PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
892 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
893 0122e054: 0000: c0042d00 00040280 00000000 00000000 00000000 00000000
894 t3 opcode: CP_SET_CONSTANT (2d) (7 dwords)
895 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
896 PA_CL_GB_VERT_CLIP_ADJ: 1.000000
897 PA_CL_GB_VERT_DISC_ADJ: 1.000000
898 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
899 PA_CL_GB_HORZ_DISC_ADJ: 1.000000
900 0122e06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
901 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
902 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
903 PA_SC_WINDOW_SCISSOR_BR: { X = 16 | Y = 32 }
904 0122e088: 0000: c0022d00 00040081 00000000 00200010
905 t3 opcode: CP_SET_CONSTANT (2d) (8 dwords)
906 PA_CL_VPORT_XSCALE: 8.000000
907 PA_CL_VPORT_XOFFSET: 8.000000
908 PA_CL_VPORT_YSCALE: 16.000000
909 PA_CL_VPORT_YOFFSET: 16.000000
910 PA_CL_VPORT_ZSCALE: 0.000000
911 PA_CL_VPORT_ZOFFSET: 0.000000
912 0122e098: 0000: c0062d00 0004010f 41000000 41000000 41800000 41800000 00000000 00000000
913 t3 opcode: CP_SET_CONSTANT (2d) (10 dwords)
914 0122e0c0: 8.000000 16.000000 0.000000 0.000000 8.000000 16.000000 0.000000 0.000000
915 0122e0b8: 0000: c0082d00 00000184 41000000 41800000 00000000 00000000 41000000 41800000
916 *
917 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
918 vertex shader, start=0000, size=0015
919 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2)
920 03: 19481000 00262688 00000020 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0)
921 04: 13480000 40262688 00001020 FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1)
922 0000 0000 c200 ALLOC POSITION SIZE(0x0)
923 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1)
924 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position
925 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
926 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1)
927 06: 000f8000 00000000 c2000000 ALU: MAXv export0 = R0, R0
928 0000 0000 0000 NOP
929 0122e0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
930 0122e100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000
931 0122e120: 0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000
932 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
933 fragment shader, start=0000, size=000c
934 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1)
935 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
936 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
937 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1)
938 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor
939 0000 0000 0000 NOP
940 0122e140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
941 0122e160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
942 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
943 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
944 0122e17c: 0000: c0012d00 00040181 00000106
945 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
946 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
947 0122e188: 0000: c0012d00 00040180 10030002
948 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
949 0122e19c: 0.000000 0.000000 0.000000 0.000000
950 0122e194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000
951 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
952 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
953 0122e1ac: 0000: c0012d00 00040202 00000c20
954 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
955 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
956 0122e1b8: 0000: c0012d00 00040201 00000000
957 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
958 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
959 0122e1c4: 0000: c0012d00 00040104 0000000f
960 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
961 RB_BLEND_RED: 0
962 RB_BLEND_GREEN: 0
963 RB_BLEND_BLUE: 0
964 RB_BLEND_ALPHA: 0
965 0122e1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000
966 t3 opcode: CP_SET_CONSTANT (2d) (8 dwords)
967 set texture const 0000
968 clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel
969 filter min/mag: point/point
970 swizzle: xyzw
971 addr=01254000 (flags=820), size=16x32, pitch=32, format=FMT_1_REVERSE
972 mipaddr=00000000 (flags=200)
973 0122e1e8: 0000: c0062d00 00010000 00424800 01254820 0003e00f 00000d11 00000000 00000200
974 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
975 VGT_INDX_OFFSET: 0
976 0122e208: 0000: c0012d00 00040102 00000000
977 t0 write TC_CNTL_STATUS (0e00)
978 TC_CNTL_STATUS: { L2_INVALIDATE }
979 0122e214: 0000: 00000e00 00000001
980 t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords)
981 0122e21c: 0000: c0035200 000005d0 00000000 00001000 00000001
982 t3 opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
983 0122e230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
984 t0 write CP_SCRATCH_REG7 (057f)
985 CP_SCRATCH_REG7: 17
986 :0,0,21,17
987 0122e24c: 0000: 0000057f 00000011
988 t3 opcode: CP_NOP (10) (2 dwords)
989 0122e254: 0000: c0001000 00000000
990 t3 opcode: CP_DRAW_INDX (22) (3 dwords)
991 { VIZ_QUERY = 0 }
992 { PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 }
993 draw: 0
994 prim_type: DI_PT_TRIFAN (5)
995 source_select: DI_SRC_SEL_AUTO_INDEX (2)
996 num_indices: 1407
997 draw[2] register values
998 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
999 + 00000fff RBBM_PM_OVERRIDE2: 0xfff
1000 + 00000000 CP_PERFMON_CNTL: 0
1001 !+ 00000015 CP_SCRATCH_REG6: 21
1002 :0,0,21,17
1003 !+ 00000011 CP_SCRATCH_REG7: 17
1004 :0,0,21,17
1005 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
1006 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE }
1007 + 00000002 TP0_CHICKEN: 0x2
1008 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
1009 + 00000020 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
1010 !+ 01244009 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1244000 }
1011 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
1012 !+ 00200010 PA_SC_SCREEN_SCISSOR_BR: { X = 16 | Y = 32 }
1013 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
1014 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
1015 !+ 00200010 PA_SC_WINDOW_SCISSOR_BR: { X = 16 | Y = 32 }
1016 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff
1017 + 00000000 VGT_MIN_VTX_INDX: 0
1018 + 00000000 VGT_INDX_OFFSET: 0
1019 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
1020 + 00000000 RB_BLEND_RED: 0
1021 + 00000000 RB_BLEND_GREEN: 0
1022 + 00000000 RB_BLEND_BLUE: 0
1023 + 00000000 RB_BLEND_ALPHA: 0
1024 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
1025 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
1026 + 00000000 RB_ALPHA_REF: 0
1027 !+ 41000000 PA_CL_VPORT_XSCALE: 8.000000
1028 !+ 41000000 PA_CL_VPORT_XOFFSET: 8.000000
1029 !+ 41800000 PA_CL_VPORT_YSCALE: 16.000000
1030 !+ 41800000 PA_CL_VPORT_YOFFSET: 16.000000
1031 + 00000000 PA_CL_VPORT_ZSCALE: 0.000000
1032 + 00000000 PA_CL_VPORT_ZOFFSET: 0.000000
1033 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
1034 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
1035 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
1036 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
1037 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
1038 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
1039 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
1040 + 00000c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
1041 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
1042 + 00090244 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
1043 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
1044 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
1045 + 88888888 RB_SAMPLE_POS: 0x88888888
1046 + 00000000 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
1047 + 00000000 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
1048 + 00000000 PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
1049 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
1050 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
1051 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
1052 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
1053 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
1054 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000
1055 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000
1056 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
1057 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000
1058 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
1059 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
1060 + 0000ffff PA_SC_AA_MASK: 0xffff
1061 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
1062 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
1063 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
1064 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff
1065 0122e25c: 0000: c0012200 00000000 00040085
1066 t0 write CP_SCRATCH_REG7 (057f)
1067 NEEDS WFI: CP_SCRATCH_REG7 (57f)
1068 CP_SCRATCH_REG7: 18
1069 :0,0,21,18
1070 0122e268: 0000: 0000057f 00000012
1071 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
1072 0122e270: 0000: c0002600 00000000
1073 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
1074 { EVENT = CACHE_FLUSH }
1075 event CACHE_FLUSH
1076 0122e278: 0000: c0004600 00000006
1077 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
1078 { EVENT = CACHE_FLUSH }
1079 event CACHE_FLUSH
1080 0122e280: 0000: c0004600 00000006
1081 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
1082 { EVENT = CACHE_FLUSH }
1083 event CACHE_FLUSH
1084 0122e288: 0000: c0004600 00000006
1085 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
1086 { EVENT = CACHE_FLUSH }
1087 event CACHE_FLUSH
1088 0122e290: 0000: c0004600 00000006
1089 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
1090 { EVENT = CACHE_FLUSH }
1091 event CACHE_FLUSH
1092 0122e298: 0000: c0004600 00000006
1093 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
1094 { EVENT = CACHE_FLUSH }
1095 event CACHE_FLUSH
1096 0122e2a0: 0000: c0004600 00000006
1097 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
1098 { EVENT = CACHE_FLUSH }
1099 event CACHE_FLUSH
1100 0122e2a8: 0000: c0004600 00000006
1101 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
1102 { EVENT = CACHE_FLUSH }
1103 event CACHE_FLUSH
1104 0122e2b0: 0000: c0004600 00000006
1105 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
1106 { EVENT = CACHE_FLUSH }
1107 event CACHE_FLUSH
1108 0122e2b8: 0000: c0004600 00000006
1109 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
1110 { EVENT = CACHE_FLUSH }
1111 event CACHE_FLUSH
1112 0122e2c0: 0000: c0004600 00000006
1113 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
1114 { EVENT = CACHE_FLUSH }
1115 event CACHE_FLUSH
1116 0122e2c8: 0000: c0004600 00000006
1117 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
1118 { EVENT = CACHE_FLUSH }
1119 event CACHE_FLUSH
1120 0122e2d0: 0000: c0004600 00000006
1121 0122d1d8: 0000: c0013700 0122e000 000000b6
1122 t2 nop
1123 ############################################################
1124 vertices: 0
1125 cmd: deqp-gles2/185: fence=1253
1126 ############################################################
1127 cmdstream: 124 dwords
1128 t0 write RB_BC_CONTROL (0f01)
1129 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
1130 0122f000: 0000: 00000f01 1c004046
1131 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1132 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
1133 0122f008: 0000: c0012d00 00040293 00000020
1134 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1135 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
1136 0122f014: 0000: c0012d00 00040316 00000002
1137 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1138 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
1139 0122f020: 0000: c0012d00 00040317 00000002
1140 t0 write CP_PERFMON_CNTL (0444)
1141 CP_PERFMON_CNTL: 0
1142 0122f02c: 0000: 00000444 00000000
1143 t0 write RBBM_PM_OVERRIDE1 (039c)
1144 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
1145 RBBM_PM_OVERRIDE2: 0xfff
1146 0122f034: 0000: 0001039c ffffffff 00000fff
1147 t0 write TP0_CHICKEN (0e1e)
1148 TP0_CHICKEN: 0x2
1149 0122f040: 0000: 00000e1e 00000002
1150 t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
1151 0122f048: 0000: c0003b00 00007fff
1152 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1153 SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
1154 0122f050: 0000: c0012d00 00040307 00100020
1155 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1156 SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
1157 0122f05c: 0000: c0012d00 00040308 000e0120
1158 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
1159 VGT_MAX_VTX_INDX: 0xffffffff
1160 VGT_MIN_VTX_INDX: 0
1161 0122f068: 0000: c0022d00 00040100 ffffffff 00000000
1162 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1163 VGT_INDX_OFFSET: 0
1164 0122f078: 0000: c0012d00 00040102 00000000
1165 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1166 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
1167 0122f084: 0000: c0012d00 00040181 00000004
1168 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1169 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
1170 0122f090: 0000: c0012d00 00040182 ffffffff
1171 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1172 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
1173 0122f09c: 0000: c0012d00 00040301 00000000
1174 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1175 PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
1176 0122f0a8: 0000: c0012d00 00040300 00000000
1177 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1178 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
1179 0122f0b4: 0000: c0012d00 00040080 00000000
1180 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1181 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
1182 0122f0c0: 0000: c0012d00 00040208 00000004
1183 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1184 RB_SAMPLE_POS: 0x88888888
1185 0122f0cc: 0000: c0012d00 0004020a 88888888
1186 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1187 RB_COLOR_DEST_MASK: 0xffffffff
1188 0122f0d8: 0000: c0012d00 00040326 ffffffff
1189 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1190 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
1191 0122f0e4: 0000: c0012d00 0004031b 0003c000
1192 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
1193 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
1194 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
1195 0122f0f0: 0000: c0022d00 00040183 00000000 00000000
1196 t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
1197 0122f100: 0000: c0004b00 00000000
1198 t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords)
1199 0122f108: 0000: c0035200 000005d0 00000000 5f601000 00000001
1200 t0 write SQ_INST_STORE_MANAGMENT (0d02)
1201 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
1202 0122f11c: 0000: 00000d02 00000180
1203 t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
1204 0122f124: 0000: c0003b00 00000300
1205 t3 opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
1206 0122f12c: 0000: c0004a00 80000180
1207 t3 opcode: CP_SET_CONSTANT (2d) (14 dwords)
1208 0122f13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
1209 0122f15c: 2.000000 0.750000 0.375000 0.250000
1210 0122f134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
1211 0122f154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
1212 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1213 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
1214 0122f16c: 0000: c0012d00 00040104 0000000f
1215 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
1216 RB_BLEND_RED: 0
1217 RB_BLEND_GREEN: 0
1218 RB_BLEND_BLUE: 0
1219 RB_BLEND_ALPHA: 0xff
1220 0122f178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
1221 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1222 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
1223 0122f190: 0000: c0012d00 00040206 0000043f
1224 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1225 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
1226 0122f19c: 0000: c0012d00 00040000 00000020
1227 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1228 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1246000 }
1229 0122f1a8: 0000: c0012d00 00040001 01246009
1230 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
1231 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
1232 PA_SC_SCREEN_SCISSOR_BR: { X = 8 | Y = 16 }
1233 0122f1b4: 0000: c0022d00 0004000e 80000000 00100008
1234 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1235 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
1236 0122f1c4: 0000: c0012d00 00040080 00000000
1237 t0 write CP_SCRATCH_REG6 (057e)
1238 CP_SCRATCH_REG6: 27
1239 :0,0,27,18
1240 0122f1d0: 0000: 0000057e 0000001b
1241 t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
1242 ibaddr:0122e000
1243 ibsize:000000b6
1244 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
1245 set shader const 0078
1246 0122e000: 0000: c0042d00 00010078 0112d183 00100000 0112d183 00100000
1247 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1248 PA_SC_AA_MASK: 0xffff
1249 0122e018: 0000: c0012d00 00040312 0000ffff
1250 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1251 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
1252 0122e024: 0000: c0012d00 00040200 00000000
1253 t3 opcode: CP_SET_CONSTANT (2d) (5 dwords)
1254 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
1255 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
1256 RB_ALPHA_REF: 0
1257 0122e030: 0000: c0032d00 0004010c 00000000 00000000 00000000
1258 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
1259 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
1260 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
1261 0122e044: 0000: c0022d00 00040204 00000000 00090244
1262 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
1263 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
1264 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
1265 PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
1266 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
1267 0122e054: 0000: c0042d00 00040280 00000000 00000000 00000000 00000000
1268 t3 opcode: CP_SET_CONSTANT (2d) (7 dwords)
1269 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
1270 PA_CL_GB_VERT_CLIP_ADJ: 1.000000
1271 PA_CL_GB_VERT_DISC_ADJ: 1.000000
1272 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
1273 PA_CL_GB_HORZ_DISC_ADJ: 1.000000
1274 0122e06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
1275 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
1276 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
1277 PA_SC_WINDOW_SCISSOR_BR: { X = 8 | Y = 16 }
1278 0122e088: 0000: c0022d00 00040081 00000000 00100008
1279 t3 opcode: CP_SET_CONSTANT (2d) (8 dwords)
1280 PA_CL_VPORT_XSCALE: 4.000000
1281 PA_CL_VPORT_XOFFSET: 4.000000
1282 PA_CL_VPORT_YSCALE: 8.000000
1283 PA_CL_VPORT_YOFFSET: 8.000000
1284 PA_CL_VPORT_ZSCALE: 0.000000
1285 PA_CL_VPORT_ZOFFSET: 0.000000
1286 0122e098: 0000: c0062d00 0004010f 40800000 40800000 41000000 41000000 00000000 00000000
1287 t3 opcode: CP_SET_CONSTANT (2d) (10 dwords)
1288 0122e0c0: 4.000000 8.000000 0.000000 0.000000 4.000000 8.000000 0.000000 0.000000
1289 0122e0b8: 0000: c0082d00 00000184 40800000 41000000 00000000 00000000 40800000 41000000
1290 *
1291 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
1292 vertex shader, start=0000, size=0015
1293 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2)
1294 03: 19481000 00262688 00000020 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0)
1295 04: 13480000 40262688 00001020 FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1)
1296 0000 0000 c200 ALLOC POSITION SIZE(0x0)
1297 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1)
1298 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position
1299 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
1300 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1)
1301 06: 000f8000 00000000 c2000000 ALU: MAXv export0 = R0, R0
1302 0000 0000 0000 NOP
1303 0122e0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
1304 0122e100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000
1305 0122e120: 0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000
1306 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
1307 fragment shader, start=0000, size=000c
1308 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1)
1309 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
1310 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
1311 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1)
1312 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor
1313 0000 0000 0000 NOP
1314 0122e140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
1315 0122e160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
1316 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1317 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
1318 0122e17c: 0000: c0012d00 00040181 00000106
1319 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1320 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
1321 0122e188: 0000: c0012d00 00040180 10030002
1322 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
1323 0122e19c: 0.000000 0.000000 0.000000 0.000000
1324 0122e194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000
1325 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1326 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
1327 0122e1ac: 0000: c0012d00 00040202 00000c20
1328 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1329 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
1330 0122e1b8: 0000: c0012d00 00040201 00000000
1331 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1332 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
1333 0122e1c4: 0000: c0012d00 00040104 0000000f
1334 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
1335 RB_BLEND_RED: 0
1336 RB_BLEND_GREEN: 0
1337 RB_BLEND_BLUE: 0
1338 RB_BLEND_ALPHA: 0
1339 0122e1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000
1340 t3 opcode: CP_SET_CONSTANT (2d) (8 dwords)
1341 set texture const 0000
1342 clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel
1343 filter min/mag: point/point
1344 swizzle: xyzw
1345 addr=01254000 (flags=820), size=8x16, pitch=32, format=FMT_1_REVERSE
1346 mipaddr=00000000 (flags=200)
1347 0122e1e8: 0000: c0062d00 00010000 00424800 01254820 0001e007 00000d11 00000000 00000200
1348 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1349 VGT_INDX_OFFSET: 0
1350 0122e208: 0000: c0012d00 00040102 00000000
1351 t0 write TC_CNTL_STATUS (0e00)
1352 TC_CNTL_STATUS: { L2_INVALIDATE }
1353 0122e214: 0000: 00000e00 00000001
1354 t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords)
1355 0122e21c: 0000: c0035200 000005d0 00000000 00001000 00000001
1356 t3 opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
1357 0122e230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
1358 t0 write CP_SCRATCH_REG7 (057f)
1359 CP_SCRATCH_REG7: 23
1360 :0,0,27,23
1361 0122e24c: 0000: 0000057f 00000017
1362 t3 opcode: CP_NOP (10) (2 dwords)
1363 0122e254: 0000: c0001000 00000000
1364 t3 opcode: CP_DRAW_INDX (22) (3 dwords)
1365 { VIZ_QUERY = 0 }
1366 { PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 }
1367 draw: 0
1368 prim_type: DI_PT_TRIFAN (5)
1369 source_select: DI_SRC_SEL_AUTO_INDEX (2)
1370 num_indices: 1407
1371 draw[3] register values
1372 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
1373 + 00000fff RBBM_PM_OVERRIDE2: 0xfff
1374 + 00000000 CP_PERFMON_CNTL: 0
1375 !+ 0000001b CP_SCRATCH_REG6: 27
1376 :0,0,27,23
1377 !+ 00000017 CP_SCRATCH_REG7: 23
1378 :0,0,27,23
1379 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
1380 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE }
1381 + 00000002 TP0_CHICKEN: 0x2
1382 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
1383 + 00000020 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
1384 !+ 01246009 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1246000 }
1385 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
1386 !+ 00100008 PA_SC_SCREEN_SCISSOR_BR: { X = 8 | Y = 16 }
1387 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
1388 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
1389 !+ 00100008 PA_SC_WINDOW_SCISSOR_BR: { X = 8 | Y = 16 }
1390 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff
1391 + 00000000 VGT_MIN_VTX_INDX: 0
1392 + 00000000 VGT_INDX_OFFSET: 0
1393 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
1394 + 00000000 RB_BLEND_RED: 0
1395 + 00000000 RB_BLEND_GREEN: 0
1396 + 00000000 RB_BLEND_BLUE: 0
1397 + 00000000 RB_BLEND_ALPHA: 0
1398 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
1399 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
1400 + 00000000 RB_ALPHA_REF: 0
1401 !+ 40800000 PA_CL_VPORT_XSCALE: 4.000000
1402 !+ 40800000 PA_CL_VPORT_XOFFSET: 4.000000
1403 !+ 41000000 PA_CL_VPORT_YSCALE: 8.000000
1404 !+ 41000000 PA_CL_VPORT_YOFFSET: 8.000000
1405 + 00000000 PA_CL_VPORT_ZSCALE: 0.000000
1406 + 00000000 PA_CL_VPORT_ZOFFSET: 0.000000
1407 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
1408 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
1409 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
1410 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
1411 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
1412 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
1413 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
1414 + 00000c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
1415 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
1416 + 00090244 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
1417 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
1418 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
1419 + 88888888 RB_SAMPLE_POS: 0x88888888
1420 + 00000000 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
1421 + 00000000 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
1422 + 00000000 PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
1423 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
1424 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
1425 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
1426 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
1427 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
1428 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000
1429 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000
1430 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
1431 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000
1432 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
1433 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
1434 + 0000ffff PA_SC_AA_MASK: 0xffff
1435 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
1436 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
1437 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
1438 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff
1439 0122e25c: 0000: c0012200 00000000 00040085
1440 t0 write CP_SCRATCH_REG7 (057f)
1441 NEEDS WFI: CP_SCRATCH_REG7 (57f)
1442 CP_SCRATCH_REG7: 24
1443 :0,0,27,24
1444 0122e268: 0000: 0000057f 00000018
1445 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
1446 0122e270: 0000: c0002600 00000000
1447 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
1448 { EVENT = CACHE_FLUSH }
1449 event CACHE_FLUSH
1450 0122e278: 0000: c0004600 00000006
1451 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
1452 { EVENT = CACHE_FLUSH }
1453 event CACHE_FLUSH
1454 0122e280: 0000: c0004600 00000006
1455 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
1456 { EVENT = CACHE_FLUSH }
1457 event CACHE_FLUSH
1458 0122e288: 0000: c0004600 00000006
1459 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
1460 { EVENT = CACHE_FLUSH }
1461 event CACHE_FLUSH
1462 0122e290: 0000: c0004600 00000006
1463 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
1464 { EVENT = CACHE_FLUSH }
1465 event CACHE_FLUSH
1466 0122e298: 0000: c0004600 00000006
1467 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
1468 { EVENT = CACHE_FLUSH }
1469 event CACHE_FLUSH
1470 0122e2a0: 0000: c0004600 00000006
1471 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
1472 { EVENT = CACHE_FLUSH }
1473 event CACHE_FLUSH
1474 0122e2a8: 0000: c0004600 00000006
1475 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
1476 { EVENT = CACHE_FLUSH }
1477 event CACHE_FLUSH
1478 0122e2b0: 0000: c0004600 00000006
1479 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
1480 { EVENT = CACHE_FLUSH }
1481 event CACHE_FLUSH
1482 0122e2b8: 0000: c0004600 00000006
1483 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
1484 { EVENT = CACHE_FLUSH }
1485 event CACHE_FLUSH
1486 0122e2c0: 0000: c0004600 00000006
1487 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
1488 { EVENT = CACHE_FLUSH }
1489 event CACHE_FLUSH
1490 0122e2c8: 0000: c0004600 00000006
1491 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
1492 { EVENT = CACHE_FLUSH }
1493 event CACHE_FLUSH
1494 0122e2d0: 0000: c0004600 00000006
1495 0122f1d8: 0000: c0013700 0122e000 000000b6
1496 t2 nop
1497 ############################################################
1498 vertices: 0
1499 cmd: deqp-gles2/185: fence=1254
1500 ############################################################
1501 cmdstream: 124 dwords
1502 t0 write RB_BC_CONTROL (0f01)
1503 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
1504 0122d000: 0000: 00000f01 1c004046
1505 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1506 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
1507 0122d008: 0000: c0012d00 00040293 00000020
1508 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1509 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
1510 0122d014: 0000: c0012d00 00040316 00000002
1511 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1512 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
1513 0122d020: 0000: c0012d00 00040317 00000002
1514 t0 write CP_PERFMON_CNTL (0444)
1515 CP_PERFMON_CNTL: 0
1516 0122d02c: 0000: 00000444 00000000
1517 t0 write RBBM_PM_OVERRIDE1 (039c)
1518 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
1519 RBBM_PM_OVERRIDE2: 0xfff
1520 0122d034: 0000: 0001039c ffffffff 00000fff
1521 t0 write TP0_CHICKEN (0e1e)
1522 TP0_CHICKEN: 0x2
1523 0122d040: 0000: 00000e1e 00000002
1524 t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
1525 0122d048: 0000: c0003b00 00007fff
1526 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1527 SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
1528 0122d050: 0000: c0012d00 00040307 00100020
1529 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1530 SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
1531 0122d05c: 0000: c0012d00 00040308 000e0120
1532 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
1533 VGT_MAX_VTX_INDX: 0xffffffff
1534 VGT_MIN_VTX_INDX: 0
1535 0122d068: 0000: c0022d00 00040100 ffffffff 00000000
1536 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1537 VGT_INDX_OFFSET: 0
1538 0122d078: 0000: c0012d00 00040102 00000000
1539 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1540 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
1541 0122d084: 0000: c0012d00 00040181 00000004
1542 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1543 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
1544 0122d090: 0000: c0012d00 00040182 ffffffff
1545 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1546 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
1547 0122d09c: 0000: c0012d00 00040301 00000000
1548 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1549 PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
1550 0122d0a8: 0000: c0012d00 00040300 00000000
1551 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1552 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
1553 0122d0b4: 0000: c0012d00 00040080 00000000
1554 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1555 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
1556 0122d0c0: 0000: c0012d00 00040208 00000004
1557 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1558 RB_SAMPLE_POS: 0x88888888
1559 0122d0cc: 0000: c0012d00 0004020a 88888888
1560 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1561 RB_COLOR_DEST_MASK: 0xffffffff
1562 0122d0d8: 0000: c0012d00 00040326 ffffffff
1563 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1564 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
1565 0122d0e4: 0000: c0012d00 0004031b 0003c000
1566 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
1567 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
1568 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
1569 0122d0f0: 0000: c0022d00 00040183 00000000 00000000
1570 t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
1571 0122d100: 0000: c0004b00 00000000
1572 t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords)
1573 0122d108: 0000: c0035200 000005d0 00000000 5f601000 00000001
1574 t0 write SQ_INST_STORE_MANAGMENT (0d02)
1575 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
1576 0122d11c: 0000: 00000d02 00000180
1577 t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
1578 0122d124: 0000: c0003b00 00000300
1579 t3 opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
1580 0122d12c: 0000: c0004a00 80000180
1581 t3 opcode: CP_SET_CONSTANT (2d) (14 dwords)
1582 0122d13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
1583 0122d15c: 2.000000 0.750000 0.375000 0.250000
1584 0122d134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
1585 0122d154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
1586 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1587 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
1588 0122d16c: 0000: c0012d00 00040104 0000000f
1589 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
1590 RB_BLEND_RED: 0
1591 RB_BLEND_GREEN: 0
1592 RB_BLEND_BLUE: 0
1593 RB_BLEND_ALPHA: 0xff
1594 0122d178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
1595 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1596 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
1597 0122d190: 0000: c0012d00 00040206 0000043f
1598 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1599 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
1600 0122d19c: 0000: c0012d00 00040000 00000020
1601 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1602 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1248000 }
1603 0122d1a8: 0000: c0012d00 00040001 01248009
1604 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
1605 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
1606 PA_SC_SCREEN_SCISSOR_BR: { X = 4 | Y = 8 }
1607 0122d1b4: 0000: c0022d00 0004000e 80000000 00080004
1608 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1609 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
1610 0122d1c4: 0000: c0012d00 00040080 00000000
1611 t0 write CP_SCRATCH_REG6 (057e)
1612 CP_SCRATCH_REG6: 33
1613 :0,0,33,24
1614 0122d1d0: 0000: 0000057e 00000021
1615 t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
1616 ibaddr:0122e000
1617 ibsize:000000b6
1618 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
1619 set shader const 0078
1620 0122e000: 0000: c0042d00 00010078 0112d203 00100000 0112d203 00100000
1621 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1622 PA_SC_AA_MASK: 0xffff
1623 0122e018: 0000: c0012d00 00040312 0000ffff
1624 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1625 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
1626 0122e024: 0000: c0012d00 00040200 00000000
1627 t3 opcode: CP_SET_CONSTANT (2d) (5 dwords)
1628 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
1629 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
1630 RB_ALPHA_REF: 0
1631 0122e030: 0000: c0032d00 0004010c 00000000 00000000 00000000
1632 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
1633 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
1634 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
1635 0122e044: 0000: c0022d00 00040204 00000000 00090244
1636 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
1637 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
1638 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
1639 PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
1640 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
1641 0122e054: 0000: c0042d00 00040280 00000000 00000000 00000000 00000000
1642 t3 opcode: CP_SET_CONSTANT (2d) (7 dwords)
1643 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
1644 PA_CL_GB_VERT_CLIP_ADJ: 1.000000
1645 PA_CL_GB_VERT_DISC_ADJ: 1.000000
1646 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
1647 PA_CL_GB_HORZ_DISC_ADJ: 1.000000
1648 0122e06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
1649 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
1650 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
1651 PA_SC_WINDOW_SCISSOR_BR: { X = 4 | Y = 8 }
1652 0122e088: 0000: c0022d00 00040081 00000000 00080004
1653 t3 opcode: CP_SET_CONSTANT (2d) (8 dwords)
1654 PA_CL_VPORT_XSCALE: 2.000000
1655 PA_CL_VPORT_XOFFSET: 2.000000
1656 PA_CL_VPORT_YSCALE: 4.000000
1657 PA_CL_VPORT_YOFFSET: 4.000000
1658 PA_CL_VPORT_ZSCALE: 0.000000
1659 PA_CL_VPORT_ZOFFSET: 0.000000
1660 0122e098: 0000: c0062d00 0004010f 40000000 40000000 40800000 40800000 00000000 00000000
1661 t3 opcode: CP_SET_CONSTANT (2d) (10 dwords)
1662 0122e0c0: 2.000000 4.000000 0.000000 0.000000 2.000000 4.000000 0.000000 0.000000
1663 0122e0b8: 0000: c0082d00 00000184 40000000 40800000 00000000 00000000 40000000 40800000
1664 *
1665 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
1666 vertex shader, start=0000, size=0015
1667 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2)
1668 03: 19481000 00262688 00000020 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0)
1669 04: 13480000 40262688 00001020 FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1)
1670 0000 0000 c200 ALLOC POSITION SIZE(0x0)
1671 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1)
1672 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position
1673 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
1674 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1)
1675 06: 000f8000 00000000 c2000000 ALU: MAXv export0 = R0, R0
1676 0000 0000 0000 NOP
1677 0122e0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
1678 0122e100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000
1679 0122e120: 0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000
1680 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
1681 fragment shader, start=0000, size=000c
1682 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1)
1683 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
1684 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
1685 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1)
1686 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor
1687 0000 0000 0000 NOP
1688 0122e140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
1689 0122e160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
1690 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1691 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
1692 0122e17c: 0000: c0012d00 00040181 00000106
1693 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1694 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
1695 0122e188: 0000: c0012d00 00040180 10030002
1696 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
1697 0122e19c: 0.000000 0.000000 0.000000 0.000000
1698 0122e194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000
1699 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1700 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
1701 0122e1ac: 0000: c0012d00 00040202 00000c20
1702 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1703 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
1704 0122e1b8: 0000: c0012d00 00040201 00000000
1705 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1706 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
1707 0122e1c4: 0000: c0012d00 00040104 0000000f
1708 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
1709 RB_BLEND_RED: 0
1710 RB_BLEND_GREEN: 0
1711 RB_BLEND_BLUE: 0
1712 RB_BLEND_ALPHA: 0
1713 0122e1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000
1714 t3 opcode: CP_SET_CONSTANT (2d) (8 dwords)
1715 set texture const 0000
1716 clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel
1717 filter min/mag: point/point
1718 swizzle: xyzw
1719 addr=01254000 (flags=820), size=4x8, pitch=32, format=FMT_1_REVERSE
1720 mipaddr=00000000 (flags=200)
1721 0122e1e8: 0000: c0062d00 00010000 00424800 01254820 0000e003 00000d11 00000000 00000200
1722 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1723 VGT_INDX_OFFSET: 0
1724 0122e208: 0000: c0012d00 00040102 00000000
1725 t0 write TC_CNTL_STATUS (0e00)
1726 TC_CNTL_STATUS: { L2_INVALIDATE }
1727 0122e214: 0000: 00000e00 00000001
1728 t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords)
1729 0122e21c: 0000: c0035200 000005d0 00000000 00001000 00000001
1730 t3 opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
1731 0122e230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
1732 t0 write CP_SCRATCH_REG7 (057f)
1733 CP_SCRATCH_REG7: 29
1734 :0,0,33,29
1735 0122e24c: 0000: 0000057f 0000001d
1736 t3 opcode: CP_NOP (10) (2 dwords)
1737 0122e254: 0000: c0001000 00000000
1738 t3 opcode: CP_DRAW_INDX (22) (3 dwords)
1739 { VIZ_QUERY = 0 }
1740 { PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 }
1741 draw: 0
1742 prim_type: DI_PT_TRIFAN (5)
1743 source_select: DI_SRC_SEL_AUTO_INDEX (2)
1744 num_indices: 1407
1745 draw[4] register values
1746 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
1747 + 00000fff RBBM_PM_OVERRIDE2: 0xfff
1748 + 00000000 CP_PERFMON_CNTL: 0
1749 !+ 00000021 CP_SCRATCH_REG6: 33
1750 :0,0,33,29
1751 !+ 0000001d CP_SCRATCH_REG7: 29
1752 :0,0,33,29
1753 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
1754 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE }
1755 + 00000002 TP0_CHICKEN: 0x2
1756 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
1757 + 00000020 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
1758 !+ 01248009 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1248000 }
1759 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
1760 !+ 00080004 PA_SC_SCREEN_SCISSOR_BR: { X = 4 | Y = 8 }
1761 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
1762 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
1763 !+ 00080004 PA_SC_WINDOW_SCISSOR_BR: { X = 4 | Y = 8 }
1764 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff
1765 + 00000000 VGT_MIN_VTX_INDX: 0
1766 + 00000000 VGT_INDX_OFFSET: 0
1767 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
1768 + 00000000 RB_BLEND_RED: 0
1769 + 00000000 RB_BLEND_GREEN: 0
1770 + 00000000 RB_BLEND_BLUE: 0
1771 + 00000000 RB_BLEND_ALPHA: 0
1772 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
1773 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
1774 + 00000000 RB_ALPHA_REF: 0
1775 !+ 40000000 PA_CL_VPORT_XSCALE: 2.000000
1776 !+ 40000000 PA_CL_VPORT_XOFFSET: 2.000000
1777 !+ 40800000 PA_CL_VPORT_YSCALE: 4.000000
1778 !+ 40800000 PA_CL_VPORT_YOFFSET: 4.000000
1779 + 00000000 PA_CL_VPORT_ZSCALE: 0.000000
1780 + 00000000 PA_CL_VPORT_ZOFFSET: 0.000000
1781 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
1782 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
1783 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
1784 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
1785 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
1786 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
1787 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
1788 + 00000c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
1789 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
1790 + 00090244 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
1791 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
1792 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
1793 + 88888888 RB_SAMPLE_POS: 0x88888888
1794 + 00000000 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
1795 + 00000000 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
1796 + 00000000 PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
1797 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
1798 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
1799 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
1800 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
1801 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
1802 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000
1803 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000
1804 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
1805 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000
1806 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
1807 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
1808 + 0000ffff PA_SC_AA_MASK: 0xffff
1809 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
1810 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
1811 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
1812 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff
1813 0122e25c: 0000: c0012200 00000000 00040085
1814 t0 write CP_SCRATCH_REG7 (057f)
1815 NEEDS WFI: CP_SCRATCH_REG7 (57f)
1816 CP_SCRATCH_REG7: 30
1817 :0,0,33,30
1818 0122e268: 0000: 0000057f 0000001e
1819 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
1820 0122e270: 0000: c0002600 00000000
1821 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
1822 { EVENT = CACHE_FLUSH }
1823 event CACHE_FLUSH
1824 0122e278: 0000: c0004600 00000006
1825 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
1826 { EVENT = CACHE_FLUSH }
1827 event CACHE_FLUSH
1828 0122e280: 0000: c0004600 00000006
1829 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
1830 { EVENT = CACHE_FLUSH }
1831 event CACHE_FLUSH
1832 0122e288: 0000: c0004600 00000006
1833 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
1834 { EVENT = CACHE_FLUSH }
1835 event CACHE_FLUSH
1836 0122e290: 0000: c0004600 00000006
1837 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
1838 { EVENT = CACHE_FLUSH }
1839 event CACHE_FLUSH
1840 0122e298: 0000: c0004600 00000006
1841 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
1842 { EVENT = CACHE_FLUSH }
1843 event CACHE_FLUSH
1844 0122e2a0: 0000: c0004600 00000006
1845 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
1846 { EVENT = CACHE_FLUSH }
1847 event CACHE_FLUSH
1848 0122e2a8: 0000: c0004600 00000006
1849 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
1850 { EVENT = CACHE_FLUSH }
1851 event CACHE_FLUSH
1852 0122e2b0: 0000: c0004600 00000006
1853 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
1854 { EVENT = CACHE_FLUSH }
1855 event CACHE_FLUSH
1856 0122e2b8: 0000: c0004600 00000006
1857 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
1858 { EVENT = CACHE_FLUSH }
1859 event CACHE_FLUSH
1860 0122e2c0: 0000: c0004600 00000006
1861 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
1862 { EVENT = CACHE_FLUSH }
1863 event CACHE_FLUSH
1864 0122e2c8: 0000: c0004600 00000006
1865 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
1866 { EVENT = CACHE_FLUSH }
1867 event CACHE_FLUSH
1868 0122e2d0: 0000: c0004600 00000006
1869 0122d1d8: 0000: c0013700 0122e000 000000b6
1870 t2 nop
1871 ############################################################
1872 vertices: 0
1873 cmd: deqp-gles2/185: fence=1255
1874 ############################################################
1875 cmdstream: 124 dwords
1876 t0 write RB_BC_CONTROL (0f01)
1877 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
1878 0122f000: 0000: 00000f01 1c004046
1879 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1880 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
1881 0122f008: 0000: c0012d00 00040293 00000020
1882 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1883 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
1884 0122f014: 0000: c0012d00 00040316 00000002
1885 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1886 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
1887 0122f020: 0000: c0012d00 00040317 00000002
1888 t0 write CP_PERFMON_CNTL (0444)
1889 CP_PERFMON_CNTL: 0
1890 0122f02c: 0000: 00000444 00000000
1891 t0 write RBBM_PM_OVERRIDE1 (039c)
1892 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
1893 RBBM_PM_OVERRIDE2: 0xfff
1894 0122f034: 0000: 0001039c ffffffff 00000fff
1895 t0 write TP0_CHICKEN (0e1e)
1896 TP0_CHICKEN: 0x2
1897 0122f040: 0000: 00000e1e 00000002
1898 t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
1899 0122f048: 0000: c0003b00 00007fff
1900 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1901 SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
1902 0122f050: 0000: c0012d00 00040307 00100020
1903 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1904 SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
1905 0122f05c: 0000: c0012d00 00040308 000e0120
1906 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
1907 VGT_MAX_VTX_INDX: 0xffffffff
1908 VGT_MIN_VTX_INDX: 0
1909 0122f068: 0000: c0022d00 00040100 ffffffff 00000000
1910 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1911 VGT_INDX_OFFSET: 0
1912 0122f078: 0000: c0012d00 00040102 00000000
1913 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1914 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
1915 0122f084: 0000: c0012d00 00040181 00000004
1916 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1917 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
1918 0122f090: 0000: c0012d00 00040182 ffffffff
1919 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1920 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
1921 0122f09c: 0000: c0012d00 00040301 00000000
1922 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1923 PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
1924 0122f0a8: 0000: c0012d00 00040300 00000000
1925 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1926 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
1927 0122f0b4: 0000: c0012d00 00040080 00000000
1928 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1929 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
1930 0122f0c0: 0000: c0012d00 00040208 00000004
1931 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1932 RB_SAMPLE_POS: 0x88888888
1933 0122f0cc: 0000: c0012d00 0004020a 88888888
1934 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1935 RB_COLOR_DEST_MASK: 0xffffffff
1936 0122f0d8: 0000: c0012d00 00040326 ffffffff
1937 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1938 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
1939 0122f0e4: 0000: c0012d00 0004031b 0003c000
1940 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
1941 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
1942 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
1943 0122f0f0: 0000: c0022d00 00040183 00000000 00000000
1944 t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
1945 0122f100: 0000: c0004b00 00000000
1946 t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords)
1947 0122f108: 0000: c0035200 000005d0 00000000 5f601000 00000001
1948 t0 write SQ_INST_STORE_MANAGMENT (0d02)
1949 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
1950 0122f11c: 0000: 00000d02 00000180
1951 t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
1952 0122f124: 0000: c0003b00 00000300
1953 t3 opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
1954 0122f12c: 0000: c0004a00 80000180
1955 t3 opcode: CP_SET_CONSTANT (2d) (14 dwords)
1956 0122f13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
1957 0122f15c: 2.000000 0.750000 0.375000 0.250000
1958 0122f134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
1959 0122f154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
1960 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1961 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
1962 0122f16c: 0000: c0012d00 00040104 0000000f
1963 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
1964 RB_BLEND_RED: 0
1965 RB_BLEND_GREEN: 0
1966 RB_BLEND_BLUE: 0
1967 RB_BLEND_ALPHA: 0xff
1968 0122f178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
1969 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1970 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
1971 0122f190: 0000: c0012d00 00040206 0000043f
1972 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1973 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
1974 0122f19c: 0000: c0012d00 00040000 00000020
1975 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1976 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x124a000 }
1977 0122f1a8: 0000: c0012d00 00040001 0124a009
1978 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
1979 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
1980 PA_SC_SCREEN_SCISSOR_BR: { X = 2 | Y = 4 }
1981 0122f1b4: 0000: c0022d00 0004000e 80000000 00040002
1982 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1983 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
1984 0122f1c4: 0000: c0012d00 00040080 00000000
1985 t0 write CP_SCRATCH_REG6 (057e)
1986 CP_SCRATCH_REG6: 39
1987 :0,0,39,30
1988 0122f1d0: 0000: 0000057e 00000027
1989 t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
1990 ibaddr:0122e000
1991 ibsize:000000b6
1992 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
1993 set shader const 0078
1994 0122e000: 0000: c0042d00 00010078 0112d283 00100000 0112d283 00100000
1995 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1996 PA_SC_AA_MASK: 0xffff
1997 0122e018: 0000: c0012d00 00040312 0000ffff
1998 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
1999 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
2000 0122e024: 0000: c0012d00 00040200 00000000
2001 t3 opcode: CP_SET_CONSTANT (2d) (5 dwords)
2002 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
2003 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
2004 RB_ALPHA_REF: 0
2005 0122e030: 0000: c0032d00 0004010c 00000000 00000000 00000000
2006 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
2007 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
2008 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
2009 0122e044: 0000: c0022d00 00040204 00000000 00090244
2010 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
2011 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
2012 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
2013 PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
2014 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
2015 0122e054: 0000: c0042d00 00040280 00000000 00000000 00000000 00000000
2016 t3 opcode: CP_SET_CONSTANT (2d) (7 dwords)
2017 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
2018 PA_CL_GB_VERT_CLIP_ADJ: 1.000000
2019 PA_CL_GB_VERT_DISC_ADJ: 1.000000
2020 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
2021 PA_CL_GB_HORZ_DISC_ADJ: 1.000000
2022 0122e06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
2023 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
2024 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
2025 PA_SC_WINDOW_SCISSOR_BR: { X = 2 | Y = 4 }
2026 0122e088: 0000: c0022d00 00040081 00000000 00040002
2027 t3 opcode: CP_SET_CONSTANT (2d) (8 dwords)
2028 PA_CL_VPORT_XSCALE: 1.000000
2029 PA_CL_VPORT_XOFFSET: 1.000000
2030 PA_CL_VPORT_YSCALE: 2.000000
2031 PA_CL_VPORT_YOFFSET: 2.000000
2032 PA_CL_VPORT_ZSCALE: 0.000000
2033 PA_CL_VPORT_ZOFFSET: 0.000000
2034 0122e098: 0000: c0062d00 0004010f 3f800000 3f800000 40000000 40000000 00000000 00000000
2035 t3 opcode: CP_SET_CONSTANT (2d) (10 dwords)
2036 0122e0c0: 1.000000 2.000000 0.000000 0.000000 1.000000 2.000000 0.000000 0.000000
2037 0122e0b8: 0000: c0082d00 00000184 3f800000 40000000 00000000 00000000 3f800000 40000000
2038 *
2039 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
2040 vertex shader, start=0000, size=0015
2041 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2)
2042 03: 19481000 00262688 00000020 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0)
2043 04: 13480000 40262688 00001020 FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1)
2044 0000 0000 c200 ALLOC POSITION SIZE(0x0)
2045 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1)
2046 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position
2047 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
2048 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1)
2049 06: 000f8000 00000000 c2000000 ALU: MAXv export0 = R0, R0
2050 0000 0000 0000 NOP
2051 0122e0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
2052 0122e100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000
2053 0122e120: 0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000
2054 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
2055 fragment shader, start=0000, size=000c
2056 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1)
2057 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
2058 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
2059 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1)
2060 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor
2061 0000 0000 0000 NOP
2062 0122e140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
2063 0122e160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
2064 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2065 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
2066 0122e17c: 0000: c0012d00 00040181 00000106
2067 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2068 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
2069 0122e188: 0000: c0012d00 00040180 10030002
2070 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
2071 0122e19c: 0.000000 0.000000 0.000000 0.000000
2072 0122e194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000
2073 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2074 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
2075 0122e1ac: 0000: c0012d00 00040202 00000c20
2076 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2077 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
2078 0122e1b8: 0000: c0012d00 00040201 00000000
2079 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2080 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
2081 0122e1c4: 0000: c0012d00 00040104 0000000f
2082 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
2083 RB_BLEND_RED: 0
2084 RB_BLEND_GREEN: 0
2085 RB_BLEND_BLUE: 0
2086 RB_BLEND_ALPHA: 0
2087 0122e1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000
2088 t3 opcode: CP_SET_CONSTANT (2d) (8 dwords)
2089 set texture const 0000
2090 clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel
2091 filter min/mag: point/point
2092 swizzle: xyzw
2093 addr=01254000 (flags=820), size=2x4, pitch=32, format=FMT_1_REVERSE
2094 mipaddr=00000000 (flags=200)
2095 0122e1e8: 0000: c0062d00 00010000 00424800 01254820 00006001 00000d11 00000000 00000200
2096 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2097 VGT_INDX_OFFSET: 0
2098 0122e208: 0000: c0012d00 00040102 00000000
2099 t0 write TC_CNTL_STATUS (0e00)
2100 TC_CNTL_STATUS: { L2_INVALIDATE }
2101 0122e214: 0000: 00000e00 00000001
2102 t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords)
2103 0122e21c: 0000: c0035200 000005d0 00000000 00001000 00000001
2104 t3 opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
2105 0122e230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
2106 t0 write CP_SCRATCH_REG7 (057f)
2107 CP_SCRATCH_REG7: 35
2108 :0,0,39,35
2109 0122e24c: 0000: 0000057f 00000023
2110 t3 opcode: CP_NOP (10) (2 dwords)
2111 0122e254: 0000: c0001000 00000000
2112 t3 opcode: CP_DRAW_INDX (22) (3 dwords)
2113 { VIZ_QUERY = 0 }
2114 { PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 }
2115 draw: 0
2116 prim_type: DI_PT_TRIFAN (5)
2117 source_select: DI_SRC_SEL_AUTO_INDEX (2)
2118 num_indices: 1407
2119 draw[5] register values
2120 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
2121 + 00000fff RBBM_PM_OVERRIDE2: 0xfff
2122 + 00000000 CP_PERFMON_CNTL: 0
2123 !+ 00000027 CP_SCRATCH_REG6: 39
2124 :0,0,39,35
2125 !+ 00000023 CP_SCRATCH_REG7: 35
2126 :0,0,39,35
2127 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
2128 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE }
2129 + 00000002 TP0_CHICKEN: 0x2
2130 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
2131 + 00000020 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
2132 !+ 0124a009 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x124a000 }
2133 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
2134 !+ 00040002 PA_SC_SCREEN_SCISSOR_BR: { X = 2 | Y = 4 }
2135 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
2136 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
2137 !+ 00040002 PA_SC_WINDOW_SCISSOR_BR: { X = 2 | Y = 4 }
2138 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff
2139 + 00000000 VGT_MIN_VTX_INDX: 0
2140 + 00000000 VGT_INDX_OFFSET: 0
2141 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
2142 + 00000000 RB_BLEND_RED: 0
2143 + 00000000 RB_BLEND_GREEN: 0
2144 + 00000000 RB_BLEND_BLUE: 0
2145 + 00000000 RB_BLEND_ALPHA: 0
2146 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
2147 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
2148 + 00000000 RB_ALPHA_REF: 0
2149 !+ 3f800000 PA_CL_VPORT_XSCALE: 1.000000
2150 !+ 3f800000 PA_CL_VPORT_XOFFSET: 1.000000
2151 !+ 40000000 PA_CL_VPORT_YSCALE: 2.000000
2152 !+ 40000000 PA_CL_VPORT_YOFFSET: 2.000000
2153 + 00000000 PA_CL_VPORT_ZSCALE: 0.000000
2154 + 00000000 PA_CL_VPORT_ZOFFSET: 0.000000
2155 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
2156 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
2157 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
2158 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
2159 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
2160 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
2161 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
2162 + 00000c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
2163 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
2164 + 00090244 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
2165 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
2166 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
2167 + 88888888 RB_SAMPLE_POS: 0x88888888
2168 + 00000000 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
2169 + 00000000 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
2170 + 00000000 PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
2171 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
2172 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
2173 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
2174 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
2175 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
2176 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000
2177 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000
2178 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
2179 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000
2180 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
2181 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
2182 + 0000ffff PA_SC_AA_MASK: 0xffff
2183 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
2184 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
2185 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
2186 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff
2187 0122e25c: 0000: c0012200 00000000 00040085
2188 t0 write CP_SCRATCH_REG7 (057f)
2189 NEEDS WFI: CP_SCRATCH_REG7 (57f)
2190 CP_SCRATCH_REG7: 36
2191 :0,0,39,36
2192 0122e268: 0000: 0000057f 00000024
2193 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
2194 0122e270: 0000: c0002600 00000000
2195 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
2196 { EVENT = CACHE_FLUSH }
2197 event CACHE_FLUSH
2198 0122e278: 0000: c0004600 00000006
2199 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
2200 { EVENT = CACHE_FLUSH }
2201 event CACHE_FLUSH
2202 0122e280: 0000: c0004600 00000006
2203 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
2204 { EVENT = CACHE_FLUSH }
2205 event CACHE_FLUSH
2206 0122e288: 0000: c0004600 00000006
2207 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
2208 { EVENT = CACHE_FLUSH }
2209 event CACHE_FLUSH
2210 0122e290: 0000: c0004600 00000006
2211 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
2212 { EVENT = CACHE_FLUSH }
2213 event CACHE_FLUSH
2214 0122e298: 0000: c0004600 00000006
2215 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
2216 { EVENT = CACHE_FLUSH }
2217 event CACHE_FLUSH
2218 0122e2a0: 0000: c0004600 00000006
2219 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
2220 { EVENT = CACHE_FLUSH }
2221 event CACHE_FLUSH
2222 0122e2a8: 0000: c0004600 00000006
2223 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
2224 { EVENT = CACHE_FLUSH }
2225 event CACHE_FLUSH
2226 0122e2b0: 0000: c0004600 00000006
2227 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
2228 { EVENT = CACHE_FLUSH }
2229 event CACHE_FLUSH
2230 0122e2b8: 0000: c0004600 00000006
2231 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
2232 { EVENT = CACHE_FLUSH }
2233 event CACHE_FLUSH
2234 0122e2c0: 0000: c0004600 00000006
2235 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
2236 { EVENT = CACHE_FLUSH }
2237 event CACHE_FLUSH
2238 0122e2c8: 0000: c0004600 00000006
2239 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
2240 { EVENT = CACHE_FLUSH }
2241 event CACHE_FLUSH
2242 0122e2d0: 0000: c0004600 00000006
2243 0122f1d8: 0000: c0013700 0122e000 000000b6
2244 t2 nop
2245 ############################################################
2246 vertices: 0
2247 cmd: deqp-gles2/185: fence=1256
2248 ############################################################
2249 cmdstream: 124 dwords
2250 t0 write RB_BC_CONTROL (0f01)
2251 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
2252 0122d000: 0000: 00000f01 1c004046
2253 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2254 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
2255 0122d008: 0000: c0012d00 00040293 00000020
2256 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2257 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
2258 0122d014: 0000: c0012d00 00040316 00000002
2259 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2260 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
2261 0122d020: 0000: c0012d00 00040317 00000002
2262 t0 write CP_PERFMON_CNTL (0444)
2263 CP_PERFMON_CNTL: 0
2264 0122d02c: 0000: 00000444 00000000
2265 t0 write RBBM_PM_OVERRIDE1 (039c)
2266 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
2267 RBBM_PM_OVERRIDE2: 0xfff
2268 0122d034: 0000: 0001039c ffffffff 00000fff
2269 t0 write TP0_CHICKEN (0e1e)
2270 TP0_CHICKEN: 0x2
2271 0122d040: 0000: 00000e1e 00000002
2272 t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
2273 0122d048: 0000: c0003b00 00007fff
2274 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2275 SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
2276 0122d050: 0000: c0012d00 00040307 00100020
2277 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2278 SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
2279 0122d05c: 0000: c0012d00 00040308 000e0120
2280 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
2281 VGT_MAX_VTX_INDX: 0xffffffff
2282 VGT_MIN_VTX_INDX: 0
2283 0122d068: 0000: c0022d00 00040100 ffffffff 00000000
2284 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2285 VGT_INDX_OFFSET: 0
2286 0122d078: 0000: c0012d00 00040102 00000000
2287 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2288 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
2289 0122d084: 0000: c0012d00 00040181 00000004
2290 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2291 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
2292 0122d090: 0000: c0012d00 00040182 ffffffff
2293 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2294 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
2295 0122d09c: 0000: c0012d00 00040301 00000000
2296 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2297 PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
2298 0122d0a8: 0000: c0012d00 00040300 00000000
2299 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2300 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
2301 0122d0b4: 0000: c0012d00 00040080 00000000
2302 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2303 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
2304 0122d0c0: 0000: c0012d00 00040208 00000004
2305 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2306 RB_SAMPLE_POS: 0x88888888
2307 0122d0cc: 0000: c0012d00 0004020a 88888888
2308 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2309 RB_COLOR_DEST_MASK: 0xffffffff
2310 0122d0d8: 0000: c0012d00 00040326 ffffffff
2311 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2312 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
2313 0122d0e4: 0000: c0012d00 0004031b 0003c000
2314 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
2315 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
2316 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
2317 0122d0f0: 0000: c0022d00 00040183 00000000 00000000
2318 t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
2319 0122d100: 0000: c0004b00 00000000
2320 t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords)
2321 0122d108: 0000: c0035200 000005d0 00000000 5f601000 00000001
2322 t0 write SQ_INST_STORE_MANAGMENT (0d02)
2323 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
2324 0122d11c: 0000: 00000d02 00000180
2325 t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
2326 0122d124: 0000: c0003b00 00000300
2327 t3 opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
2328 0122d12c: 0000: c0004a00 80000180
2329 t3 opcode: CP_SET_CONSTANT (2d) (14 dwords)
2330 0122d13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
2331 0122d15c: 2.000000 0.750000 0.375000 0.250000
2332 0122d134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
2333 0122d154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
2334 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2335 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
2336 0122d16c: 0000: c0012d00 00040104 0000000f
2337 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
2338 RB_BLEND_RED: 0
2339 RB_BLEND_GREEN: 0
2340 RB_BLEND_BLUE: 0
2341 RB_BLEND_ALPHA: 0xff
2342 0122d178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
2343 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2344 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
2345 0122d190: 0000: c0012d00 00040206 0000043f
2346 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2347 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
2348 0122d19c: 0000: c0012d00 00040000 00000020
2349 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2350 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x124c000 }
2351 0122d1a8: 0000: c0012d00 00040001 0124c009
2352 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
2353 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
2354 PA_SC_SCREEN_SCISSOR_BR: { X = 1 | Y = 2 }
2355 0122d1b4: 0000: c0022d00 0004000e 80000000 00020001
2356 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2357 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
2358 0122d1c4: 0000: c0012d00 00040080 00000000
2359 t0 write CP_SCRATCH_REG6 (057e)
2360 CP_SCRATCH_REG6: 45
2361 :0,0,45,36
2362 0122d1d0: 0000: 0000057e 0000002d
2363 t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
2364 ibaddr:0122e000
2365 ibsize:000000b6
2366 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
2367 set shader const 0078
2368 0122e000: 0000: c0042d00 00010078 0112d303 00100000 0112d303 00100000
2369 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2370 PA_SC_AA_MASK: 0xffff
2371 0122e018: 0000: c0012d00 00040312 0000ffff
2372 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2373 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
2374 0122e024: 0000: c0012d00 00040200 00000000
2375 t3 opcode: CP_SET_CONSTANT (2d) (5 dwords)
2376 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
2377 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
2378 RB_ALPHA_REF: 0
2379 0122e030: 0000: c0032d00 0004010c 00000000 00000000 00000000
2380 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
2381 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
2382 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
2383 0122e044: 0000: c0022d00 00040204 00000000 00090244
2384 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
2385 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
2386 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
2387 PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
2388 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
2389 0122e054: 0000: c0042d00 00040280 00000000 00000000 00000000 00000000
2390 t3 opcode: CP_SET_CONSTANT (2d) (7 dwords)
2391 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
2392 PA_CL_GB_VERT_CLIP_ADJ: 1.000000
2393 PA_CL_GB_VERT_DISC_ADJ: 1.000000
2394 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
2395 PA_CL_GB_HORZ_DISC_ADJ: 1.000000
2396 0122e06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
2397 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
2398 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
2399 PA_SC_WINDOW_SCISSOR_BR: { X = 1 | Y = 2 }
2400 0122e088: 0000: c0022d00 00040081 00000000 00020001
2401 t3 opcode: CP_SET_CONSTANT (2d) (8 dwords)
2402 PA_CL_VPORT_XSCALE: 0.500000
2403 PA_CL_VPORT_XOFFSET: 0.500000
2404 PA_CL_VPORT_YSCALE: 1.000000
2405 PA_CL_VPORT_YOFFSET: 1.000000
2406 PA_CL_VPORT_ZSCALE: 0.000000
2407 PA_CL_VPORT_ZOFFSET: 0.000000
2408 0122e098: 0000: c0062d00 0004010f 3f000000 3f000000 3f800000 3f800000 00000000 00000000
2409 t3 opcode: CP_SET_CONSTANT (2d) (10 dwords)
2410 0122e0c0: 0.500000 1.000000 0.000000 0.000000 0.500000 1.000000 0.000000 0.000000
2411 0122e0b8: 0000: c0082d00 00000184 3f000000 3f800000 00000000 00000000 3f000000 3f800000
2412 *
2413 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
2414 vertex shader, start=0000, size=0015
2415 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2)
2416 03: 19481000 00262688 00000020 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0)
2417 04: 13480000 40262688 00001020 FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1)
2418 0000 0000 c200 ALLOC POSITION SIZE(0x0)
2419 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1)
2420 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position
2421 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
2422 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1)
2423 06: 000f8000 00000000 c2000000 ALU: MAXv export0 = R0, R0
2424 0000 0000 0000 NOP
2425 0122e0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
2426 0122e100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000
2427 0122e120: 0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000
2428 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
2429 fragment shader, start=0000, size=000c
2430 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1)
2431 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
2432 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
2433 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1)
2434 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor
2435 0000 0000 0000 NOP
2436 0122e140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
2437 0122e160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
2438 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2439 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
2440 0122e17c: 0000: c0012d00 00040181 00000106
2441 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2442 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
2443 0122e188: 0000: c0012d00 00040180 10030002
2444 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
2445 0122e19c: 0.000000 0.000000 0.000000 0.000000
2446 0122e194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000
2447 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2448 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
2449 0122e1ac: 0000: c0012d00 00040202 00000c20
2450 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2451 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
2452 0122e1b8: 0000: c0012d00 00040201 00000000
2453 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2454 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
2455 0122e1c4: 0000: c0012d00 00040104 0000000f
2456 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
2457 RB_BLEND_RED: 0
2458 RB_BLEND_GREEN: 0
2459 RB_BLEND_BLUE: 0
2460 RB_BLEND_ALPHA: 0
2461 0122e1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000
2462 t3 opcode: CP_SET_CONSTANT (2d) (8 dwords)
2463 set texture const 0000
2464 clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel
2465 filter min/mag: point/point
2466 swizzle: xyzw
2467 addr=01254000 (flags=820), size=1x2, pitch=32, format=FMT_1_REVERSE
2468 mipaddr=00000000 (flags=200)
2469 0122e1e8: 0000: c0062d00 00010000 00424800 01254820 00002000 00000d11 00000000 00000200
2470 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2471 VGT_INDX_OFFSET: 0
2472 0122e208: 0000: c0012d00 00040102 00000000
2473 t0 write TC_CNTL_STATUS (0e00)
2474 TC_CNTL_STATUS: { L2_INVALIDATE }
2475 0122e214: 0000: 00000e00 00000001
2476 t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords)
2477 0122e21c: 0000: c0035200 000005d0 00000000 00001000 00000001
2478 t3 opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
2479 0122e230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
2480 t0 write CP_SCRATCH_REG7 (057f)
2481 CP_SCRATCH_REG7: 41
2482 :0,0,45,41
2483 0122e24c: 0000: 0000057f 00000029
2484 t3 opcode: CP_NOP (10) (2 dwords)
2485 0122e254: 0000: c0001000 00000000
2486 t3 opcode: CP_DRAW_INDX (22) (3 dwords)
2487 { VIZ_QUERY = 0 }
2488 { PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 }
2489 draw: 0
2490 prim_type: DI_PT_TRIFAN (5)
2491 source_select: DI_SRC_SEL_AUTO_INDEX (2)
2492 num_indices: 1407
2493 draw[6] register values
2494 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
2495 + 00000fff RBBM_PM_OVERRIDE2: 0xfff
2496 + 00000000 CP_PERFMON_CNTL: 0
2497 !+ 0000002d CP_SCRATCH_REG6: 45
2498 :0,0,45,41
2499 !+ 00000029 CP_SCRATCH_REG7: 41
2500 :0,0,45,41
2501 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
2502 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE }
2503 + 00000002 TP0_CHICKEN: 0x2
2504 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
2505 + 00000020 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
2506 !+ 0124c009 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x124c000 }
2507 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
2508 !+ 00020001 PA_SC_SCREEN_SCISSOR_BR: { X = 1 | Y = 2 }
2509 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
2510 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
2511 !+ 00020001 PA_SC_WINDOW_SCISSOR_BR: { X = 1 | Y = 2 }
2512 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff
2513 + 00000000 VGT_MIN_VTX_INDX: 0
2514 + 00000000 VGT_INDX_OFFSET: 0
2515 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
2516 + 00000000 RB_BLEND_RED: 0
2517 + 00000000 RB_BLEND_GREEN: 0
2518 + 00000000 RB_BLEND_BLUE: 0
2519 + 00000000 RB_BLEND_ALPHA: 0
2520 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
2521 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
2522 + 00000000 RB_ALPHA_REF: 0
2523 !+ 3f000000 PA_CL_VPORT_XSCALE: 0.500000
2524 !+ 3f000000 PA_CL_VPORT_XOFFSET: 0.500000
2525 !+ 3f800000 PA_CL_VPORT_YSCALE: 1.000000
2526 !+ 3f800000 PA_CL_VPORT_YOFFSET: 1.000000
2527 + 00000000 PA_CL_VPORT_ZSCALE: 0.000000
2528 + 00000000 PA_CL_VPORT_ZOFFSET: 0.000000
2529 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
2530 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
2531 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
2532 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
2533 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
2534 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
2535 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
2536 + 00000c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
2537 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
2538 + 00090244 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
2539 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
2540 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
2541 + 88888888 RB_SAMPLE_POS: 0x88888888
2542 + 00000000 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
2543 + 00000000 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
2544 + 00000000 PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
2545 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
2546 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
2547 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
2548 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
2549 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
2550 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000
2551 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000
2552 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
2553 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000
2554 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
2555 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
2556 + 0000ffff PA_SC_AA_MASK: 0xffff
2557 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
2558 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
2559 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
2560 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff
2561 0122e25c: 0000: c0012200 00000000 00040085
2562 t0 write CP_SCRATCH_REG7 (057f)
2563 NEEDS WFI: CP_SCRATCH_REG7 (57f)
2564 CP_SCRATCH_REG7: 42
2565 :0,0,45,42
2566 0122e268: 0000: 0000057f 0000002a
2567 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
2568 0122e270: 0000: c0002600 00000000
2569 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
2570 { EVENT = CACHE_FLUSH }
2571 event CACHE_FLUSH
2572 0122e278: 0000: c0004600 00000006
2573 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
2574 { EVENT = CACHE_FLUSH }
2575 event CACHE_FLUSH
2576 0122e280: 0000: c0004600 00000006
2577 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
2578 { EVENT = CACHE_FLUSH }
2579 event CACHE_FLUSH
2580 0122e288: 0000: c0004600 00000006
2581 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
2582 { EVENT = CACHE_FLUSH }
2583 event CACHE_FLUSH
2584 0122e290: 0000: c0004600 00000006
2585 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
2586 { EVENT = CACHE_FLUSH }
2587 event CACHE_FLUSH
2588 0122e298: 0000: c0004600 00000006
2589 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
2590 { EVENT = CACHE_FLUSH }
2591 event CACHE_FLUSH
2592 0122e2a0: 0000: c0004600 00000006
2593 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
2594 { EVENT = CACHE_FLUSH }
2595 event CACHE_FLUSH
2596 0122e2a8: 0000: c0004600 00000006
2597 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
2598 { EVENT = CACHE_FLUSH }
2599 event CACHE_FLUSH
2600 0122e2b0: 0000: c0004600 00000006
2601 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
2602 { EVENT = CACHE_FLUSH }
2603 event CACHE_FLUSH
2604 0122e2b8: 0000: c0004600 00000006
2605 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
2606 { EVENT = CACHE_FLUSH }
2607 event CACHE_FLUSH
2608 0122e2c0: 0000: c0004600 00000006
2609 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
2610 { EVENT = CACHE_FLUSH }
2611 event CACHE_FLUSH
2612 0122e2c8: 0000: c0004600 00000006
2613 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
2614 { EVENT = CACHE_FLUSH }
2615 event CACHE_FLUSH
2616 0122e2d0: 0000: c0004600 00000006
2617 0122d1d8: 0000: c0013700 0122e000 000000b6
2618 t2 nop
2619 ############################################################
2620 vertices: 0
2621 cmd: deqp-gles2/185: fence=1257
2622 ############################################################
2623 cmdstream: 124 dwords
2624 t0 write RB_BC_CONTROL (0f01)
2625 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
2626 0122f000: 0000: 00000f01 1c004046
2627 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2628 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
2629 0122f008: 0000: c0012d00 00040293 00000020
2630 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2631 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
2632 0122f014: 0000: c0012d00 00040316 00000002
2633 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2634 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
2635 0122f020: 0000: c0012d00 00040317 00000002
2636 t0 write CP_PERFMON_CNTL (0444)
2637 CP_PERFMON_CNTL: 0
2638 0122f02c: 0000: 00000444 00000000
2639 t0 write RBBM_PM_OVERRIDE1 (039c)
2640 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
2641 RBBM_PM_OVERRIDE2: 0xfff
2642 0122f034: 0000: 0001039c ffffffff 00000fff
2643 t0 write TP0_CHICKEN (0e1e)
2644 TP0_CHICKEN: 0x2
2645 0122f040: 0000: 00000e1e 00000002
2646 t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
2647 0122f048: 0000: c0003b00 00007fff
2648 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2649 SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
2650 0122f050: 0000: c0012d00 00040307 00100020
2651 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2652 SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
2653 0122f05c: 0000: c0012d00 00040308 000e0120
2654 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
2655 VGT_MAX_VTX_INDX: 0xffffffff
2656 VGT_MIN_VTX_INDX: 0
2657 0122f068: 0000: c0022d00 00040100 ffffffff 00000000
2658 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2659 VGT_INDX_OFFSET: 0
2660 0122f078: 0000: c0012d00 00040102 00000000
2661 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2662 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
2663 0122f084: 0000: c0012d00 00040181 00000004
2664 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2665 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
2666 0122f090: 0000: c0012d00 00040182 ffffffff
2667 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2668 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
2669 0122f09c: 0000: c0012d00 00040301 00000000
2670 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2671 PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
2672 0122f0a8: 0000: c0012d00 00040300 00000000
2673 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2674 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
2675 0122f0b4: 0000: c0012d00 00040080 00000000
2676 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2677 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
2678 0122f0c0: 0000: c0012d00 00040208 00000004
2679 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2680 RB_SAMPLE_POS: 0x88888888
2681 0122f0cc: 0000: c0012d00 0004020a 88888888
2682 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2683 RB_COLOR_DEST_MASK: 0xffffffff
2684 0122f0d8: 0000: c0012d00 00040326 ffffffff
2685 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2686 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
2687 0122f0e4: 0000: c0012d00 0004031b 0003c000
2688 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
2689 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
2690 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
2691 0122f0f0: 0000: c0022d00 00040183 00000000 00000000
2692 t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
2693 0122f100: 0000: c0004b00 00000000
2694 t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords)
2695 0122f108: 0000: c0035200 000005d0 00000000 5f601000 00000001
2696 t0 write SQ_INST_STORE_MANAGMENT (0d02)
2697 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
2698 0122f11c: 0000: 00000d02 00000180
2699 t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
2700 0122f124: 0000: c0003b00 00000300
2701 t3 opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
2702 0122f12c: 0000: c0004a00 80000180
2703 t3 opcode: CP_SET_CONSTANT (2d) (14 dwords)
2704 0122f13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
2705 0122f15c: 2.000000 0.750000 0.375000 0.250000
2706 0122f134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
2707 0122f154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
2708 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2709 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
2710 0122f16c: 0000: c0012d00 00040104 0000000f
2711 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
2712 RB_BLEND_RED: 0
2713 RB_BLEND_GREEN: 0
2714 RB_BLEND_BLUE: 0
2715 RB_BLEND_ALPHA: 0xff
2716 0122f178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
2717 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2718 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
2719 0122f190: 0000: c0012d00 00040206 0000043f
2720 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2721 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
2722 0122f19c: 0000: c0012d00 00040000 00000020
2723 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2724 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x124e000 }
2725 0122f1a8: 0000: c0012d00 00040001 0124e009
2726 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
2727 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
2728 PA_SC_SCREEN_SCISSOR_BR: { X = 1 | Y = 1 }
2729 0122f1b4: 0000: c0022d00 0004000e 80000000 00010001
2730 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2731 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
2732 0122f1c4: 0000: c0012d00 00040080 00000000
2733 t0 write CP_SCRATCH_REG6 (057e)
2734 CP_SCRATCH_REG6: 51
2735 :0,0,51,42
2736 0122f1d0: 0000: 0000057e 00000033
2737 t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
2738 ibaddr:0122e000
2739 ibsize:000000b6
2740 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
2741 set shader const 0078
2742 0122e000: 0000: c0042d00 00010078 0112d383 00100000 0112d383 00100000
2743 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2744 PA_SC_AA_MASK: 0xffff
2745 0122e018: 0000: c0012d00 00040312 0000ffff
2746 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2747 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
2748 0122e024: 0000: c0012d00 00040200 00000000
2749 t3 opcode: CP_SET_CONSTANT (2d) (5 dwords)
2750 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
2751 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
2752 RB_ALPHA_REF: 0
2753 0122e030: 0000: c0032d00 0004010c 00000000 00000000 00000000
2754 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
2755 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
2756 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
2757 0122e044: 0000: c0022d00 00040204 00000000 00090244
2758 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
2759 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
2760 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
2761 PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
2762 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
2763 0122e054: 0000: c0042d00 00040280 00000000 00000000 00000000 00000000
2764 t3 opcode: CP_SET_CONSTANT (2d) (7 dwords)
2765 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
2766 PA_CL_GB_VERT_CLIP_ADJ: 1.000000
2767 PA_CL_GB_VERT_DISC_ADJ: 1.000000
2768 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
2769 PA_CL_GB_HORZ_DISC_ADJ: 1.000000
2770 0122e06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
2771 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
2772 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
2773 PA_SC_WINDOW_SCISSOR_BR: { X = 1 | Y = 1 }
2774 0122e088: 0000: c0022d00 00040081 00000000 00010001
2775 t3 opcode: CP_SET_CONSTANT (2d) (8 dwords)
2776 PA_CL_VPORT_XSCALE: 0.500000
2777 PA_CL_VPORT_XOFFSET: 0.500000
2778 PA_CL_VPORT_YSCALE: 0.500000
2779 PA_CL_VPORT_YOFFSET: 0.500000
2780 PA_CL_VPORT_ZSCALE: 0.000000
2781 PA_CL_VPORT_ZOFFSET: 0.000000
2782 0122e098: 0000: c0062d00 0004010f 3f000000 3f000000 3f000000 3f000000 00000000 00000000
2783 t3 opcode: CP_SET_CONSTANT (2d) (10 dwords)
2784 0122e0c0: 0.500000 0.500000 0.000000 0.000000 0.500000 0.500000 0.000000 0.000000
2785 0122e0b8: 0000: c0082d00 00000184 3f000000 3f000000 00000000 00000000 3f000000 3f000000
2786 *
2787 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
2788 vertex shader, start=0000, size=0015
2789 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2)
2790 03: 19481000 00262688 00000020 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0)
2791 04: 13480000 40262688 00001020 FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1)
2792 0000 0000 c200 ALLOC POSITION SIZE(0x0)
2793 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1)
2794 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position
2795 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
2796 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1)
2797 06: 000f8000 00000000 c2000000 ALU: MAXv export0 = R0, R0
2798 0000 0000 0000 NOP
2799 0122e0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
2800 0122e100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000
2801 0122e120: 0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000
2802 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
2803 fragment shader, start=0000, size=000c
2804 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1)
2805 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
2806 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
2807 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1)
2808 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor
2809 0000 0000 0000 NOP
2810 0122e140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
2811 0122e160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
2812 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2813 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
2814 0122e17c: 0000: c0012d00 00040181 00000106
2815 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2816 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
2817 0122e188: 0000: c0012d00 00040180 10030002
2818 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
2819 0122e19c: 0.000000 0.000000 0.000000 0.000000
2820 0122e194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000
2821 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2822 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
2823 0122e1ac: 0000: c0012d00 00040202 00000c20
2824 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2825 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
2826 0122e1b8: 0000: c0012d00 00040201 00000000
2827 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2828 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
2829 0122e1c4: 0000: c0012d00 00040104 0000000f
2830 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
2831 RB_BLEND_RED: 0
2832 RB_BLEND_GREEN: 0
2833 RB_BLEND_BLUE: 0
2834 RB_BLEND_ALPHA: 0
2835 0122e1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000
2836 t3 opcode: CP_SET_CONSTANT (2d) (8 dwords)
2837 set texture const 0000
2838 clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel
2839 filter min/mag: point/point
2840 swizzle: xyzw
2841 addr=01254000 (flags=820), size=1x1, pitch=32, format=FMT_1_REVERSE
2842 mipaddr=00000000 (flags=200)
2843 0122e1e8: 0000: c0062d00 00010000 00424800 01254820 00000000 00000d11 00000000 00000200
2844 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
2845 VGT_INDX_OFFSET: 0
2846 0122e208: 0000: c0012d00 00040102 00000000
2847 t0 write TC_CNTL_STATUS (0e00)
2848 TC_CNTL_STATUS: { L2_INVALIDATE }
2849 0122e214: 0000: 00000e00 00000001
2850 t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords)
2851 0122e21c: 0000: c0035200 000005d0 00000000 00001000 00000001
2852 t3 opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
2853 0122e230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
2854 t0 write CP_SCRATCH_REG7 (057f)
2855 CP_SCRATCH_REG7: 47
2856 :0,0,51,47
2857 0122e24c: 0000: 0000057f 0000002f
2858 t3 opcode: CP_NOP (10) (2 dwords)
2859 0122e254: 0000: c0001000 00000000
2860 t3 opcode: CP_DRAW_INDX (22) (3 dwords)
2861 { VIZ_QUERY = 0 }
2862 { PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 }
2863 draw: 0
2864 prim_type: DI_PT_TRIFAN (5)
2865 source_select: DI_SRC_SEL_AUTO_INDEX (2)
2866 num_indices: 1407
2867 draw[7] register values
2868 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
2869 + 00000fff RBBM_PM_OVERRIDE2: 0xfff
2870 + 00000000 CP_PERFMON_CNTL: 0
2871 !+ 00000033 CP_SCRATCH_REG6: 51
2872 :0,0,51,47
2873 !+ 0000002f CP_SCRATCH_REG7: 47
2874 :0,0,51,47
2875 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
2876 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE }
2877 + 00000002 TP0_CHICKEN: 0x2
2878 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
2879 + 00000020 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
2880 !+ 0124e009 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x124e000 }
2881 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
2882 !+ 00010001 PA_SC_SCREEN_SCISSOR_BR: { X = 1 | Y = 1 }
2883 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
2884 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
2885 !+ 00010001 PA_SC_WINDOW_SCISSOR_BR: { X = 1 | Y = 1 }
2886 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff
2887 + 00000000 VGT_MIN_VTX_INDX: 0
2888 + 00000000 VGT_INDX_OFFSET: 0
2889 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
2890 + 00000000 RB_BLEND_RED: 0
2891 + 00000000 RB_BLEND_GREEN: 0
2892 + 00000000 RB_BLEND_BLUE: 0
2893 + 00000000 RB_BLEND_ALPHA: 0
2894 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
2895 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
2896 + 00000000 RB_ALPHA_REF: 0
2897 + 3f000000 PA_CL_VPORT_XSCALE: 0.500000
2898 + 3f000000 PA_CL_VPORT_XOFFSET: 0.500000
2899 !+ 3f000000 PA_CL_VPORT_YSCALE: 0.500000
2900 !+ 3f000000 PA_CL_VPORT_YOFFSET: 0.500000
2901 + 00000000 PA_CL_VPORT_ZSCALE: 0.000000
2902 + 00000000 PA_CL_VPORT_ZOFFSET: 0.000000
2903 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
2904 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
2905 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
2906 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
2907 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
2908 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
2909 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
2910 + 00000c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
2911 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
2912 + 00090244 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
2913 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
2914 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
2915 + 88888888 RB_SAMPLE_POS: 0x88888888
2916 + 00000000 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
2917 + 00000000 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
2918 + 00000000 PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
2919 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
2920 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
2921 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
2922 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
2923 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
2924 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000
2925 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000
2926 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
2927 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000
2928 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
2929 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
2930 + 0000ffff PA_SC_AA_MASK: 0xffff
2931 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
2932 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
2933 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
2934 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff
2935 0122e25c: 0000: c0012200 00000000 00040085
2936 t0 write CP_SCRATCH_REG7 (057f)
2937 NEEDS WFI: CP_SCRATCH_REG7 (57f)
2938 CP_SCRATCH_REG7: 48
2939 :0,0,51,48
2940 0122e268: 0000: 0000057f 00000030
2941 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
2942 0122e270: 0000: c0002600 00000000
2943 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
2944 { EVENT = CACHE_FLUSH }
2945 event CACHE_FLUSH
2946 0122e278: 0000: c0004600 00000006
2947 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
2948 { EVENT = CACHE_FLUSH }
2949 event CACHE_FLUSH
2950 0122e280: 0000: c0004600 00000006
2951 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
2952 { EVENT = CACHE_FLUSH }
2953 event CACHE_FLUSH
2954 0122e288: 0000: c0004600 00000006
2955 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
2956 { EVENT = CACHE_FLUSH }
2957 event CACHE_FLUSH
2958 0122e290: 0000: c0004600 00000006
2959 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
2960 { EVENT = CACHE_FLUSH }
2961 event CACHE_FLUSH
2962 0122e298: 0000: c0004600 00000006
2963 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
2964 { EVENT = CACHE_FLUSH }
2965 event CACHE_FLUSH
2966 0122e2a0: 0000: c0004600 00000006
2967 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
2968 { EVENT = CACHE_FLUSH }
2969 event CACHE_FLUSH
2970 0122e2a8: 0000: c0004600 00000006
2971 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
2972 { EVENT = CACHE_FLUSH }
2973 event CACHE_FLUSH
2974 0122e2b0: 0000: c0004600 00000006
2975 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
2976 { EVENT = CACHE_FLUSH }
2977 event CACHE_FLUSH
2978 0122e2b8: 0000: c0004600 00000006
2979 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
2980 { EVENT = CACHE_FLUSH }
2981 event CACHE_FLUSH
2982 0122e2c0: 0000: c0004600 00000006
2983 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
2984 { EVENT = CACHE_FLUSH }
2985 event CACHE_FLUSH
2986 0122e2c8: 0000: c0004600 00000006
2987 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
2988 { EVENT = CACHE_FLUSH }
2989 event CACHE_FLUSH
2990 0122e2d0: 0000: c0004600 00000006
2991 0122f1d8: 0000: c0013700 0122e000 000000b6
2992 t2 nop
2993 ############################################################
2994 vertices: 0
2995 cmd: deqp-gles2/185: fence=1258
2996 ############################################################
2997 cmdstream: 124 dwords
2998 t0 write RB_BC_CONTROL (0f01)
2999 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
3000 0122d000: 0000: 00000f01 1c004046
3001 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3002 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
3003 0122d008: 0000: c0012d00 00040293 00000020
3004 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3005 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
3006 0122d014: 0000: c0012d00 00040316 00000002
3007 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3008 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
3009 0122d020: 0000: c0012d00 00040317 00000002
3010 t0 write CP_PERFMON_CNTL (0444)
3011 CP_PERFMON_CNTL: 0
3012 0122d02c: 0000: 00000444 00000000
3013 t0 write RBBM_PM_OVERRIDE1 (039c)
3014 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
3015 RBBM_PM_OVERRIDE2: 0xfff
3016 0122d034: 0000: 0001039c ffffffff 00000fff
3017 t0 write TP0_CHICKEN (0e1e)
3018 TP0_CHICKEN: 0x2
3019 0122d040: 0000: 00000e1e 00000002
3020 t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
3021 0122d048: 0000: c0003b00 00007fff
3022 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3023 SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
3024 0122d050: 0000: c0012d00 00040307 00100020
3025 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3026 SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
3027 0122d05c: 0000: c0012d00 00040308 000e0120
3028 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
3029 VGT_MAX_VTX_INDX: 0xffffffff
3030 VGT_MIN_VTX_INDX: 0
3031 0122d068: 0000: c0022d00 00040100 ffffffff 00000000
3032 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3033 VGT_INDX_OFFSET: 0
3034 0122d078: 0000: c0012d00 00040102 00000000
3035 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3036 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
3037 0122d084: 0000: c0012d00 00040181 00000004
3038 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3039 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
3040 0122d090: 0000: c0012d00 00040182 ffffffff
3041 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3042 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
3043 0122d09c: 0000: c0012d00 00040301 00000000
3044 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3045 PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
3046 0122d0a8: 0000: c0012d00 00040300 00000000
3047 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3048 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
3049 0122d0b4: 0000: c0012d00 00040080 00000000
3050 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3051 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
3052 0122d0c0: 0000: c0012d00 00040208 00000004
3053 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3054 RB_SAMPLE_POS: 0x88888888
3055 0122d0cc: 0000: c0012d00 0004020a 88888888
3056 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3057 RB_COLOR_DEST_MASK: 0xffffffff
3058 0122d0d8: 0000: c0012d00 00040326 ffffffff
3059 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3060 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
3061 0122d0e4: 0000: c0012d00 0004031b 0003c000
3062 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
3063 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
3064 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
3065 0122d0f0: 0000: c0022d00 00040183 00000000 00000000
3066 t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
3067 0122d100: 0000: c0004b00 00000000
3068 t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords)
3069 0122d108: 0000: c0035200 000005d0 00000000 5f601000 00000001
3070 t0 write SQ_INST_STORE_MANAGMENT (0d02)
3071 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
3072 0122d11c: 0000: 00000d02 00000180
3073 t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
3074 0122d124: 0000: c0003b00 00000300
3075 t3 opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
3076 0122d12c: 0000: c0004a00 80000180
3077 t3 opcode: CP_SET_CONSTANT (2d) (14 dwords)
3078 0122d13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
3079 0122d15c: 2.000000 0.750000 0.375000 0.250000
3080 0122d134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
3081 0122d154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
3082 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3083 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
3084 0122d16c: 0000: c0012d00 00040104 0000000f
3085 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
3086 RB_BLEND_RED: 0
3087 RB_BLEND_GREEN: 0
3088 RB_BLEND_BLUE: 0
3089 RB_BLEND_ALPHA: 0xff
3090 0122d178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
3091 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3092 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
3093 0122d190: 0000: c0012d00 00040206 0000043f
3094 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3095 RB_SURFACE_INFO: { SURFACE_PITCH = 64 | MSAA_SAMPLES = 0 }
3096 0122d19c: 0000: c0012d00 00040000 00000040
3097 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3098 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1230000 }
3099 0122d1a8: 0000: c0012d00 00040001 01230009
3100 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
3101 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
3102 PA_SC_SCREEN_SCISSOR_BR: { X = 64 | Y = 128 }
3103 0122d1b4: 0000: c0022d00 0004000e 80000000 00800040
3104 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3105 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
3106 0122d1c4: 0000: c0012d00 00040080 00000000
3107 t0 write CP_SCRATCH_REG6 (057e)
3108 CP_SCRATCH_REG6: 57
3109 :0,0,57,48
3110 0122d1d0: 0000: 0000057e 00000039
3111 t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
3112 ibaddr:0122e000
3113 ibsize:000000b6
3114 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
3115 set shader const 0078
3116 0122e000: 0000: c0042d00 00010078 0112d403 00100000 0112d403 00100000
3117 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3118 PA_SC_AA_MASK: 0xffff
3119 0122e018: 0000: c0012d00 00040312 0000ffff
3120 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3121 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
3122 0122e024: 0000: c0012d00 00040200 00000000
3123 t3 opcode: CP_SET_CONSTANT (2d) (5 dwords)
3124 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
3125 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
3126 RB_ALPHA_REF: 0
3127 0122e030: 0000: c0032d00 0004010c 00000000 00000000 00000000
3128 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
3129 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
3130 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
3131 0122e044: 0000: c0022d00 00040204 00000000 00090244
3132 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
3133 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
3134 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
3135 PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
3136 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
3137 0122e054: 0000: c0042d00 00040280 00000000 00000000 00000000 00000000
3138 t3 opcode: CP_SET_CONSTANT (2d) (7 dwords)
3139 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
3140 PA_CL_GB_VERT_CLIP_ADJ: 1.000000
3141 PA_CL_GB_VERT_DISC_ADJ: 1.000000
3142 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
3143 PA_CL_GB_HORZ_DISC_ADJ: 1.000000
3144 0122e06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
3145 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
3146 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
3147 PA_SC_WINDOW_SCISSOR_BR: { X = 64 | Y = 128 }
3148 0122e088: 0000: c0022d00 00040081 00000000 00800040
3149 t3 opcode: CP_SET_CONSTANT (2d) (8 dwords)
3150 PA_CL_VPORT_XSCALE: 32.000000
3151 PA_CL_VPORT_XOFFSET: 32.000000
3152 PA_CL_VPORT_YSCALE: 64.000000
3153 PA_CL_VPORT_YOFFSET: 64.000000
3154 PA_CL_VPORT_ZSCALE: 0.000000
3155 PA_CL_VPORT_ZOFFSET: 0.000000
3156 0122e098: 0000: c0062d00 0004010f 42000000 42000000 42800000 42800000 00000000 00000000
3157 t3 opcode: CP_SET_CONSTANT (2d) (10 dwords)
3158 0122e0c0: 32.000000 64.000000 0.000000 0.000000 32.000000 64.000000 0.000000 0.000000
3159 0122e0b8: 0000: c0082d00 00000184 42000000 42800000 00000000 00000000 42000000 42800000
3160 *
3161 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
3162 vertex shader, start=0000, size=0015
3163 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2)
3164 03: 19481000 00262688 00000020 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0)
3165 04: 13480000 40262688 00001020 FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1)
3166 0000 0000 c200 ALLOC POSITION SIZE(0x0)
3167 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1)
3168 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position
3169 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
3170 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1)
3171 06: 000f8000 00000000 c2000000 ALU: MAXv export0 = R0, R0
3172 0000 0000 0000 NOP
3173 0122e0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
3174 0122e100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000
3175 0122e120: 0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000
3176 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
3177 fragment shader, start=0000, size=000c
3178 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1)
3179 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
3180 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
3181 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1)
3182 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor
3183 0000 0000 0000 NOP
3184 0122e140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
3185 0122e160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
3186 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3187 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
3188 0122e17c: 0000: c0012d00 00040181 00000106
3189 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3190 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
3191 0122e188: 0000: c0012d00 00040180 10030002
3192 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
3193 0122e19c: 0.000000 0.000000 0.000000 0.000000
3194 0122e194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000
3195 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3196 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
3197 0122e1ac: 0000: c0012d00 00040202 00000c20
3198 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3199 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
3200 0122e1b8: 0000: c0012d00 00040201 00000000
3201 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3202 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
3203 0122e1c4: 0000: c0012d00 00040104 0000000f
3204 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
3205 RB_BLEND_RED: 0
3206 RB_BLEND_GREEN: 0
3207 RB_BLEND_BLUE: 0
3208 RB_BLEND_ALPHA: 0
3209 0122e1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000
3210 t3 opcode: CP_SET_CONSTANT (2d) (8 dwords)
3211 set texture const 0000
3212 clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel
3213 filter min/mag: point/point
3214 swizzle: xyzw
3215 addr=0110d000 (flags=820), size=64x128, pitch=16448, format=FMT_1_REVERSE
3216 mipaddr=00000000 (flags=200)
3217 0122e1e8: 0000: c0062d00 00010000 80824800 0110d820 000fe03f 00000d11 00000000 00000200
3218 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3219 VGT_INDX_OFFSET: 0
3220 0122e208: 0000: c0012d00 00040102 00000000
3221 t0 write TC_CNTL_STATUS (0e00)
3222 TC_CNTL_STATUS: { L2_INVALIDATE }
3223 0122e214: 0000: 00000e00 00000001
3224 t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords)
3225 0122e21c: 0000: c0035200 000005d0 00000000 00001000 00000001
3226 t3 opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
3227 0122e230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
3228 t0 write CP_SCRATCH_REG7 (057f)
3229 CP_SCRATCH_REG7: 53
3230 :0,0,57,53
3231 0122e24c: 0000: 0000057f 00000035
3232 t3 opcode: CP_NOP (10) (2 dwords)
3233 0122e254: 0000: c0001000 00000000
3234 t3 opcode: CP_DRAW_INDX (22) (3 dwords)
3235 { VIZ_QUERY = 0 }
3236 { PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 }
3237 draw: 0
3238 prim_type: DI_PT_TRIFAN (5)
3239 source_select: DI_SRC_SEL_AUTO_INDEX (2)
3240 num_indices: 1407
3241 draw[8] register values
3242 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
3243 + 00000fff RBBM_PM_OVERRIDE2: 0xfff
3244 + 00000000 CP_PERFMON_CNTL: 0
3245 !+ 00000039 CP_SCRATCH_REG6: 57
3246 :0,0,57,53
3247 !+ 00000035 CP_SCRATCH_REG7: 53
3248 :0,0,57,53
3249 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
3250 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE }
3251 + 00000002 TP0_CHICKEN: 0x2
3252 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
3253 !+ 00000040 RB_SURFACE_INFO: { SURFACE_PITCH = 64 | MSAA_SAMPLES = 0 }
3254 !+ 01230009 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1230000 }
3255 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
3256 !+ 00800040 PA_SC_SCREEN_SCISSOR_BR: { X = 64 | Y = 128 }
3257 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
3258 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
3259 !+ 00800040 PA_SC_WINDOW_SCISSOR_BR: { X = 64 | Y = 128 }
3260 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff
3261 + 00000000 VGT_MIN_VTX_INDX: 0
3262 + 00000000 VGT_INDX_OFFSET: 0
3263 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
3264 + 00000000 RB_BLEND_RED: 0
3265 + 00000000 RB_BLEND_GREEN: 0
3266 + 00000000 RB_BLEND_BLUE: 0
3267 + 00000000 RB_BLEND_ALPHA: 0
3268 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
3269 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
3270 + 00000000 RB_ALPHA_REF: 0
3271 !+ 42000000 PA_CL_VPORT_XSCALE: 32.000000
3272 !+ 42000000 PA_CL_VPORT_XOFFSET: 32.000000
3273 !+ 42800000 PA_CL_VPORT_YSCALE: 64.000000
3274 !+ 42800000 PA_CL_VPORT_YOFFSET: 64.000000
3275 + 00000000 PA_CL_VPORT_ZSCALE: 0.000000
3276 + 00000000 PA_CL_VPORT_ZOFFSET: 0.000000
3277 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
3278 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
3279 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
3280 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
3281 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
3282 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
3283 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
3284 + 00000c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
3285 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
3286 + 00090244 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
3287 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
3288 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
3289 + 88888888 RB_SAMPLE_POS: 0x88888888
3290 + 00000000 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
3291 + 00000000 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
3292 + 00000000 PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
3293 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
3294 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
3295 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
3296 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
3297 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
3298 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000
3299 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000
3300 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
3301 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000
3302 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
3303 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
3304 + 0000ffff PA_SC_AA_MASK: 0xffff
3305 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
3306 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
3307 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
3308 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff
3309 0122e25c: 0000: c0012200 00000000 00040085
3310 t0 write CP_SCRATCH_REG7 (057f)
3311 NEEDS WFI: CP_SCRATCH_REG7 (57f)
3312 CP_SCRATCH_REG7: 54
3313 :0,0,57,54
3314 0122e268: 0000: 0000057f 00000036
3315 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
3316 0122e270: 0000: c0002600 00000000
3317 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
3318 { EVENT = CACHE_FLUSH }
3319 event CACHE_FLUSH
3320 0122e278: 0000: c0004600 00000006
3321 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
3322 { EVENT = CACHE_FLUSH }
3323 event CACHE_FLUSH
3324 0122e280: 0000: c0004600 00000006
3325 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
3326 { EVENT = CACHE_FLUSH }
3327 event CACHE_FLUSH
3328 0122e288: 0000: c0004600 00000006
3329 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
3330 { EVENT = CACHE_FLUSH }
3331 event CACHE_FLUSH
3332 0122e290: 0000: c0004600 00000006
3333 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
3334 { EVENT = CACHE_FLUSH }
3335 event CACHE_FLUSH
3336 0122e298: 0000: c0004600 00000006
3337 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
3338 { EVENT = CACHE_FLUSH }
3339 event CACHE_FLUSH
3340 0122e2a0: 0000: c0004600 00000006
3341 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
3342 { EVENT = CACHE_FLUSH }
3343 event CACHE_FLUSH
3344 0122e2a8: 0000: c0004600 00000006
3345 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
3346 { EVENT = CACHE_FLUSH }
3347 event CACHE_FLUSH
3348 0122e2b0: 0000: c0004600 00000006
3349 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
3350 { EVENT = CACHE_FLUSH }
3351 event CACHE_FLUSH
3352 0122e2b8: 0000: c0004600 00000006
3353 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
3354 { EVENT = CACHE_FLUSH }
3355 event CACHE_FLUSH
3356 0122e2c0: 0000: c0004600 00000006
3357 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
3358 { EVENT = CACHE_FLUSH }
3359 event CACHE_FLUSH
3360 0122e2c8: 0000: c0004600 00000006
3361 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
3362 { EVENT = CACHE_FLUSH }
3363 event CACHE_FLUSH
3364 0122e2d0: 0000: c0004600 00000006
3365 0122d1d8: 0000: c0013700 0122e000 000000b6
3366 t2 nop
3367 ############################################################
3368 vertices: 0
3369 cmd: deqp-gles2/185: fence=1259
3370 ############################################################
3371 cmdstream: 340 dwords
3372 t0 write RB_BC_CONTROL (0f01)
3373 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
3374 0110a000: 0000: 00000f01 1c004046
3375 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3376 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
3377 0110a008: 0000: c0012d00 00040293 00000020
3378 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3379 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
3380 0110a014: 0000: c0012d00 00040316 00000002
3381 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3382 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
3383 0110a020: 0000: c0012d00 00040317 00000002
3384 t0 write CP_PERFMON_CNTL (0444)
3385 CP_PERFMON_CNTL: 0
3386 0110a02c: 0000: 00000444 00000000
3387 t0 write RBBM_PM_OVERRIDE1 (039c)
3388 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
3389 RBBM_PM_OVERRIDE2: 0xfff
3390 0110a034: 0000: 0001039c ffffffff 00000fff
3391 t0 write TP0_CHICKEN (0e1e)
3392 TP0_CHICKEN: 0x2
3393 0110a040: 0000: 00000e1e 00000002
3394 t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
3395 0110a048: 0000: c0003b00 00007fff
3396 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3397 SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
3398 0110a050: 0000: c0012d00 00040307 00100020
3399 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3400 SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
3401 0110a05c: 0000: c0012d00 00040308 000e0120
3402 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
3403 VGT_MAX_VTX_INDX: 0xffffffff
3404 VGT_MIN_VTX_INDX: 0
3405 0110a068: 0000: c0022d00 00040100 ffffffff 00000000
3406 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3407 VGT_INDX_OFFSET: 0
3408 0110a078: 0000: c0012d00 00040102 00000000
3409 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3410 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
3411 0110a084: 0000: c0012d00 00040181 00000004
3412 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3413 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
3414 0110a090: 0000: c0012d00 00040182 ffffffff
3415 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3416 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
3417 0110a09c: 0000: c0012d00 00040301 00000000
3418 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3419 PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
3420 0110a0a8: 0000: c0012d00 00040300 00000000
3421 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3422 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
3423 0110a0b4: 0000: c0012d00 00040080 00000000
3424 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3425 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
3426 0110a0c0: 0000: c0012d00 00040208 00000004
3427 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3428 RB_SAMPLE_POS: 0x88888888
3429 0110a0cc: 0000: c0012d00 0004020a 88888888
3430 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3431 RB_COLOR_DEST_MASK: 0xffffffff
3432 0110a0d8: 0000: c0012d00 00040326 ffffffff
3433 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3434 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
3435 0110a0e4: 0000: c0012d00 0004031b 0003c000
3436 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
3437 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
3438 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
3439 0110a0f0: 0000: c0022d00 00040183 00000000 00000000
3440 t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
3441 0110a100: 0000: c0004b00 00000000
3442 t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords)
3443 0110a108: 0000: c0035200 000005d0 00000000 5f601000 00000001
3444 t0 write SQ_INST_STORE_MANAGMENT (0d02)
3445 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
3446 0110a11c: 0000: 00000d02 00000180
3447 t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
3448 0110a124: 0000: c0003b00 00000300
3449 t3 opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
3450 0110a12c: 0000: c0004a00 80000180
3451 t3 opcode: CP_SET_CONSTANT (2d) (14 dwords)
3452 0110a13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
3453 0110a15c: 2.000000 0.750000 0.375000 0.250000
3454 0110a134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
3455 0110a154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
3456 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3457 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
3458 0110a16c: 0000: c0012d00 00040104 0000000f
3459 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
3460 RB_BLEND_RED: 0
3461 RB_BLEND_GREEN: 0
3462 RB_BLEND_BLUE: 0
3463 RB_BLEND_ALPHA: 0xff
3464 0110a178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
3465 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3466 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
3467 0110a190: 0000: c0012d00 00040206 0000043f
3468 t3 opcode: CP_SET_CONSTANT (2d) (5 dwords)
3469 RB_SURFACE_INFO: { SURFACE_PITCH = 128 | MSAA_SAMPLES = 0 }
3470 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 }
3471 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_24_8 | DEPTH_BASE = 65536 }
3472 0110a19c: 0000: c0032d00 00040000 00000080 00000205 00010001
3473 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3474 VGT_CURRENT_BIN_ID_MIN: { COLUMN = 0 | ROW = 0 | GUARD_BAND_MASK = 0 }
3475 0110a1b0: 0000: c0012d00 00040207 00000000
3476 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3477 VGT_CURRENT_BIN_ID_MAX: { COLUMN = 0 | ROW = 0 | GUARD_BAND_MASK = 0 }
3478 0110a1bc: 0000: c0012d00 00040203 00000000
3479 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
3480 0110a1d0: 3.069580 0.000000 8441856.000000 8454144.000000
3481 0110a1c8: 0000: c0042d00 0000000c 40447400 00000000 4b00d000 4b010000
3482 t3 opcode: CP_SET_CONSTANT (2d) (10 dwords)
3483 0110a1e8: 0.125490 0.125490 0.500000 0.000000 0.000980 0.000980 0.000000 0.000000
3484 0110a1e0: 0000: c0082d00 0000018c 3e008081 3e008081 3f000000 00000000 3a808081 3a808081
3485 *
3486 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3487 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 0 }
3488 0110a208: 0000: c0012d00 00040316 00000000
3489 t0 write CP_SCRATCH_REG6 (057e)
3490 CP_SCRATCH_REG6: 67
3491 :0,0,67,54
3492 0110a214: 0000: 0000057e 00000043
3493 t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
3494 ibaddr:0110c000
3495 ibsize:000000c5
3496 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
3497 set shader const 0078
3498 0110c000: 0000: c0042d00 00010078 0112d483 00100000 0112d4c3 00100000
3499 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (102 dwords)
3500 vertex shader, start=0000, size=0063
3501 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
3502 100b 0003 1000 EXEC ADDR(0xb) CNT(0x1)
3503 0b: 19480000 00262688 00000010 (S)FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(16) CONST(20, 0)
3504 400c 0002 1000 EXEC ADDR(0xc) CNT(0x4)
3505 0c: 00010001 00036c00 82000000 (S)ALU: MAXv R1.x___ = R0.wyzw, C0.xxxx
3506 0d: 4c110302 0000006c 60400201 ALU: ADDv R2.x___ = C0, R2
3507 RECIP_IEEE R3.x___ = R1.xxxx
3508 0e: 000f0004 00006c00 c1000300 ALU: MULv R4 = R0, R3.xxxx
3509 0f: 000f0005 00000000 4b420441 ALU: MULADDv R5 = C1, C2, R4
3510 0000 0000 c200 ALLOC POSITION SIZE(0x0)
3511 1010 0000 1000 EXEC ADDR(0x10) CNT(0x1)
3512 10: 000f803e 00000000 c2000000 ALU: MAXv export62 = R0, R0 ; gl_Position
3513 0000 0000 c600 ALLOC MEMORY SIZE(0x0)
3514 2011 0000 2000 EXEC_END ADDR(0x11) CNT(0x2)
3515 11: 000f8020 20136c00 4b010203 ALU: MULADDv export32 = C3, C1.wyww, R2.xxxx
3516 12: 000f8021 00000000 4b440543 ALU: MULADDv export33 = C3, C4, R5
3517 0000 0000 c600 ALLOC MEMORY SIZE(0x0)
3518 2013 0000 1000 EXEC ADDR(0x13) CNT(0x2)
3519 13: 000f8020 20136c00 4b010204 ALU: MULADDv export32 = C4, C1.wyww, R2.xxxx
3520 14: 000f8021 00000000 4b460545 ALU: MULADDv export33 = C5, C6, R5
3521 0000 0000 c600 ALLOC MEMORY SIZE(0x0)
3522 2015 0000 1000 EXEC ADDR(0x15) CNT(0x2)
3523 15: 000f8020 20136c00 4b010205 ALU: MULADDv export32 = C5, C1.wyww, R2.xxxx
3524 16: 000f8021 00000000 4b480547 ALU: MULADDv export33 = C7, C8, R5
3525 0000 0000 c600 ALLOC MEMORY SIZE(0x0)
3526 2017 0000 1000 EXEC ADDR(0x17) CNT(0x2)
3527 17: 000f8020 20136c00 4b010206 ALU: MULADDv export32 = C6, C1.wyww, R2.xxxx
3528 18: 000f8021 00000000 4b4a0549 ALU: MULADDv export33 = C9, C10, R5
3529 0000 0000 c600 ALLOC MEMORY SIZE(0x0)
3530 2019 0000 1000 EXEC ADDR(0x19) CNT(0x2)
3531 19: 000f8020 20136c00 4b010207 ALU: MULADDv export32 = C7, C1.wyww, R2.xxxx
3532 1a: 000f8021 00000000 4b4c054b ALU: MULADDv export33 = C11, C12, R5
3533 0000 0000 c600 ALLOC MEMORY SIZE(0x0)
3534 201b 0000 1000 EXEC ADDR(0x1b) CNT(0x2)
3535 1b: 000f8020 20136c00 4b010208 ALU: MULADDv export32 = C8, C1.wyww, R2.xxxx
3536 1c: 000f8021 00000000 4b4e054d ALU: MULADDv export33 = C13, C14, R5
3537 0000 0000 c600 ALLOC MEMORY SIZE(0x0)
3538 201d 0000 1000 EXEC ADDR(0x1d) CNT(0x2)
3539 1d: 000f8020 20136c00 4b010209 ALU: MULADDv export32 = C9, C1.wyww, R2.xxxx
3540 1e: 000f8021 00000000 4b50054f ALU: MULADDv export33 = C15, C16, R5
3541 0000 0000 c600 ALLOC MEMORY SIZE(0x0)
3542 201f 0000 2000 EXEC_END ADDR(0x1f) CNT(0x2)
3543 1f: 000f8020 20136c00 4b01020a ALU: MULADDv export32 = C10, C1.wyww, R2.xxxx
3544 20: 000f8021 00000000 4b520551 ALU: MULADDv export33 = C17, C18, R5
3545 0000 0000 0000 NOP
3546 0110c018: 0000: c0642b00 00000000 00000063 00000000 100bc400 10000003 0002400c 00001000
3547 0110c038: 0020: c2000000 00001010 00001000 c6000000 00002011 00002000 c6000000 00002013
3548 0110c058: 0040: 00001000 c6000000 00002015 00001000 c6000000 00002017 00001000 c6000000
3549 0110c078: 0060: 00002019 00001000 c6000000 0000201b 00001000 c6000000 0000201d 00001000
3550 0110c098: 0080: c6000000 0000201f 00002000 00000000 19480000 00262688 00000010 00010001
3551 0110c0b8: 00a0: 00036c00 82000000 4c110302 0000006c 60400201 000f0004 00006c00 c1000300
3552 0110c0d8: 00c0: 000f0005 00000000 4b420441 000f803e 00000000 c2000000 000f8020 20136c00
3553 0110c0f8: 00e0: 4b010203 000f8021 00000000 4b440543 000f8020 20136c00 4b010204 000f8021
3554 0110c118: 0100: 00000000 4b460545 000f8020 20136c00 4b010205 000f8021 00000000 4b480547
3555 0110c138: 0120: 000f8020 20136c00 4b010206 000f8021 00000000 4b4a0549 000f8020 20136c00
3556 0110c158: 0140: 4b010207 000f8021 00000000 4b4c054b 000f8020 20136c00 4b010208 000f8021
3557 0110c178: 0160: 00000000 4b4e054d 000f8020 20136c00 4b010209 000f8021 00000000 4b50054f
3558 0110c198: 0180: 000f8020 20136c00 4b01020a 000f8021 00000000 4b520551
3559 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3560 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
3561 0110c1b0: 0000: c0012d00 00040181 00000006
3562 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3563 SQ_PROGRAM_CNTL: { VS_REGS = 5 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 | GEN_INDEX_VTX }
3564 0110c1bc: 0000: c0012d00 00040180 90030005
3565 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
3566 0110c1d0: 0.000000 0.000000 0.000000 0.000000
3567 0110c1c8: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000
3568 t3 opcode: CP_SET_CONSTANT (2d) (10 dwords)
3569 0110c1e8: 128.000000 128.000000 0.500000 0.000000 128.000000 -128.000000 0.500000 0.000000
3570 0110c1e0: 0000: c0082d00 00000184 43000000 43000000 3f000000 00000000 43000000 c3000000
3571 0110c200: 0020: 3f000000 00000000
3572 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3573 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
3574 0110c208: 0000: c0012d00 00040201 00000000
3575 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3576 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
3577 0110c214: 0000: c0012d00 00040104 0000000f
3578 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3579 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_POINTS | BACK_PTYPE = PC_DRAW_POINTS | FACE_KILL_ENABLE }
3580 0110c220: 0000: c0012d00 00040205 40000000
3581 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3582 VGT_INDX_OFFSET: 0
3583 0110c22c: 0000: c0012d00 00040102 00000000
3584 t0 write TC_CNTL_STATUS (0e00)
3585 TC_CNTL_STATUS: { L2_INVALIDATE }
3586 0110c238: 0000: 00000e00 00000001
3587 t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords)
3588 0110c240: 0000: c0035200 000005d0 00000000 00001000 00000001
3589 t3 opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
3590 0110c254: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
3591 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
3592 0110c278: 0.000000 0.000000 0.000000 0.000000
3593 0110c270: 0000: c0042d00 00000180 00000000 00000000 00000000 00000000
3594 t0 write CP_SCRATCH_REG7 (057f)
3595 CP_SCRATCH_REG7: 61
3596 :0,0,67,61
3597 0110c288: 0000: 0000057f 0000003d
3598 t3 opcode: CP_DRAW_INDX (22) (5 dwords)
3599 { VIZ_QUERY = 0 }
3600 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x60000 }
3601 { NUM_INDICES = 18011360 }
3602 { INDX_BASE = 0xc }
3603 draw: 0
3604 prim_type: DI_PT_TRILIST (4)
3605 source_select: DI_SRC_SEL_DMA (0)
3606 num_indices: 18011360
3607 draw[9] register values
3608 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
3609 + 00000fff RBBM_PM_OVERRIDE2: 0xfff
3610 + 00000000 CP_PERFMON_CNTL: 0
3611 !+ 00000043 CP_SCRATCH_REG6: 67
3612 :0,0,67,61
3613 !+ 0000003d CP_SCRATCH_REG7: 61
3614 :0,0,67,61
3615 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
3616 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE }
3617 + 00000002 TP0_CHICKEN: 0x2
3618 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
3619 !+ 00000080 RB_SURFACE_INFO: { SURFACE_PITCH = 128 | MSAA_SAMPLES = 0 }
3620 !+ 00000205 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 }
3621 !+ 00010001 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_24_8 | DEPTH_BASE = 65536 }
3622 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
3623 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff
3624 + 00000000 VGT_MIN_VTX_INDX: 0
3625 + 00000000 VGT_INDX_OFFSET: 0
3626 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
3627 + 00000000 RB_BLEND_RED: 0
3628 + 00000000 RB_BLEND_GREEN: 0
3629 + 00000000 RB_BLEND_BLUE: 0
3630 !+ 000000ff RB_BLEND_ALPHA: 0xff
3631 !+ 90030005 SQ_PROGRAM_CNTL: { VS_REGS = 5 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 | GEN_INDEX_VTX }
3632 !+ 00000006 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
3633 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
3634 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
3635 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
3636 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
3637 + 00000000 VGT_CURRENT_BIN_ID_MAX: { COLUMN = 0 | ROW = 0 | GUARD_BAND_MASK = 0 }
3638 !+ 40000000 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_POINTS | BACK_PTYPE = PC_DRAW_POINTS | FACE_KILL_ENABLE }
3639 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
3640 + 00000000 VGT_CURRENT_BIN_ID_MIN: { COLUMN = 0 | ROW = 0 | GUARD_BAND_MASK = 0 }
3641 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
3642 + 88888888 RB_SAMPLE_POS: 0x88888888
3643 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
3644 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
3645 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
3646 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
3647 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
3648 !+ 00000000 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 0 }
3649 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
3650 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
3651 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff
3652 0110c290: 0000: c0032200 00000000 00060004 0112d4e0 0000000c
3653 t0 write CP_SCRATCH_REG7 (057f)
3654 NEEDS WFI: CP_SCRATCH_REG7 (57f)
3655 CP_SCRATCH_REG7: 62
3656 :0,0,67,62
3657 0110c2a4: 0000: 0000057f 0000003e
3658 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
3659 0110c2ac: 0000: c0002600 00000000
3660 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
3661 { EVENT = CACHE_FLUSH }
3662 event CACHE_FLUSH
3663 0110c2b4: 0000: c0004600 00000006
3664 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
3665 { EVENT = CACHE_FLUSH }
3666 event CACHE_FLUSH
3667 0110c2bc: 0000: c0004600 00000006
3668 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
3669 { EVENT = CACHE_FLUSH }
3670 event CACHE_FLUSH
3671 0110c2c4: 0000: c0004600 00000006
3672 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
3673 { EVENT = CACHE_FLUSH }
3674 event CACHE_FLUSH
3675 0110c2cc: 0000: c0004600 00000006
3676 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
3677 { EVENT = CACHE_FLUSH }
3678 event CACHE_FLUSH
3679 0110c2d4: 0000: c0004600 00000006
3680 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
3681 { EVENT = CACHE_FLUSH }
3682 event CACHE_FLUSH
3683 0110c2dc: 0000: c0004600 00000006
3684 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
3685 { EVENT = CACHE_FLUSH }
3686 event CACHE_FLUSH
3687 0110c2e4: 0000: c0004600 00000006
3688 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
3689 { EVENT = CACHE_FLUSH }
3690 event CACHE_FLUSH
3691 0110c2ec: 0000: c0004600 00000006
3692 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
3693 { EVENT = CACHE_FLUSH }
3694 event CACHE_FLUSH
3695 0110c2f4: 0000: c0004600 00000006
3696 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
3697 { EVENT = CACHE_FLUSH }
3698 event CACHE_FLUSH
3699 0110c2fc: 0000: c0004600 00000006
3700 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
3701 { EVENT = CACHE_FLUSH }
3702 event CACHE_FLUSH
3703 0110c304: 0000: c0004600 00000006
3704 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
3705 { EVENT = CACHE_FLUSH }
3706 event CACHE_FLUSH
3707 0110c30c: 0000: c0004600 00000006
3708 0110a21c: 0000: c0013700 0110c000 000000c5
3709 t2 nop
3710 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3711 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
3712 0110a234: 0000: c0012d00 00040316 00000002
3713 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3714 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 }
3715 0110a240: 0000: c0012d00 00040001 00000205
3716 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
3717 PA_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 }
3718 PA_SC_SCREEN_SCISSOR_BR: { X = 128 | Y = 128 }
3719 0110a24c: 0000: c0022d00 0004000e 00000000 00800080
3720 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3721 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 }
3722 0110a25c: 0000: c0012d00 00040001 00000205
3723 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3724 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
3725 0110a268: 0000: c0012d00 00040080 00000000
3726 t3 opcode: CP_MEM_WRITE (3d) (3 dwords)
3727 { ADDR_LO = 0x100903c }
3728 { ADDR_HI = 0x800080 }
3729 gpuaddr:0100903c
3730 0110a27c: 0.000000
3731 0110a274: 0000: c0013d00 0100903c 00800080
3732 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3733 RB_COPY_DEST_OFFSET: { X = 0 | Y = 0 }
3734 0110a280: 0000: c0012d00 0004031c 00000000
3735 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
3736 0110a294: 0.000000 0.000000 0.000000 0.000000
3737 0110a28c: 0000: c0042d00 00000580 00000000 00000000 00000000 00000000
3738 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3739 VGT_CURRENT_BIN_ID_MIN: { COLUMN = 1 | ROW = 1 | GUARD_BAND_MASK = 0 }
3740 0110a2a4: 0000: c0012d00 00040207 00000009
3741 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3742 VGT_CURRENT_BIN_ID_MAX: { COLUMN = 1 | ROW = 1 | GUARD_BAND_MASK = 0 }
3743 0110a2b0: 0000: c0012d00 00040203 00000009
3744 t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
3745 0110a2bc: 0000: c0004b00 0111d000
3746 t0 write CP_SCRATCH_REG6 (057e)
3747 CP_SCRATCH_REG6: 69
3748 :0,0,69,62
3749 0110a2c4: 0000: 0000057e 00000045
3750 t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
3751 ibaddr:0110b000
3752 ibsize:00000198
3753 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
3754 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
3755 PA_SC_WINDOW_SCISSOR_BR: { X = 16383 | Y = 16383 }
3756 0110b000: 0000: c0022d00 00040081 00000000 3fff3fff
3757 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
3758 PA_CL_VPORT_XSCALE: 4096.000000
3759 PA_CL_VPORT_XOFFSET: 4096.000000
3760 PA_CL_VPORT_YSCALE: 4096.000000
3761 PA_CL_VPORT_YOFFSET: 4096.000000
3762 0110b010: 0000: c0042d00 0004010f 45800000 45800000 45800000 45800000
3763 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
3764 set shader const 009c
3765 0110b028: 0000: c0022d00 0001009c 01009003 00000024
3766 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3767 VGT_INDX_OFFSET: 0
3768 0110b038: 0000: c0012d00 00040102 00000000
3769 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
3770 vertex shader, start=0000, size=000c
3771 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
3772 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1)
3773 02: 19a80000 00392a88 0000000c (S)FETCH: VERTEX R0.xyz1 = R0.x FMT_32_32_32_FLOAT UNSIGNED STRIDE(12) CONST(26, 0)
3774 0000 0000 c200 ALLOC POSITION SIZE(0x0)
3775 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1)
3776 03: 000f803e 00000000 c2000000 (S)ALU: MAXv export62 = R0, R0 ; gl_Position
3777 0110b044: 0000: c00d2b00 00000000 0000000c 00000000 1002c400 10000003 00000000 1003c200
3778 0110b064: 0020: 20000002 19a80000 00392a88 0000000c 000f803e 00000000 c2000000
3779 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (9 dwords)
3780 fragment shader, start=0000, size=0006
3781 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
3782 1001 0002 2000 EXEC_END ADDR(0x1) CNT(0x1)
3783 01: 000f8000 00000000 02000000 (S)ALU: MAXv export0 = C0, C0 ; gl_FragColor
3784 0110b080: 0000: c0072b00 00000001 00000006 00000000 1001c400 20000002 000f8000 00000000
3785 0110b0a0: 0020: 02000000
3786 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3787 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
3788 0110b0a4: 0000: c0012d00 00040181 00000006
3789 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3790 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 128 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
3791 0110b0b0: 0000: c0012d00 00040180 10038002
3792 t0 write TC_CNTL_STATUS (0e00)
3793 TC_CNTL_STATUS: { L2_INVALIDATE }
3794 0110b0bc: 0000: 00000e00 00000001
3795 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3796 RB_DEPTHCONTROL: { STENCIL_ENABLE | Z_ENABLE | Z_WRITE_ENABLE | EARLY_Z_ENABLE | ZFUNC = FUNC_ALWAYS | STENCILFUNC = FUNC_ALWAYS | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_REPLACE | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
3797 0110b0c4: 0000: c0012d00 00040200 0000877f
3798 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3799 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_ALWAYS | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
3800 0110b0d0: 0000: c0012d00 00040202 00000c27
3801 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
3802 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
3803 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | MSAA_ENABLE | PROVOKING_VTX_LAST }
3804 0110b0dc: 0000: c0022d00 00040204 00000000 00088240
3805 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3806 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 3 | MAX_SAMPLE_DIST = 0 }
3807 0110b0ec: 0000: c0012d00 00040301 00000003
3808 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3809 PA_SC_AA_MASK: 0xffff
3810 0110b0f8: 0000: c0012d00 00040312 0000ffff
3811 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3812 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
3813 0110b104: 0000: c0012d00 00040104 0000000f
3814 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3815 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
3816 0110b110: 0000: c0012d00 00040201 00000000
3817 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3818 PA_SC_SCREEN_SCISSOR_BR: { X = 32 | Y = 64 }
3819 0110b11c: 0000: c0012d00 0004000f 00400020
3820 t3 opcode: CP_SET_CONSTANT (2d) (5 dwords)
3821 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 2 }
3822 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0 }
3823 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_24_8 | DEPTH_BASE = 32768 }
3824 0110b128: 0000: c0032d00 00040000 00008020 00000005 00008001
3825 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
3826 0110b144: 0.501961 0.250980 0.125490 1.000000
3827 0110b13c: 0000: c0042d00 00000480 3f008081 3e808081 3e008081 3f800000
3828 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
3829 PA_CL_VPORT_ZSCALE: 0.000000
3830 PA_CL_VPORT_ZOFFSET: 0.996586
3831 0110b154: 0000: c0022d00 00040113 00000000 3f7f2041
3832 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
3833 RB_STENCILREFMASK_BF: { STENCILREF = 0x80 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 }
3834 RB_STENCILREFMASK: { STENCILREF = 0x80 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 }
3835 0110b164: 0000: c0022d00 0004010c ffff0080 ffff0080
3836 t0 write CP_SCRATCH_REG7 (057f)
3837 CP_SCRATCH_REG7: 1
3838 :0,0,69,1
3839 0110b174: 0000: 0000057f 00000001
3840 t3 opcode: CP_DRAW_INDX (22) (3 dwords)
3841 { VIZ_QUERY = 0 }
3842 { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x30000 }
3843 draw: 0
3844 prim_type: DI_PT_RECTLIST (8)
3845 source_select: DI_SRC_SEL_AUTO_INDEX (2)
3846 num_indices: 1407
3847 draw[10] register values
3848 !+ 00000045 CP_SCRATCH_REG6: 69
3849 :0,0,69,1
3850 !+ 00000001 CP_SCRATCH_REG7: 1
3851 :0,0,69,1
3852 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE }
3853 !+ 00008020 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 2 }
3854 !+ 00000005 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0 }
3855 !+ 00008001 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_24_8 | DEPTH_BASE = 32768 }
3856 !+ 00000000 PA_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 }
3857 !+ 00400020 PA_SC_SCREEN_SCISSOR_BR: { X = 32 | Y = 64 }
3858 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
3859 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
3860 !+ 3fff3fff PA_SC_WINDOW_SCISSOR_BR: { X = 16383 | Y = 16383 }
3861 + 00000000 VGT_INDX_OFFSET: 0
3862 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
3863 !+ ffff0080 RB_STENCILREFMASK_BF: { STENCILREF = 0x80 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 }
3864 !+ ffff0080 RB_STENCILREFMASK: { STENCILREF = 0x80 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 }
3865 !+ 45800000 PA_CL_VPORT_XSCALE: 4096.000000
3866 !+ 45800000 PA_CL_VPORT_XOFFSET: 4096.000000
3867 !+ 45800000 PA_CL_VPORT_YSCALE: 4096.000000
3868 !+ 45800000 PA_CL_VPORT_YOFFSET: 4096.000000
3869 + 00000000 PA_CL_VPORT_ZSCALE: 0.000000
3870 !+ 3f7f2041 PA_CL_VPORT_ZOFFSET: 0.996586
3871 !+ 10038002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 128 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
3872 + 00000006 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
3873 !+ 0000877f RB_DEPTHCONTROL: { STENCIL_ENABLE | Z_ENABLE | Z_WRITE_ENABLE | EARLY_Z_ENABLE | ZFUNC = FUNC_ALWAYS | STENCILFUNC = FUNC_ALWAYS | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_REPLACE | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
3874 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
3875 !+ 00000c27 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_ALWAYS | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
3876 !+ 00000009 VGT_CURRENT_BIN_ID_MAX: { COLUMN = 1 | ROW = 1 | GUARD_BAND_MASK = 0 }
3877 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
3878 !+ 00088240 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | MSAA_ENABLE | PROVOKING_VTX_LAST }
3879 !+ 00000009 VGT_CURRENT_BIN_ID_MIN: { COLUMN = 1 | ROW = 1 | GUARD_BAND_MASK = 0 }
3880 !+ 00000003 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 3 | MAX_SAMPLE_DIST = 0 }
3881 + 0000ffff PA_SC_AA_MASK: 0xffff
3882 !+ 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
3883 + 00000000 RB_COPY_DEST_OFFSET: { X = 0 | Y = 0 }
3884 0110b17c: 0000: c0012200 00000000 00030088
3885 t0 write CP_SCRATCH_REG7 (057f)
3886 NEEDS WFI: CP_SCRATCH_REG7 (57f)
3887 CP_SCRATCH_REG7: 2
3888 :0,0,69,2
3889 0110b188: 0000: 0000057f 00000002
3890 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3891 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
3892 0110b190: 0000: c0012d00 00040301 00000000
3893 t3 opcode: CP_LOAD_CONSTANT_CONTEXT (2e) (4 dwords)
3894 0110b19c: 0000: c0022e00 01009000 0004000f 00000001
3895 t3 opcode: CP_SET_CONSTANT (2d) (5 dwords)
3896 RB_SURFACE_INFO: { SURFACE_PITCH = 128 | MSAA_SAMPLES = 0 }
3897 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 }
3898 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_24_8 | DEPTH_BASE = 65536 }
3899 0110b1ac: 0000: c0032d00 00040000 00000080 00000205 00010001
3900 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
3901 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
3902 PA_SC_WINDOW_SCISSOR_BR: { X = 16383 | Y = 16383 }
3903 0110b1c0: 0000: c0022d00 00040081 00000000 3fff3fff
3904 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
3905 PA_CL_VPORT_XSCALE: 4096.000000
3906 PA_CL_VPORT_XOFFSET: 4096.000000
3907 PA_CL_VPORT_YSCALE: 4096.000000
3908 PA_CL_VPORT_YOFFSET: 4096.000000
3909 0110b1d0: 0000: c0042d00 0004010f 45800000 45800000 45800000 45800000
3910 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
3911 set shader const 009c
3912 0110b1e8: 0000: c0022d00 0001009c 01009003 00000024
3913 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3914 VGT_INDX_OFFSET: 0
3915 0110b1f8: 0000: c0012d00 00040102 00000000
3916 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
3917 vertex shader, start=0000, size=000c
3918 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
3919 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1)
3920 02: 19a80000 00392a88 0000000c (S)FETCH: VERTEX R0.xyz1 = R0.x FMT_32_32_32_FLOAT UNSIGNED STRIDE(12) CONST(26, 0)
3921 0000 0000 c200 ALLOC POSITION SIZE(0x0)
3922 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1)
3923 03: 000f803e 00000000 c2000000 (S)ALU: MAXv export62 = R0, R0 ; gl_Position
3924 0110b204: 0000: c00d2b00 00000000 0000000c 00000000 1002c400 10000003 00000000 1003c200
3925 0110b224: 0020: 20000002 19a80000 00392a88 0000000c 000f803e 00000000 c2000000
3926 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (9 dwords)
3927 fragment shader, start=0000, size=0006
3928 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
3929 1001 0002 2000 EXEC_END ADDR(0x1) CNT(0x1)
3930 01: 000f8000 00000000 02000000 (S)ALU: MAXv export0 = C0, C0 ; gl_FragColor
3931 0110b240: 0000: c0072b00 00000001 00000006 00000000 1001c400 20000002 000f8000 00000000
3932 0110b260: 0020: 02000000
3933 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3934 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
3935 0110b264: 0000: c0012d00 00040181 00000006
3936 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3937 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 128 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
3938 0110b270: 0000: c0012d00 00040180 10038002
3939 t0 write TC_CNTL_STATUS (0e00)
3940 NEEDS WFI: TC_CNTL_STATUS (e00)
3941 TC_CNTL_STATUS: { L2_INVALIDATE }
3942 0110b27c: 0000: 00000e00 00000001
3943 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3944 RB_DEPTHCONTROL: { STENCIL_ENABLE | Z_ENABLE | Z_WRITE_ENABLE | EARLY_Z_ENABLE | ZFUNC = FUNC_ALWAYS | STENCILFUNC = FUNC_ALWAYS | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_REPLACE | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
3945 0110b284: 0000: c0012d00 00040200 0000877f
3946 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3947 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_ALWAYS | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
3948 0110b290: 0000: c0012d00 00040202 00000c27
3949 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
3950 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
3951 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | MSAA_ENABLE | PROVOKING_VTX_LAST }
3952 0110b29c: 0000: c0022d00 00040204 00000000 00088240
3953 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3954 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 3 | MAX_SAMPLE_DIST = 0 }
3955 0110b2ac: 0000: c0012d00 00040301 00000003
3956 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3957 PA_SC_AA_MASK: 0xffff
3958 0110b2b8: 0000: c0012d00 00040312 0000ffff
3959 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3960 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
3961 0110b2c4: 0000: c0012d00 00040104 0000000f
3962 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3963 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
3964 0110b2d0: 0000: c0012d00 00040201 00000000
3965 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
3966 PA_SC_SCREEN_SCISSOR_BR: { X = 32 | Y = 128 }
3967 0110b2dc: 0000: c0012d00 0004000f 00800020
3968 t3 opcode: CP_SET_CONSTANT (2d) (5 dwords)
3969 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 2 }
3970 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0 }
3971 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_24_8 | DEPTH_BASE = 65536 }
3972 0110b2e8: 0000: c0032d00 00040000 00008020 00000005 00010001
3973 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
3974 0110b304: 0.501961 0.250980 0.125490 1.000000
3975 0110b2fc: 0000: c0042d00 00000480 3f008081 3e808081 3e008081 3f800000
3976 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
3977 PA_CL_VPORT_ZSCALE: 0.000000
3978 PA_CL_VPORT_ZOFFSET: 1.000000
3979 0110b314: 0000: c0022d00 00040113 00000000 3f800000
3980 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
3981 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 }
3982 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 }
3983 0110b324: 0000: c0022d00 0004010c ffff0000 ffff0000
3984 t0 write CP_SCRATCH_REG7 (057f)
3985 NEEDS WFI: CP_SCRATCH_REG7 (57f)
3986 CP_SCRATCH_REG7: 3
3987 :0,0,69,3
3988 0110b334: 0000: 0000057f 00000003
3989 t3 opcode: CP_DRAW_INDX (22) (3 dwords)
3990 { VIZ_QUERY = 0 }
3991 { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x30000 }
3992 draw: 1
3993 prim_type: DI_PT_RECTLIST (8)
3994 source_select: DI_SRC_SEL_AUTO_INDEX (2)
3995 num_indices: 1407
3996 draw[11] register values
3997 !+ 00000003 CP_SCRATCH_REG7: 3
3998 :0,0,69,3
3999 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE }
4000 + 00008020 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 2 }
4001 + 00000005 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0 }
4002 !+ 00010001 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_24_8 | DEPTH_BASE = 65536 }
4003 !+ 00800020 PA_SC_SCREEN_SCISSOR_BR: { X = 32 | Y = 128 }
4004 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
4005 + 3fff3fff PA_SC_WINDOW_SCISSOR_BR: { X = 16383 | Y = 16383 }
4006 + 00000000 VGT_INDX_OFFSET: 0
4007 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
4008 !+ ffff0000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 }
4009 !+ ffff0000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 }
4010 + 45800000 PA_CL_VPORT_XSCALE: 4096.000000
4011 + 45800000 PA_CL_VPORT_XOFFSET: 4096.000000
4012 + 45800000 PA_CL_VPORT_YSCALE: 4096.000000
4013 + 45800000 PA_CL_VPORT_YOFFSET: 4096.000000
4014 + 00000000 PA_CL_VPORT_ZSCALE: 0.000000
4015 !+ 3f800000 PA_CL_VPORT_ZOFFSET: 1.000000
4016 + 10038002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 128 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
4017 + 00000006 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
4018 + 0000877f RB_DEPTHCONTROL: { STENCIL_ENABLE | Z_ENABLE | Z_WRITE_ENABLE | EARLY_Z_ENABLE | ZFUNC = FUNC_ALWAYS | STENCILFUNC = FUNC_ALWAYS | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_REPLACE | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
4019 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
4020 + 00000c27 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_ALWAYS | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
4021 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
4022 + 00088240 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | MSAA_ENABLE | PROVOKING_VTX_LAST }
4023 + 00000003 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 3 | MAX_SAMPLE_DIST = 0 }
4024 + 0000ffff PA_SC_AA_MASK: 0xffff
4025 0110b33c: 0000: c0012200 00000000 00030088
4026 t0 write CP_SCRATCH_REG7 (057f)
4027 NEEDS WFI: CP_SCRATCH_REG7 (57f)
4028 CP_SCRATCH_REG7: 4
4029 :0,0,69,4
4030 0110b348: 0000: 0000057f 00000004
4031 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4032 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
4033 0110b350: 0000: c0012d00 00040301 00000000
4034 t3 opcode: CP_LOAD_CONSTANT_CONTEXT (2e) (4 dwords)
4035 0110b35c: 0000: c0022e00 01009000 0004000f 00000001
4036 t3 opcode: CP_SET_CONSTANT (2d) (5 dwords)
4037 RB_SURFACE_INFO: { SURFACE_PITCH = 128 | MSAA_SAMPLES = 0 }
4038 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 }
4039 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_24_8 | DEPTH_BASE = 65536 }
4040 0110b36c: 0000: c0032d00 00040000 00000080 00000205 00010001
4041 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
4042 set shader const 0078
4043 0110b380: 0000: c0042d00 00010078 0112d483 00100000 0112d4c3 00100000
4044 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4045 PA_SC_AA_MASK: 0xffff
4046 0110b398: 0000: c0012d00 00040312 0000ffff
4047 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4048 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
4049 0110b3a4: 0000: c0012d00 00040200 00000000
4050 t3 opcode: CP_SET_CONSTANT (2d) (5 dwords)
4051 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
4052 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
4053 RB_ALPHA_REF: 0
4054 0110b3b0: 0000: c0032d00 0004010c 00000000 00000000 00000000
4055 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
4056 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
4057 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
4058 0110b3c4: 0000: c0022d00 00040204 00000000 00090240
4059 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
4060 PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 }
4061 PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 }
4062 PA_SU_LINE_CNTL: { WIDTH = 0.500000 }
4063 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
4064 0110b3d4: 0000: c0042d00 00040280 00080008 00080008 00000008 00000000
4065 t3 opcode: CP_SET_CONSTANT (2d) (7 dwords)
4066 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
4067 PA_CL_GB_VERT_CLIP_ADJ: 1.000000
4068 PA_CL_GB_VERT_DISC_ADJ: 1.000000
4069 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
4070 PA_CL_GB_HORZ_DISC_ADJ: 1.000000
4071 0110b3ec: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
4072 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
4073 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
4074 PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 }
4075 0110b408: 0000: c0022d00 00040081 00000000 01000100
4076 t3 opcode: CP_SET_CONSTANT (2d) (8 dwords)
4077 PA_CL_VPORT_XSCALE: 128.000000
4078 PA_CL_VPORT_XOFFSET: 128.000000
4079 PA_CL_VPORT_YSCALE: -128.000000
4080 PA_CL_VPORT_YOFFSET: 128.000000
4081 PA_CL_VPORT_ZSCALE: 0.500000
4082 PA_CL_VPORT_ZOFFSET: 0.500000
4083 0110b418: 0000: c0062d00 0004010f 43000000 43000000 c3000000 43000000 3f000000 3f000000
4084 t3 opcode: CP_SET_CONSTANT (2d) (10 dwords)
4085 0110b440: 128.000000 128.000000 0.500000 0.000000 128.000000 -128.000000 0.500000 0.000000
4086 0110b438: 0000: c0082d00 00000184 43000000 43000000 3f000000 00000000 43000000 c3000000
4087 0110b458: 0020: 3f000000 00000000
4088 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
4089 vertex shader, start=0000, size=0015
4090 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2)
4091 03: 19481000 00262688 00000010 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(16) CONST(20, 0)
4092 04: 13480000 40252fc8 00000008 FETCH: VERTEX R0.xy__ = R0.x FMT_32_32_FLOAT UNSIGNED STRIDE(8) CONST(20, 1)
4093 0000 0000 c200 ALLOC POSITION SIZE(0x0)
4094 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1)
4095 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position
4096 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
4097 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1)
4098 06: 00038000 00000000 c2000000 ALU: MAXv export0.xy__ = R0, R0
4099 0000 0000 0000 NOP
4100 0110b460: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
4101 0110b480: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000010 13480000
4102 0110b4a0: 0040: 40252fc8 00000008 000f803e 00000000 c2010100 00038000 00000000 c2000000
4103 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
4104 fragment shader, start=0000, size=000c
4105 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1)
4106 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
4107 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
4108 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1)
4109 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor
4110 0000 0000 0000 NOP
4111 0110b4c0: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
4112 0110b4e0: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
4113 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4114 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
4115 0110b4fc: 0000: c0012d00 00040181 00000106
4116 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4117 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
4118 0110b508: 0000: c0012d00 00040180 10030002
4119 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
4120 0110b51c: 0.000000 0.000000 0.000000 0.000000
4121 0110b514: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000
4122 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4123 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
4124 0110b52c: 0000: c0012d00 00040202 00001c20
4125 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4126 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
4127 0110b538: 0000: c0012d00 00040201 00000000
4128 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4129 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
4130 0110b544: 0000: c0012d00 00040104 0000000f
4131 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
4132 RB_BLEND_RED: 0
4133 RB_BLEND_GREEN: 0
4134 RB_BLEND_BLUE: 0
4135 RB_BLEND_ALPHA: 0
4136 0110b550: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000
4137 t3 opcode: CP_SET_CONSTANT (2d) (8 dwords)
4138 set texture const 0000
4139 clamp x/y/z: clamp-last-texel/clamp-last-texel/wrap
4140 filter min/mag: point/point
4141 swizzle: xyzw
4142 addr=01230000 (flags=820), size=64x128, pitch=16448, format=FMT_1_REVERSE
4143 mipaddr=01240000 (flags=200)
4144 0110b568: 0000: c0062d00 00010000 80804800 01230820 000fe03f 00000d11 000001c0 01240200
4145 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4146 VGT_INDX_OFFSET: 0
4147 0110b588: 0000: c0012d00 00040102 00000000
4148 t0 write TC_CNTL_STATUS (0e00)
4149 NEEDS WFI: TC_CNTL_STATUS (e00)
4150 TC_CNTL_STATUS: { L2_INVALIDATE }
4151 0110b594: 0000: 00000e00 00000001
4152 t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords)
4153 0110b59c: 0000: c0035200 000005d0 00000000 00001000 00000001
4154 t3 opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
4155 0110b5b0: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
4156 t0 write CP_SCRATCH_REG7 (057f)
4157 NEEDS WFI: CP_SCRATCH_REG7 (57f)
4158 CP_SCRATCH_REG7: 59
4159 :0,0,69,59
4160 0110b5cc: 0000: 0000057f 0000003b
4161 t3 opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
4162 0110b5d4: 0000: c0053400 00000000 0006c004 00000000 00000006 0112d4e0 0000000c
4163 t0 write CP_SCRATCH_REG7 (057f)
4164 NEEDS WFI: CP_SCRATCH_REG7 (57f)
4165 CP_SCRATCH_REG7: 60
4166 :0,0,69,60
4167 0110b5f0: 0000: 0000057f 0000003c
4168 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
4169 0110b5f8: 0000: c0002600 00000000
4170 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
4171 { EVENT = CACHE_FLUSH }
4172 event CACHE_FLUSH
4173 0110b600: 0000: c0004600 00000006
4174 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
4175 { EVENT = CACHE_FLUSH }
4176 event CACHE_FLUSH
4177 0110b608: 0000: c0004600 00000006
4178 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
4179 { EVENT = CACHE_FLUSH }
4180 event CACHE_FLUSH
4181 0110b610: 0000: c0004600 00000006
4182 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
4183 { EVENT = CACHE_FLUSH }
4184 event CACHE_FLUSH
4185 0110b618: 0000: c0004600 00000006
4186 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
4187 { EVENT = CACHE_FLUSH }
4188 event CACHE_FLUSH
4189 0110b620: 0000: c0004600 00000006
4190 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
4191 { EVENT = CACHE_FLUSH }
4192 event CACHE_FLUSH
4193 0110b628: 0000: c0004600 00000006
4194 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
4195 { EVENT = CACHE_FLUSH }
4196 event CACHE_FLUSH
4197 0110b630: 0000: c0004600 00000006
4198 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
4199 { EVENT = CACHE_FLUSH }
4200 event CACHE_FLUSH
4201 0110b638: 0000: c0004600 00000006
4202 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
4203 { EVENT = CACHE_FLUSH }
4204 event CACHE_FLUSH
4205 0110b640: 0000: c0004600 00000006
4206 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
4207 { EVENT = CACHE_FLUSH }
4208 event CACHE_FLUSH
4209 0110b648: 0000: c0004600 00000006
4210 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
4211 { EVENT = CACHE_FLUSH }
4212 event CACHE_FLUSH
4213 0110b650: 0000: c0004600 00000006
4214 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
4215 { EVENT = CACHE_FLUSH }
4216 event CACHE_FLUSH
4217 0110b658: 0000: c0004600 00000006
4218 0110a2cc: 0000: c0013700 0110b000 00000198
4219 t2 nop
4220 t0 write CP_SCRATCH_REG6 (057e)
4221 CP_SCRATCH_REG6: 71
4222 :0,0,71,60
4223 0110a2e4: 0000: 0000057e 00000047
4224 t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
4225 ibaddr:0125e000
4226 ibsize:00000064
4227 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
4228 set shader const 009c
4229 0125e000: 0000: c0022d00 0001009c 01009003 00000024
4230 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4231 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
4232 0125e010: 0000: c0012d00 00040080 00000000
4233 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4234 VGT_INDX_OFFSET: 0
4235 0125e01c: 0000: c0012d00 00040102 00000000
4236 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
4237 vertex shader, start=0000, size=000c
4238 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
4239 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1)
4240 02: 19a80000 00392a88 0000000c (S)FETCH: VERTEX R0.xyz1 = R0.x FMT_32_32_32_FLOAT UNSIGNED STRIDE(12) CONST(26, 0)
4241 0000 0000 c200 ALLOC POSITION SIZE(0x0)
4242 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1)
4243 03: 000f803e 00000000 c2000000 (S)ALU: MAXv export62 = R0, R0 ; gl_Position
4244 0125e028: 0000: c00d2b00 00000000 0000000c 00000000 1002c400 10000003 00000000 1003c200
4245 0125e048: 0020: 20000002 19a80000 00392a88 0000000c 000f803e 00000000 c2000000
4246 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (9 dwords)
4247 fragment shader, start=0000, size=0006
4248 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
4249 1001 0002 2000 EXEC_END ADDR(0x1) CNT(0x1)
4250 01: 000f8000 00000000 02000000 (S)ALU: MAXv export0 = C0, C0 ; gl_FragColor
4251 0125e064: 0000: c0072b00 00000001 00000006 00000000 1001c400 20000002 000f8000 00000000
4252 0125e084: 0020: 02000000
4253 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4254 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
4255 0125e088: 0000: c0012d00 00040181 00000006
4256 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4257 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 128 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
4258 0125e094: 0000: c0012d00 00040180 10038002
4259 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4260 PA_SC_AA_MASK: 0xffff
4261 0125e0a0: 0000: c0012d00 00040312 0000ffff
4262 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4263 RB_DEPTHCONTROL: { EARLY_Z_ENABLE | ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
4264 0125e0ac: 0000: c0012d00 00040200 00000008
4265 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4266 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | PROVOKING_VTX_LAST }
4267 0125e0b8: 0000: c0012d00 00040205 00080240
4268 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
4269 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
4270 PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 }
4271 0125e0c4: 0000: c0022d00 00040081 00000000 01000100
4272 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4273 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
4274 0125e0d4: 0000: c0012d00 00040204 00000000
4275 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
4276 PA_CL_VPORT_XSCALE: 64.000000
4277 PA_CL_VPORT_XOFFSET: 64.000000
4278 PA_CL_VPORT_YSCALE: 64.000000
4279 PA_CL_VPORT_YOFFSET: 64.000000
4280 0125e0e0: 0000: c0042d00 0004010f 42800000 42800000 42800000 42800000
4281 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4282 RB_MODECONTROL: { EDRAM_MODE = EDRAM_COPY }
4283 0125e0f8: 0000: c0012d00 00040208 00000006
4284 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4285 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x10000 }
4286 0125e104: 0000: c0012d00 00040001 00010005
4287 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
4288 RB_COPY_CONTROL: { COPY_SAMPLE_SELECT = SAMPLE_0 | CLEAR_MASK = 0 }
4289 RB_COPY_DEST_BASE: 0x10ca000
4290 RB_COPY_DEST_PITCH: 256
4291 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | LINEAR | FORMAT = COLORX_8_8_8_8 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
4292 0125e110: 0000: c0042d00 00040318 00000000 010ca000 00000008 0003c058
4293 t0 write CP_SCRATCH_REG7 (057f)
4294 CP_SCRATCH_REG7: 63
4295 :0,0,71,63
4296 0125e128: 0000: 0000057f 0000003f
4297 t3 opcode: CP_DRAW_INDX (22) (3 dwords)
4298 { VIZ_QUERY = 0 }
4299 { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x30000 }
4300 draw: 0
4301 prim_type: DI_PT_RECTLIST (8)
4302 source_select: DI_SRC_SEL_AUTO_INDEX (2)
4303 num_indices: 1407
4304 draw[12] register values
4305 !+ 00000047 CP_SCRATCH_REG6: 71
4306 :0,0,71,63
4307 !+ 0000003f CP_SCRATCH_REG7: 63
4308 :0,0,71,63
4309 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE }
4310 !+ 00000080 RB_SURFACE_INFO: { SURFACE_PITCH = 128 | MSAA_SAMPLES = 0 }
4311 !+ 00010005 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x10000 }
4312 + 00010001 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_24_8 | DEPTH_BASE = 65536 }
4313 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
4314 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
4315 !+ 01000100 PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 }
4316 + 00000000 VGT_INDX_OFFSET: 0
4317 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
4318 + 00000000 RB_BLEND_RED: 0
4319 + 00000000 RB_BLEND_GREEN: 0
4320 + 00000000 RB_BLEND_BLUE: 0
4321 !+ 00000000 RB_BLEND_ALPHA: 0
4322 !+ 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
4323 !+ 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
4324 + 00000000 RB_ALPHA_REF: 0
4325 !+ 42800000 PA_CL_VPORT_XSCALE: 64.000000
4326 !+ 42800000 PA_CL_VPORT_XOFFSET: 64.000000
4327 !+ 42800000 PA_CL_VPORT_YSCALE: 64.000000
4328 !+ 42800000 PA_CL_VPORT_YOFFSET: 64.000000
4329 !+ 3f000000 PA_CL_VPORT_ZSCALE: 0.500000
4330 !+ 3f000000 PA_CL_VPORT_ZOFFSET: 0.500000
4331 + 10038002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 128 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
4332 + 00000006 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
4333 !+ 00000008 RB_DEPTHCONTROL: { EARLY_Z_ENABLE | ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
4334 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
4335 !+ 00001c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
4336 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
4337 !+ 00080240 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | PROVOKING_VTX_LAST }
4338 !+ 00000006 RB_MODECONTROL: { EDRAM_MODE = EDRAM_COPY }
4339 !+ 00080008 PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 }
4340 !+ 00080008 PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 }
4341 !+ 00000008 PA_SU_LINE_CNTL: { WIDTH = 0.500000 }
4342 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
4343 !+ 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
4344 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
4345 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000
4346 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000
4347 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
4348 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000
4349 + 0000ffff PA_SC_AA_MASK: 0xffff
4350 + 00000000 RB_COPY_CONTROL: { COPY_SAMPLE_SELECT = SAMPLE_0 | CLEAR_MASK = 0 }
4351 !+ 010ca000 RB_COPY_DEST_BASE: 0x10ca000
4352 !+ 00000008 RB_COPY_DEST_PITCH: 256
4353 !+ 0003c058 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | LINEAR | FORMAT = COLORX_8_8_8_8 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
4354 0125e130: 0000: c0012200 00000000 00030088
4355 t0 write CP_SCRATCH_REG7 (057f)
4356 NEEDS WFI: CP_SCRATCH_REG7 (57f)
4357 CP_SCRATCH_REG7: 64
4358 :0,0,71,64
4359 0125e13c: 0000: 0000057f 00000040
4360 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4361 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0 }
4362 0125e144: 0000: c0012d00 00040001 00000005
4363 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
4364 RB_COPY_CONTROL: { COPY_SAMPLE_SELECT = SAMPLE_0 | CLEAR_MASK = 0 }
4365 RB_COPY_DEST_BASE: 0x108a000
4366 RB_COPY_DEST_PITCH: 256
4367 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_8_8_8_8 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
4368 0125e150: 0000: c0042d00 00040318 00000000 0108a000 00000008 0003c050
4369 t0 write CP_SCRATCH_REG7 (057f)
4370 NEEDS WFI: CP_SCRATCH_REG7 (57f)
4371 CP_SCRATCH_REG7: 65
4372 :0,0,71,65
4373 0125e168: 0000: 0000057f 00000041
4374 t3 opcode: CP_DRAW_INDX (22) (3 dwords)
4375 { VIZ_QUERY = 0 }
4376 { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x30000 }
4377 draw: 1
4378 prim_type: DI_PT_RECTLIST (8)
4379 source_select: DI_SRC_SEL_AUTO_INDEX (2)
4380 num_indices: 1407
4381 draw[13] register values
4382 !+ 00000041 CP_SCRATCH_REG7: 65
4383 :0,0,71,65
4384 !+ 00000005 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0 }
4385 + 00000000 RB_COPY_CONTROL: { COPY_SAMPLE_SELECT = SAMPLE_0 | CLEAR_MASK = 0 }
4386 !+ 0108a000 RB_COPY_DEST_BASE: 0x108a000
4387 + 00000008 RB_COPY_DEST_PITCH: 256
4388 !+ 0003c050 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_8_8_8_8 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
4389 0125e170: 0000: c0012200 00000000 00030088
4390 t0 write CP_SCRATCH_REG7 (057f)
4391 NEEDS WFI: CP_SCRATCH_REG7 (57f)
4392 CP_SCRATCH_REG7: 66
4393 :0,0,71,66
4394 0125e17c: 0000: 0000057f 00000042
4395 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4396 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
4397 0125e184: 0000: c0012d00 00040208 00000004
4398 0110a2ec: 0000: c0013700 0125e000 00000064
4399 t2 nop
4400 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4401 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 }
4402 0110a304: 0000: c0012d00 00040001 00000205
4403 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
4404 PA_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 }
4405 PA_SC_SCREEN_SCISSOR_BR: { X = 128 | Y = 128 }
4406 0110a310: 0000: c0022d00 0004000e 00000000 00800080
4407 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4408 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 }
4409 0110a320: 0000: c0012d00 00040001 00000205
4410 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4411 PA_SC_WINDOW_OFFSET: { X = -128 | Y = 0 }
4412 0110a32c: 0000: c0012d00 00040080 00007f80
4413 t3 opcode: CP_MEM_WRITE (3d) (3 dwords)
4414 { ADDR_LO = 0x100903c }
4415 { ADDR_HI = 0x800080 }
4416 gpuaddr:0100903c
4417 0110a340: 0.000000
4418 0110a338: 0000: c0013d00 0100903c 00800080
4419 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4420 RB_COPY_DEST_OFFSET: { X = 128 | Y = 0 }
4421 0110a344: 0000: c0012d00 0004031c 00000080
4422 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
4423 0110a358: 128.000000 0.000000 0.000000 0.000000
4424 0110a350: 0000: c0042d00 00000580 43000000 00000000 00000000 00000000
4425 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4426 VGT_CURRENT_BIN_ID_MIN: { COLUMN = 2 | ROW = 1 | GUARD_BAND_MASK = 0 }
4427 0110a368: 0000: c0012d00 00040207 0000000a
4428 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4429 VGT_CURRENT_BIN_ID_MAX: { COLUMN = 2 | ROW = 1 | GUARD_BAND_MASK = 0 }
4430 0110a374: 0000: c0012d00 00040203 0000000a
4431 t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
4432 0110a380: 0000: c0004b00 0111d000
4433 t0 write CP_SCRATCH_REG6 (057e)
4434 NEEDS WFI: CP_SCRATCH_REG6 (57e)
4435 CP_SCRATCH_REG6: 73
4436 :0,0,73,66
4437 0110a388: 0000: 0000057e 00000049
4438 t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
4439 ibaddr:0110b000
4440 ibsize:00000198
4441 0110a390: 0000: c0013700 0110b000 00000198
4442 t2 nop
4443 t0 write CP_SCRATCH_REG6 (057e)
4444 NEEDS WFI: CP_SCRATCH_REG6 (57e)
4445 CP_SCRATCH_REG6: 75
4446 :0,0,75,66
4447 0110a3a8: 0000: 0000057e 0000004b
4448 t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
4449 ibaddr:0125e000
4450 ibsize:00000064
4451 0110a3b0: 0000: c0013700 0125e000 00000064
4452 t2 nop
4453 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4454 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 }
4455 0110a3c8: 0000: c0012d00 00040001 00000205
4456 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
4457 PA_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 }
4458 PA_SC_SCREEN_SCISSOR_BR: { X = 128 | Y = 128 }
4459 0110a3d4: 0000: c0022d00 0004000e 00000000 00800080
4460 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4461 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 }
4462 0110a3e4: 0000: c0012d00 00040001 00000205
4463 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4464 PA_SC_WINDOW_OFFSET: { X = 0 | Y = -128 }
4465 0110a3f0: 0000: c0012d00 00040080 7f800000
4466 t3 opcode: CP_MEM_WRITE (3d) (3 dwords)
4467 { ADDR_LO = 0x100903c }
4468 { ADDR_HI = 0x800080 }
4469 gpuaddr:0100903c
4470 0110a404: 0.000000
4471 0110a3fc: 0000: c0013d00 0100903c 00800080
4472 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4473 RB_COPY_DEST_OFFSET: { X = 0 | Y = 128 }
4474 0110a408: 0000: c0012d00 0004031c 00100000
4475 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
4476 0110a41c: 0.000000 128.000000 0.000000 0.000000
4477 0110a414: 0000: c0042d00 00000580 00000000 43000000 00000000 00000000
4478 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4479 VGT_CURRENT_BIN_ID_MIN: { COLUMN = 1 | ROW = 2 | GUARD_BAND_MASK = 0 }
4480 0110a42c: 0000: c0012d00 00040207 00000011
4481 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4482 VGT_CURRENT_BIN_ID_MAX: { COLUMN = 1 | ROW = 2 | GUARD_BAND_MASK = 0 }
4483 0110a438: 0000: c0012d00 00040203 00000011
4484 t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
4485 0110a444: 0000: c0004b00 0111d000
4486 t0 write CP_SCRATCH_REG6 (057e)
4487 NEEDS WFI: CP_SCRATCH_REG6 (57e)
4488 CP_SCRATCH_REG6: 77
4489 :0,0,77,66
4490 0110a44c: 0000: 0000057e 0000004d
4491 t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
4492 ibaddr:0110b000
4493 ibsize:00000198
4494 0110a454: 0000: c0013700 0110b000 00000198
4495 t2 nop
4496 t0 write CP_SCRATCH_REG6 (057e)
4497 NEEDS WFI: CP_SCRATCH_REG6 (57e)
4498 CP_SCRATCH_REG6: 79
4499 :0,0,79,66
4500 0110a46c: 0000: 0000057e 0000004f
4501 t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
4502 ibaddr:0125e000
4503 ibsize:00000064
4504 0110a474: 0000: c0013700 0125e000 00000064
4505 t2 nop
4506 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4507 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 }
4508 0110a48c: 0000: c0012d00 00040001 00000205
4509 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
4510 PA_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 }
4511 PA_SC_SCREEN_SCISSOR_BR: { X = 128 | Y = 128 }
4512 0110a498: 0000: c0022d00 0004000e 00000000 00800080
4513 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4514 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 }
4515 0110a4a8: 0000: c0012d00 00040001 00000205
4516 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4517 PA_SC_WINDOW_OFFSET: { X = -128 | Y = -128 }
4518 0110a4b4: 0000: c0012d00 00040080 7f807f80
4519 t3 opcode: CP_MEM_WRITE (3d) (3 dwords)
4520 { ADDR_LO = 0x100903c }
4521 { ADDR_HI = 0x800080 }
4522 gpuaddr:0100903c
4523 0110a4c8: 0.000000
4524 0110a4c0: 0000: c0013d00 0100903c 00800080
4525 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4526 RB_COPY_DEST_OFFSET: { X = 128 | Y = 128 }
4527 0110a4cc: 0000: c0012d00 0004031c 00100080
4528 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
4529 0110a4e0: 128.000000 128.000000 0.000000 0.000000
4530 0110a4d8: 0000: c0042d00 00000580 43000000 43000000 00000000 00000000
4531 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4532 VGT_CURRENT_BIN_ID_MIN: { COLUMN = 2 | ROW = 2 | GUARD_BAND_MASK = 0 }
4533 0110a4f0: 0000: c0012d00 00040207 00000012
4534 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4535 VGT_CURRENT_BIN_ID_MAX: { COLUMN = 2 | ROW = 2 | GUARD_BAND_MASK = 0 }
4536 0110a4fc: 0000: c0012d00 00040203 00000012
4537 t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
4538 0110a508: 0000: c0004b00 0111d000
4539 t0 write CP_SCRATCH_REG6 (057e)
4540 NEEDS WFI: CP_SCRATCH_REG6 (57e)
4541 CP_SCRATCH_REG6: 81
4542 :0,0,81,66
4543 0110a510: 0000: 0000057e 00000051
4544 t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
4545 ibaddr:0110b000
4546 ibsize:00000198
4547 0110a518: 0000: c0013700 0110b000 00000198
4548 t2 nop
4549 t0 write CP_SCRATCH_REG6 (057e)
4550 NEEDS WFI: CP_SCRATCH_REG6 (57e)
4551 CP_SCRATCH_REG6: 83
4552 :0,0,83,66
4553 0110a530: 0000: 0000057e 00000053
4554 t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
4555 ibaddr:0125e000
4556 ibsize:00000064
4557 0110a538: 0000: c0013700 0125e000 00000064
4558 t2 nop
4559 ############################################################
4560 vertices: 0
4561 cmd: deqp-gles2/185: fence=1260
4562 ############################################################
4563 cmdstream: 124 dwords
4564 t0 write RB_BC_CONTROL (0f01)
4565 NEEDS WFI: RB_BC_CONTROL (f01)
4566 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
4567 0122f000: 0000: 00000f01 1c004046
4568 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4569 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
4570 0122f008: 0000: c0012d00 00040293 00000020
4571 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4572 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
4573 0122f014: 0000: c0012d00 00040316 00000002
4574 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4575 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
4576 0122f020: 0000: c0012d00 00040317 00000002
4577 t0 write CP_PERFMON_CNTL (0444)
4578 NEEDS WFI: CP_PERFMON_CNTL (444)
4579 CP_PERFMON_CNTL: 0
4580 0122f02c: 0000: 00000444 00000000
4581 t0 write RBBM_PM_OVERRIDE1 (039c)
4582 NEEDS WFI: RBBM_PM_OVERRIDE1 (39c)
4583 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
4584 NEEDS WFI: RBBM_PM_OVERRIDE2 (39d)
4585 RBBM_PM_OVERRIDE2: 0xfff
4586 0122f034: 0000: 0001039c ffffffff 00000fff
4587 t0 write TP0_CHICKEN (0e1e)
4588 NEEDS WFI: TP0_CHICKEN (e1e)
4589 TP0_CHICKEN: 0x2
4590 0122f040: 0000: 00000e1e 00000002
4591 t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
4592 0122f048: 0000: c0003b00 00007fff
4593 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4594 SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
4595 0122f050: 0000: c0012d00 00040307 00100020
4596 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4597 SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
4598 0122f05c: 0000: c0012d00 00040308 000e0120
4599 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
4600 VGT_MAX_VTX_INDX: 0xffffffff
4601 VGT_MIN_VTX_INDX: 0
4602 0122f068: 0000: c0022d00 00040100 ffffffff 00000000
4603 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4604 VGT_INDX_OFFSET: 0
4605 0122f078: 0000: c0012d00 00040102 00000000
4606 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4607 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
4608 0122f084: 0000: c0012d00 00040181 00000004
4609 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4610 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
4611 0122f090: 0000: c0012d00 00040182 ffffffff
4612 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4613 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
4614 0122f09c: 0000: c0012d00 00040301 00000000
4615 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4616 PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
4617 0122f0a8: 0000: c0012d00 00040300 00000000
4618 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4619 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
4620 0122f0b4: 0000: c0012d00 00040080 00000000
4621 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4622 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
4623 0122f0c0: 0000: c0012d00 00040208 00000004
4624 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4625 RB_SAMPLE_POS: 0x88888888
4626 0122f0cc: 0000: c0012d00 0004020a 88888888
4627 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4628 RB_COLOR_DEST_MASK: 0xffffffff
4629 0122f0d8: 0000: c0012d00 00040326 ffffffff
4630 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4631 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
4632 0122f0e4: 0000: c0012d00 0004031b 0003c000
4633 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
4634 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
4635 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
4636 0122f0f0: 0000: c0022d00 00040183 00000000 00000000
4637 t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
4638 0122f100: 0000: c0004b00 00000000
4639 t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords)
4640 0122f108: 0000: c0035200 000005d0 00000000 5f601000 00000001
4641 t0 write SQ_INST_STORE_MANAGMENT (0d02)
4642 NEEDS WFI: SQ_INST_STORE_MANAGMENT (d02)
4643 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
4644 0122f11c: 0000: 00000d02 00000180
4645 t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
4646 0122f124: 0000: c0003b00 00000300
4647 t3 opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
4648 0122f12c: 0000: c0004a00 80000180
4649 t3 opcode: CP_SET_CONSTANT (2d) (14 dwords)
4650 0122f13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
4651 0122f15c: 2.000000 0.750000 0.375000 0.250000
4652 0122f134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
4653 0122f154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
4654 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4655 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
4656 0122f16c: 0000: c0012d00 00040104 0000000f
4657 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
4658 RB_BLEND_RED: 0
4659 RB_BLEND_GREEN: 0
4660 RB_BLEND_BLUE: 0
4661 RB_BLEND_ALPHA: 0xff
4662 0122f178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
4663 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4664 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
4665 0122f190: 0000: c0012d00 00040206 0000043f
4666 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4667 RB_SURFACE_INFO: { SURFACE_PITCH = 64 | MSAA_SAMPLES = 0 }
4668 0122f19c: 0000: c0012d00 00040000 00000040
4669 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4670 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1256000 }
4671 0122f1a8: 0000: c0012d00 00040001 01256245
4672 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
4673 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
4674 PA_SC_SCREEN_SCISSOR_BR: { X = 64 | Y = 128 }
4675 0122f1b4: 0000: c0022d00 0004000e 80000000 00800040
4676 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4677 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
4678 0122f1c4: 0000: c0012d00 00040080 00000000
4679 t0 write CP_SCRATCH_REG6 (057e)
4680 NEEDS WFI: CP_SCRATCH_REG6 (57e)
4681 CP_SCRATCH_REG6: 89
4682 :0,0,89,66
4683 0122f1d0: 0000: 0000057e 00000059
4684 t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
4685 ibaddr:0122e000
4686 ibsize:000000b6
4687 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
4688 set shader const 0078
4689 0122e000: 0000: c0042d00 00010078 0112d4ef 00100000 0112d4ef 00100000
4690 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4691 PA_SC_AA_MASK: 0xffff
4692 0122e018: 0000: c0012d00 00040312 0000ffff
4693 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4694 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
4695 0122e024: 0000: c0012d00 00040200 00000000
4696 t3 opcode: CP_SET_CONSTANT (2d) (5 dwords)
4697 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
4698 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
4699 RB_ALPHA_REF: 0
4700 0122e030: 0000: c0032d00 0004010c 00000000 00000000 00000000
4701 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
4702 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
4703 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
4704 0122e044: 0000: c0022d00 00040204 00000000 00090244
4705 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
4706 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
4707 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
4708 PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
4709 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
4710 0122e054: 0000: c0042d00 00040280 00000000 00000000 00000000 00000000
4711 t3 opcode: CP_SET_CONSTANT (2d) (7 dwords)
4712 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
4713 PA_CL_GB_VERT_CLIP_ADJ: 1.000000
4714 PA_CL_GB_VERT_DISC_ADJ: 1.000000
4715 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
4716 PA_CL_GB_HORZ_DISC_ADJ: 1.000000
4717 0122e06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
4718 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
4719 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
4720 PA_SC_WINDOW_SCISSOR_BR: { X = 64 | Y = 128 }
4721 0122e088: 0000: c0022d00 00040081 00000000 00800040
4722 t3 opcode: CP_SET_CONSTANT (2d) (8 dwords)
4723 PA_CL_VPORT_XSCALE: 32.000000
4724 PA_CL_VPORT_XOFFSET: 32.000000
4725 PA_CL_VPORT_YSCALE: 64.000000
4726 PA_CL_VPORT_YOFFSET: 64.000000
4727 PA_CL_VPORT_ZSCALE: 0.000000
4728 PA_CL_VPORT_ZOFFSET: 0.000000
4729 0122e098: 0000: c0062d00 0004010f 42000000 42000000 42800000 42800000 00000000 00000000
4730 t3 opcode: CP_SET_CONSTANT (2d) (10 dwords)
4731 0122e0c0: 32.000000 64.000000 0.000000 0.000000 32.000000 64.000000 0.000000 0.000000
4732 0122e0b8: 0000: c0082d00 00000184 42000000 42800000 00000000 00000000 42000000 42800000
4733 *
4734 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
4735 vertex shader, start=0000, size=0015
4736 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2)
4737 03: 19481000 00262688 00000020 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0)
4738 04: 13480000 40262688 00001020 FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1)
4739 0000 0000 c200 ALLOC POSITION SIZE(0x0)
4740 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1)
4741 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position
4742 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
4743 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1)
4744 06: 000f8000 00000000 c2000000 ALU: MAXv export0 = R0, R0
4745 0000 0000 0000 NOP
4746 0122e0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
4747 0122e100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000
4748 0122e120: 0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000
4749 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
4750 fragment shader, start=0000, size=000c
4751 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1)
4752 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
4753 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
4754 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1)
4755 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor
4756 0000 0000 0000 NOP
4757 0122e140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
4758 0122e160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
4759 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4760 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
4761 0122e17c: 0000: c0012d00 00040181 00000106
4762 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4763 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
4764 0122e188: 0000: c0012d00 00040180 10030002
4765 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
4766 0122e19c: 0.000000 0.000000 0.000000 0.000000
4767 0122e194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000
4768 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4769 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
4770 0122e1ac: 0000: c0012d00 00040202 00000c20
4771 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4772 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
4773 0122e1b8: 0000: c0012d00 00040201 00000000
4774 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4775 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
4776 0122e1c4: 0000: c0012d00 00040104 0000000f
4777 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
4778 RB_BLEND_RED: 0
4779 RB_BLEND_GREEN: 0
4780 RB_BLEND_BLUE: 0
4781 RB_BLEND_ALPHA: 0
4782 0122e1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000
4783 t3 opcode: CP_SET_CONSTANT (2d) (8 dwords)
4784 set texture const 0000
4785 clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel
4786 filter min/mag: point/point
4787 swizzle: zyxw
4788 addr=0108a000 (flags=806), size=256x256, pitch=16640, format=FMT_8_8_8_8
4789 mipaddr=00000000 (flags=200)
4790 0122e1e8: 0000: c0062d00 00010000 82024800 0108a806 001fe0ff 00000c14 00000000 00000200
4791 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4792 VGT_INDX_OFFSET: 0
4793 0122e208: 0000: c0012d00 00040102 00000000
4794 t0 write TC_CNTL_STATUS (0e00)
4795 NEEDS WFI: TC_CNTL_STATUS (e00)
4796 TC_CNTL_STATUS: { L2_INVALIDATE }
4797 0122e214: 0000: 00000e00 00000001
4798 t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords)
4799 0122e21c: 0000: c0035200 000005d0 00000000 00001000 00000001
4800 t3 opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
4801 0122e230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
4802 t0 write CP_SCRATCH_REG7 (057f)
4803 NEEDS WFI: CP_SCRATCH_REG7 (57f)
4804 CP_SCRATCH_REG7: 85
4805 :0,0,89,85
4806 0122e24c: 0000: 0000057f 00000055
4807 t3 opcode: CP_NOP (10) (2 dwords)
4808 0122e254: 0000: c0001000 00000000
4809 t3 opcode: CP_DRAW_INDX (22) (3 dwords)
4810 { VIZ_QUERY = 0 }
4811 { PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 }
4812 draw: 0
4813 prim_type: DI_PT_TRIFAN (5)
4814 source_select: DI_SRC_SEL_AUTO_INDEX (2)
4815 num_indices: 1407
4816 draw[14] register values
4817 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
4818 + 00000fff RBBM_PM_OVERRIDE2: 0xfff
4819 + 00000000 CP_PERFMON_CNTL: 0
4820 !+ 00000059 CP_SCRATCH_REG6: 89
4821 :0,0,89,85
4822 !+ 00000055 CP_SCRATCH_REG7: 85
4823 :0,0,89,85
4824 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
4825 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE }
4826 + 00000002 TP0_CHICKEN: 0x2
4827 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
4828 !+ 00000040 RB_SURFACE_INFO: { SURFACE_PITCH = 64 | MSAA_SAMPLES = 0 }
4829 !+ 01256245 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1256000 }
4830 !+ 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
4831 !+ 00800040 PA_SC_SCREEN_SCISSOR_BR: { X = 64 | Y = 128 }
4832 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
4833 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
4834 !+ 00800040 PA_SC_WINDOW_SCISSOR_BR: { X = 64 | Y = 128 }
4835 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff
4836 + 00000000 VGT_MIN_VTX_INDX: 0
4837 + 00000000 VGT_INDX_OFFSET: 0
4838 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
4839 + 00000000 RB_BLEND_RED: 0
4840 + 00000000 RB_BLEND_GREEN: 0
4841 + 00000000 RB_BLEND_BLUE: 0
4842 + 00000000 RB_BLEND_ALPHA: 0
4843 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
4844 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
4845 + 00000000 RB_ALPHA_REF: 0
4846 !+ 42000000 PA_CL_VPORT_XSCALE: 32.000000
4847 !+ 42000000 PA_CL_VPORT_XOFFSET: 32.000000
4848 + 42800000 PA_CL_VPORT_YSCALE: 64.000000
4849 + 42800000 PA_CL_VPORT_YOFFSET: 64.000000
4850 !+ 00000000 PA_CL_VPORT_ZSCALE: 0.000000
4851 !+ 00000000 PA_CL_VPORT_ZOFFSET: 0.000000
4852 !+ 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
4853 !+ 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
4854 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
4855 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
4856 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
4857 !+ 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
4858 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
4859 !+ 00000c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
4860 !+ 00000012 VGT_CURRENT_BIN_ID_MAX: { COLUMN = 2 | ROW = 2 | GUARD_BAND_MASK = 0 }
4861 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
4862 !+ 00090244 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
4863 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
4864 !+ 00000012 VGT_CURRENT_BIN_ID_MIN: { COLUMN = 2 | ROW = 2 | GUARD_BAND_MASK = 0 }
4865 !+ 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
4866 + 88888888 RB_SAMPLE_POS: 0x88888888
4867 !+ 00000000 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
4868 !+ 00000000 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
4869 !+ 00000000 PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
4870 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
4871 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
4872 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
4873 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
4874 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
4875 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000
4876 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000
4877 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
4878 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000
4879 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
4880 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
4881 + 0000ffff PA_SC_AA_MASK: 0xffff
4882 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
4883 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
4884 !+ 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
4885 !+ 00100080 RB_COPY_DEST_OFFSET: { X = 128 | Y = 128 }
4886 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff
4887 0122e25c: 0000: c0012200 00000000 00040085
4888 t0 write CP_SCRATCH_REG7 (057f)
4889 NEEDS WFI: CP_SCRATCH_REG7 (57f)
4890 CP_SCRATCH_REG7: 86
4891 :0,0,89,86
4892 0122e268: 0000: 0000057f 00000056
4893 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
4894 0122e270: 0000: c0002600 00000000
4895 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
4896 { EVENT = CACHE_FLUSH }
4897 event CACHE_FLUSH
4898 0122e278: 0000: c0004600 00000006
4899 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
4900 { EVENT = CACHE_FLUSH }
4901 event CACHE_FLUSH
4902 0122e280: 0000: c0004600 00000006
4903 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
4904 { EVENT = CACHE_FLUSH }
4905 event CACHE_FLUSH
4906 0122e288: 0000: c0004600 00000006
4907 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
4908 { EVENT = CACHE_FLUSH }
4909 event CACHE_FLUSH
4910 0122e290: 0000: c0004600 00000006
4911 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
4912 { EVENT = CACHE_FLUSH }
4913 event CACHE_FLUSH
4914 0122e298: 0000: c0004600 00000006
4915 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
4916 { EVENT = CACHE_FLUSH }
4917 event CACHE_FLUSH
4918 0122e2a0: 0000: c0004600 00000006
4919 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
4920 { EVENT = CACHE_FLUSH }
4921 event CACHE_FLUSH
4922 0122e2a8: 0000: c0004600 00000006
4923 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
4924 { EVENT = CACHE_FLUSH }
4925 event CACHE_FLUSH
4926 0122e2b0: 0000: c0004600 00000006
4927 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
4928 { EVENT = CACHE_FLUSH }
4929 event CACHE_FLUSH
4930 0122e2b8: 0000: c0004600 00000006
4931 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
4932 { EVENT = CACHE_FLUSH }
4933 event CACHE_FLUSH
4934 0122e2c0: 0000: c0004600 00000006
4935 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
4936 { EVENT = CACHE_FLUSH }
4937 event CACHE_FLUSH
4938 0122e2c8: 0000: c0004600 00000006
4939 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
4940 { EVENT = CACHE_FLUSH }
4941 event CACHE_FLUSH
4942 0122e2d0: 0000: c0004600 00000006
4943 0122f1d8: 0000: c0013700 0122e000 000000b6
4944 t2 nop
4945 ############################################################
4946 vertices: 0
4947 cmd: deqp-gles2/185: fence=1261
4948 ############################################################
4949 cmdstream: 124 dwords
4950 t0 write RB_BC_CONTROL (0f01)
4951 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
4952 0110c000: 0000: 00000f01 1c004046
4953 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4954 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
4955 0110c008: 0000: c0012d00 00040293 00000020
4956 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4957 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
4958 0110c014: 0000: c0012d00 00040316 00000002
4959 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4960 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
4961 0110c020: 0000: c0012d00 00040317 00000002
4962 t0 write CP_PERFMON_CNTL (0444)
4963 CP_PERFMON_CNTL: 0
4964 0110c02c: 0000: 00000444 00000000
4965 t0 write RBBM_PM_OVERRIDE1 (039c)
4966 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
4967 RBBM_PM_OVERRIDE2: 0xfff
4968 0110c034: 0000: 0001039c ffffffff 00000fff
4969 t0 write TP0_CHICKEN (0e1e)
4970 TP0_CHICKEN: 0x2
4971 0110c040: 0000: 00000e1e 00000002
4972 t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
4973 0110c048: 0000: c0003b00 00007fff
4974 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4975 SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
4976 0110c050: 0000: c0012d00 00040307 00100020
4977 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4978 SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
4979 0110c05c: 0000: c0012d00 00040308 000e0120
4980 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
4981 VGT_MAX_VTX_INDX: 0xffffffff
4982 VGT_MIN_VTX_INDX: 0
4983 0110c068: 0000: c0022d00 00040100 ffffffff 00000000
4984 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4985 VGT_INDX_OFFSET: 0
4986 0110c078: 0000: c0012d00 00040102 00000000
4987 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4988 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
4989 0110c084: 0000: c0012d00 00040181 00000004
4990 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4991 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
4992 0110c090: 0000: c0012d00 00040182 ffffffff
4993 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4994 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
4995 0110c09c: 0000: c0012d00 00040301 00000000
4996 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
4997 PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
4998 0110c0a8: 0000: c0012d00 00040300 00000000
4999 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
5001 0110c0b4: 0000: c0012d00 00040080 00000000
5002 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5003 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
5004 0110c0c0: 0000: c0012d00 00040208 00000004
5005 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5006 RB_SAMPLE_POS: 0x88888888
5007 0110c0cc: 0000: c0012d00 0004020a 88888888
5008 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5009 RB_COLOR_DEST_MASK: 0xffffffff
5010 0110c0d8: 0000: c0012d00 00040326 ffffffff
5011 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5012 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
5013 0110c0e4: 0000: c0012d00 0004031b 0003c000
5014 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
5015 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
5016 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
5017 0110c0f0: 0000: c0022d00 00040183 00000000 00000000
5018 t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
5019 0110c100: 0000: c0004b00 00000000
5020 t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords)
5021 0110c108: 0000: c0035200 000005d0 00000000 5f601000 00000001
5022 t0 write SQ_INST_STORE_MANAGMENT (0d02)
5023 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
5024 0110c11c: 0000: 00000d02 00000180
5025 t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
5026 0110c124: 0000: c0003b00 00000300
5027 t3 opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
5028 0110c12c: 0000: c0004a00 80000180
5029 t3 opcode: CP_SET_CONSTANT (2d) (14 dwords)
5030 0110c13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
5031 0110c15c: 2.000000 0.750000 0.375000 0.250000
5032 0110c134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
5033 0110c154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
5034 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5035 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
5036 0110c16c: 0000: c0012d00 00040104 0000000f
5037 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
5038 RB_BLEND_RED: 0
5039 RB_BLEND_GREEN: 0
5040 RB_BLEND_BLUE: 0
5041 RB_BLEND_ALPHA: 0xff
5042 0110c178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
5043 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5044 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
5045 0110c190: 0000: c0012d00 00040206 0000043f
5046 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5047 RB_SURFACE_INFO: { SURFACE_PITCH = 256 | MSAA_SAMPLES = 0 }
5048 0110c19c: 0000: c0012d00 00040000 00000100
5049 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5050 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0x108a000 }
5051 0110c1a8: 0000: c0012d00 00040001 0108a205
5052 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
5053 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
5054 PA_SC_SCREEN_SCISSOR_BR: { X = 256 | Y = 256 }
5055 0110c1b4: 0000: c0022d00 0004000e 80000000 01000100
5056 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5057 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
5058 0110c1c4: 0000: c0012d00 00040080 00000000
5059 t0 write CP_SCRATCH_REG6 (057e)
5060 CP_SCRATCH_REG6: 95
5061 :0,0,95,86
5062 0110c1d0: 0000: 0000057e 0000005f
5063 t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
5064 ibaddr:0110b000
5065 ibsize:000000b8
5066 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
5067 set shader const 0078
5068 0110b000: 0000: c0042d00 00010078 0112d56f 00100000 0112d5af 00100000
5069 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5070 PA_SC_AA_MASK: 0xffff
5071 0110b018: 0000: c0012d00 00040312 0000ffff
5072 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5073 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
5074 0110b024: 0000: c0012d00 00040200 00000000
5075 t3 opcode: CP_SET_CONSTANT (2d) (5 dwords)
5076 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
5077 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
5078 RB_ALPHA_REF: 0
5079 0110b030: 0000: c0032d00 0004010c 00000000 00000000 00000000
5080 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
5081 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
5082 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
5083 0110b044: 0000: c0022d00 00040204 00000000 00090240
5084 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
5085 PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 }
5086 PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 }
5087 PA_SU_LINE_CNTL: { WIDTH = 0.500000 }
5088 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
5089 0110b054: 0000: c0042d00 00040280 00080008 00080008 00000008 00000000
5090 t3 opcode: CP_SET_CONSTANT (2d) (7 dwords)
5091 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
5092 PA_CL_GB_VERT_CLIP_ADJ: 1.000000
5093 PA_CL_GB_VERT_DISC_ADJ: 1.000000
5094 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
5095 PA_CL_GB_HORZ_DISC_ADJ: 1.000000
5096 0110b06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
5097 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
5098 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
5099 PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 }
5100 0110b088: 0000: c0022d00 00040081 00000000 01000100
5101 t3 opcode: CP_SET_CONSTANT (2d) (8 dwords)
5102 PA_CL_VPORT_XSCALE: 128.000000
5103 PA_CL_VPORT_XOFFSET: 128.000000
5104 PA_CL_VPORT_YSCALE: -128.000000
5105 PA_CL_VPORT_YOFFSET: 128.000000
5106 PA_CL_VPORT_ZSCALE: 0.500000
5107 PA_CL_VPORT_ZOFFSET: 0.500000
5108 0110b098: 0000: c0062d00 0004010f 43000000 43000000 c3000000 43000000 3f000000 3f000000
5109 t3 opcode: CP_SET_CONSTANT (2d) (10 dwords)
5110 0110b0c0: 128.000000 128.000000 0.500000 0.000000 128.000000 -128.000000 0.500000 0.000000
5111 0110b0b8: 0000: c0082d00 00000184 43000000 43000000 3f000000 00000000 43000000 c3000000
5112 0110b0d8: 0020: 3f000000 00000000
5113 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
5114 vertex shader, start=0000, size=0015
5115 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2)
5116 03: 19481000 00262688 00000010 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(16) CONST(20, 0)
5117 04: 13480000 40252fc8 00000008 FETCH: VERTEX R0.xy__ = R0.x FMT_32_32_FLOAT UNSIGNED STRIDE(8) CONST(20, 1)
5118 0000 0000 c200 ALLOC POSITION SIZE(0x0)
5119 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1)
5120 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position
5121 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
5122 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1)
5123 06: 00038000 00000000 c2000000 ALU: MAXv export0.xy__ = R0, R0
5124 0000 0000 0000 NOP
5125 0110b0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
5126 0110b100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000010 13480000
5127 0110b120: 0040: 40252fc8 00000008 000f803e 00000000 c2010100 00038000 00000000 c2000000
5128 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
5129 fragment shader, start=0000, size=000c
5130 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1)
5131 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
5132 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
5133 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1)
5134 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor
5135 0000 0000 0000 NOP
5136 0110b140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
5137 0110b160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
5138 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5139 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
5140 0110b17c: 0000: c0012d00 00040181 00000106
5141 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5142 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
5143 0110b188: 0000: c0012d00 00040180 10030002
5144 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
5145 0110b19c: 0.000000 0.000000 0.000000 0.000000
5146 0110b194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000
5147 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5148 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
5149 0110b1ac: 0000: c0012d00 00040202 00001c20
5150 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5151 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
5152 0110b1b8: 0000: c0012d00 00040201 00000000
5153 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5154 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
5155 0110b1c4: 0000: c0012d00 00040104 0000000f
5156 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
5157 RB_BLEND_RED: 0
5158 RB_BLEND_GREEN: 0
5159 RB_BLEND_BLUE: 0
5160 RB_BLEND_ALPHA: 0
5161 0110b1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000
5162 t3 opcode: CP_SET_CONSTANT (2d) (8 dwords)
5163 set texture const 0000
5164 clamp x/y/z: clamp-last-texel/clamp-last-texel/wrap
5165 filter min/mag: point/point
5166 swizzle: xyzw
5167 addr=01230000 (flags=820), size=64x128, pitch=16448, format=FMT_1_REVERSE
5168 mipaddr=01240000 (flags=200)
5169 0110b1e8: 0000: c0062d00 00010000 80804800 01230820 000fe03f 00000d11 000001c0 01240200
5170 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5171 VGT_INDX_OFFSET: 0
5172 0110b208: 0000: c0012d00 00040102 00000000
5173 t0 write TC_CNTL_STATUS (0e00)
5174 TC_CNTL_STATUS: { L2_INVALIDATE }
5175 0110b214: 0000: 00000e00 00000001
5176 t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords)
5177 0110b21c: 0000: c0035200 000005d0 00000000 00001000 00000001
5178 t3 opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
5179 0110b230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
5180 t0 write CP_SCRATCH_REG7 (057f)
5181 CP_SCRATCH_REG7: 91
5182 :0,0,95,91
5183 0110b24c: 0000: 0000057f 0000005b
5184 t3 opcode: CP_NOP (10) (2 dwords)
5185 0110b254: 0000: c0001000 00000000
5186 t3 opcode: CP_DRAW_INDX (22) (5 dwords)
5187 { VIZ_QUERY = 0 }
5188 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x60000 }
5189 { NUM_INDICES = 18011596 }
5190 { INDX_BASE = 0xc }
5191 draw: 0
5192 prim_type: DI_PT_TRILIST (4)
5193 source_select: DI_SRC_SEL_DMA (0)
5194 num_indices: 18011596
5195 draw[15] register values
5196 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
5197 + 00000fff RBBM_PM_OVERRIDE2: 0xfff
5198 + 00000000 CP_PERFMON_CNTL: 0
5199 !+ 0000005f CP_SCRATCH_REG6: 95
5200 :0,0,95,91
5201 !+ 0000005b CP_SCRATCH_REG7: 91
5202 :0,0,95,91
5203 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
5204 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE }
5205 + 00000002 TP0_CHICKEN: 0x2
5206 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
5207 !+ 00000100 RB_SURFACE_INFO: { SURFACE_PITCH = 256 | MSAA_SAMPLES = 0 }
5208 !+ 0108a205 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0x108a000 }
5209 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
5210 !+ 01000100 PA_SC_SCREEN_SCISSOR_BR: { X = 256 | Y = 256 }
5211 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
5212 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
5213 !+ 01000100 PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 }
5214 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff
5215 + 00000000 VGT_MIN_VTX_INDX: 0
5216 + 00000000 VGT_INDX_OFFSET: 0
5217 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
5218 + 00000000 RB_BLEND_RED: 0
5219 + 00000000 RB_BLEND_GREEN: 0
5220 + 00000000 RB_BLEND_BLUE: 0
5221 + 00000000 RB_BLEND_ALPHA: 0
5222 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
5223 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
5224 + 00000000 RB_ALPHA_REF: 0
5225 !+ 43000000 PA_CL_VPORT_XSCALE: 128.000000
5226 !+ 43000000 PA_CL_VPORT_XOFFSET: 128.000000
5227 !+ c3000000 PA_CL_VPORT_YSCALE: -128.000000
5228 !+ 43000000 PA_CL_VPORT_YOFFSET: 128.000000
5229 !+ 3f000000 PA_CL_VPORT_ZSCALE: 0.500000
5230 !+ 3f000000 PA_CL_VPORT_ZOFFSET: 0.500000
5231 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
5232 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
5233 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
5234 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
5235 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
5236 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
5237 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
5238 !+ 00001c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
5239 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
5240 !+ 00090240 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
5241 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
5242 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
5243 + 88888888 RB_SAMPLE_POS: 0x88888888
5244 !+ 00080008 PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 }
5245 !+ 00080008 PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 }
5246 !+ 00000008 PA_SU_LINE_CNTL: { WIDTH = 0.500000 }
5247 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
5248 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
5249 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
5250 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
5251 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
5252 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000
5253 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000
5254 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
5255 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000
5256 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
5257 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
5258 + 0000ffff PA_SC_AA_MASK: 0xffff
5259 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
5260 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
5261 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
5262 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff
5263 0110b25c: 0000: c0032200 00000000 00060004 0112d5cc 0000000c
5264 t0 write CP_SCRATCH_REG7 (057f)
5265 NEEDS WFI: CP_SCRATCH_REG7 (57f)
5266 CP_SCRATCH_REG7: 92
5267 :0,0,95,92
5268 0110b270: 0000: 0000057f 0000005c
5269 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
5270 0110b278: 0000: c0002600 00000000
5271 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
5272 { EVENT = CACHE_FLUSH }
5273 event CACHE_FLUSH
5274 0110b280: 0000: c0004600 00000006
5275 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
5276 { EVENT = CACHE_FLUSH }
5277 event CACHE_FLUSH
5278 0110b288: 0000: c0004600 00000006
5279 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
5280 { EVENT = CACHE_FLUSH }
5281 event CACHE_FLUSH
5282 0110b290: 0000: c0004600 00000006
5283 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
5284 { EVENT = CACHE_FLUSH }
5285 event CACHE_FLUSH
5286 0110b298: 0000: c0004600 00000006
5287 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
5288 { EVENT = CACHE_FLUSH }
5289 event CACHE_FLUSH
5290 0110b2a0: 0000: c0004600 00000006
5291 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
5292 { EVENT = CACHE_FLUSH }
5293 event CACHE_FLUSH
5294 0110b2a8: 0000: c0004600 00000006
5295 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
5296 { EVENT = CACHE_FLUSH }
5297 event CACHE_FLUSH
5298 0110b2b0: 0000: c0004600 00000006
5299 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
5300 { EVENT = CACHE_FLUSH }
5301 event CACHE_FLUSH
5302 0110b2b8: 0000: c0004600 00000006
5303 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
5304 { EVENT = CACHE_FLUSH }
5305 event CACHE_FLUSH
5306 0110b2c0: 0000: c0004600 00000006
5307 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
5308 { EVENT = CACHE_FLUSH }
5309 event CACHE_FLUSH
5310 0110b2c8: 0000: c0004600 00000006
5311 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
5312 { EVENT = CACHE_FLUSH }
5313 event CACHE_FLUSH
5314 0110b2d0: 0000: c0004600 00000006
5315 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
5316 { EVENT = CACHE_FLUSH }
5317 event CACHE_FLUSH
5318 0110b2d8: 0000: c0004600 00000006
5319 0110c1d8: 0000: c0013700 0110b000 000000b8
5320 t2 nop
5321 ############################################################
5322 vertices: 0
5323 cmd: deqp-gles2/185: fence=1262
5324 ############################################################
5325 cmdstream: 124 dwords
5326 t0 write RB_BC_CONTROL (0f01)
5327 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
5328 0122d000: 0000: 00000f01 1c004046
5329 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5330 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
5331 0122d008: 0000: c0012d00 00040293 00000020
5332 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5333 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
5334 0122d014: 0000: c0012d00 00040316 00000002
5335 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5336 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
5337 0122d020: 0000: c0012d00 00040317 00000002
5338 t0 write CP_PERFMON_CNTL (0444)
5339 CP_PERFMON_CNTL: 0
5340 0122d02c: 0000: 00000444 00000000
5341 t0 write RBBM_PM_OVERRIDE1 (039c)
5342 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
5343 RBBM_PM_OVERRIDE2: 0xfff
5344 0122d034: 0000: 0001039c ffffffff 00000fff
5345 t0 write TP0_CHICKEN (0e1e)
5346 TP0_CHICKEN: 0x2
5347 0122d040: 0000: 00000e1e 00000002
5348 t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
5349 0122d048: 0000: c0003b00 00007fff
5350 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5351 SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
5352 0122d050: 0000: c0012d00 00040307 00100020
5353 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5354 SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
5355 0122d05c: 0000: c0012d00 00040308 000e0120
5356 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
5357 VGT_MAX_VTX_INDX: 0xffffffff
5358 VGT_MIN_VTX_INDX: 0
5359 0122d068: 0000: c0022d00 00040100 ffffffff 00000000
5360 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5361 VGT_INDX_OFFSET: 0
5362 0122d078: 0000: c0012d00 00040102 00000000
5363 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5364 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
5365 0122d084: 0000: c0012d00 00040181 00000004
5366 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5367 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
5368 0122d090: 0000: c0012d00 00040182 ffffffff
5369 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5370 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
5371 0122d09c: 0000: c0012d00 00040301 00000000
5372 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5373 PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
5374 0122d0a8: 0000: c0012d00 00040300 00000000
5375 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5376 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
5377 0122d0b4: 0000: c0012d00 00040080 00000000
5378 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5379 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
5380 0122d0c0: 0000: c0012d00 00040208 00000004
5381 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5382 RB_SAMPLE_POS: 0x88888888
5383 0122d0cc: 0000: c0012d00 0004020a 88888888
5384 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5385 RB_COLOR_DEST_MASK: 0xffffffff
5386 0122d0d8: 0000: c0012d00 00040326 ffffffff
5387 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5388 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
5389 0122d0e4: 0000: c0012d00 0004031b 0003c000
5390 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
5391 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
5392 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
5393 0122d0f0: 0000: c0022d00 00040183 00000000 00000000
5394 t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
5395 0122d100: 0000: c0004b00 00000000
5396 t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords)
5397 0122d108: 0000: c0035200 000005d0 00000000 5f601000 00000001
5398 t0 write SQ_INST_STORE_MANAGMENT (0d02)
5399 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
5400 0122d11c: 0000: 00000d02 00000180
5401 t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
5402 0122d124: 0000: c0003b00 00000300
5403 t3 opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
5404 0122d12c: 0000: c0004a00 80000180
5405 t3 opcode: CP_SET_CONSTANT (2d) (14 dwords)
5406 0122d13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
5407 0122d15c: 2.000000 0.750000 0.375000 0.250000
5408 0122d134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
5409 0122d154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
5410 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5411 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
5412 0122d16c: 0000: c0012d00 00040104 0000000f
5413 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
5414 RB_BLEND_RED: 0
5415 RB_BLEND_GREEN: 0
5416 RB_BLEND_BLUE: 0
5417 RB_BLEND_ALPHA: 0xff
5418 0122d178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
5419 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5420 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
5421 0122d190: 0000: c0012d00 00040206 0000043f
5422 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5423 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
5424 0122d19c: 0000: c0012d00 00040000 00000020
5425 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5426 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1254000 }
5427 0122d1a8: 0000: c0012d00 00040001 01254245
5428 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
5429 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
5430 PA_SC_SCREEN_SCISSOR_BR: { X = 32 | Y = 64 }
5431 0122d1b4: 0000: c0022d00 0004000e 80000000 00400020
5432 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5433 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
5434 0122d1c4: 0000: c0012d00 00040080 00000000
5435 t0 write CP_SCRATCH_REG6 (057e)
5436 CP_SCRATCH_REG6: 101
5437 :0,0,101,92
5438 0122d1d0: 0000: 0000057e 00000065
5439 t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
5440 ibaddr:0122e000
5441 ibsize:000000b6
5442 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
5443 set shader const 0078
5444 0122e000: 0000: c0042d00 00010078 0112d5db 00100000 0112d5db 00100000
5445 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5446 PA_SC_AA_MASK: 0xffff
5447 0122e018: 0000: c0012d00 00040312 0000ffff
5448 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5449 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
5450 0122e024: 0000: c0012d00 00040200 00000000
5451 t3 opcode: CP_SET_CONSTANT (2d) (5 dwords)
5452 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
5453 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
5454 RB_ALPHA_REF: 0
5455 0122e030: 0000: c0032d00 0004010c 00000000 00000000 00000000
5456 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
5457 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
5458 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
5459 0122e044: 0000: c0022d00 00040204 00000000 00090244
5460 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
5461 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
5462 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
5463 PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
5464 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
5465 0122e054: 0000: c0042d00 00040280 00000000 00000000 00000000 00000000
5466 t3 opcode: CP_SET_CONSTANT (2d) (7 dwords)
5467 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
5468 PA_CL_GB_VERT_CLIP_ADJ: 1.000000
5469 PA_CL_GB_VERT_DISC_ADJ: 1.000000
5470 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
5471 PA_CL_GB_HORZ_DISC_ADJ: 1.000000
5472 0122e06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
5473 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
5474 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
5475 PA_SC_WINDOW_SCISSOR_BR: { X = 32 | Y = 64 }
5476 0122e088: 0000: c0022d00 00040081 00000000 00400020
5477 t3 opcode: CP_SET_CONSTANT (2d) (8 dwords)
5478 PA_CL_VPORT_XSCALE: 16.000000
5479 PA_CL_VPORT_XOFFSET: 16.000000
5480 PA_CL_VPORT_YSCALE: 32.000000
5481 PA_CL_VPORT_YOFFSET: 32.000000
5482 PA_CL_VPORT_ZSCALE: 0.000000
5483 PA_CL_VPORT_ZOFFSET: 0.000000
5484 0122e098: 0000: c0062d00 0004010f 41800000 41800000 42000000 42000000 00000000 00000000
5485 t3 opcode: CP_SET_CONSTANT (2d) (10 dwords)
5486 0122e0c0: 16.000000 32.000000 0.000000 0.000000 16.000000 32.000000 0.000000 0.000000
5487 0122e0b8: 0000: c0082d00 00000184 41800000 42000000 00000000 00000000 41800000 42000000
5488 *
5489 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
5490 vertex shader, start=0000, size=0015
5491 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2)
5492 03: 19481000 00262688 00000020 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0)
5493 04: 13480000 40262688 00001020 FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1)
5494 0000 0000 c200 ALLOC POSITION SIZE(0x0)
5495 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1)
5496 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position
5497 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
5498 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1)
5499 06: 000f8000 00000000 c2000000 ALU: MAXv export0 = R0, R0
5500 0000 0000 0000 NOP
5501 0122e0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
5502 0122e100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000
5503 0122e120: 0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000
5504 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
5505 fragment shader, start=0000, size=000c
5506 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1)
5507 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
5508 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
5509 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1)
5510 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor
5511 0000 0000 0000 NOP
5512 0122e140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
5513 0122e160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
5514 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5515 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
5516 0122e17c: 0000: c0012d00 00040181 00000106
5517 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5518 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
5519 0122e188: 0000: c0012d00 00040180 10030002
5520 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
5521 0122e19c: 0.000000 0.000000 0.000000 0.000000
5522 0122e194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000
5523 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5524 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
5525 0122e1ac: 0000: c0012d00 00040202 00000c20
5526 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5527 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
5528 0122e1b8: 0000: c0012d00 00040201 00000000
5529 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5530 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
5531 0122e1c4: 0000: c0012d00 00040104 0000000f
5532 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
5533 RB_BLEND_RED: 0
5534 RB_BLEND_GREEN: 0
5535 RB_BLEND_BLUE: 0
5536 RB_BLEND_ALPHA: 0
5537 0122e1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000
5538 t3 opcode: CP_SET_CONSTANT (2d) (8 dwords)
5539 set texture const 0000
5540 clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel
5541 filter min/mag: point/point
5542 swizzle: zyxw
5543 addr=0108a000 (flags=806), size=256x256, pitch=16640, format=FMT_8_8_8_8
5544 mipaddr=00000000 (flags=200)
5545 0122e1e8: 0000: c0062d00 00010000 82024800 0108a806 001fe0ff 00000c14 00000000 00000200
5546 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5547 VGT_INDX_OFFSET: 0
5548 0122e208: 0000: c0012d00 00040102 00000000
5549 t0 write TC_CNTL_STATUS (0e00)
5550 TC_CNTL_STATUS: { L2_INVALIDATE }
5551 0122e214: 0000: 00000e00 00000001
5552 t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords)
5553 0122e21c: 0000: c0035200 000005d0 00000000 00001000 00000001
5554 t3 opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
5555 0122e230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
5556 t0 write CP_SCRATCH_REG7 (057f)
5557 CP_SCRATCH_REG7: 97
5558 :0,0,101,97
5559 0122e24c: 0000: 0000057f 00000061
5560 t3 opcode: CP_NOP (10) (2 dwords)
5561 0122e254: 0000: c0001000 00000000
5562 t3 opcode: CP_DRAW_INDX (22) (3 dwords)
5563 { VIZ_QUERY = 0 }
5564 { PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 }
5565 draw: 0
5566 prim_type: DI_PT_TRIFAN (5)
5567 source_select: DI_SRC_SEL_AUTO_INDEX (2)
5568 num_indices: 1407
5569 draw[16] register values
5570 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
5571 + 00000fff RBBM_PM_OVERRIDE2: 0xfff
5572 + 00000000 CP_PERFMON_CNTL: 0
5573 !+ 00000065 CP_SCRATCH_REG6: 101
5574 :0,0,101,97
5575 !+ 00000061 CP_SCRATCH_REG7: 97
5576 :0,0,101,97
5577 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
5578 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE }
5579 + 00000002 TP0_CHICKEN: 0x2
5580 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
5581 !+ 00000020 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
5582 !+ 01254245 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1254000 }
5583 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
5584 !+ 00400020 PA_SC_SCREEN_SCISSOR_BR: { X = 32 | Y = 64 }
5585 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
5586 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
5587 !+ 00400020 PA_SC_WINDOW_SCISSOR_BR: { X = 32 | Y = 64 }
5588 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff
5589 + 00000000 VGT_MIN_VTX_INDX: 0
5590 + 00000000 VGT_INDX_OFFSET: 0
5591 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
5592 + 00000000 RB_BLEND_RED: 0
5593 + 00000000 RB_BLEND_GREEN: 0
5594 + 00000000 RB_BLEND_BLUE: 0
5595 + 00000000 RB_BLEND_ALPHA: 0
5596 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
5597 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
5598 + 00000000 RB_ALPHA_REF: 0
5599 !+ 41800000 PA_CL_VPORT_XSCALE: 16.000000
5600 !+ 41800000 PA_CL_VPORT_XOFFSET: 16.000000
5601 !+ 42000000 PA_CL_VPORT_YSCALE: 32.000000
5602 !+ 42000000 PA_CL_VPORT_YOFFSET: 32.000000
5603 !+ 00000000 PA_CL_VPORT_ZSCALE: 0.000000
5604 !+ 00000000 PA_CL_VPORT_ZOFFSET: 0.000000
5605 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
5606 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
5607 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
5608 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
5609 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
5610 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
5611 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
5612 !+ 00000c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
5613 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
5614 !+ 00090244 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
5615 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
5616 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
5617 + 88888888 RB_SAMPLE_POS: 0x88888888
5618 !+ 00000000 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
5619 !+ 00000000 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
5620 !+ 00000000 PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
5621 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
5622 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
5623 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
5624 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
5625 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
5626 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000
5627 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000
5628 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
5629 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000
5630 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
5631 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
5632 + 0000ffff PA_SC_AA_MASK: 0xffff
5633 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
5634 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
5635 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
5636 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff
5637 0122e25c: 0000: c0012200 00000000 00040085
5638 t0 write CP_SCRATCH_REG7 (057f)
5639 NEEDS WFI: CP_SCRATCH_REG7 (57f)
5640 CP_SCRATCH_REG7: 98
5641 :0,0,101,98
5642 0122e268: 0000: 0000057f 00000062
5643 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
5644 0122e270: 0000: c0002600 00000000
5645 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
5646 { EVENT = CACHE_FLUSH }
5647 event CACHE_FLUSH
5648 0122e278: 0000: c0004600 00000006
5649 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
5650 { EVENT = CACHE_FLUSH }
5651 event CACHE_FLUSH
5652 0122e280: 0000: c0004600 00000006
5653 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
5654 { EVENT = CACHE_FLUSH }
5655 event CACHE_FLUSH
5656 0122e288: 0000: c0004600 00000006
5657 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
5658 { EVENT = CACHE_FLUSH }
5659 event CACHE_FLUSH
5660 0122e290: 0000: c0004600 00000006
5661 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
5662 { EVENT = CACHE_FLUSH }
5663 event CACHE_FLUSH
5664 0122e298: 0000: c0004600 00000006
5665 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
5666 { EVENT = CACHE_FLUSH }
5667 event CACHE_FLUSH
5668 0122e2a0: 0000: c0004600 00000006
5669 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
5670 { EVENT = CACHE_FLUSH }
5671 event CACHE_FLUSH
5672 0122e2a8: 0000: c0004600 00000006
5673 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
5674 { EVENT = CACHE_FLUSH }
5675 event CACHE_FLUSH
5676 0122e2b0: 0000: c0004600 00000006
5677 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
5678 { EVENT = CACHE_FLUSH }
5679 event CACHE_FLUSH
5680 0122e2b8: 0000: c0004600 00000006
5681 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
5682 { EVENT = CACHE_FLUSH }
5683 event CACHE_FLUSH
5684 0122e2c0: 0000: c0004600 00000006
5685 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
5686 { EVENT = CACHE_FLUSH }
5687 event CACHE_FLUSH
5688 0122e2c8: 0000: c0004600 00000006
5689 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
5690 { EVENT = CACHE_FLUSH }
5691 event CACHE_FLUSH
5692 0122e2d0: 0000: c0004600 00000006
5693 0122d1d8: 0000: c0013700 0122e000 000000b6
5694 t2 nop
5695 ############################################################
5696 vertices: 0
5697 cmd: deqp-gles2/185: fence=1263
5698 ############################################################
5699 cmdstream: 124 dwords
5700 t0 write RB_BC_CONTROL (0f01)
5701 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
5702 0110a000: 0000: 00000f01 1c004046
5703 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5704 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
5705 0110a008: 0000: c0012d00 00040293 00000020
5706 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5707 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
5708 0110a014: 0000: c0012d00 00040316 00000002
5709 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5710 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
5711 0110a020: 0000: c0012d00 00040317 00000002
5712 t0 write CP_PERFMON_CNTL (0444)
5713 CP_PERFMON_CNTL: 0
5714 0110a02c: 0000: 00000444 00000000
5715 t0 write RBBM_PM_OVERRIDE1 (039c)
5716 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
5717 RBBM_PM_OVERRIDE2: 0xfff
5718 0110a034: 0000: 0001039c ffffffff 00000fff
5719 t0 write TP0_CHICKEN (0e1e)
5720 TP0_CHICKEN: 0x2
5721 0110a040: 0000: 00000e1e 00000002
5722 t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
5723 0110a048: 0000: c0003b00 00007fff
5724 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5725 SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
5726 0110a050: 0000: c0012d00 00040307 00100020
5727 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5728 SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
5729 0110a05c: 0000: c0012d00 00040308 000e0120
5730 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
5731 VGT_MAX_VTX_INDX: 0xffffffff
5732 VGT_MIN_VTX_INDX: 0
5733 0110a068: 0000: c0022d00 00040100 ffffffff 00000000
5734 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5735 VGT_INDX_OFFSET: 0
5736 0110a078: 0000: c0012d00 00040102 00000000
5737 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5738 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
5739 0110a084: 0000: c0012d00 00040181 00000004
5740 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5741 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
5742 0110a090: 0000: c0012d00 00040182 ffffffff
5743 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5744 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
5745 0110a09c: 0000: c0012d00 00040301 00000000
5746 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5747 PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
5748 0110a0a8: 0000: c0012d00 00040300 00000000
5749 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5750 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
5751 0110a0b4: 0000: c0012d00 00040080 00000000
5752 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5753 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
5754 0110a0c0: 0000: c0012d00 00040208 00000004
5755 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5756 RB_SAMPLE_POS: 0x88888888
5757 0110a0cc: 0000: c0012d00 0004020a 88888888
5758 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5759 RB_COLOR_DEST_MASK: 0xffffffff
5760 0110a0d8: 0000: c0012d00 00040326 ffffffff
5761 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5762 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
5763 0110a0e4: 0000: c0012d00 0004031b 0003c000
5764 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
5765 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
5766 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
5767 0110a0f0: 0000: c0022d00 00040183 00000000 00000000
5768 t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
5769 0110a100: 0000: c0004b00 00000000
5770 t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords)
5771 0110a108: 0000: c0035200 000005d0 00000000 5f601000 00000001
5772 t0 write SQ_INST_STORE_MANAGMENT (0d02)
5773 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
5774 0110a11c: 0000: 00000d02 00000180
5775 t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
5776 0110a124: 0000: c0003b00 00000300
5777 t3 opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
5778 0110a12c: 0000: c0004a00 80000180
5779 t3 opcode: CP_SET_CONSTANT (2d) (14 dwords)
5780 0110a13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
5781 0110a15c: 2.000000 0.750000 0.375000 0.250000
5782 0110a134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
5783 0110a154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
5784 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5785 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
5786 0110a16c: 0000: c0012d00 00040104 0000000f
5787 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
5788 RB_BLEND_RED: 0
5789 RB_BLEND_GREEN: 0
5790 RB_BLEND_BLUE: 0
5791 RB_BLEND_ALPHA: 0xff
5792 0110a178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
5793 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5794 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
5795 0110a190: 0000: c0012d00 00040206 0000043f
5796 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5797 RB_SURFACE_INFO: { SURFACE_PITCH = 256 | MSAA_SAMPLES = 0 }
5798 0110a19c: 0000: c0012d00 00040000 00000100
5799 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5800 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0x108a000 }
5801 0110a1a8: 0000: c0012d00 00040001 0108a205
5802 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
5803 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
5804 PA_SC_SCREEN_SCISSOR_BR: { X = 256 | Y = 256 }
5805 0110a1b4: 0000: c0022d00 0004000e 80000000 01000100
5806 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5807 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
5808 0110a1c4: 0000: c0012d00 00040080 00000000
5809 t0 write CP_SCRATCH_REG6 (057e)
5810 CP_SCRATCH_REG6: 107
5811 :0,0,107,98
5812 0110a1d0: 0000: 0000057e 0000006b
5813 t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
5814 ibaddr:0110b000
5815 ibsize:000000b8
5816 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
5817 set shader const 0078
5818 0110b000: 0000: c0042d00 00010078 0112d65b 00100000 0112d69b 00100000
5819 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5820 PA_SC_AA_MASK: 0xffff
5821 0110b018: 0000: c0012d00 00040312 0000ffff
5822 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5823 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
5824 0110b024: 0000: c0012d00 00040200 00000000
5825 t3 opcode: CP_SET_CONSTANT (2d) (5 dwords)
5826 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
5827 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
5828 RB_ALPHA_REF: 0
5829 0110b030: 0000: c0032d00 0004010c 00000000 00000000 00000000
5830 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
5831 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
5832 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
5833 0110b044: 0000: c0022d00 00040204 00000000 00090240
5834 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
5835 PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 }
5836 PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 }
5837 PA_SU_LINE_CNTL: { WIDTH = 0.500000 }
5838 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
5839 0110b054: 0000: c0042d00 00040280 00080008 00080008 00000008 00000000
5840 t3 opcode: CP_SET_CONSTANT (2d) (7 dwords)
5841 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
5842 PA_CL_GB_VERT_CLIP_ADJ: 1.000000
5843 PA_CL_GB_VERT_DISC_ADJ: 1.000000
5844 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
5845 PA_CL_GB_HORZ_DISC_ADJ: 1.000000
5846 0110b06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
5847 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
5848 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
5849 PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 }
5850 0110b088: 0000: c0022d00 00040081 00000000 01000100
5851 t3 opcode: CP_SET_CONSTANT (2d) (8 dwords)
5852 PA_CL_VPORT_XSCALE: 128.000000
5853 PA_CL_VPORT_XOFFSET: 128.000000
5854 PA_CL_VPORT_YSCALE: -128.000000
5855 PA_CL_VPORT_YOFFSET: 128.000000
5856 PA_CL_VPORT_ZSCALE: 0.500000
5857 PA_CL_VPORT_ZOFFSET: 0.500000
5858 0110b098: 0000: c0062d00 0004010f 43000000 43000000 c3000000 43000000 3f000000 3f000000
5859 t3 opcode: CP_SET_CONSTANT (2d) (10 dwords)
5860 0110b0c0: 128.000000 128.000000 0.500000 0.000000 128.000000 -128.000000 0.500000 0.000000
5861 0110b0b8: 0000: c0082d00 00000184 43000000 43000000 3f000000 00000000 43000000 c3000000
5862 0110b0d8: 0020: 3f000000 00000000
5863 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
5864 vertex shader, start=0000, size=0015
5865 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2)
5866 03: 19481000 00262688 00000010 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(16) CONST(20, 0)
5867 04: 13480000 40252fc8 00000008 FETCH: VERTEX R0.xy__ = R0.x FMT_32_32_FLOAT UNSIGNED STRIDE(8) CONST(20, 1)
5868 0000 0000 c200 ALLOC POSITION SIZE(0x0)
5869 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1)
5870 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position
5871 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
5872 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1)
5873 06: 00038000 00000000 c2000000 ALU: MAXv export0.xy__ = R0, R0
5874 0000 0000 0000 NOP
5875 0110b0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
5876 0110b100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000010 13480000
5877 0110b120: 0040: 40252fc8 00000008 000f803e 00000000 c2010100 00038000 00000000 c2000000
5878 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
5879 fragment shader, start=0000, size=000c
5880 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1)
5881 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
5882 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
5883 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1)
5884 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor
5885 0000 0000 0000 NOP
5886 0110b140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
5887 0110b160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
5888 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5889 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
5890 0110b17c: 0000: c0012d00 00040181 00000106
5891 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5892 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
5893 0110b188: 0000: c0012d00 00040180 10030002
5894 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
5895 0110b19c: 0.000000 0.000000 0.000000 0.000000
5896 0110b194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000
5897 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5898 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
5899 0110b1ac: 0000: c0012d00 00040202 00001c20
5900 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5901 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
5902 0110b1b8: 0000: c0012d00 00040201 00000000
5903 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5904 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
5905 0110b1c4: 0000: c0012d00 00040104 0000000f
5906 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
5907 RB_BLEND_RED: 0
5908 RB_BLEND_GREEN: 0
5909 RB_BLEND_BLUE: 0
5910 RB_BLEND_ALPHA: 0
5911 0110b1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000
5912 t3 opcode: CP_SET_CONSTANT (2d) (8 dwords)
5913 set texture const 0000
5914 clamp x/y/z: clamp-last-texel/clamp-last-texel/wrap
5915 filter min/mag: point/point
5916 swizzle: xyzw
5917 addr=01230000 (flags=820), size=64x128, pitch=16448, format=FMT_1_REVERSE
5918 mipaddr=01240000 (flags=200)
5919 0110b1e8: 0000: c0062d00 00010000 80804800 01230820 000fe03f 00000d11 000001c0 01240200
5920 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
5921 VGT_INDX_OFFSET: 0
5922 0110b208: 0000: c0012d00 00040102 00000000
5923 t0 write TC_CNTL_STATUS (0e00)
5924 TC_CNTL_STATUS: { L2_INVALIDATE }
5925 0110b214: 0000: 00000e00 00000001
5926 t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords)
5927 0110b21c: 0000: c0035200 000005d0 00000000 00001000 00000001
5928 t3 opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
5929 0110b230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
5930 t0 write CP_SCRATCH_REG7 (057f)
5931 CP_SCRATCH_REG7: 103
5932 :0,0,107,103
5933 0110b24c: 0000: 0000057f 00000067
5934 t3 opcode: CP_NOP (10) (2 dwords)
5935 0110b254: 0000: c0001000 00000000
5936 t3 opcode: CP_DRAW_INDX (22) (5 dwords)
5937 { VIZ_QUERY = 0 }
5938 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x60000 }
5939 { NUM_INDICES = 18011832 }
5940 { INDX_BASE = 0xc }
5941 draw: 0
5942 prim_type: DI_PT_TRILIST (4)
5943 source_select: DI_SRC_SEL_DMA (0)
5944 num_indices: 18011832
5945 draw[17] register values
5946 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
5947 + 00000fff RBBM_PM_OVERRIDE2: 0xfff
5948 + 00000000 CP_PERFMON_CNTL: 0
5949 !+ 0000006b CP_SCRATCH_REG6: 107
5950 :0,0,107,103
5951 !+ 00000067 CP_SCRATCH_REG7: 103
5952 :0,0,107,103
5953 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
5954 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE }
5955 + 00000002 TP0_CHICKEN: 0x2
5956 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
5957 !+ 00000100 RB_SURFACE_INFO: { SURFACE_PITCH = 256 | MSAA_SAMPLES = 0 }
5958 !+ 0108a205 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0x108a000 }
5959 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
5960 !+ 01000100 PA_SC_SCREEN_SCISSOR_BR: { X = 256 | Y = 256 }
5961 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
5962 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
5963 !+ 01000100 PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 }
5964 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff
5965 + 00000000 VGT_MIN_VTX_INDX: 0
5966 + 00000000 VGT_INDX_OFFSET: 0
5967 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
5968 + 00000000 RB_BLEND_RED: 0
5969 + 00000000 RB_BLEND_GREEN: 0
5970 + 00000000 RB_BLEND_BLUE: 0
5971 + 00000000 RB_BLEND_ALPHA: 0
5972 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
5973 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
5974 + 00000000 RB_ALPHA_REF: 0
5975 !+ 43000000 PA_CL_VPORT_XSCALE: 128.000000
5976 !+ 43000000 PA_CL_VPORT_XOFFSET: 128.000000
5977 !+ c3000000 PA_CL_VPORT_YSCALE: -128.000000
5978 !+ 43000000 PA_CL_VPORT_YOFFSET: 128.000000
5979 !+ 3f000000 PA_CL_VPORT_ZSCALE: 0.500000
5980 !+ 3f000000 PA_CL_VPORT_ZOFFSET: 0.500000
5981 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
5982 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
5983 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
5984 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
5985 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
5986 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
5987 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
5988 !+ 00001c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
5989 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
5990 !+ 00090240 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
5991 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
5992 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
5993 + 88888888 RB_SAMPLE_POS: 0x88888888
5994 !+ 00080008 PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 }
5995 !+ 00080008 PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 }
5996 !+ 00000008 PA_SU_LINE_CNTL: { WIDTH = 0.500000 }
5997 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
5998 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
5999 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
6000 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
6001 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
6002 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000
6003 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000
6004 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
6005 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000
6006 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
6007 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
6008 + 0000ffff PA_SC_AA_MASK: 0xffff
6009 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
6010 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
6011 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
6012 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff
6013 0110b25c: 0000: c0032200 00000000 00060004 0112d6b8 0000000c
6014 t0 write CP_SCRATCH_REG7 (057f)
6015 NEEDS WFI: CP_SCRATCH_REG7 (57f)
6016 CP_SCRATCH_REG7: 104
6017 :0,0,107,104
6018 0110b270: 0000: 0000057f 00000068
6019 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
6020 0110b278: 0000: c0002600 00000000
6021 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
6022 { EVENT = CACHE_FLUSH }
6023 event CACHE_FLUSH
6024 0110b280: 0000: c0004600 00000006
6025 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
6026 { EVENT = CACHE_FLUSH }
6027 event CACHE_FLUSH
6028 0110b288: 0000: c0004600 00000006
6029 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
6030 { EVENT = CACHE_FLUSH }
6031 event CACHE_FLUSH
6032 0110b290: 0000: c0004600 00000006
6033 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
6034 { EVENT = CACHE_FLUSH }
6035 event CACHE_FLUSH
6036 0110b298: 0000: c0004600 00000006
6037 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
6038 { EVENT = CACHE_FLUSH }
6039 event CACHE_FLUSH
6040 0110b2a0: 0000: c0004600 00000006
6041 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
6042 { EVENT = CACHE_FLUSH }
6043 event CACHE_FLUSH
6044 0110b2a8: 0000: c0004600 00000006
6045 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
6046 { EVENT = CACHE_FLUSH }
6047 event CACHE_FLUSH
6048 0110b2b0: 0000: c0004600 00000006
6049 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
6050 { EVENT = CACHE_FLUSH }
6051 event CACHE_FLUSH
6052 0110b2b8: 0000: c0004600 00000006
6053 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
6054 { EVENT = CACHE_FLUSH }
6055 event CACHE_FLUSH
6056 0110b2c0: 0000: c0004600 00000006
6057 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
6058 { EVENT = CACHE_FLUSH }
6059 event CACHE_FLUSH
6060 0110b2c8: 0000: c0004600 00000006
6061 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
6062 { EVENT = CACHE_FLUSH }
6063 event CACHE_FLUSH
6064 0110b2d0: 0000: c0004600 00000006
6065 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
6066 { EVENT = CACHE_FLUSH }
6067 event CACHE_FLUSH
6068 0110b2d8: 0000: c0004600 00000006
6069 0110a1d8: 0000: c0013700 0110b000 000000b8
6070 t2 nop
6071 ############################################################
6072 vertices: 0
6073 cmd: deqp-gles2/185: fence=1264
6074 ############################################################
6075 cmdstream: 124 dwords
6076 t0 write RB_BC_CONTROL (0f01)
6077 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
6078 0122f000: 0000: 00000f01 1c004046
6079 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6080 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
6081 0122f008: 0000: c0012d00 00040293 00000020
6082 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6083 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
6084 0122f014: 0000: c0012d00 00040316 00000002
6085 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6086 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
6087 0122f020: 0000: c0012d00 00040317 00000002
6088 t0 write CP_PERFMON_CNTL (0444)
6089 CP_PERFMON_CNTL: 0
6090 0122f02c: 0000: 00000444 00000000
6091 t0 write RBBM_PM_OVERRIDE1 (039c)
6092 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
6093 RBBM_PM_OVERRIDE2: 0xfff
6094 0122f034: 0000: 0001039c ffffffff 00000fff
6095 t0 write TP0_CHICKEN (0e1e)
6096 TP0_CHICKEN: 0x2
6097 0122f040: 0000: 00000e1e 00000002
6098 t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
6099 0122f048: 0000: c0003b00 00007fff
6100 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6101 SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
6102 0122f050: 0000: c0012d00 00040307 00100020
6103 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6104 SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
6105 0122f05c: 0000: c0012d00 00040308 000e0120
6106 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
6107 VGT_MAX_VTX_INDX: 0xffffffff
6108 VGT_MIN_VTX_INDX: 0
6109 0122f068: 0000: c0022d00 00040100 ffffffff 00000000
6110 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6111 VGT_INDX_OFFSET: 0
6112 0122f078: 0000: c0012d00 00040102 00000000
6113 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6114 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
6115 0122f084: 0000: c0012d00 00040181 00000004
6116 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6117 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
6118 0122f090: 0000: c0012d00 00040182 ffffffff
6119 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6120 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
6121 0122f09c: 0000: c0012d00 00040301 00000000
6122 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6123 PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
6124 0122f0a8: 0000: c0012d00 00040300 00000000
6125 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6126 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
6127 0122f0b4: 0000: c0012d00 00040080 00000000
6128 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6129 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
6130 0122f0c0: 0000: c0012d00 00040208 00000004
6131 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6132 RB_SAMPLE_POS: 0x88888888
6133 0122f0cc: 0000: c0012d00 0004020a 88888888
6134 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6135 RB_COLOR_DEST_MASK: 0xffffffff
6136 0122f0d8: 0000: c0012d00 00040326 ffffffff
6137 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6138 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
6139 0122f0e4: 0000: c0012d00 0004031b 0003c000
6140 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
6141 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
6142 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
6143 0122f0f0: 0000: c0022d00 00040183 00000000 00000000
6144 t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
6145 0122f100: 0000: c0004b00 00000000
6146 t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords)
6147 0122f108: 0000: c0035200 000005d0 00000000 5f601000 00000001
6148 t0 write SQ_INST_STORE_MANAGMENT (0d02)
6149 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
6150 0122f11c: 0000: 00000d02 00000180
6151 t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
6152 0122f124: 0000: c0003b00 00000300
6153 t3 opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
6154 0122f12c: 0000: c0004a00 80000180
6155 t3 opcode: CP_SET_CONSTANT (2d) (14 dwords)
6156 0122f13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
6157 0122f15c: 2.000000 0.750000 0.375000 0.250000
6158 0122f134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
6159 0122f154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
6160 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6161 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
6162 0122f16c: 0000: c0012d00 00040104 0000000f
6163 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
6164 RB_BLEND_RED: 0
6165 RB_BLEND_GREEN: 0
6166 RB_BLEND_BLUE: 0
6167 RB_BLEND_ALPHA: 0xff
6168 0122f178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
6169 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6170 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
6171 0122f190: 0000: c0012d00 00040206 0000043f
6172 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6173 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
6174 0122f19c: 0000: c0012d00 00040000 00000020
6175 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6176 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1266000 }
6177 0122f1a8: 0000: c0012d00 00040001 01266245
6178 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
6179 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
6180 PA_SC_SCREEN_SCISSOR_BR: { X = 16 | Y = 32 }
6181 0122f1b4: 0000: c0022d00 0004000e 80000000 00200010
6182 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6183 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
6184 0122f1c4: 0000: c0012d00 00040080 00000000
6185 t0 write CP_SCRATCH_REG6 (057e)
6186 CP_SCRATCH_REG6: 113
6187 :0,0,113,104
6188 0122f1d0: 0000: 0000057e 00000071
6189 t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
6190 ibaddr:0122e000
6191 ibsize:000000b6
6192 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
6193 set shader const 0078
6194 0122e000: 0000: c0042d00 00010078 0112d6c7 00100000 0112d6c7 00100000
6195 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6196 PA_SC_AA_MASK: 0xffff
6197 0122e018: 0000: c0012d00 00040312 0000ffff
6198 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6199 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
6200 0122e024: 0000: c0012d00 00040200 00000000
6201 t3 opcode: CP_SET_CONSTANT (2d) (5 dwords)
6202 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
6203 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
6204 RB_ALPHA_REF: 0
6205 0122e030: 0000: c0032d00 0004010c 00000000 00000000 00000000
6206 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
6207 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
6208 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
6209 0122e044: 0000: c0022d00 00040204 00000000 00090244
6210 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
6211 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
6212 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
6213 PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
6214 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
6215 0122e054: 0000: c0042d00 00040280 00000000 00000000 00000000 00000000
6216 t3 opcode: CP_SET_CONSTANT (2d) (7 dwords)
6217 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
6218 PA_CL_GB_VERT_CLIP_ADJ: 1.000000
6219 PA_CL_GB_VERT_DISC_ADJ: 1.000000
6220 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
6221 PA_CL_GB_HORZ_DISC_ADJ: 1.000000
6222 0122e06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
6223 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
6224 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
6225 PA_SC_WINDOW_SCISSOR_BR: { X = 16 | Y = 32 }
6226 0122e088: 0000: c0022d00 00040081 00000000 00200010
6227 t3 opcode: CP_SET_CONSTANT (2d) (8 dwords)
6228 PA_CL_VPORT_XSCALE: 8.000000
6229 PA_CL_VPORT_XOFFSET: 8.000000
6230 PA_CL_VPORT_YSCALE: 16.000000
6231 PA_CL_VPORT_YOFFSET: 16.000000
6232 PA_CL_VPORT_ZSCALE: 0.000000
6233 PA_CL_VPORT_ZOFFSET: 0.000000
6234 0122e098: 0000: c0062d00 0004010f 41000000 41000000 41800000 41800000 00000000 00000000
6235 t3 opcode: CP_SET_CONSTANT (2d) (10 dwords)
6236 0122e0c0: 8.000000 16.000000 0.000000 0.000000 8.000000 16.000000 0.000000 0.000000
6237 0122e0b8: 0000: c0082d00 00000184 41000000 41800000 00000000 00000000 41000000 41800000
6238 *
6239 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
6240 vertex shader, start=0000, size=0015
6241 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2)
6242 03: 19481000 00262688 00000020 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0)
6243 04: 13480000 40262688 00001020 FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1)
6244 0000 0000 c200 ALLOC POSITION SIZE(0x0)
6245 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1)
6246 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position
6247 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
6248 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1)
6249 06: 000f8000 00000000 c2000000 ALU: MAXv export0 = R0, R0
6250 0000 0000 0000 NOP
6251 0122e0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
6252 0122e100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000
6253 0122e120: 0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000
6254 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
6255 fragment shader, start=0000, size=000c
6256 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1)
6257 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
6258 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
6259 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1)
6260 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor
6261 0000 0000 0000 NOP
6262 0122e140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
6263 0122e160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
6264 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6265 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
6266 0122e17c: 0000: c0012d00 00040181 00000106
6267 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6268 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
6269 0122e188: 0000: c0012d00 00040180 10030002
6270 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
6271 0122e19c: 0.000000 0.000000 0.000000 0.000000
6272 0122e194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000
6273 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6274 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
6275 0122e1ac: 0000: c0012d00 00040202 00000c20
6276 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6277 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
6278 0122e1b8: 0000: c0012d00 00040201 00000000
6279 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6280 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
6281 0122e1c4: 0000: c0012d00 00040104 0000000f
6282 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
6283 RB_BLEND_RED: 0
6284 RB_BLEND_GREEN: 0
6285 RB_BLEND_BLUE: 0
6286 RB_BLEND_ALPHA: 0
6287 0122e1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000
6288 t3 opcode: CP_SET_CONSTANT (2d) (8 dwords)
6289 set texture const 0000
6290 clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel
6291 filter min/mag: point/point
6292 swizzle: zyxw
6293 addr=0108a000 (flags=806), size=256x256, pitch=16640, format=FMT_8_8_8_8
6294 mipaddr=00000000 (flags=200)
6295 0122e1e8: 0000: c0062d00 00010000 82024800 0108a806 001fe0ff 00000c14 00000000 00000200
6296 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6297 VGT_INDX_OFFSET: 0
6298 0122e208: 0000: c0012d00 00040102 00000000
6299 t0 write TC_CNTL_STATUS (0e00)
6300 TC_CNTL_STATUS: { L2_INVALIDATE }
6301 0122e214: 0000: 00000e00 00000001
6302 t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords)
6303 0122e21c: 0000: c0035200 000005d0 00000000 00001000 00000001
6304 t3 opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
6305 0122e230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
6306 t0 write CP_SCRATCH_REG7 (057f)
6307 CP_SCRATCH_REG7: 109
6308 :0,0,113,109
6309 0122e24c: 0000: 0000057f 0000006d
6310 t3 opcode: CP_NOP (10) (2 dwords)
6311 0122e254: 0000: c0001000 00000000
6312 t3 opcode: CP_DRAW_INDX (22) (3 dwords)
6313 { VIZ_QUERY = 0 }
6314 { PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 }
6315 draw: 0
6316 prim_type: DI_PT_TRIFAN (5)
6317 source_select: DI_SRC_SEL_AUTO_INDEX (2)
6318 num_indices: 1407
6319 draw[18] register values
6320 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
6321 + 00000fff RBBM_PM_OVERRIDE2: 0xfff
6322 + 00000000 CP_PERFMON_CNTL: 0
6323 !+ 00000071 CP_SCRATCH_REG6: 113
6324 :0,0,113,109
6325 !+ 0000006d CP_SCRATCH_REG7: 109
6326 :0,0,113,109
6327 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
6328 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE }
6329 + 00000002 TP0_CHICKEN: 0x2
6330 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
6331 !+ 00000020 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
6332 !+ 01266245 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1266000 }
6333 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
6334 !+ 00200010 PA_SC_SCREEN_SCISSOR_BR: { X = 16 | Y = 32 }
6335 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
6336 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
6337 !+ 00200010 PA_SC_WINDOW_SCISSOR_BR: { X = 16 | Y = 32 }
6338 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff
6339 + 00000000 VGT_MIN_VTX_INDX: 0
6340 + 00000000 VGT_INDX_OFFSET: 0
6341 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
6342 + 00000000 RB_BLEND_RED: 0
6343 + 00000000 RB_BLEND_GREEN: 0
6344 + 00000000 RB_BLEND_BLUE: 0
6345 + 00000000 RB_BLEND_ALPHA: 0
6346 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
6347 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
6348 + 00000000 RB_ALPHA_REF: 0
6349 !+ 41000000 PA_CL_VPORT_XSCALE: 8.000000
6350 !+ 41000000 PA_CL_VPORT_XOFFSET: 8.000000
6351 !+ 41800000 PA_CL_VPORT_YSCALE: 16.000000
6352 !+ 41800000 PA_CL_VPORT_YOFFSET: 16.000000
6353 !+ 00000000 PA_CL_VPORT_ZSCALE: 0.000000
6354 !+ 00000000 PA_CL_VPORT_ZOFFSET: 0.000000
6355 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
6356 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
6357 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
6358 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
6359 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
6360 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
6361 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
6362 !+ 00000c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
6363 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
6364 !+ 00090244 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
6365 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
6366 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
6367 + 88888888 RB_SAMPLE_POS: 0x88888888
6368 !+ 00000000 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
6369 !+ 00000000 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
6370 !+ 00000000 PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
6371 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
6372 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
6373 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
6374 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
6375 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
6376 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000
6377 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000
6378 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
6379 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000
6380 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
6381 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
6382 + 0000ffff PA_SC_AA_MASK: 0xffff
6383 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
6384 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
6385 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
6386 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff
6387 0122e25c: 0000: c0012200 00000000 00040085
6388 t0 write CP_SCRATCH_REG7 (057f)
6389 NEEDS WFI: CP_SCRATCH_REG7 (57f)
6390 CP_SCRATCH_REG7: 110
6391 :0,0,113,110
6392 0122e268: 0000: 0000057f 0000006e
6393 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
6394 0122e270: 0000: c0002600 00000000
6395 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
6396 { EVENT = CACHE_FLUSH }
6397 event CACHE_FLUSH
6398 0122e278: 0000: c0004600 00000006
6399 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
6400 { EVENT = CACHE_FLUSH }
6401 event CACHE_FLUSH
6402 0122e280: 0000: c0004600 00000006
6403 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
6404 { EVENT = CACHE_FLUSH }
6405 event CACHE_FLUSH
6406 0122e288: 0000: c0004600 00000006
6407 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
6408 { EVENT = CACHE_FLUSH }
6409 event CACHE_FLUSH
6410 0122e290: 0000: c0004600 00000006
6411 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
6412 { EVENT = CACHE_FLUSH }
6413 event CACHE_FLUSH
6414 0122e298: 0000: c0004600 00000006
6415 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
6416 { EVENT = CACHE_FLUSH }
6417 event CACHE_FLUSH
6418 0122e2a0: 0000: c0004600 00000006
6419 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
6420 { EVENT = CACHE_FLUSH }
6421 event CACHE_FLUSH
6422 0122e2a8: 0000: c0004600 00000006
6423 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
6424 { EVENT = CACHE_FLUSH }
6425 event CACHE_FLUSH
6426 0122e2b0: 0000: c0004600 00000006
6427 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
6428 { EVENT = CACHE_FLUSH }
6429 event CACHE_FLUSH
6430 0122e2b8: 0000: c0004600 00000006
6431 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
6432 { EVENT = CACHE_FLUSH }
6433 event CACHE_FLUSH
6434 0122e2c0: 0000: c0004600 00000006
6435 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
6436 { EVENT = CACHE_FLUSH }
6437 event CACHE_FLUSH
6438 0122e2c8: 0000: c0004600 00000006
6439 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
6440 { EVENT = CACHE_FLUSH }
6441 event CACHE_FLUSH
6442 0122e2d0: 0000: c0004600 00000006
6443 0122f1d8: 0000: c0013700 0122e000 000000b6
6444 t2 nop
6445 ############################################################
6446 vertices: 0
6447 cmd: deqp-gles2/185: fence=1265
6448 ############################################################
6449 cmdstream: 124 dwords
6450 t0 write RB_BC_CONTROL (0f01)
6451 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
6452 0110c000: 0000: 00000f01 1c004046
6453 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6454 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
6455 0110c008: 0000: c0012d00 00040293 00000020
6456 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6457 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
6458 0110c014: 0000: c0012d00 00040316 00000002
6459 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6460 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
6461 0110c020: 0000: c0012d00 00040317 00000002
6462 t0 write CP_PERFMON_CNTL (0444)
6463 CP_PERFMON_CNTL: 0
6464 0110c02c: 0000: 00000444 00000000
6465 t0 write RBBM_PM_OVERRIDE1 (039c)
6466 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
6467 RBBM_PM_OVERRIDE2: 0xfff
6468 0110c034: 0000: 0001039c ffffffff 00000fff
6469 t0 write TP0_CHICKEN (0e1e)
6470 TP0_CHICKEN: 0x2
6471 0110c040: 0000: 00000e1e 00000002
6472 t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
6473 0110c048: 0000: c0003b00 00007fff
6474 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6475 SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
6476 0110c050: 0000: c0012d00 00040307 00100020
6477 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6478 SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
6479 0110c05c: 0000: c0012d00 00040308 000e0120
6480 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
6481 VGT_MAX_VTX_INDX: 0xffffffff
6482 VGT_MIN_VTX_INDX: 0
6483 0110c068: 0000: c0022d00 00040100 ffffffff 00000000
6484 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6485 VGT_INDX_OFFSET: 0
6486 0110c078: 0000: c0012d00 00040102 00000000
6487 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6488 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
6489 0110c084: 0000: c0012d00 00040181 00000004
6490 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6491 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
6492 0110c090: 0000: c0012d00 00040182 ffffffff
6493 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6494 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
6495 0110c09c: 0000: c0012d00 00040301 00000000
6496 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6497 PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
6498 0110c0a8: 0000: c0012d00 00040300 00000000
6499 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6500 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
6501 0110c0b4: 0000: c0012d00 00040080 00000000
6502 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6503 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
6504 0110c0c0: 0000: c0012d00 00040208 00000004
6505 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6506 RB_SAMPLE_POS: 0x88888888
6507 0110c0cc: 0000: c0012d00 0004020a 88888888
6508 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6509 RB_COLOR_DEST_MASK: 0xffffffff
6510 0110c0d8: 0000: c0012d00 00040326 ffffffff
6511 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6512 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
6513 0110c0e4: 0000: c0012d00 0004031b 0003c000
6514 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
6515 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
6516 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
6517 0110c0f0: 0000: c0022d00 00040183 00000000 00000000
6518 t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
6519 0110c100: 0000: c0004b00 00000000
6520 t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords)
6521 0110c108: 0000: c0035200 000005d0 00000000 5f601000 00000001
6522 t0 write SQ_INST_STORE_MANAGMENT (0d02)
6523 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
6524 0110c11c: 0000: 00000d02 00000180
6525 t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
6526 0110c124: 0000: c0003b00 00000300
6527 t3 opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
6528 0110c12c: 0000: c0004a00 80000180
6529 t3 opcode: CP_SET_CONSTANT (2d) (14 dwords)
6530 0110c13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
6531 0110c15c: 2.000000 0.750000 0.375000 0.250000
6532 0110c134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
6533 0110c154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
6534 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6535 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
6536 0110c16c: 0000: c0012d00 00040104 0000000f
6537 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
6538 RB_BLEND_RED: 0
6539 RB_BLEND_GREEN: 0
6540 RB_BLEND_BLUE: 0
6541 RB_BLEND_ALPHA: 0xff
6542 0110c178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
6543 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6544 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
6545 0110c190: 0000: c0012d00 00040206 0000043f
6546 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6547 RB_SURFACE_INFO: { SURFACE_PITCH = 256 | MSAA_SAMPLES = 0 }
6548 0110c19c: 0000: c0012d00 00040000 00000100
6549 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6550 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0x108a000 }
6551 0110c1a8: 0000: c0012d00 00040001 0108a205
6552 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
6553 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
6554 PA_SC_SCREEN_SCISSOR_BR: { X = 256 | Y = 256 }
6555 0110c1b4: 0000: c0022d00 0004000e 80000000 01000100
6556 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6557 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
6558 0110c1c4: 0000: c0012d00 00040080 00000000
6559 t0 write CP_SCRATCH_REG6 (057e)
6560 CP_SCRATCH_REG6: 119
6561 :0,0,119,110
6562 0110c1d0: 0000: 0000057e 00000077
6563 t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
6564 ibaddr:0110b000
6565 ibsize:000000b8
6566 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
6567 set shader const 0078
6568 0110b000: 0000: c0042d00 00010078 0112d747 00100000 0112d787 00100000
6569 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6570 PA_SC_AA_MASK: 0xffff
6571 0110b018: 0000: c0012d00 00040312 0000ffff
6572 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6573 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
6574 0110b024: 0000: c0012d00 00040200 00000000
6575 t3 opcode: CP_SET_CONSTANT (2d) (5 dwords)
6576 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
6577 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
6578 RB_ALPHA_REF: 0
6579 0110b030: 0000: c0032d00 0004010c 00000000 00000000 00000000
6580 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
6581 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
6582 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
6583 0110b044: 0000: c0022d00 00040204 00000000 00090240
6584 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
6585 PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 }
6586 PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 }
6587 PA_SU_LINE_CNTL: { WIDTH = 0.500000 }
6588 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
6589 0110b054: 0000: c0042d00 00040280 00080008 00080008 00000008 00000000
6590 t3 opcode: CP_SET_CONSTANT (2d) (7 dwords)
6591 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
6592 PA_CL_GB_VERT_CLIP_ADJ: 1.000000
6593 PA_CL_GB_VERT_DISC_ADJ: 1.000000
6594 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
6595 PA_CL_GB_HORZ_DISC_ADJ: 1.000000
6596 0110b06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
6597 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
6598 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
6599 PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 }
6600 0110b088: 0000: c0022d00 00040081 00000000 01000100
6601 t3 opcode: CP_SET_CONSTANT (2d) (8 dwords)
6602 PA_CL_VPORT_XSCALE: 128.000000
6603 PA_CL_VPORT_XOFFSET: 128.000000
6604 PA_CL_VPORT_YSCALE: -128.000000
6605 PA_CL_VPORT_YOFFSET: 128.000000
6606 PA_CL_VPORT_ZSCALE: 0.500000
6607 PA_CL_VPORT_ZOFFSET: 0.500000
6608 0110b098: 0000: c0062d00 0004010f 43000000 43000000 c3000000 43000000 3f000000 3f000000
6609 t3 opcode: CP_SET_CONSTANT (2d) (10 dwords)
6610 0110b0c0: 128.000000 128.000000 0.500000 0.000000 128.000000 -128.000000 0.500000 0.000000
6611 0110b0b8: 0000: c0082d00 00000184 43000000 43000000 3f000000 00000000 43000000 c3000000
6612 0110b0d8: 0020: 3f000000 00000000
6613 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
6614 vertex shader, start=0000, size=0015
6615 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2)
6616 03: 19481000 00262688 00000010 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(16) CONST(20, 0)
6617 04: 13480000 40252fc8 00000008 FETCH: VERTEX R0.xy__ = R0.x FMT_32_32_FLOAT UNSIGNED STRIDE(8) CONST(20, 1)
6618 0000 0000 c200 ALLOC POSITION SIZE(0x0)
6619 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1)
6620 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position
6621 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
6622 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1)
6623 06: 00038000 00000000 c2000000 ALU: MAXv export0.xy__ = R0, R0
6624 0000 0000 0000 NOP
6625 0110b0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
6626 0110b100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000010 13480000
6627 0110b120: 0040: 40252fc8 00000008 000f803e 00000000 c2010100 00038000 00000000 c2000000
6628 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
6629 fragment shader, start=0000, size=000c
6630 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1)
6631 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
6632 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
6633 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1)
6634 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor
6635 0000 0000 0000 NOP
6636 0110b140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
6637 0110b160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
6638 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6639 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
6640 0110b17c: 0000: c0012d00 00040181 00000106
6641 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6642 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
6643 0110b188: 0000: c0012d00 00040180 10030002
6644 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
6645 0110b19c: 0.000000 0.000000 0.000000 0.000000
6646 0110b194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000
6647 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6648 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
6649 0110b1ac: 0000: c0012d00 00040202 00001c20
6650 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6651 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
6652 0110b1b8: 0000: c0012d00 00040201 00000000
6653 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6654 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
6655 0110b1c4: 0000: c0012d00 00040104 0000000f
6656 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
6657 RB_BLEND_RED: 0
6658 RB_BLEND_GREEN: 0
6659 RB_BLEND_BLUE: 0
6660 RB_BLEND_ALPHA: 0
6661 0110b1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000
6662 t3 opcode: CP_SET_CONSTANT (2d) (8 dwords)
6663 set texture const 0000
6664 clamp x/y/z: clamp-last-texel/clamp-last-texel/wrap
6665 filter min/mag: point/point
6666 swizzle: xyzw
6667 addr=01230000 (flags=820), size=64x128, pitch=16448, format=FMT_1_REVERSE
6668 mipaddr=01240000 (flags=200)
6669 0110b1e8: 0000: c0062d00 00010000 80804800 01230820 000fe03f 00000d11 000001c0 01240200
6670 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6671 VGT_INDX_OFFSET: 0
6672 0110b208: 0000: c0012d00 00040102 00000000
6673 t0 write TC_CNTL_STATUS (0e00)
6674 TC_CNTL_STATUS: { L2_INVALIDATE }
6675 0110b214: 0000: 00000e00 00000001
6676 t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords)
6677 0110b21c: 0000: c0035200 000005d0 00000000 00001000 00000001
6678 t3 opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
6679 0110b230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
6680 t0 write CP_SCRATCH_REG7 (057f)
6681 CP_SCRATCH_REG7: 115
6682 :0,0,119,115
6683 0110b24c: 0000: 0000057f 00000073
6684 t3 opcode: CP_NOP (10) (2 dwords)
6685 0110b254: 0000: c0001000 00000000
6686 t3 opcode: CP_DRAW_INDX (22) (5 dwords)
6687 { VIZ_QUERY = 0 }
6688 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x60000 }
6689 { NUM_INDICES = 18012068 }
6690 { INDX_BASE = 0xc }
6691 draw: 0
6692 prim_type: DI_PT_TRILIST (4)
6693 source_select: DI_SRC_SEL_DMA (0)
6694 num_indices: 18012068
6695 draw[19] register values
6696 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
6697 + 00000fff RBBM_PM_OVERRIDE2: 0xfff
6698 + 00000000 CP_PERFMON_CNTL: 0
6699 !+ 00000077 CP_SCRATCH_REG6: 119
6700 :0,0,119,115
6701 !+ 00000073 CP_SCRATCH_REG7: 115
6702 :0,0,119,115
6703 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
6704 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE }
6705 + 00000002 TP0_CHICKEN: 0x2
6706 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
6707 !+ 00000100 RB_SURFACE_INFO: { SURFACE_PITCH = 256 | MSAA_SAMPLES = 0 }
6708 !+ 0108a205 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0x108a000 }
6709 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
6710 !+ 01000100 PA_SC_SCREEN_SCISSOR_BR: { X = 256 | Y = 256 }
6711 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
6712 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
6713 !+ 01000100 PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 }
6714 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff
6715 + 00000000 VGT_MIN_VTX_INDX: 0
6716 + 00000000 VGT_INDX_OFFSET: 0
6717 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
6718 + 00000000 RB_BLEND_RED: 0
6719 + 00000000 RB_BLEND_GREEN: 0
6720 + 00000000 RB_BLEND_BLUE: 0
6721 + 00000000 RB_BLEND_ALPHA: 0
6722 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
6723 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
6724 + 00000000 RB_ALPHA_REF: 0
6725 !+ 43000000 PA_CL_VPORT_XSCALE: 128.000000
6726 !+ 43000000 PA_CL_VPORT_XOFFSET: 128.000000
6727 !+ c3000000 PA_CL_VPORT_YSCALE: -128.000000
6728 !+ 43000000 PA_CL_VPORT_YOFFSET: 128.000000
6729 !+ 3f000000 PA_CL_VPORT_ZSCALE: 0.500000
6730 !+ 3f000000 PA_CL_VPORT_ZOFFSET: 0.500000
6731 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
6732 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
6733 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
6734 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
6735 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
6736 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
6737 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
6738 !+ 00001c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
6739 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
6740 !+ 00090240 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
6741 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
6742 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
6743 + 88888888 RB_SAMPLE_POS: 0x88888888
6744 !+ 00080008 PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 }
6745 !+ 00080008 PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 }
6746 !+ 00000008 PA_SU_LINE_CNTL: { WIDTH = 0.500000 }
6747 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
6748 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
6749 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
6750 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
6751 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
6752 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000
6753 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000
6754 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
6755 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000
6756 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
6757 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
6758 + 0000ffff PA_SC_AA_MASK: 0xffff
6759 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
6760 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
6761 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
6762 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff
6763 0110b25c: 0000: c0032200 00000000 00060004 0112d7a4 0000000c
6764 t0 write CP_SCRATCH_REG7 (057f)
6765 NEEDS WFI: CP_SCRATCH_REG7 (57f)
6766 CP_SCRATCH_REG7: 116
6767 :0,0,119,116
6768 0110b270: 0000: 0000057f 00000074
6769 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
6770 0110b278: 0000: c0002600 00000000
6771 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
6772 { EVENT = CACHE_FLUSH }
6773 event CACHE_FLUSH
6774 0110b280: 0000: c0004600 00000006
6775 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
6776 { EVENT = CACHE_FLUSH }
6777 event CACHE_FLUSH
6778 0110b288: 0000: c0004600 00000006
6779 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
6780 { EVENT = CACHE_FLUSH }
6781 event CACHE_FLUSH
6782 0110b290: 0000: c0004600 00000006
6783 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
6784 { EVENT = CACHE_FLUSH }
6785 event CACHE_FLUSH
6786 0110b298: 0000: c0004600 00000006
6787 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
6788 { EVENT = CACHE_FLUSH }
6789 event CACHE_FLUSH
6790 0110b2a0: 0000: c0004600 00000006
6791 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
6792 { EVENT = CACHE_FLUSH }
6793 event CACHE_FLUSH
6794 0110b2a8: 0000: c0004600 00000006
6795 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
6796 { EVENT = CACHE_FLUSH }
6797 event CACHE_FLUSH
6798 0110b2b0: 0000: c0004600 00000006
6799 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
6800 { EVENT = CACHE_FLUSH }
6801 event CACHE_FLUSH
6802 0110b2b8: 0000: c0004600 00000006
6803 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
6804 { EVENT = CACHE_FLUSH }
6805 event CACHE_FLUSH
6806 0110b2c0: 0000: c0004600 00000006
6807 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
6808 { EVENT = CACHE_FLUSH }
6809 event CACHE_FLUSH
6810 0110b2c8: 0000: c0004600 00000006
6811 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
6812 { EVENT = CACHE_FLUSH }
6813 event CACHE_FLUSH
6814 0110b2d0: 0000: c0004600 00000006
6815 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
6816 { EVENT = CACHE_FLUSH }
6817 event CACHE_FLUSH
6818 0110b2d8: 0000: c0004600 00000006
6819 0110c1d8: 0000: c0013700 0110b000 000000b8
6820 t2 nop
6821 ############################################################
6822 vertices: 0
6823 cmd: deqp-gles2/185: fence=1266
6824 ############################################################
6825 cmdstream: 124 dwords
6826 t0 write RB_BC_CONTROL (0f01)
6827 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
6828 0122d000: 0000: 00000f01 1c004046
6829 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6830 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
6831 0122d008: 0000: c0012d00 00040293 00000020
6832 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6833 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
6834 0122d014: 0000: c0012d00 00040316 00000002
6835 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6836 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
6837 0122d020: 0000: c0012d00 00040317 00000002
6838 t0 write CP_PERFMON_CNTL (0444)
6839 CP_PERFMON_CNTL: 0
6840 0122d02c: 0000: 00000444 00000000
6841 t0 write RBBM_PM_OVERRIDE1 (039c)
6842 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
6843 RBBM_PM_OVERRIDE2: 0xfff
6844 0122d034: 0000: 0001039c ffffffff 00000fff
6845 t0 write TP0_CHICKEN (0e1e)
6846 TP0_CHICKEN: 0x2
6847 0122d040: 0000: 00000e1e 00000002
6848 t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
6849 0122d048: 0000: c0003b00 00007fff
6850 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6851 SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
6852 0122d050: 0000: c0012d00 00040307 00100020
6853 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6854 SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
6855 0122d05c: 0000: c0012d00 00040308 000e0120
6856 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
6857 VGT_MAX_VTX_INDX: 0xffffffff
6858 VGT_MIN_VTX_INDX: 0
6859 0122d068: 0000: c0022d00 00040100 ffffffff 00000000
6860 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6861 VGT_INDX_OFFSET: 0
6862 0122d078: 0000: c0012d00 00040102 00000000
6863 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6864 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
6865 0122d084: 0000: c0012d00 00040181 00000004
6866 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6867 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
6868 0122d090: 0000: c0012d00 00040182 ffffffff
6869 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6870 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
6871 0122d09c: 0000: c0012d00 00040301 00000000
6872 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6873 PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
6874 0122d0a8: 0000: c0012d00 00040300 00000000
6875 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6876 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
6877 0122d0b4: 0000: c0012d00 00040080 00000000
6878 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6879 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
6880 0122d0c0: 0000: c0012d00 00040208 00000004
6881 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6882 RB_SAMPLE_POS: 0x88888888
6883 0122d0cc: 0000: c0012d00 0004020a 88888888
6884 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6885 RB_COLOR_DEST_MASK: 0xffffffff
6886 0122d0d8: 0000: c0012d00 00040326 ffffffff
6887 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6888 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
6889 0122d0e4: 0000: c0012d00 0004031b 0003c000
6890 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
6891 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
6892 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
6893 0122d0f0: 0000: c0022d00 00040183 00000000 00000000
6894 t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
6895 0122d100: 0000: c0004b00 00000000
6896 t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords)
6897 0122d108: 0000: c0035200 000005d0 00000000 5f601000 00000001
6898 t0 write SQ_INST_STORE_MANAGMENT (0d02)
6899 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
6900 0122d11c: 0000: 00000d02 00000180
6901 t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
6902 0122d124: 0000: c0003b00 00000300
6903 t3 opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
6904 0122d12c: 0000: c0004a00 80000180
6905 t3 opcode: CP_SET_CONSTANT (2d) (14 dwords)
6906 0122d13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
6907 0122d15c: 2.000000 0.750000 0.375000 0.250000
6908 0122d134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
6909 0122d154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
6910 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6911 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
6912 0122d16c: 0000: c0012d00 00040104 0000000f
6913 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
6914 RB_BLEND_RED: 0
6915 RB_BLEND_GREEN: 0
6916 RB_BLEND_BLUE: 0
6917 RB_BLEND_ALPHA: 0xff
6918 0122d178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
6919 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6920 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
6921 0122d190: 0000: c0012d00 00040206 0000043f
6922 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6923 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
6924 0122d19c: 0000: c0012d00 00040000 00000020
6925 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6926 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1266000 }
6927 0122d1a8: 0000: c0012d00 00040001 01266245
6928 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
6929 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
6930 PA_SC_SCREEN_SCISSOR_BR: { X = 8 | Y = 16 }
6931 0122d1b4: 0000: c0022d00 0004000e 80000000 00100008
6932 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6933 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
6934 0122d1c4: 0000: c0012d00 00040080 00000000
6935 t0 write CP_SCRATCH_REG6 (057e)
6936 CP_SCRATCH_REG6: 125
6937 :0,0,125,116
6938 0122d1d0: 0000: 0000057e 0000007d
6939 t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
6940 ibaddr:0122e000
6941 ibsize:000000b6
6942 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
6943 set shader const 0078
6944 0122e000: 0000: c0042d00 00010078 0112d7b3 00100000 0112d7b3 00100000
6945 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6946 PA_SC_AA_MASK: 0xffff
6947 0122e018: 0000: c0012d00 00040312 0000ffff
6948 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
6949 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
6950 0122e024: 0000: c0012d00 00040200 00000000
6951 t3 opcode: CP_SET_CONSTANT (2d) (5 dwords)
6952 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
6953 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
6954 RB_ALPHA_REF: 0
6955 0122e030: 0000: c0032d00 0004010c 00000000 00000000 00000000
6956 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
6957 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
6958 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
6959 0122e044: 0000: c0022d00 00040204 00000000 00090244
6960 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
6961 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
6962 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
6963 PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
6964 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
6965 0122e054: 0000: c0042d00 00040280 00000000 00000000 00000000 00000000
6966 t3 opcode: CP_SET_CONSTANT (2d) (7 dwords)
6967 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
6968 PA_CL_GB_VERT_CLIP_ADJ: 1.000000
6969 PA_CL_GB_VERT_DISC_ADJ: 1.000000
6970 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
6971 PA_CL_GB_HORZ_DISC_ADJ: 1.000000
6972 0122e06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
6973 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
6974 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
6975 PA_SC_WINDOW_SCISSOR_BR: { X = 8 | Y = 16 }
6976 0122e088: 0000: c0022d00 00040081 00000000 00100008
6977 t3 opcode: CP_SET_CONSTANT (2d) (8 dwords)
6978 PA_CL_VPORT_XSCALE: 4.000000
6979 PA_CL_VPORT_XOFFSET: 4.000000
6980 PA_CL_VPORT_YSCALE: 8.000000
6981 PA_CL_VPORT_YOFFSET: 8.000000
6982 PA_CL_VPORT_ZSCALE: 0.000000
6983 PA_CL_VPORT_ZOFFSET: 0.000000
6984 0122e098: 0000: c0062d00 0004010f 40800000 40800000 41000000 41000000 00000000 00000000
6985 t3 opcode: CP_SET_CONSTANT (2d) (10 dwords)
6986 0122e0c0: 4.000000 8.000000 0.000000 0.000000 4.000000 8.000000 0.000000 0.000000
6987 0122e0b8: 0000: c0082d00 00000184 40800000 41000000 00000000 00000000 40800000 41000000
6988 *
6989 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
6990 vertex shader, start=0000, size=0015
6991 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2)
6992 03: 19481000 00262688 00000020 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0)
6993 04: 13480000 40262688 00001020 FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1)
6994 0000 0000 c200 ALLOC POSITION SIZE(0x0)
6995 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1)
6996 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position
6997 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
6998 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1)
6999 06: 000f8000 00000000 c2000000 ALU: MAXv export0 = R0, R0
7000 0000 0000 0000 NOP
7001 0122e0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
7002 0122e100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000
7003 0122e120: 0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000
7004 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
7005 fragment shader, start=0000, size=000c
7006 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1)
7007 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
7008 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
7009 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1)
7010 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor
7011 0000 0000 0000 NOP
7012 0122e140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
7013 0122e160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
7014 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7015 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
7016 0122e17c: 0000: c0012d00 00040181 00000106
7017 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7018 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
7019 0122e188: 0000: c0012d00 00040180 10030002
7020 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
7021 0122e19c: 0.000000 0.000000 0.000000 0.000000
7022 0122e194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000
7023 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7024 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
7025 0122e1ac: 0000: c0012d00 00040202 00000c20
7026 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7027 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
7028 0122e1b8: 0000: c0012d00 00040201 00000000
7029 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7030 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
7031 0122e1c4: 0000: c0012d00 00040104 0000000f
7032 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
7033 RB_BLEND_RED: 0
7034 RB_BLEND_GREEN: 0
7035 RB_BLEND_BLUE: 0
7036 RB_BLEND_ALPHA: 0
7037 0122e1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000
7038 t3 opcode: CP_SET_CONSTANT (2d) (8 dwords)
7039 set texture const 0000
7040 clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel
7041 filter min/mag: point/point
7042 swizzle: zyxw
7043 addr=0108a000 (flags=806), size=256x256, pitch=16640, format=FMT_8_8_8_8
7044 mipaddr=00000000 (flags=200)
7045 0122e1e8: 0000: c0062d00 00010000 82024800 0108a806 001fe0ff 00000c14 00000000 00000200
7046 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7047 VGT_INDX_OFFSET: 0
7048 0122e208: 0000: c0012d00 00040102 00000000
7049 t0 write TC_CNTL_STATUS (0e00)
7050 TC_CNTL_STATUS: { L2_INVALIDATE }
7051 0122e214: 0000: 00000e00 00000001
7052 t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords)
7053 0122e21c: 0000: c0035200 000005d0 00000000 00001000 00000001
7054 t3 opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
7055 0122e230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
7056 t0 write CP_SCRATCH_REG7 (057f)
7057 CP_SCRATCH_REG7: 121
7058 :0,0,125,121
7059 0122e24c: 0000: 0000057f 00000079
7060 t3 opcode: CP_NOP (10) (2 dwords)
7061 0122e254: 0000: c0001000 00000000
7062 t3 opcode: CP_DRAW_INDX (22) (3 dwords)
7063 { VIZ_QUERY = 0 }
7064 { PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 }
7065 draw: 0
7066 prim_type: DI_PT_TRIFAN (5)
7067 source_select: DI_SRC_SEL_AUTO_INDEX (2)
7068 num_indices: 1407
7069 draw[20] register values
7070 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
7071 + 00000fff RBBM_PM_OVERRIDE2: 0xfff
7072 + 00000000 CP_PERFMON_CNTL: 0
7073 !+ 0000007d CP_SCRATCH_REG6: 125
7074 :0,0,125,121
7075 !+ 00000079 CP_SCRATCH_REG7: 121
7076 :0,0,125,121
7077 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
7078 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE }
7079 + 00000002 TP0_CHICKEN: 0x2
7080 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
7081 !+ 00000020 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
7082 !+ 01266245 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1266000 }
7083 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
7084 !+ 00100008 PA_SC_SCREEN_SCISSOR_BR: { X = 8 | Y = 16 }
7085 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
7086 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
7087 !+ 00100008 PA_SC_WINDOW_SCISSOR_BR: { X = 8 | Y = 16 }
7088 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff
7089 + 00000000 VGT_MIN_VTX_INDX: 0
7090 + 00000000 VGT_INDX_OFFSET: 0
7091 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
7092 + 00000000 RB_BLEND_RED: 0
7093 + 00000000 RB_BLEND_GREEN: 0
7094 + 00000000 RB_BLEND_BLUE: 0
7095 + 00000000 RB_BLEND_ALPHA: 0
7096 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
7097 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
7098 + 00000000 RB_ALPHA_REF: 0
7099 !+ 40800000 PA_CL_VPORT_XSCALE: 4.000000
7100 !+ 40800000 PA_CL_VPORT_XOFFSET: 4.000000
7101 !+ 41000000 PA_CL_VPORT_YSCALE: 8.000000
7102 !+ 41000000 PA_CL_VPORT_YOFFSET: 8.000000
7103 !+ 00000000 PA_CL_VPORT_ZSCALE: 0.000000
7104 !+ 00000000 PA_CL_VPORT_ZOFFSET: 0.000000
7105 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
7106 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
7107 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
7108 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
7109 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
7110 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
7111 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
7112 !+ 00000c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
7113 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
7114 !+ 00090244 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
7115 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
7116 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
7117 + 88888888 RB_SAMPLE_POS: 0x88888888
7118 !+ 00000000 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
7119 !+ 00000000 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
7120 !+ 00000000 PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
7121 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
7122 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
7123 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
7124 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
7125 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
7126 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000
7127 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000
7128 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
7129 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000
7130 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
7131 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
7132 + 0000ffff PA_SC_AA_MASK: 0xffff
7133 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
7134 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
7135 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
7136 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff
7137 0122e25c: 0000: c0012200 00000000 00040085
7138 t0 write CP_SCRATCH_REG7 (057f)
7139 NEEDS WFI: CP_SCRATCH_REG7 (57f)
7140 CP_SCRATCH_REG7: 122
7141 :0,0,125,122
7142 0122e268: 0000: 0000057f 0000007a
7143 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
7144 0122e270: 0000: c0002600 00000000
7145 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
7146 { EVENT = CACHE_FLUSH }
7147 event CACHE_FLUSH
7148 0122e278: 0000: c0004600 00000006
7149 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
7150 { EVENT = CACHE_FLUSH }
7151 event CACHE_FLUSH
7152 0122e280: 0000: c0004600 00000006
7153 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
7154 { EVENT = CACHE_FLUSH }
7155 event CACHE_FLUSH
7156 0122e288: 0000: c0004600 00000006
7157 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
7158 { EVENT = CACHE_FLUSH }
7159 event CACHE_FLUSH
7160 0122e290: 0000: c0004600 00000006
7161 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
7162 { EVENT = CACHE_FLUSH }
7163 event CACHE_FLUSH
7164 0122e298: 0000: c0004600 00000006
7165 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
7166 { EVENT = CACHE_FLUSH }
7167 event CACHE_FLUSH
7168 0122e2a0: 0000: c0004600 00000006
7169 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
7170 { EVENT = CACHE_FLUSH }
7171 event CACHE_FLUSH
7172 0122e2a8: 0000: c0004600 00000006
7173 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
7174 { EVENT = CACHE_FLUSH }
7175 event CACHE_FLUSH
7176 0122e2b0: 0000: c0004600 00000006
7177 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
7178 { EVENT = CACHE_FLUSH }
7179 event CACHE_FLUSH
7180 0122e2b8: 0000: c0004600 00000006
7181 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
7182 { EVENT = CACHE_FLUSH }
7183 event CACHE_FLUSH
7184 0122e2c0: 0000: c0004600 00000006
7185 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
7186 { EVENT = CACHE_FLUSH }
7187 event CACHE_FLUSH
7188 0122e2c8: 0000: c0004600 00000006
7189 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
7190 { EVENT = CACHE_FLUSH }
7191 event CACHE_FLUSH
7192 0122e2d0: 0000: c0004600 00000006
7193 0122d1d8: 0000: c0013700 0122e000 000000b6
7194 t2 nop
7195 ############################################################
7196 vertices: 0
7197 cmd: deqp-gles2/185: fence=1267
7198 ############################################################
7199 cmdstream: 124 dwords
7200 t0 write RB_BC_CONTROL (0f01)
7201 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
7202 0110a000: 0000: 00000f01 1c004046
7203 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7204 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
7205 0110a008: 0000: c0012d00 00040293 00000020
7206 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7207 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
7208 0110a014: 0000: c0012d00 00040316 00000002
7209 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7210 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
7211 0110a020: 0000: c0012d00 00040317 00000002
7212 t0 write CP_PERFMON_CNTL (0444)
7213 CP_PERFMON_CNTL: 0
7214 0110a02c: 0000: 00000444 00000000
7215 t0 write RBBM_PM_OVERRIDE1 (039c)
7216 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
7217 RBBM_PM_OVERRIDE2: 0xfff
7218 0110a034: 0000: 0001039c ffffffff 00000fff
7219 t0 write TP0_CHICKEN (0e1e)
7220 TP0_CHICKEN: 0x2
7221 0110a040: 0000: 00000e1e 00000002
7222 t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
7223 0110a048: 0000: c0003b00 00007fff
7224 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7225 SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
7226 0110a050: 0000: c0012d00 00040307 00100020
7227 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7228 SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
7229 0110a05c: 0000: c0012d00 00040308 000e0120
7230 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
7231 VGT_MAX_VTX_INDX: 0xffffffff
7232 VGT_MIN_VTX_INDX: 0
7233 0110a068: 0000: c0022d00 00040100 ffffffff 00000000
7234 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7235 VGT_INDX_OFFSET: 0
7236 0110a078: 0000: c0012d00 00040102 00000000
7237 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7238 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
7239 0110a084: 0000: c0012d00 00040181 00000004
7240 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7241 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
7242 0110a090: 0000: c0012d00 00040182 ffffffff
7243 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7244 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
7245 0110a09c: 0000: c0012d00 00040301 00000000
7246 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7247 PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
7248 0110a0a8: 0000: c0012d00 00040300 00000000
7249 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7250 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
7251 0110a0b4: 0000: c0012d00 00040080 00000000
7252 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7253 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
7254 0110a0c0: 0000: c0012d00 00040208 00000004
7255 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7256 RB_SAMPLE_POS: 0x88888888
7257 0110a0cc: 0000: c0012d00 0004020a 88888888
7258 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7259 RB_COLOR_DEST_MASK: 0xffffffff
7260 0110a0d8: 0000: c0012d00 00040326 ffffffff
7261 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7262 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
7263 0110a0e4: 0000: c0012d00 0004031b 0003c000
7264 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
7265 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
7266 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
7267 0110a0f0: 0000: c0022d00 00040183 00000000 00000000
7268 t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
7269 0110a100: 0000: c0004b00 00000000
7270 t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords)
7271 0110a108: 0000: c0035200 000005d0 00000000 5f601000 00000001
7272 t0 write SQ_INST_STORE_MANAGMENT (0d02)
7273 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
7274 0110a11c: 0000: 00000d02 00000180
7275 t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
7276 0110a124: 0000: c0003b00 00000300
7277 t3 opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
7278 0110a12c: 0000: c0004a00 80000180
7279 t3 opcode: CP_SET_CONSTANT (2d) (14 dwords)
7280 0110a13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
7281 0110a15c: 2.000000 0.750000 0.375000 0.250000
7282 0110a134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
7283 0110a154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
7284 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7285 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
7286 0110a16c: 0000: c0012d00 00040104 0000000f
7287 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
7288 RB_BLEND_RED: 0
7289 RB_BLEND_GREEN: 0
7290 RB_BLEND_BLUE: 0
7291 RB_BLEND_ALPHA: 0xff
7292 0110a178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
7293 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7294 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
7295 0110a190: 0000: c0012d00 00040206 0000043f
7296 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7297 RB_SURFACE_INFO: { SURFACE_PITCH = 256 | MSAA_SAMPLES = 0 }
7298 0110a19c: 0000: c0012d00 00040000 00000100
7299 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7300 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0x108a000 }
7301 0110a1a8: 0000: c0012d00 00040001 0108a205
7302 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
7303 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
7304 PA_SC_SCREEN_SCISSOR_BR: { X = 256 | Y = 256 }
7305 0110a1b4: 0000: c0022d00 0004000e 80000000 01000100
7306 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7307 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
7308 0110a1c4: 0000: c0012d00 00040080 00000000
7309 t0 write CP_SCRATCH_REG6 (057e)
7310 CP_SCRATCH_REG6: 131
7311 :0,0,131,122
7312 0110a1d0: 0000: 0000057e 00000083
7313 t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
7314 ibaddr:0110b000
7315 ibsize:000000b8
7316 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
7317 set shader const 0078
7318 0110b000: 0000: c0042d00 00010078 0112d833 00100000 0112d873 00100000
7319 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7320 PA_SC_AA_MASK: 0xffff
7321 0110b018: 0000: c0012d00 00040312 0000ffff
7322 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7323 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
7324 0110b024: 0000: c0012d00 00040200 00000000
7325 t3 opcode: CP_SET_CONSTANT (2d) (5 dwords)
7326 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
7327 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
7328 RB_ALPHA_REF: 0
7329 0110b030: 0000: c0032d00 0004010c 00000000 00000000 00000000
7330 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
7331 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
7332 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
7333 0110b044: 0000: c0022d00 00040204 00000000 00090240
7334 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
7335 PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 }
7336 PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 }
7337 PA_SU_LINE_CNTL: { WIDTH = 0.500000 }
7338 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
7339 0110b054: 0000: c0042d00 00040280 00080008 00080008 00000008 00000000
7340 t3 opcode: CP_SET_CONSTANT (2d) (7 dwords)
7341 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
7342 PA_CL_GB_VERT_CLIP_ADJ: 1.000000
7343 PA_CL_GB_VERT_DISC_ADJ: 1.000000
7344 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
7345 PA_CL_GB_HORZ_DISC_ADJ: 1.000000
7346 0110b06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
7347 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
7348 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
7349 PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 }
7350 0110b088: 0000: c0022d00 00040081 00000000 01000100
7351 t3 opcode: CP_SET_CONSTANT (2d) (8 dwords)
7352 PA_CL_VPORT_XSCALE: 128.000000
7353 PA_CL_VPORT_XOFFSET: 128.000000
7354 PA_CL_VPORT_YSCALE: -128.000000
7355 PA_CL_VPORT_YOFFSET: 128.000000
7356 PA_CL_VPORT_ZSCALE: 0.500000
7357 PA_CL_VPORT_ZOFFSET: 0.500000
7358 0110b098: 0000: c0062d00 0004010f 43000000 43000000 c3000000 43000000 3f000000 3f000000
7359 t3 opcode: CP_SET_CONSTANT (2d) (10 dwords)
7360 0110b0c0: 128.000000 128.000000 0.500000 0.000000 128.000000 -128.000000 0.500000 0.000000
7361 0110b0b8: 0000: c0082d00 00000184 43000000 43000000 3f000000 00000000 43000000 c3000000
7362 0110b0d8: 0020: 3f000000 00000000
7363 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
7364 vertex shader, start=0000, size=0015
7365 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2)
7366 03: 19481000 00262688 00000010 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(16) CONST(20, 0)
7367 04: 13480000 40252fc8 00000008 FETCH: VERTEX R0.xy__ = R0.x FMT_32_32_FLOAT UNSIGNED STRIDE(8) CONST(20, 1)
7368 0000 0000 c200 ALLOC POSITION SIZE(0x0)
7369 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1)
7370 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position
7371 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
7372 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1)
7373 06: 00038000 00000000 c2000000 ALU: MAXv export0.xy__ = R0, R0
7374 0000 0000 0000 NOP
7375 0110b0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
7376 0110b100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000010 13480000
7377 0110b120: 0040: 40252fc8 00000008 000f803e 00000000 c2010100 00038000 00000000 c2000000
7378 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
7379 fragment shader, start=0000, size=000c
7380 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1)
7381 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
7382 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
7383 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1)
7384 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor
7385 0000 0000 0000 NOP
7386 0110b140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
7387 0110b160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
7388 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7389 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
7390 0110b17c: 0000: c0012d00 00040181 00000106
7391 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7392 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
7393 0110b188: 0000: c0012d00 00040180 10030002
7394 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
7395 0110b19c: 0.000000 0.000000 0.000000 0.000000
7396 0110b194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000
7397 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7398 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
7399 0110b1ac: 0000: c0012d00 00040202 00001c20
7400 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7401 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
7402 0110b1b8: 0000: c0012d00 00040201 00000000
7403 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7404 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
7405 0110b1c4: 0000: c0012d00 00040104 0000000f
7406 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
7407 RB_BLEND_RED: 0
7408 RB_BLEND_GREEN: 0
7409 RB_BLEND_BLUE: 0
7410 RB_BLEND_ALPHA: 0
7411 0110b1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000
7412 t3 opcode: CP_SET_CONSTANT (2d) (8 dwords)
7413 set texture const 0000
7414 clamp x/y/z: clamp-last-texel/clamp-last-texel/wrap
7415 filter min/mag: point/point
7416 swizzle: xyzw
7417 addr=01230000 (flags=820), size=64x128, pitch=16448, format=FMT_1_REVERSE
7418 mipaddr=01240000 (flags=200)
7419 0110b1e8: 0000: c0062d00 00010000 80804800 01230820 000fe03f 00000d11 000001c0 01240200
7420 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7421 VGT_INDX_OFFSET: 0
7422 0110b208: 0000: c0012d00 00040102 00000000
7423 t0 write TC_CNTL_STATUS (0e00)
7424 TC_CNTL_STATUS: { L2_INVALIDATE }
7425 0110b214: 0000: 00000e00 00000001
7426 t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords)
7427 0110b21c: 0000: c0035200 000005d0 00000000 00001000 00000001
7428 t3 opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
7429 0110b230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
7430 t0 write CP_SCRATCH_REG7 (057f)
7431 CP_SCRATCH_REG7: 127
7432 :0,0,131,127
7433 0110b24c: 0000: 0000057f 0000007f
7434 t3 opcode: CP_NOP (10) (2 dwords)
7435 0110b254: 0000: c0001000 00000000
7436 t3 opcode: CP_DRAW_INDX (22) (5 dwords)
7437 { VIZ_QUERY = 0 }
7438 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x60000 }
7439 { NUM_INDICES = 18012304 }
7440 { INDX_BASE = 0xc }
7441 draw: 0
7442 prim_type: DI_PT_TRILIST (4)
7443 source_select: DI_SRC_SEL_DMA (0)
7444 num_indices: 18012304
7445 draw[21] register values
7446 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
7447 + 00000fff RBBM_PM_OVERRIDE2: 0xfff
7448 + 00000000 CP_PERFMON_CNTL: 0
7449 !+ 00000083 CP_SCRATCH_REG6: 131
7450 :0,0,131,127
7451 !+ 0000007f CP_SCRATCH_REG7: 127
7452 :0,0,131,127
7453 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
7454 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE }
7455 + 00000002 TP0_CHICKEN: 0x2
7456 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
7457 !+ 00000100 RB_SURFACE_INFO: { SURFACE_PITCH = 256 | MSAA_SAMPLES = 0 }
7458 !+ 0108a205 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0x108a000 }
7459 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
7460 !+ 01000100 PA_SC_SCREEN_SCISSOR_BR: { X = 256 | Y = 256 }
7461 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
7462 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
7463 !+ 01000100 PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 }
7464 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff
7465 + 00000000 VGT_MIN_VTX_INDX: 0
7466 + 00000000 VGT_INDX_OFFSET: 0
7467 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
7468 + 00000000 RB_BLEND_RED: 0
7469 + 00000000 RB_BLEND_GREEN: 0
7470 + 00000000 RB_BLEND_BLUE: 0
7471 + 00000000 RB_BLEND_ALPHA: 0
7472 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
7473 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
7474 + 00000000 RB_ALPHA_REF: 0
7475 !+ 43000000 PA_CL_VPORT_XSCALE: 128.000000
7476 !+ 43000000 PA_CL_VPORT_XOFFSET: 128.000000
7477 !+ c3000000 PA_CL_VPORT_YSCALE: -128.000000
7478 !+ 43000000 PA_CL_VPORT_YOFFSET: 128.000000
7479 !+ 3f000000 PA_CL_VPORT_ZSCALE: 0.500000
7480 !+ 3f000000 PA_CL_VPORT_ZOFFSET: 0.500000
7481 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
7482 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
7483 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
7484 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
7485 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
7486 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
7487 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
7488 !+ 00001c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
7489 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
7490 !+ 00090240 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
7491 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
7492 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
7493 + 88888888 RB_SAMPLE_POS: 0x88888888
7494 !+ 00080008 PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 }
7495 !+ 00080008 PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 }
7496 !+ 00000008 PA_SU_LINE_CNTL: { WIDTH = 0.500000 }
7497 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
7498 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
7499 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
7500 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
7501 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
7502 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000
7503 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000
7504 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
7505 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000
7506 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
7507 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
7508 + 0000ffff PA_SC_AA_MASK: 0xffff
7509 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
7510 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
7511 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
7512 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff
7513 0110b25c: 0000: c0032200 00000000 00060004 0112d890 0000000c
7514 t0 write CP_SCRATCH_REG7 (057f)
7515 NEEDS WFI: CP_SCRATCH_REG7 (57f)
7516 CP_SCRATCH_REG7: 128
7517 :0,0,131,128
7518 0110b270: 0000: 0000057f 00000080
7519 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
7520 0110b278: 0000: c0002600 00000000
7521 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
7522 { EVENT = CACHE_FLUSH }
7523 event CACHE_FLUSH
7524 0110b280: 0000: c0004600 00000006
7525 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
7526 { EVENT = CACHE_FLUSH }
7527 event CACHE_FLUSH
7528 0110b288: 0000: c0004600 00000006
7529 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
7530 { EVENT = CACHE_FLUSH }
7531 event CACHE_FLUSH
7532 0110b290: 0000: c0004600 00000006
7533 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
7534 { EVENT = CACHE_FLUSH }
7535 event CACHE_FLUSH
7536 0110b298: 0000: c0004600 00000006
7537 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
7538 { EVENT = CACHE_FLUSH }
7539 event CACHE_FLUSH
7540 0110b2a0: 0000: c0004600 00000006
7541 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
7542 { EVENT = CACHE_FLUSH }
7543 event CACHE_FLUSH
7544 0110b2a8: 0000: c0004600 00000006
7545 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
7546 { EVENT = CACHE_FLUSH }
7547 event CACHE_FLUSH
7548 0110b2b0: 0000: c0004600 00000006
7549 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
7550 { EVENT = CACHE_FLUSH }
7551 event CACHE_FLUSH
7552 0110b2b8: 0000: c0004600 00000006
7553 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
7554 { EVENT = CACHE_FLUSH }
7555 event CACHE_FLUSH
7556 0110b2c0: 0000: c0004600 00000006
7557 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
7558 { EVENT = CACHE_FLUSH }
7559 event CACHE_FLUSH
7560 0110b2c8: 0000: c0004600 00000006
7561 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
7562 { EVENT = CACHE_FLUSH }
7563 event CACHE_FLUSH
7564 0110b2d0: 0000: c0004600 00000006
7565 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
7566 { EVENT = CACHE_FLUSH }
7567 event CACHE_FLUSH
7568 0110b2d8: 0000: c0004600 00000006
7569 0110a1d8: 0000: c0013700 0110b000 000000b8
7570 t2 nop
7571 ############################################################
7572 vertices: 0
7573 cmd: deqp-gles2/185: fence=1268
7574 ############################################################
7575 cmdstream: 124 dwords
7576 t0 write RB_BC_CONTROL (0f01)
7577 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
7578 0122f000: 0000: 00000f01 1c004046
7579 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7580 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
7581 0122f008: 0000: c0012d00 00040293 00000020
7582 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7583 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
7584 0122f014: 0000: c0012d00 00040316 00000002
7585 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7586 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
7587 0122f020: 0000: c0012d00 00040317 00000002
7588 t0 write CP_PERFMON_CNTL (0444)
7589 CP_PERFMON_CNTL: 0
7590 0122f02c: 0000: 00000444 00000000
7591 t0 write RBBM_PM_OVERRIDE1 (039c)
7592 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
7593 RBBM_PM_OVERRIDE2: 0xfff
7594 0122f034: 0000: 0001039c ffffffff 00000fff
7595 t0 write TP0_CHICKEN (0e1e)
7596 TP0_CHICKEN: 0x2
7597 0122f040: 0000: 00000e1e 00000002
7598 t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
7599 0122f048: 0000: c0003b00 00007fff
7600 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7601 SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
7602 0122f050: 0000: c0012d00 00040307 00100020
7603 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7604 SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
7605 0122f05c: 0000: c0012d00 00040308 000e0120
7606 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
7607 VGT_MAX_VTX_INDX: 0xffffffff
7608 VGT_MIN_VTX_INDX: 0
7609 0122f068: 0000: c0022d00 00040100 ffffffff 00000000
7610 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7611 VGT_INDX_OFFSET: 0
7612 0122f078: 0000: c0012d00 00040102 00000000
7613 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7614 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
7615 0122f084: 0000: c0012d00 00040181 00000004
7616 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7617 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
7618 0122f090: 0000: c0012d00 00040182 ffffffff
7619 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7620 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
7621 0122f09c: 0000: c0012d00 00040301 00000000
7622 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7623 PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
7624 0122f0a8: 0000: c0012d00 00040300 00000000
7625 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7626 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
7627 0122f0b4: 0000: c0012d00 00040080 00000000
7628 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7629 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
7630 0122f0c0: 0000: c0012d00 00040208 00000004
7631 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7632 RB_SAMPLE_POS: 0x88888888
7633 0122f0cc: 0000: c0012d00 0004020a 88888888
7634 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7635 RB_COLOR_DEST_MASK: 0xffffffff
7636 0122f0d8: 0000: c0012d00 00040326 ffffffff
7637 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7638 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
7639 0122f0e4: 0000: c0012d00 0004031b 0003c000
7640 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
7641 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
7642 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
7643 0122f0f0: 0000: c0022d00 00040183 00000000 00000000
7644 t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
7645 0122f100: 0000: c0004b00 00000000
7646 t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords)
7647 0122f108: 0000: c0035200 000005d0 00000000 5f601000 00000001
7648 t0 write SQ_INST_STORE_MANAGMENT (0d02)
7649 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
7650 0122f11c: 0000: 00000d02 00000180
7651 t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
7652 0122f124: 0000: c0003b00 00000300
7653 t3 opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
7654 0122f12c: 0000: c0004a00 80000180
7655 t3 opcode: CP_SET_CONSTANT (2d) (14 dwords)
7656 0122f13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
7657 0122f15c: 2.000000 0.750000 0.375000 0.250000
7658 0122f134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
7659 0122f154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
7660 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7661 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
7662 0122f16c: 0000: c0012d00 00040104 0000000f
7663 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
7664 RB_BLEND_RED: 0
7665 RB_BLEND_GREEN: 0
7666 RB_BLEND_BLUE: 0
7667 RB_BLEND_ALPHA: 0xff
7668 0122f178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
7669 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7670 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
7671 0122f190: 0000: c0012d00 00040206 0000043f
7672 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7673 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
7674 0122f19c: 0000: c0012d00 00040000 00000020
7675 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7676 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1266000 }
7677 0122f1a8: 0000: c0012d00 00040001 01266245
7678 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
7679 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
7680 PA_SC_SCREEN_SCISSOR_BR: { X = 4 | Y = 8 }
7681 0122f1b4: 0000: c0022d00 0004000e 80000000 00080004
7682 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7683 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
7684 0122f1c4: 0000: c0012d00 00040080 00000000
7685 t0 write CP_SCRATCH_REG6 (057e)
7686 CP_SCRATCH_REG6: 137
7687 :0,0,137,128
7688 0122f1d0: 0000: 0000057e 00000089
7689 t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
7690 ibaddr:0122e000
7691 ibsize:000000b6
7692 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
7693 set shader const 0078
7694 0122e000: 0000: c0042d00 00010078 0112d89f 00100000 0112d89f 00100000
7695 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7696 PA_SC_AA_MASK: 0xffff
7697 0122e018: 0000: c0012d00 00040312 0000ffff
7698 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7699 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
7700 0122e024: 0000: c0012d00 00040200 00000000
7701 t3 opcode: CP_SET_CONSTANT (2d) (5 dwords)
7702 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
7703 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
7704 RB_ALPHA_REF: 0
7705 0122e030: 0000: c0032d00 0004010c 00000000 00000000 00000000
7706 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
7707 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
7708 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
7709 0122e044: 0000: c0022d00 00040204 00000000 00090244
7710 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
7711 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
7712 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
7713 PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
7714 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
7715 0122e054: 0000: c0042d00 00040280 00000000 00000000 00000000 00000000
7716 t3 opcode: CP_SET_CONSTANT (2d) (7 dwords)
7717 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
7718 PA_CL_GB_VERT_CLIP_ADJ: 1.000000
7719 PA_CL_GB_VERT_DISC_ADJ: 1.000000
7720 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
7721 PA_CL_GB_HORZ_DISC_ADJ: 1.000000
7722 0122e06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
7723 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
7724 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
7725 PA_SC_WINDOW_SCISSOR_BR: { X = 4 | Y = 8 }
7726 0122e088: 0000: c0022d00 00040081 00000000 00080004
7727 t3 opcode: CP_SET_CONSTANT (2d) (8 dwords)
7728 PA_CL_VPORT_XSCALE: 2.000000
7729 PA_CL_VPORT_XOFFSET: 2.000000
7730 PA_CL_VPORT_YSCALE: 4.000000
7731 PA_CL_VPORT_YOFFSET: 4.000000
7732 PA_CL_VPORT_ZSCALE: 0.000000
7733 PA_CL_VPORT_ZOFFSET: 0.000000
7734 0122e098: 0000: c0062d00 0004010f 40000000 40000000 40800000 40800000 00000000 00000000
7735 t3 opcode: CP_SET_CONSTANT (2d) (10 dwords)
7736 0122e0c0: 2.000000 4.000000 0.000000 0.000000 2.000000 4.000000 0.000000 0.000000
7737 0122e0b8: 0000: c0082d00 00000184 40000000 40800000 00000000 00000000 40000000 40800000
7738 *
7739 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
7740 vertex shader, start=0000, size=0015
7741 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2)
7742 03: 19481000 00262688 00000020 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0)
7743 04: 13480000 40262688 00001020 FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1)
7744 0000 0000 c200 ALLOC POSITION SIZE(0x0)
7745 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1)
7746 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position
7747 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
7748 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1)
7749 06: 000f8000 00000000 c2000000 ALU: MAXv export0 = R0, R0
7750 0000 0000 0000 NOP
7751 0122e0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
7752 0122e100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000
7753 0122e120: 0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000
7754 t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
7755 fragment shader, start=0000, size=000c
7756 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1)
7757 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
7758 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0)
7759 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1)
7760 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor
7761 0000 0000 0000 NOP
7762 0122e140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
7763 0122e160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
7764 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7765 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
7766 0122e17c: 0000: c0012d00 00040181 00000106
7767 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7768 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
7769 0122e188: 0000: c0012d00 00040180 10030002
7770 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
7771 0122e19c: 0.000000 0.000000 0.000000 0.000000
7772 0122e194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000
7773 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7774 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
7775 0122e1ac: 0000: c0012d00 00040202 00000c20
7776 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7777 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
7778 0122e1b8: 0000: c0012d00 00040201 00000000
7779 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7780 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
7781 0122e1c4: 0000: c0012d00 00040104 0000000f
7782 t3 opcode: CP_SET_CONSTANT (2d) (6 dwords)
7783 RB_BLEND_RED: 0
7784 RB_BLEND_GREEN: 0
7785 RB_BLEND_BLUE: 0
7786 RB_BLEND_ALPHA: 0
7787 0122e1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000
7788 t3 opcode: CP_SET_CONSTANT (2d) (8 dwords)
7789 set texture const 0000
7790 clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel
7791 filter min/mag: point/point
7792 swizzle: zyxw
7793 addr=0108a000 (flags=806), size=256x256, pitch=16640, format=FMT_8_8_8_8
7794 mipaddr=00000000 (flags=200)
7795 0122e1e8: 0000: c0062d00 00010000 82024800 0108a806 001fe0ff 00000c14 00000000 00000200
7796 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
7797 VGT_INDX_OFFSET: 0
7798 0122e208: 0000: c0012d00 00040102 00000000
7799 t0 write TC_CNTL_STATUS (0e00)
7800 TC_CNTL_STATUS: { L2_INVALIDATE }
7801 0122e214: 0000: 00000e00 00000001
7802 t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords)
7803 0122e21c: 0000: c0035200 000005d0 00000000 00001000 00000001
7804 t3 opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
7805 0122e230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
7806 t0 write CP_SCRATCH_REG7 (057f)
7807 CP_SCRATCH_REG7: 133
7808 :0,0,137,133
7809 0122e24c: 0000: 0000057f 00000085
7810 t3 opcode: CP_NOP (10) (2 dwords)
7811 0122e254: 0000: c0001000 00000000
7812 t3 opcode: CP_DRAW_INDX (22) (3 dwords)
7813 { VIZ_QUERY = 0 }
7814 { PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 }
7815 draw: 0
7816 prim_type: DI_PT_TRIFAN (5)
7817 source_select: DI_SRC_SEL_AUTO_INDEX (2)
7818 num_indices: 1407
7819 draw[22] register values
7820 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
7821 + 00000fff RBBM_PM_OVERRIDE2: 0xfff
7822 + 00000000 CP_PERFMON_CNTL: 0
7823 !+ 00000089 CP_SCRATCH_REG6: 137
7824 :0,0,137,133
7825 !+ 00000085 CP_SCRATCH_REG7: 133
7826 :0,0,137,133
7827 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
7828 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE }
7829 + 00000002 TP0_CHICKEN: 0x2
7830 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
7831 !+ 00000020 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
7832 !+ 01266245 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1266000 }
7833 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
7834 !+ 00080004 PA_SC_SCREEN_SCISSOR_BR: { X = 4 | Y = 8 }
7835 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
7836 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
7837 !+ 00080004 PA_SC_WINDOW_SCISSOR_BR: { X = 4 | Y = 8 }
7838 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff
7839 + 00000000 VGT_MIN_VTX_INDX: 0
7840 + 00000000 VGT_INDX_OFFSET: 0
7841 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
7842 + 00000000 RB_BLEND_RED: 0
7843 + 00000000 RB_BLEND_GREEN: 0
7844 + 00000000 RB_BLEND_BLUE: 0
7845 + 00000000 RB_BLEND_ALPHA: 0
7846 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
7847 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
7848 + 00000000 RB_ALPHA_REF: 0
7849 !+ 40000000 PA_CL_VPORT_XSCALE: 2.000000
7850 !+ 40000000 PA_CL_VPORT_XOFFSET: 2.000000
7851 !+ 40800000 PA_CL_VPORT_YSCALE: 4.000000
7852 !+ 40800000 PA_CL_VPORT_YOFFSET: 4.000000
7853 !+ 00000000 PA_CL_VPORT_ZSCALE: 0.000000
7854 !+ 00000000 PA_CL_VPORT_ZOFFSET: 0.000000
7855 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
7856 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
7857 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
7858 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
7859 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
7860 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
7861 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
7862 !+ 00000c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
7863 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
7864 !+ 00090244 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
7865 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
7866 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
7867 + 88888888 RB_SAMPLE_POS: 0x88888888
7868 !+ 00000000 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
7869 !+ 00000000 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
7870 !+ 00000000 PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
7871 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
7872 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
7873 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
7874 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
7875 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
7876 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000
7877 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000
7878 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
7879 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000
7880 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
7881 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
7882 + 0000ffff PA_SC_AA_MASK: 0xffff
7883 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
7884 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
7885 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
7886 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff
7887 0122e25c: 0000: c0012200 00000000 00040085
7888 t0 write CP_SCRATCH_REG7 (057f)
7889 NEEDS WFI: CP_SCRATCH_REG7 (57f)
7890 CP_SCRATCH_REG7: 134
7891 :0,0,137,134
7892 0122e268: 0000: 0000057f 00000086
7893 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
7894 0122e270: 0000: c0002600 00000000
7895 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
7896 { EVENT = CACHE_FLUSH }
7897 event CACHE_FLUSH
7898 0122e278: 0000: c0004600 00000006
7899 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
7900 { EVENT = CACHE_FLUSH }
7901 event CACHE_FLUSH
7902 0122e280: 0000: c0004600 00000006
7903 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
7904 { EVENT = CACHE_FLUSH }
7905 event CACHE_FLUSH
7906 0122e288: 0000: c0004600 00000006
7907 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
7908 { EVENT = CACHE_FLUSH }
7909 event CACHE_FLUSH
7910 0122e290: 0000: c0004600 00000006
7911 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
7912 { EVENT = CACHE_FLUSH }
7913 event CACHE_FLUSH
7914 0122e298: 0000: c0004600 00000006
7915 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
7916 { EVENT = CACHE_FLUSH }
7917 event CACHE_FLUSH
7918 0122e2a0: 0000: c0004600 00000006
7919 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
7920 { EVENT = CACHE_FLUSH }
7921 event CACHE_FLUSH
7922 0122e2a8: 0000: c0004600 00000006
7923 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
7924 { EVENT = CACHE_FLUSH }
7925 event CACHE_FLUSH
7926 0122e2b0: 0000: c0004600 00000006
7927 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
7928 { EVENT = CACHE_FLUSH }
7929 event CACHE_FLUSH
7930 0122e2b8: 0000: c0004600 00000006
7931 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
7932 { EVENT = CACHE_FLUSH }
7933 event CACHE_FLUSH
7934 0122e2c0: 0000: c0004600 00000006
7935 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
7936 { EVENT = CACHE_FLUSH }
7937 event CACHE_FLUSH
7938 0122e2c8: 0000: c0004600 00000006
7939 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
7940 { EVENT = CACHE_FLUSH }
7941 event CACHE_FLUSH
7942 0122e2d0: 0000: c0004600 00000006
7943 0122f1d8: 0000: c0013700 0122e000 000000b6
7944 t2 nop
7945 ############################################################
7946 vertices: 0