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freedreno: deduplicate a3xx+ disasm
[mesa.git] / src / freedreno / .gitlab-ci / reference / glxgears-a420.log
1 Reading src/freedreno/.gitlab-ci/traces/glxgears-a420.rd.gz...
2 gpu_id: 420
3 cmd: X/23360: fence=1029603
4 cmd: glxgears/23375: fence=1029604
5 ############################################################
6 cmdstream: 414 dwords
7 t0 write RBBM_PERFCTR_CTL (0170)
8 RBBM_PERFCTR_CTL: 0x1
9 108ce000: 0000: 00000170 00000001
10 t0 write GRAS_DEBUG_ECO_CONTROL (0c81)
11 GRAS_DEBUG_ECO_CONTROL: 0
12 108ce008: 0000: 00000c81 00000000
13 t0 write SP_MODE_CONTROL (0ec3)
14 SP_MODE_CONTROL: 0x6
15 108ce010: 0000: 00000ec3 00000006
16 t0 write TPL1_TP_MODE_CONTROL (0f03)
17 TPL1_TP_MODE_CONTROL: 0x3a
18 108ce018: 0000: 00000f03 0000003a
19 t0 write UNKNOWN_0D01 (0d01)
20 UNKNOWN_0D01: 0x1
21 108ce020: 0000: 00000d01 00000001
22 t0 write UNKNOWN_0E42 (0e42)
23 UNKNOWN_0E42: 0
24 108ce028: 0000: 00000e42 00000000
25 t0 write UCHE_CACHE_WAYS_VFD (0e8c)
26 UCHE_CACHE_WAYS_VFD: 0x7
27 108ce030: 0000: 00000e8c 00000007
28 t0 write UCHE_CACHE_MODE_CONTROL (0e80)
29 UCHE_CACHE_MODE_CONTROL: 0
30 108ce038: 0000: 00000e80 00000000
31 t0 write UCHE_INVALIDATE0 (0e8a)
32 UCHE_INVALIDATE0: 0
33 UCHE_INVALIDATE1: 0x12
34 108ce040: 0000: 00010e8a 00000000 00000012
35 t0 write HLSQ_MODE_CONTROL (0e05)
36 HLSQ_MODE_CONTROL: 0
37 108ce04c: 0000: 00000e05 00000000
38 t0 write UNKNOWN_0CC5 (0cc5)
39 UNKNOWN_0CC5: 0x6
40 108ce054: 0000: 00000cc5 00000006
41 t0 write UNKNOWN_0CC6 (0cc6)
42 UNKNOWN_0CC6: 0
43 108ce05c: 0000: 00000cc6 00000000
44 t0 write UNKNOWN_0EC2 (0ec2)
45 UNKNOWN_0EC2: 0x40000
46 108ce064: 0000: 00000ec2 00040000
47 t0 write UNKNOWN_2001 (2001)
48 UNKNOWN_2001: 0
49 108ce06c: 0000: 00002001 00000000
50 t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
51 108ce074: 0000: c0003b00 00001000
52 t0 write UNKNOWN_20EF (20ef)
53 UNKNOWN_20EF: 0
54 108ce07c: 0000: 000020ef 00000000
55 t0 write RB_BLEND_RED (20f0)
56 RB_BLEND_RED: { UINT = 0 | SINT = 0 | FLOAT = 0.000000 }
57 RB_BLEND_RED_F32: 0.000000
58 RB_BLEND_GREEN: { UINT = 0 | SINT = 0 | FLOAT = 0.000000 }
59 RB_BLEND_GREEN_F32: 0.007813
60 108ce084: 0000: 000320f0 00000000 00000000 00000000 3c0000ff
61 t0 write UNKNOWN_2152 (2152)
62 UNKNOWN_2152: 0
63 108ce098: 0000: 00002152 00000000
64 t0 write UNKNOWN_2153 (2153)
65 UNKNOWN_2153: 0
66 108ce0a0: 0000: 00002153 00000000
67 t0 write UNKNOWN_2154 (2154)
68 UNKNOWN_2154: 0
69 108ce0a8: 0000: 00002154 00000000
70 t0 write UNKNOWN_2155 (2155)
71 UNKNOWN_2155: 0
72 108ce0b0: 0000: 00002155 00000000
73 t0 write UNKNOWN_2156 (2156)
74 UNKNOWN_2156: 0
75 108ce0b8: 0000: 00002156 00000000
76 t0 write UNKNOWN_2157 (2157)
77 UNKNOWN_2157: 0
78 108ce0c0: 0000: 00002157 00000000
79 t0 write UNKNOWN_21C3 (21c3)
80 UNKNOWN_21C3: 0x1d
81 108ce0c8: 0000: 000021c3 0000001d
82 t0 write PC_GS_PARAM (21e5)
83 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS }
84 108ce0d0: 0000: 000021e5 00000000
85 t0 write UNKNOWN_21E6 (21e6)
86 UNKNOWN_21E6: 0x1
87 108ce0d8: 0000: 000021e6 00000001
88 t0 write PC_HS_PARAM (21e7)
89 PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING }
90 108ce0e0: 0000: 000021e7 00000000
91 t0 write UNKNOWN_22D7 (22d7)
92 UNKNOWN_22D7: 0
93 108ce0e8: 0000: 000022d7 00000000
94 t0 write TPL1_TP_TEX_OFFSET (2380)
95 TPL1_TP_TEX_OFFSET: 0
96 108ce0f0: 0000: 00002380 00000000
97 t0 write TPL1_TP_TEX_COUNT (2381)
98 TPL1_TP_TEX_COUNT: { VS = 16 | HS = 0 | DS = 0 | GS = 0 }
99 108ce0f8: 0000: 00002381 00000010
100 t0 write TPL1_TP_FS_TEX_COUNT (23a0)
101 TPL1_TP_FS_TEX_COUNT: 0x10
102 108ce100: 0000: 000023a0 00000010
103 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords)
104 { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 }
105 { ADDR_LO = 0 }
106 108ce108: 0000: c0014300 00040000 00000000
107 t0 write SP_VS_PVT_MEM_PARAM (22e2)
108 SP_VS_PVT_MEM_PARAM: 0x8000001
109 SP_VS_PVT_MEM_ADDR: 0x10cd7000
110 108ce114: 0000: 000122e2 08000001 10cd7000
111 t0 write SP_FS_PVT_MEM_PARAM (22ec)
112 SP_FS_PVT_MEM_PARAM: 0x8000001
113 SP_FS_PVT_MEM_ADDR: 0x10cd9000
114 108ce120: 0000: 000122ec 08000001 10cd9000
115 t0 write GRAS_SC_CONTROL (207b)
116 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 }
117 108ce12c: 0000: 0000207b 00000800
118 t0 write RB_MSAA_CONTROL (20a2)
119 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 }
120 108ce134: 0000: 000020a2 00001000
121 t0 write GRAS_CL_GB_CLIP_ADJ (2004)
122 GRAS_CL_GB_CLIP_ADJ: { HORZ = 0 | VERT = 0 }
123 108ce13c: 0000: 00002004 00000000
124 t0 write RB_ALPHA_CONTROL (20f8)
125 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS }
126 108ce144: 0000: 000020f8 00000e00
127 t0 write RB_FS_OUTPUT (20f9)
128 RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff }
129 108ce14c: 0000: 000020f9 ffff0000
130 t0 write GRAS_ALPHA_CONTROL (2073)
131 GRAS_ALPHA_CONTROL: { 0 }
132 108ce154: 0000: 00002073 00000000
133 t0 write VSC_BIN_SIZE (0c00)
134 VSC_BIN_SIZE: { WIDTH = 320 | HEIGHT = 320 }
135 108ce15c: 0000: 00000c00 0000014a
136 t0 write VSC_SIZE_ADDRESS (0c01)
137 VSC_SIZE_ADDRESS: 0x10cdb000
138 108ce164: 0000: 00000c01 10cdb000
139 t0 write VSC_PIPE_CONFIG[0].REG (0c08)
140 VSC_PIPE_CONFIG[0].REG: { X = 0 | Y = 0 | W = 1 | H = 1 }
141 VSC_PIPE_CONFIG[0x1].REG: { X = 0 | Y = 0 | W = 0 | H = 0 }
142 VSC_PIPE_CONFIG[0x2].REG: { X = 0 | Y = 0 | W = 0 | H = 0 }
143 VSC_PIPE_CONFIG[0x3].REG: { X = 0 | Y = 0 | W = 0 | H = 0 }
144 VSC_PIPE_CONFIG[0x4].REG: { X = 0 | Y = 0 | W = 0 | H = 0 }
145 VSC_PIPE_CONFIG[0x5].REG: { X = 0 | Y = 0 | W = 0 | H = 0 }
146 VSC_PIPE_CONFIG[0x6].REG: { X = 0 | Y = 0 | W = 0 | H = 0 }
147 VSC_PIPE_CONFIG[0x7].REG: { X = 0 | Y = 0 | W = 0 | H = 0 }
148 108ce16c: 0000: 00070c08 01100000 00000000 00000000 00000000 00000000 00000000 00000000
149 *
150 t0 write VSC_PIPE_DATA_ADDRESS[0].REG (0c10)
151 VSC_PIPE_DATA_ADDRESS[0].REG: 0x10cdc000
152 VSC_PIPE_DATA_ADDRESS[0x1].REG: 0x10d1c000
153 VSC_PIPE_DATA_ADDRESS[0x2].REG: 0x10d5c000
154 VSC_PIPE_DATA_ADDRESS[0x3].REG: 0x10d9c000
155 VSC_PIPE_DATA_ADDRESS[0x4].REG: 0x10ddc000
156 VSC_PIPE_DATA_ADDRESS[0x5].REG: 0x10e1c000
157 VSC_PIPE_DATA_ADDRESS[0x6].REG: 0x10e5c000
158 VSC_PIPE_DATA_ADDRESS[0x7].REG: 0x10e9c000
159 108ce190: 0000: 00070c10 10cdc000 10d1c000 10d5c000 10d9c000 10ddc000 10e1c000 10e5c000
160 108ce1b0: 0020: 10e9c000
161 t0 write VSC_PIPE_DATA_LENGTH[0].REG (0c18)
162 VSC_PIPE_DATA_LENGTH[0].REG: 0x3ffe0
163 VSC_PIPE_DATA_LENGTH[0x1].REG: 0x3ffe0
164 VSC_PIPE_DATA_LENGTH[0x2].REG: 0x3ffe0
165 VSC_PIPE_DATA_LENGTH[0x3].REG: 0x3ffe0
166 VSC_PIPE_DATA_LENGTH[0x4].REG: 0x3ffe0
167 VSC_PIPE_DATA_LENGTH[0x5].REG: 0x3ffe0
168 VSC_PIPE_DATA_LENGTH[0x6].REG: 0x3ffe0
169 VSC_PIPE_DATA_LENGTH[0x7].REG: 0x3ffe0
170 108ce1b4: 0000: 00070c18 0003ffe0 0003ffe0 0003ffe0 0003ffe0 0003ffe0 0003ffe0 0003ffe0
171 108ce1d4: 0020: 0003ffe0
172 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
173 108ce1d8: 0000: c0002600 00000000
174 t0 write RB_FRAME_BUFFER_DIMENSION (0ce0)
175 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 300 | HEIGHT = 300 }
176 108ce1e0: 0000: 00000ce0 012c012c
177 t0 write RB_MODE_CONTROL (20a0)
178 RB_MODE_CONTROL: { WIDTH = 320 | HEIGHT = 320 | ENABLE_GMEM }
179 108ce1e8: 0000: 000020a0 00010a0a
180 t0 write RB_DEPTH_INFO (2103)
181 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_24_8 | DEPTH_BASE = 0x64000 }
182 RB_DEPTH_PITCH: 1280
183 RB_DEPTH_PITCH2: 1280
184 108ce1f0: 0000: 00022103 00064002 00000028 00000028
185 t0 write RB_STENCIL_INFO (2108)
186 RB_STENCIL_INFO: { STENCIL_BASE = 0 }
187 RB_STENCIL_PITCH: 0
188 108ce200: 0000: 00012108 00000000 00000000
189 t0 write GRAS_DEPTH_CONTROL (2077)
190 GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_24_8 }
191 108ce20c: 0000: 00002077 00000002
192 t0 write PC_VSTREAM_CONTROL (21c2)
193 PC_VSTREAM_CONTROL: { SIZE = 0 | N = 0 }
194 108ce214: 0000: 000021c2 00000000
195 t3 opcode: (null) (4c) (4 dwords)
196 108ce21c: 0000: c0024c00 00000000 00000000 012b012b
197 t0 write RB_MRT[0].BUF_INFO (20a5)
198 RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WXYZ | COLOR_BUF_PITCH = 1280 }
199 RB_MRT[0].BASE: 0
200 RB_MRT[0].CONTROL3: { STRIDE = 1280 }
201 108ce22c: 0000: 000220a5 0014089a 00000000 00002800
202 t0 write RB_MRT[0x1].BUF_INFO (20aa)
203 RB_MRT[0x1].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 }
204 RB_MRT[0x1].BASE: 0
205 RB_MRT[0x1].CONTROL3: { STRIDE = 0 }
206 108ce23c: 0000: 000220aa 00000080 00000000 00000000
207 t0 write RB_MRT[0x2].BUF_INFO (20af)
208 RB_MRT[0x2].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 }
209 RB_MRT[0x2].BASE: 0
210 RB_MRT[0x2].CONTROL3: { STRIDE = 0 }
211 108ce24c: 0000: 000220af 00000080 00000000 00000000
212 t0 write RB_MRT[0x3].BUF_INFO (20b4)
213 RB_MRT[0x3].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 }
214 RB_MRT[0x3].BASE: 0
215 RB_MRT[0x3].CONTROL3: { STRIDE = 0 }
216 108ce25c: 0000: 000220b4 00000080 00000000 00000000
217 t0 write RB_MRT[0x4].BUF_INFO (20b9)
218 RB_MRT[0x4].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 }
219 RB_MRT[0x4].BASE: 0
220 RB_MRT[0x4].CONTROL3: { STRIDE = 0 }
221 108ce26c: 0000: 000220b9 00000080 00000000 00000000
222 t0 write RB_MRT[0x5].BUF_INFO (20be)
223 RB_MRT[0x5].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 }
224 RB_MRT[0x5].BASE: 0
225 RB_MRT[0x5].CONTROL3: { STRIDE = 0 }
226 108ce27c: 0000: 000220be 00000080 00000000 00000000
227 t0 write RB_MRT[0x6].BUF_INFO (20c3)
228 RB_MRT[0x6].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 }
229 RB_MRT[0x6].BASE: 0
230 RB_MRT[0x6].CONTROL3: { STRIDE = 0 }
231 108ce28c: 0000: 000220c3 00000080 00000000 00000000
232 t0 write RB_MRT[0x7].BUF_INFO (20c8)
233 RB_MRT[0x7].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 }
234 RB_MRT[0x7].BASE: 0
235 RB_MRT[0x7].CONTROL3: { STRIDE = 0 }
236 108ce29c: 0000: 000220c8 00000080 00000000 00000000
237 t0 write RB_BIN_OFFSET (210d)
238 RB_BIN_OFFSET: { X = 0 | Y = 0 }
239 108ce2ac: 0000: 0000210d 00000000
240 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c)
241 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 }
242 GRAS_SC_SCREEN_SCISSOR_BR: { X = 299 | Y = 299 }
243 108ce2b4: 0000: 0001207c 00000000 012b012b
244 t0 write RB_RENDER_CONTROL (20a1)
245 RB_RENDER_CONTROL: { 0x8 }
246 108ce2c0: 0000: 000020a1 00000008
247 t0 write CP_SCRATCH[0x6].REG (057e)
248 CP_SCRATCH[0x6].REG: 0x73
249 :0,0,115,0
250 108ce2c8: 0000: 0000057e 00000073
251 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords)
252 ibaddr:109ce000
253 ibsize:00000f2e
254 t0 write CP_SCRATCH[0x5].REG (057d)
255 CP_SCRATCH[0x5].REG: 0x1
256 :0,1,115,0
257 109ce000: 0000: 0000057d 00000001
258 t0 write RB_RENDER_COMPONENTS (20fb)
259 RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 }
260 109ce008: 0000: 000020fb 0000000f
261 t0 write RB_ALPHA_CONTROL (20f8)
262 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_NEVER }
263 109ce010: 0000: 000020f8 00000000
264 t0 write RB_STENCIL_CONTROL (2106)
265 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP }
266 RB_STENCIL_CONTROL2: { 0 }
267 109ce018: 0000: 00012106 00000000 00000000
268 t0 write RB_STENCILREFMASK (210b)
269 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
270 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
271 109ce024: 0000: 0001210b 00000000 00000000
272 t0 write RB_DEPTH_CONTROL (2101)
273 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_ALWAYS | Z_TEST_ENABLE }
274 109ce030: 0000: 00002101 80000076
275 t0 write GRAS_ALPHA_CONTROL (2073)
276 GRAS_ALPHA_CONTROL: { 0 }
277 109ce038: 0000: 00002073 00000000
278 t0 write GRAS_SU_MODE_CONTROL (2078)
279 GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.000000 | RENDERING_PASS }
280 109ce040: 0000: 00002078 00100004
281 t0 write GRAS_SU_POINT_MINMAX (2070)
282 GRAS_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
283 GRAS_SU_POINT_SIZE: 0.000000
284 109ce048: 0000: 00012070 00000000 00000000
285 t0 write GRAS_SU_POLY_OFFSET_SCALE (2074)
286 GRAS_SU_POLY_OFFSET_SCALE: 0.000000
287 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000
288 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000
289 109ce054: 0000: 00022074 00000000 00000000 00000000
290 t0 write GRAS_CL_CLIP_CNTL (2000)
291 GRAS_CL_CLIP_CNTL: { 0x80000 }
292 109ce064: 0000: 00002000 00080000
293 t0 write PC_PRIM_VTX_CNTL (21c4)
294 PC_PRIM_VTX_CNTL: { VAROUT = 0 | PROVOKING_VTX_LAST }
295 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
296 109ce06c: 0000: 000121c4 02000000 00000012
297 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c)
298 GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 }
299 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
300 109ce078: 0000: 0001209c 012b012b 00000000
301 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
302 109ce084: 0000: c0002600 00000000
303 t0 write GRAS_CL_VPORT_XOFFSET_0 (2008)
304 GRAS_CL_VPORT_XOFFSET_0: 150.000000
305 GRAS_CL_VPORT_XSCALE_0: 150.000000
306 GRAS_CL_VPORT_YOFFSET_0: 150.000000
307 GRAS_CL_VPORT_YSCALE_0: -150.000000
308 GRAS_CL_VPORT_ZOFFSET_0: 0.000000
309 GRAS_CL_VPORT_ZSCALE_0: 1.000000
310 109ce08c: 0000: 00052008 43160000 43160000 43160000 c3160000 00000000 3f800000
311 t0 write RB_VPORT_Z_CLAMP[0].MIN (2120)
312 RB_VPORT_Z_CLAMP[0].MIN: 0
313 RB_VPORT_Z_CLAMP[0].MAX: 0xffffff
314 109ce0a8: 0000: 00012120 00000000 00ffffff
315 t0 write HLSQ_UPDATE_CONTROL (23db)
316 HLSQ_UPDATE_CONTROL: 0x3
317 109ce0b4: 0000: 000023db 00000003
318 t0 write HLSQ_CONTROL_0_REG (23c0)
319 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE }
320 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x }
321 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x }
322 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
323 HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 }
324 109ce0bc: 0000: 000423c0 28000250 fcfc0100 fff3f3f0 fcfcfcfc 00fcfcfc
325 t0 write HLSQ_VS_CONTROL_REG (23c5)
326 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 }
327 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 }
328 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
329 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
330 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
331 109ce0d4: 0000: 000423c5 01000042 017e423e 007e4200 007e4200 007e4200
332 t0 write SP_SP_CTRL_REG (22c0)
333 SP_SP_CTRL_REG: { 0x140010 }
334 109ce0ec: 0000: 000022c0 00140010
335 t0 write SP_INSTR_CACHE_CTRL (22c1)
336 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f }
337 109ce0f4: 0000: 000022c1 000005ff
338 t0 write SP_VS_LENGTH_REG (22e5)
339 SP_VS_LENGTH_REG: 1
340 109ce0fc: 0000: 000022e5 00000001
341 t0 write SP_VS_CTRL_REG0 (22c4)
342 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE }
343 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 4 }
344 SP_VS_PARAM_REG: { POSREGID = r0.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 0 }
345 109ce104: 0000: 000222c4 00200400 04000042 0000fc00
346 t0 write SP_VS_OBJ_OFFSET_REG (22e0)
347 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 }
348 SP_VS_OBJ_START: 0x1073c000
349 109ce114: 0000: 000122e0 00000000 1073c000
350 t0 write SP_FS_LENGTH_REG (22ef)
351 SP_FS_LENGTH_REG: 1
352 109ce120: 0000: 000022ef 00000001
353 t0 write SP_FS_CTRL_REG0 (22e8)
354 SP_FS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE }
355 SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | 0x80000000 }
356 109ce128: 0000: 000122e8 00340400 8000003e
357 t0 write SP_FS_OBJ_OFFSET_REG (22ea)
358 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
359 SP_FS_OBJ_START: 0x1073b000
360 109ce134: 0000: 000122ea 7e420000 1073b000
361 t0 write SP_HS_OBJ_OFFSET_REG (230d)
362 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
363 109ce140: 0000: 0000230d 7e420000
364 t0 write SP_DS_OBJ_OFFSET_REG (2334)
365 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
366 109ce148: 0000: 00002334 7e420000
367 t0 write SP_GS_OBJ_OFFSET_REG (235b)
368 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
369 109ce150: 0000: 0000235b 7e420000
370 t0 write GRAS_CNTL (2003)
371 GRAS_CNTL: { 0 }
372 109ce158: 0000: 00002003 00000000
373 t0 write RB_RENDER_CONTROL2 (20a3)
374 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 }
375 109ce160: 0000: 000020a3 00000000
376 t0 write RB_FS_OUTPUT_REG (2100)
377 RB_FS_OUTPUT_REG: { MRT = 1 }
378 109ce168: 0000: 00002100 00000001
379 t0 write SP_FS_OUTPUT_REG (22f0)
380 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x }
381 109ce170: 0000: 000022f0 0000fc01
382 t0 write SP_FS_MRT[0].REG (22f1)
383 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM }
384 SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 }
385 SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 }
386 SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 }
387 SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 }
388 SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 }
389 SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 }
390 SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 }
391 109ce178: 0000: 000722f1 0001a000 00000000 00000000 00000000 00000000 00000000 00000000
392 *
393 t0 write VPC_ATTR (2140)
394 VPC_ATTR: { TOTALATTR = 0 | THRDASSIGN = 1 | 0x40000000 }
395 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 0 | NUMNONPOSVSVAR = 0 }
396 109ce19c: 0000: 00012140 40001000 00000000
397 t0 write VPC_VARYING_INTERP[0].MODE (2142)
398 VPC_VARYING_INTERP[0].MODE: 0
399 VPC_VARYING_INTERP[0x1].MODE: 0
400 VPC_VARYING_INTERP[0x2].MODE: 0
401 VPC_VARYING_INTERP[0x3].MODE: 0
402 VPC_VARYING_INTERP[0x4].MODE: 0
403 VPC_VARYING_INTERP[0x5].MODE: 0
404 VPC_VARYING_INTERP[0x6].MODE: 0
405 VPC_VARYING_INTERP[0x7].MODE: 0
406 109ce1a8: 0000: 00072142 00000000 00000000 00000000 00000000 00000000 00000000 00000000
407 *
408 t0 write VPC_VARYING_PS_REPL[0].MODE (214a)
409 VPC_VARYING_PS_REPL[0].MODE: 0
410 VPC_VARYING_PS_REPL[0x1].MODE: 0
411 VPC_VARYING_PS_REPL[0x2].MODE: 0
412 VPC_VARYING_PS_REPL[0x3].MODE: 0
413 VPC_VARYING_PS_REPL[0x4].MODE: 0
414 VPC_VARYING_PS_REPL[0x5].MODE: 0
415 VPC_VARYING_PS_REPL[0x6].MODE: 0
416 VPC_VARYING_PS_REPL[0x7].MODE: 0
417 109ce1cc: 0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000
418 *
419 t3 opcode: CP_LOAD_STATE4 (30) (35 dwords)
420 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 }
421 { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 }
422 :0:0000:0000[03000000x_00000000x] end
423 :0:0001:0001[00000000x_00000000x] nop
424 :0:0002:0002[00000000x_00000000x] nop
425 :0:0003:0003[00000000x_00000000x] nop
426 :0:0004:0004[00000000x_00000000x] nop
427 Register Stats:
428 - used (half): (cnt=0, max=0)
429 - used (full): (cnt=0, max=0)
430 - input (half): (cnt=0, max=0)
431 - input (full): (cnt=0, max=0)
432 - max const: 0
433
434 - output (half): (cnt=0, max=0) (estimated)
435 - output (full): (cnt=0, max=0) (estimated)
436 - shaderdb: 5 instructions, 4 nops, 1 non-nops, (5 instlen), 0 half, 0 full
437 - shaderdb: 0 (ss), 0 (sy)
438 109ce1f0: 0000: c0213000 00600000 00000000 00000000 03000000 00000000 00000000 00000000
439 *
440 t3 opcode: CP_LOAD_STATE4 (30) (35 dwords)
441 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 }
442 { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 }
443 :1:0000:0000[20244000x_00000000x] mov.f32f32 r0.x, c0.x
444 :1:0001:0001[20244001x_00000001x] mov.f32f32 r0.y, c0.y
445 :1:0002:0002[20244002x_00000002x] mov.f32f32 r0.z, c0.z
446 :1:0003:0003[20244003x_00000003x] mov.f32f32 r0.w, c0.w
447 :0:0004:0004[03000000x_00000000x] end
448 :0:0005:0005[00000000x_00000000x] nop
449 :0:0006:0006[00000000x_00000000x] nop
450 :0:0007:0007[00000000x_00000000x] nop
451 :0:0008:0008[00000000x_00000000x] nop
452 Register Stats:
453 - used (half): (cnt=0, max=0)
454 - used (full): 0-3 (cnt=4, max=3)
455 - input (half): (cnt=0, max=0)
456 - input (full): (cnt=0, max=0)
457 - max const: 3
458
459 - output (half): (cnt=0, max=0) (estimated)
460 - output (full): 0-3 (cnt=4, max=3) (estimated)
461 - shaderdb: 9 instructions, 8 nops, 1 non-nops, (9 instlen), 0 half, 1 full
462 - shaderdb: 0 (ss), 0 (sy)
463 109ce27c: 0000: c0213000 00700000 00000000 00000000 20244000 00000001 20244001 00000002
464 109ce29c: 0020: 20244002 00000003 20244003 00000000 03000000 00000000 00000000 00000000
465 *
466 t3 opcode: CP_LOAD_STATE4 (30) (19 dwords)
467 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 4 }
468 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 }
469 109ce314: 0.000000 0.000000 0.000000 0.000000 -nan -nan 0.000000 0.000000
470 109ce334: 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000
471 109ce314: 0000: 00000000 00000000 00000000 00000000 ffffffff ffffffff 00000405 00000000
472 109ce334: 0020: 00000000 00000000 02070000 00000000 00000000 00000000 00000000 00000000
473 109ce308: 0000: c0113000 01300000 00000001 00000000 00000000 00000000 00000000 ffffffff
474 109ce328: 0020: ffffffff 00000405 00000000 00000000 00000000 02070000 00000000 00000000
475 *
476 t0 write RB_MRT[0].CONTROL (20a4)
477 RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf }
478 109ce354: 0000: 000020a4 0f000c00
479 t0 write RB_MRT[0].BLEND_CONTROL (20a8)
480 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
481 109ce35c: 0000: 000020a8 00000000
482 t0 write RB_MRT[0x1].CONTROL (20a9)
483 RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 }
484 109ce364: 0000: 000020a9 00000c00
485 t0 write RB_MRT[0x1].BLEND_CONTROL (20ad)
486 RB_MRT[0x1].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
487 109ce36c: 0000: 000020ad 00000000
488 t0 write RB_MRT[0x2].CONTROL (20ae)
489 RB_MRT[0x2].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 }
490 109ce374: 0000: 000020ae 00000c00
491 t0 write RB_MRT[0x2].BLEND_CONTROL (20b2)
492 RB_MRT[0x2].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
493 109ce37c: 0000: 000020b2 00000000
494 t0 write RB_MRT[0x3].CONTROL (20b3)
495 RB_MRT[0x3].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 }
496 109ce384: 0000: 000020b3 00000c00
497 t0 write RB_MRT[0x3].BLEND_CONTROL (20b7)
498 RB_MRT[0x3].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
499 109ce38c: 0000: 000020b7 00000000
500 t0 write RB_MRT[0x4].CONTROL (20b8)
501 RB_MRT[0x4].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 }
502 109ce394: 0000: 000020b8 00000c00
503 t0 write RB_MRT[0x4].BLEND_CONTROL (20bc)
504 RB_MRT[0x4].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
505 109ce39c: 0000: 000020bc 00000000
506 t0 write RB_MRT[0x5].CONTROL (20bd)
507 RB_MRT[0x5].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 }
508 109ce3a4: 0000: 000020bd 00000c00
509 t0 write RB_MRT[0x5].BLEND_CONTROL (20c1)
510 RB_MRT[0x5].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
511 109ce3ac: 0000: 000020c1 00000000
512 t0 write RB_MRT[0x6].CONTROL (20c2)
513 RB_MRT[0x6].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 }
514 109ce3b4: 0000: 000020c2 00000c00
515 t0 write RB_MRT[0x6].BLEND_CONTROL (20c6)
516 RB_MRT[0x6].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
517 109ce3bc: 0000: 000020c6 00000000
518 t0 write RB_MRT[0x7].CONTROL (20c7)
519 RB_MRT[0x7].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 }
520 109ce3c4: 0000: 000020c7 00000c00
521 t0 write RB_MRT[0x7].BLEND_CONTROL (20cb)
522 RB_MRT[0x7].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
523 109ce3cc: 0000: 000020cb 00000000
524 t0 write RB_FS_OUTPUT (20f9)
525 RB_FS_OUTPUT: { ENABLE_BLEND = 0 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff }
526 109ce3d4: 0000: 000020f9 ffff0100
527 t0 write RB_BLEND_RED (20f0)
528 RB_BLEND_RED: { UINT = 0 | SINT = 0 | FLOAT = 0.000000 }
529 RB_BLEND_RED_F32: 0.000000
530 RB_BLEND_GREEN: { UINT = 0 | SINT = 0 | FLOAT = 0.000000 }
531 RB_BLEND_GREEN_F32: 0.000000
532 RB_BLEND_BLUE: { UINT = 0 | SINT = 0 | FLOAT = 0.000000 }
533 RB_BLEND_BLUE_F32: 0.000000
534 RB_BLEND_ALPHA: { UINT = 0 | SINT = 0 | FLOAT = 0.000000 }
535 RB_BLEND_ALPHA_F32: 0.000000
536 109ce3dc: 0000: 000720f0 00000000 00000000 00000000 00000000 00000000 00000000 00000000
537 *
538 t0 write VFD_FETCH[0].INSTR_0 (220a)
539 VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 12 }
540 VFD_FETCH[0].INSTR_1: 0x1074a000
541 VFD_FETCH[0].INSTR_2: { SIZE = 0x1000 }
542 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 }
543 109ce400: 0000: 0003220a 0000060b 1074a000 00001000 00000001
544 t0 write VFD_DECODE[0].INSTR (228a)
545 VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID }
546 109ce414: 0000: 0000228a 2c0000df
547 t0 write VFD_CONTROL_0 (2200)
548 VFD_CONTROL_0: { TOTALATTRTOVS = 4 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 | 0xa0000 }
549 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x }
550 VFD_CONTROL_2: 0
551 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x }
552 VFD_CONTROL_4: 0
553 109ce41c: 0000: 00042200 041a0004 fcfc0081 00000000 0000fc00 00000000
554 t0 write UCHE_INVALIDATE0 (0e8a)
555 UCHE_INVALIDATE0: 0
556 UCHE_INVALIDATE1: 0x12
557 109ce434: 0000: 00010e8a 00000000 00000012
558 t0 write VFD_INDEX_OFFSET (2208)
559 VFD_INDEX_OFFSET: 0
560 UNKNOWN_2209: 0
561 109ce440: 0000: 00012208 00000000 00000000
562 t0 write PC_RESTART_INDEX (21c6)
563 PC_RESTART_INDEX: 0xffffffff
564 109ce44c: 0000: 000021c6 ffffffff
565 t0 write CP_SCRATCH[0x7].REG (057f)
566 CP_SCRATCH[0x7].REG: 0x2
567 :0,1,115,2
568 109ce454: 0000: 0000057f 00000002
569 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
570 { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS }
571 { NUM_INSTANCES = 1 }
572 { NUM_INDICES = 2 }
573 draw[0] register values
574 !+ 00000001 RBBM_PERFCTR_CTL: 0x1
575 !+ 00000001 CP_SCRATCH[0x5].REG: 0x1
576 :0,1,115,2
577 !+ 00000073 CP_SCRATCH[0x6].REG: 0x73
578 :0,1,115,2
579 !+ 00000002 CP_SCRATCH[0x7].REG: 0x2
580 :0,1,115,2
581 !+ 0000014a VSC_BIN_SIZE: { WIDTH = 320 | HEIGHT = 320 }
582 !+ 10cdb000 VSC_SIZE_ADDRESS: 0x10cdb000
583 !+ 01100000 VSC_PIPE_CONFIG[0].REG: { X = 0 | Y = 0 | W = 1 | H = 1 }
584 + 00000000 VSC_PIPE_CONFIG[0x1].REG: { X = 0 | Y = 0 | W = 0 | H = 0 }
585 + 00000000 VSC_PIPE_CONFIG[0x2].REG: { X = 0 | Y = 0 | W = 0 | H = 0 }
586 + 00000000 VSC_PIPE_CONFIG[0x3].REG: { X = 0 | Y = 0 | W = 0 | H = 0 }
587 + 00000000 VSC_PIPE_CONFIG[0x4].REG: { X = 0 | Y = 0 | W = 0 | H = 0 }
588 + 00000000 VSC_PIPE_CONFIG[0x5].REG: { X = 0 | Y = 0 | W = 0 | H = 0 }
589 + 00000000 VSC_PIPE_CONFIG[0x6].REG: { X = 0 | Y = 0 | W = 0 | H = 0 }
590 + 00000000 VSC_PIPE_CONFIG[0x7].REG: { X = 0 | Y = 0 | W = 0 | H = 0 }
591 !+ 10cdc000 VSC_PIPE_DATA_ADDRESS[0].REG: 0x10cdc000
592 !+ 10d1c000 VSC_PIPE_DATA_ADDRESS[0x1].REG: 0x10d1c000
593 !+ 10d5c000 VSC_PIPE_DATA_ADDRESS[0x2].REG: 0x10d5c000
594 !+ 10d9c000 VSC_PIPE_DATA_ADDRESS[0x3].REG: 0x10d9c000
595 !+ 10ddc000 VSC_PIPE_DATA_ADDRESS[0x4].REG: 0x10ddc000
596 !+ 10e1c000 VSC_PIPE_DATA_ADDRESS[0x5].REG: 0x10e1c000
597 !+ 10e5c000 VSC_PIPE_DATA_ADDRESS[0x6].REG: 0x10e5c000
598 !+ 10e9c000 VSC_PIPE_DATA_ADDRESS[0x7].REG: 0x10e9c000
599 !+ 0003ffe0 VSC_PIPE_DATA_LENGTH[0].REG: 0x3ffe0
600 !+ 0003ffe0 VSC_PIPE_DATA_LENGTH[0x1].REG: 0x3ffe0
601 !+ 0003ffe0 VSC_PIPE_DATA_LENGTH[0x2].REG: 0x3ffe0
602 !+ 0003ffe0 VSC_PIPE_DATA_LENGTH[0x3].REG: 0x3ffe0
603 !+ 0003ffe0 VSC_PIPE_DATA_LENGTH[0x4].REG: 0x3ffe0
604 !+ 0003ffe0 VSC_PIPE_DATA_LENGTH[0x5].REG: 0x3ffe0
605 !+ 0003ffe0 VSC_PIPE_DATA_LENGTH[0x6].REG: 0x3ffe0
606 !+ 0003ffe0 VSC_PIPE_DATA_LENGTH[0x7].REG: 0x3ffe0
607 + 00000000 GRAS_DEBUG_ECO_CONTROL: 0
608 !+ 00000006 UNKNOWN_0CC5: 0x6
609 + 00000000 UNKNOWN_0CC6: 0
610 !+ 012c012c RB_FRAME_BUFFER_DIMENSION: { WIDTH = 300 | HEIGHT = 300 }
611 !+ 00000001 UNKNOWN_0D01: 0x1
612 + 00000000 HLSQ_MODE_CONTROL: 0
613 + 00000000 UNKNOWN_0E42: 0
614 + 00000000 UCHE_CACHE_MODE_CONTROL: 0
615 + 00000000 UCHE_INVALIDATE0: 0
616 !+ 00000012 UCHE_INVALIDATE1: 0x12
617 !+ 00000007 UCHE_CACHE_WAYS_VFD: 0x7
618 !+ 00040000 UNKNOWN_0EC2: 0x40000
619 !+ 00000006 SP_MODE_CONTROL: 0x6
620 !+ 0000003a TPL1_TP_MODE_CONTROL: 0x3a
621 !+ 00080000 GRAS_CL_CLIP_CNTL: { 0x80000 }
622 + 00000000 UNKNOWN_2001: 0
623 + 00000000 GRAS_CNTL: { 0 }
624 + 00000000 GRAS_CL_GB_CLIP_ADJ: { HORZ = 0 | VERT = 0 }
625 !+ 43160000 GRAS_CL_VPORT_XOFFSET_0: 150.000000
626 !+ 43160000 GRAS_CL_VPORT_XSCALE_0: 150.000000
627 !+ 43160000 GRAS_CL_VPORT_YOFFSET_0: 150.000000
628 !+ c3160000 GRAS_CL_VPORT_YSCALE_0: -150.000000
629 + 00000000 GRAS_CL_VPORT_ZOFFSET_0: 0.000000
630 !+ 3f800000 GRAS_CL_VPORT_ZSCALE_0: 1.000000
631 + 00000000 GRAS_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
632 + 00000000 GRAS_SU_POINT_SIZE: 0.000000
633 + 00000000 GRAS_ALPHA_CONTROL: { 0 }
634 + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000
635 + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000
636 + 00000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000
637 !+ 00000002 GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_24_8 }
638 !+ 00100004 GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.000000 | RENDERING_PASS }
639 !+ 00000800 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 }
640 + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 }
641 !+ 012b012b GRAS_SC_SCREEN_SCISSOR_BR: { X = 299 | Y = 299 }
642 !+ 012b012b GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 }
643 + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
644 !+ 00010a0a RB_MODE_CONTROL: { WIDTH = 320 | HEIGHT = 320 | ENABLE_GMEM }
645 !+ 00000008 RB_RENDER_CONTROL: { 0x8 }
646 !+ 00001000 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 }
647 + 00000000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 }
648 !+ 0f000c00 RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf }
649 !+ 0014089a RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WXYZ | COLOR_BUF_PITCH = 1280 }
650 + 00000000 RB_MRT[0].BASE: 0
651 !+ 00002800 RB_MRT[0].CONTROL3: { STRIDE = 1280 }
652 + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
653 !+ 00000c00 RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 }
654 !+ 00000080 RB_MRT[0x1].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 }
655 + 00000000 RB_MRT[0x1].BASE: 0
656 + 00000000 RB_MRT[0x1].CONTROL3: { STRIDE = 0 }
657 + 00000000 RB_MRT[0x1].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
658 !+ 00000c00 RB_MRT[0x2].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 }
659 !+ 00000080 RB_MRT[0x2].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 }
660 + 00000000 RB_MRT[0x2].BASE: 0
661 + 00000000 RB_MRT[0x2].CONTROL3: { STRIDE = 0 }
662 + 00000000 RB_MRT[0x2].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
663 !+ 00000c00 RB_MRT[0x3].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 }
664 !+ 00000080 RB_MRT[0x3].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 }
665 + 00000000 RB_MRT[0x3].BASE: 0
666 + 00000000 RB_MRT[0x3].CONTROL3: { STRIDE = 0 }
667 + 00000000 RB_MRT[0x3].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
668 !+ 00000c00 RB_MRT[0x4].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 }
669 !+ 00000080 RB_MRT[0x4].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 }
670 + 00000000 RB_MRT[0x4].BASE: 0
671 + 00000000 RB_MRT[0x4].CONTROL3: { STRIDE = 0 }
672 + 00000000 RB_MRT[0x4].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
673 !+ 00000c00 RB_MRT[0x5].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 }
674 !+ 00000080 RB_MRT[0x5].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 }
675 + 00000000 RB_MRT[0x5].BASE: 0
676 + 00000000 RB_MRT[0x5].CONTROL3: { STRIDE = 0 }
677 + 00000000 RB_MRT[0x5].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
678 !+ 00000c00 RB_MRT[0x6].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 }
679 !+ 00000080 RB_MRT[0x6].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 }
680 + 00000000 RB_MRT[0x6].BASE: 0
681 + 00000000 RB_MRT[0x6].CONTROL3: { STRIDE = 0 }
682 + 00000000 RB_MRT[0x6].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
683 !+ 00000c00 RB_MRT[0x7].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 }
684 !+ 00000080 RB_MRT[0x7].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 }
685 + 00000000 RB_MRT[0x7].BASE: 0
686 + 00000000 RB_MRT[0x7].CONTROL3: { STRIDE = 0 }
687 + 00000000 RB_MRT[0x7].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
688 + 00000000 UNKNOWN_20EF: 0
689 + 00000000 RB_BLEND_RED: { UINT = 0 | SINT = 0 | FLOAT = 0.000000 }
690 + 00000000 RB_BLEND_RED_F32: 0.000000
691 + 00000000 RB_BLEND_GREEN: { UINT = 0 | SINT = 0 | FLOAT = 0.000000 }
692 + 00000000 RB_BLEND_GREEN_F32: 0.000000
693 + 00000000 RB_BLEND_BLUE: { UINT = 0 | SINT = 0 | FLOAT = 0.000000 }
694 + 00000000 RB_BLEND_BLUE_F32: 0.000000
695 + 00000000 RB_BLEND_ALPHA: { UINT = 0 | SINT = 0 | FLOAT = 0.000000 }
696 + 00000000 RB_BLEND_ALPHA_F32: 0.000000
697 + 00000000 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_NEVER }
698 !+ ffff0100 RB_FS_OUTPUT: { ENABLE_BLEND = 0 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff }
699 !+ 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 }
700 !+ 00000001 RB_FS_OUTPUT_REG: { MRT = 1 }
701 !+ 80000076 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_ALWAYS | Z_TEST_ENABLE }
702 !+ 00064002 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_24_8 | DEPTH_BASE = 0x64000 }
703 !+ 00000028 RB_DEPTH_PITCH: 1280
704 !+ 00000028 RB_DEPTH_PITCH2: 1280
705 + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP }
706 + 00000000 RB_STENCIL_CONTROL2: { 0 }
707 + 00000000 RB_STENCIL_INFO: { STENCIL_BASE = 0 }
708 + 00000000 RB_STENCIL_PITCH: 0
709 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
710 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
711 + 00000000 RB_BIN_OFFSET: { X = 0 | Y = 0 }
712 + 00000000 RB_VPORT_Z_CLAMP[0].MIN: 0
713 !+ 00ffffff RB_VPORT_Z_CLAMP[0].MAX: 0xffffff
714 !+ 40001000 VPC_ATTR: { TOTALATTR = 0 | THRDASSIGN = 1 | 0x40000000 }
715 + 00000000 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 0 | NUMNONPOSVSVAR = 0 }
716 + 00000000 VPC_VARYING_INTERP[0].MODE: 0
717 + 00000000 VPC_VARYING_INTERP[0x1].MODE: 0
718 + 00000000 VPC_VARYING_INTERP[0x2].MODE: 0
719 + 00000000 VPC_VARYING_INTERP[0x3].MODE: 0
720 + 00000000 VPC_VARYING_INTERP[0x4].MODE: 0
721 + 00000000 VPC_VARYING_INTERP[0x5].MODE: 0
722 + 00000000 VPC_VARYING_INTERP[0x6].MODE: 0
723 + 00000000 VPC_VARYING_INTERP[0x7].MODE: 0
724 + 00000000 VPC_VARYING_PS_REPL[0].MODE: 0
725 + 00000000 VPC_VARYING_PS_REPL[0x1].MODE: 0
726 + 00000000 VPC_VARYING_PS_REPL[0x2].MODE: 0
727 + 00000000 VPC_VARYING_PS_REPL[0x3].MODE: 0
728 + 00000000 VPC_VARYING_PS_REPL[0x4].MODE: 0
729 + 00000000 VPC_VARYING_PS_REPL[0x5].MODE: 0
730 + 00000000 VPC_VARYING_PS_REPL[0x6].MODE: 0
731 + 00000000 VPC_VARYING_PS_REPL[0x7].MODE: 0
732 + 00000000 UNKNOWN_2152: 0
733 + 00000000 UNKNOWN_2153: 0
734 + 00000000 UNKNOWN_2154: 0
735 + 00000000 UNKNOWN_2155: 0
736 + 00000000 UNKNOWN_2156: 0
737 + 00000000 UNKNOWN_2157: 0
738 + 00000000 PC_VSTREAM_CONTROL: { SIZE = 0 | N = 0 }
739 !+ 0000001d UNKNOWN_21C3: 0x1d
740 !+ 02000000 PC_PRIM_VTX_CNTL: { VAROUT = 0 | PROVOKING_VTX_LAST }
741 !+ 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
742 !+ ffffffff PC_RESTART_INDEX: 0xffffffff
743 + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS }
744 !+ 00000001 UNKNOWN_21E6: 0x1
745 + 00000000 PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING }
746 !+ 041a0004 VFD_CONTROL_0: { TOTALATTRTOVS = 4 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 | 0xa0000 }
747 !+ fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x }
748 + 00000000 VFD_CONTROL_2: 0
749 !+ 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x }
750 + 00000000 VFD_CONTROL_4: 0
751 + 00000000 VFD_INDEX_OFFSET: 0
752 + 00000000 UNKNOWN_2209: 0
753 !+ 0000060b VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 12 }
754 !+ 1074a000 VFD_FETCH[0].INSTR_1: 0x1074a000
755 !+ 00001000 VFD_FETCH[0].INSTR_2: { SIZE = 0x1000 }
756 !+ 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 }
757 !+ 2c0000df VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID }
758 !+ 00140010 SP_SP_CTRL_REG: { 0x140010 }
759 !+ 000005ff SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f }
760 !+ 00200400 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE }
761 !+ 04000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 4 }
762 !+ 0000fc00 SP_VS_PARAM_REG: { POSREGID = r0.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 0 }
763 + 00000000 UNKNOWN_22D7: 0
764 + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 }
765 !+ 1073c000 SP_VS_OBJ_START: 0x1073c000
766 !+ 08000001 SP_VS_PVT_MEM_PARAM: 0x8000001
767 !+ 10cd7000 SP_VS_PVT_MEM_ADDR: 0x10cd7000
768 !+ 00000001 SP_VS_LENGTH_REG: 1
769 !+ 00340400 SP_FS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE }
770 !+ 8000003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | 0x80000000 }
771 !+ 7e420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
772 !+ 1073b000 SP_FS_OBJ_START: 0x1073b000
773 !+ 08000001 SP_FS_PVT_MEM_PARAM: 0x8000001
774 !+ 10cd9000 SP_FS_PVT_MEM_ADDR: 0x10cd9000
775 !+ 00000001 SP_FS_LENGTH_REG: 1
776 !+ 0000fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x }
777 !+ 0001a000 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM }
778 + 00000000 SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 }
779 + 00000000 SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 }
780 + 00000000 SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 }
781 + 00000000 SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 }
782 + 00000000 SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 }
783 + 00000000 SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 }
784 + 00000000 SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 }
785 !+ 7e420000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
786 !+ 7e420000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
787 !+ 7e420000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
788 + 00000000 TPL1_TP_TEX_OFFSET: 0
789 !+ 00000010 TPL1_TP_TEX_COUNT: { VS = 16 | HS = 0 | DS = 0 | GS = 0 }
790 !+ 00000010 TPL1_TP_FS_TEX_COUNT: 0x10
791 !+ 28000250 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE }
792 !+ fcfc0100 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x }
793 !+ fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x }
794 !+ fcfcfcfc HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
795 !+ 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 }
796 !+ 01000042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 }
797 !+ 017e423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 }
798 !+ 007e4200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
799 !+ 007e4200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
800 !+ 007e4200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
801 !+ 00000003 HLSQ_UPDATE_CONTROL: 0x3
802 109ce45c: 0000: c0023800 00000888 00000001 00000002
803 t0 write CP_SCRATCH[0x7].REG (057f)
804 CP_SCRATCH[0x7].REG: 0x3
805 :0,1,115,3
806 109ce46c: 0000: 0000057f 00000003
807 t0 write CP_SCRATCH[0x5].REG (057d)
808 CP_SCRATCH[0x5].REG: 0x7
809 :0,7,115,3
810 109ce474: 0000: 0000057d 00000007
811 t0 write RB_ALPHA_CONTROL (20f8)
812 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_NEVER }
813 109ce47c: 0000: 000020f8 00000000
814 t0 write RB_STENCIL_CONTROL (2106)
815 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP }
816 RB_STENCIL_CONTROL2: { 0 }
817 109ce484: 0000: 00012106 00000000 00000000
818 t0 write RB_STENCILREFMASK (210b)
819 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
820 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
821 109ce490: 0000: 0001210b 00000000 00000000
822 t0 write RB_DEPTH_CONTROL (2101)
823 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE }
824 109ce49c: 0000: 00002101 80000016
825 t0 write GRAS_ALPHA_CONTROL (2073)
826 GRAS_ALPHA_CONTROL: { 0 }
827 109ce4a4: 0000: 00002073 00000000
828 t0 write GRAS_SU_MODE_CONTROL (2078)
829 GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 | RENDERING_PASS }
830 109ce4ac: 0000: 00002078 00100012
831 t0 write GRAS_SU_POINT_MINMAX (2070)
832 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 }
833 GRAS_SU_POINT_SIZE: 1.000000
834 109ce4b4: 0000: 00012070 00100010 00000010
835 t0 write GRAS_SU_POLY_OFFSET_SCALE (2074)
836 GRAS_SU_POLY_OFFSET_SCALE: 0.000000
837 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000
838 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000
839 109ce4c0: 0000: 00022074 00000000 00000000 00000000
840 t0 write GRAS_CL_CLIP_CNTL (2000)
841 GRAS_CL_CLIP_CNTL: { 0x80000 }
842 109ce4d0: 0000: 00002000 00080000
843 t0 write PC_PRIM_VTX_CNTL (21c4)
844 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
845 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
846 109ce4d8: 0000: 000121c4 02000001 00000012
847 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c)
848 GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 }
849 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
850 109ce4e4: 0000: 0001209c 012b012b 00000000
851 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
852 109ce4f0: 0000: c0002600 00000000
853 t0 write GRAS_CL_VPORT_XOFFSET_0 (2008)
854 GRAS_CL_VPORT_XOFFSET_0: 150.000000
855 GRAS_CL_VPORT_XSCALE_0: 150.000000
856 GRAS_CL_VPORT_YOFFSET_0: 150.000000
857 GRAS_CL_VPORT_YSCALE_0: -150.000000
858 GRAS_CL_VPORT_ZOFFSET_0: 0.500000
859 GRAS_CL_VPORT_ZSCALE_0: 0.500000
860 109ce4f8: 0000: 00052008 43160000 43160000 43160000 c3160000 3f000000 3f000000
861 t0 write RB_VPORT_Z_CLAMP[0].MIN (2120)
862 RB_VPORT_Z_CLAMP[0].MIN: 0
863 RB_VPORT_Z_CLAMP[0].MAX: 0xffffff
864 109ce514: 0000: 00012120 00000000 00ffffff
865 t0 write HLSQ_UPDATE_CONTROL (23db)
866 HLSQ_UPDATE_CONTROL: 0x3
867 109ce520: 0000: 000023db 00000003
868 t0 write HLSQ_CONTROL_0_REG (23c0)
869 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE }
870 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x }
871 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x }
872 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
873 HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 }
874 109ce528: 0000: 000423c0 28000250 fcfc0100 fff3f3f0 fcfcfcfc 00fcfcfc
875 t0 write HLSQ_VS_CONTROL_REG (23c5)
876 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 }
877 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 }
878 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
879 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
880 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
881 109ce540: 0000: 000423c5 04000042 017e423e 007e4200 007e4200 007e4200
882 t0 write SP_SP_CTRL_REG (22c0)
883 SP_SP_CTRL_REG: { 0x140010 }
884 109ce558: 0000: 000022c0 00140010
885 t0 write SP_INSTR_CACHE_CTRL (22c1)
886 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f }
887 109ce560: 0000: 000022c1 000005ff
888 t0 write SP_VS_LENGTH_REG (22e5)
889 SP_VS_LENGTH_REG: 4
890 109ce568: 0000: 000022e5 00000004
891 t0 write SP_VS_CTRL_REG0 (22c4)
892 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 4 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE }
893 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 4 }
894 SP_VS_PARAM_REG: { POSREGID = r1.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 }
895 109ce570: 0000: 000222c4 00201000 04000042 0010fc06
896 t0 write SP_VS_OUT[0].REG (22c7)
897 SP_VS_OUT[0].REG: { A_REGID = r2.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 }
898 109ce580: 0000: 000022c7 00001e0a
899 t0 write SP_VS_VPC_DST[0].REG (22d8)
900 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 }
901 109ce588: 0000: 000022d8 08080808
902 t0 write SP_VS_OBJ_OFFSET_REG (22e0)
903 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 }
904 SP_VS_OBJ_START: 0x10cd0000
905 109ce590: 0000: 000122e0 00000000 10cd0000
906 t0 write SP_FS_LENGTH_REG (22ef)
907 SP_FS_LENGTH_REG: 1
908 109ce59c: 0000: 000022ef 00000001
909 t0 write SP_FS_CTRL_REG0 (22e8)
910 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE }
911 SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 }
912 109ce5a4: 0000: 000122e8 00340402 8010003e
913 t0 write SP_FS_OBJ_OFFSET_REG (22ea)
914 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
915 SP_FS_OBJ_START: 0x10cd2000
916 109ce5b0: 0000: 000122ea 7e420000 10cd2000
917 t0 write SP_HS_OBJ_OFFSET_REG (230d)
918 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
919 109ce5bc: 0000: 0000230d 7e420000
920 t0 write SP_DS_OBJ_OFFSET_REG (2334)
921 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
922 109ce5c4: 0000: 00002334 7e420000
923 t0 write SP_GS_OBJ_OFFSET_REG (235b)
924 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
925 109ce5cc: 0000: 0000235b 7e420000
926 t0 write GRAS_CNTL (2003)
927 GRAS_CNTL: { 0 }
928 109ce5d4: 0000: 00002003 00000000
929 t0 write RB_RENDER_CONTROL2 (20a3)
930 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 }
931 109ce5dc: 0000: 000020a3 00000000
932 t0 write RB_FS_OUTPUT_REG (2100)
933 RB_FS_OUTPUT_REG: { MRT = 1 }
934 109ce5e4: 0000: 00002100 00000001
935 t0 write SP_FS_OUTPUT_REG (22f0)
936 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x }
937 109ce5ec: 0000: 000022f0 0000fc01
938 t0 write SP_FS_MRT[0].REG (22f1)
939 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM }
940 SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 }
941 SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 }
942 SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 }
943 SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 }
944 SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 }
945 SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 }
946 SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 }
947 109ce5f4: 0000: 000722f1 0001a000 00000000 00000000 00000000 00000000 00000000 00000000
948 *
949 t0 write VPC_ATTR (2140)
950 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 }
951 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 }
952 109ce618: 0000: 00012140 42001004 00040400
953 t0 write VPC_VARYING_INTERP[0].MODE (2142)
954 VPC_VARYING_INTERP[0].MODE: 0x55
955 VPC_VARYING_INTERP[0x1].MODE: 0
956 VPC_VARYING_INTERP[0x2].MODE: 0
957 VPC_VARYING_INTERP[0x3].MODE: 0
958 VPC_VARYING_INTERP[0x4].MODE: 0
959 VPC_VARYING_INTERP[0x5].MODE: 0
960 VPC_VARYING_INTERP[0x6].MODE: 0
961 VPC_VARYING_INTERP[0x7].MODE: 0
962 109ce624: 0000: 00072142 00000055 00000000 00000000 00000000 00000000 00000000 00000000
963 *
964 t0 write VPC_VARYING_PS_REPL[0].MODE (214a)
965 VPC_VARYING_PS_REPL[0].MODE: 0
966 VPC_VARYING_PS_REPL[0x1].MODE: 0
967 VPC_VARYING_PS_REPL[0x2].MODE: 0
968 VPC_VARYING_PS_REPL[0x3].MODE: 0
969 VPC_VARYING_PS_REPL[0x4].MODE: 0
970 VPC_VARYING_PS_REPL[0x5].MODE: 0
971 VPC_VARYING_PS_REPL[0x6].MODE: 0
972 VPC_VARYING_PS_REPL[0x7].MODE: 0
973 109ce648: 0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000
974 *
975 t3 opcode: CP_LOAD_STATE4 (30) (131 dwords)
976 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 }
977 { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 }
978 :2:0000:0000[40700000x_10000002x] mul.f r0.x, r0.z, c0.x
979 :2:0001:0001[40700001x_10030002x] mul.f r0.y, r0.z, c0.w
980 :3:0002:0002[63818000x_00001004x] mad.f32 r0.x, c1.x, r0.w, r0.x
981 :3:0003:0003[63818001x_00011007x] mad.f32 r0.y, c1.w, r0.w, r0.y
982 :3:0004:0004[63820000x_00001008x] mad.f32 r0.x, c2.x, r1.x, r0.x
983 :3:0005:0005[63820001x_0001100bx] mad.f32 r0.y, c2.w, r1.x, r0.y
984 :3:0006:0006[63828006x_0000100cx] mad.f32 r1.z, c3.x, r1.y, r0.x
985 :2:0007:0007[40700000x_10010002x] mul.f r0.x, r0.z, c0.y
986 :3:0008:0008[63828009x_0001100fx] mad.f32 r2.y, c3.w, r1.y, r0.y
987 :3:0009:0009[63818000x_00001005x] mad.f32 r0.x, c1.y, r0.w, r0.x
988 :1:0010:0010[20244001x_00000010x] mov.f32f32 r0.y, c4.x
989 :3:0011:0011[63820000x_00001009x] mad.f32 r0.x, c2.y, r1.x, r0.x
990 :0:0012:0012[00000000x_00000000x] nop
991 :3:0013:0013[63828007x_0000100dx] mad.f32 r1.w, c3.y, r1.y, r0.x
992 :2:0014:0014[40700000x_10020002x] mul.f r0.x, r0.z, c0.z
993 :1:0015:0015[20244002x_00000015x] mov.f32f32 r0.z, c5.y
994 :3:0016:0016[63818000x_00001006x] mad.f32 r0.x, c1.z, r0.w, r0.x
995 :1:0017:0017[20244003x_00000016x] mov.f32f32 r0.w, c5.z
996 :3:0018:0018[63820000x_0000100ax] mad.f32 r0.x, c2.z, r1.x, r0.x
997 :1:0019:0019[20244004x_00000017x] mov.f32f32 r1.x, c5.w
998 :3:0020:0020[63828008x_0000100ex] mad.f32 r2.x, c3.z, r1.y, r0.x
999 :1:0021:0021[20244000x_00000011x] mov.f32f32 r0.x, c4.y
1000 :2:0022:0022[40100002x_00021021x] add.f r0.z, c8.y, r0.z
1001 :2:0023:0023[4050040dx_00041017x] (sat)max.f r3.y, c5.w, r1.x
1002 :2:0024:0024[40100003x_00031022x] add.f r0.w, c8.z, r0.w
1003 :2:0025:0025[40700000x_00001011x] mul.f r0.x, c4.y, r0.x
1004 :0:0026:0026[00000000x_00000000x] nop
1005 :3:0027:0027[63808000x_00001010x] mad.f32 r0.x, c4.x, r0.y, r0.x
1006 :1:0028:0028[20244001x_00000012x] mov.f32f32 r0.y, c4.z
1007 :0:0029:0029[00000200x_00000000x] (rpt2)nop
1008 :3:0030:0032[63808000x_00001012x] mad.f32 r0.x, c4.z, r0.y, r0.x
1009 :1:0031:0033[20244001x_00000014x] mov.f32f32 r0.y, c5.x
1010 :0:0032:0034[00000200x_00000000x] (rpt2)nop
1011 :2:0033:0037[40100001x_00011020x] add.f r0.y, c8.x, r0.y
1012 :0:0034:0038[00000000x_00000000x] nop
1013 :4:0035:0039[80300000x_00000000x] rsq r0.x, r0.x
1014 :2:0036:0040[40701004x_00001011x] (ss)mul.f r1.x, c4.y, r0.x
1015 :0:0037:0041[00000200x_00000000x] (rpt2)nop
1016 :2:0038:0044[40700004x_10190004x] mul.f r1.x, r1.x, c6.y
1017 :2:0039:0045[40700005x_00001010x] mul.f r1.y, c4.x, r0.x
1018 :0:0040:0046[00000200x_00000000x] (rpt2)nop
1019 :3:0041:0049[63828004x_00041018x] mad.f32 r1.x, c6.x, r1.y, r1.x
1020 :2:0042:0050[40700000x_00001012x] mul.f r0.x, c4.z, r0.x
1021 :0:0043:0051[00000200x_00000000x] (rpt2)nop
1022 :3:0044:0054[63800000x_0004101ax] mad.f32 r0.x, c6.z, r0.x, r1.x
1023 :0:0045:0055[00000200x_00000000x] (rpt2)nop
1024 :2:0046:0058[40b00004x_00001034x] cmps.f.lt r1.x, c13.x, r0.x
1025 :2:0047:0059[40500000x_00001034x] max.f r0.x, c13.x, r0.x
1026 :0:0048:0060[00000100x_00000000x] (rpt1)nop
1027 :1:0049:0062[200c4004x_00000004x] cov.u32f32 r1.x, r1.x
1028 :3:0050:0063[63800001x_00011024x] mad.f32 r0.y, c9.x, r0.x, r0.y
1029 :3:0051:0064[63800002x_00021025x] mad.f32 r0.z, c9.y, r0.x, r0.z
1030 :3:0052:0065[63800000x_00031026x] mad.f32 r0.x, c9.z, r0.x, r0.w
1031 :3:0053:0066[6382040ax_00011028x] (sat)mad.f32 r2.z, c10.x, r1.x, r0.y
1032 :3:0054:0067[6382040bx_00021029x] (sat)mad.f32 r2.w, c10.y, r1.x, r0.z
1033 :3:0055:0068[6382040cx_0000102ax] (sat)mad.f32 r3.x, c10.z, r1.x, r0.x
1034 :0:0056:0069[03000000x_00000000x] end
1035 :0:0057:0070[00000000x_00000000x] nop
1036 :0:0058:0071[00000000x_00000000x] nop
1037 :0:0059:0072[00000000x_00000000x] nop
1038 :0:0060:0073[00000000x_00000000x] nop
1039 Register Stats:
1040 - used (half): (cnt=0, max=0)
1041 - used (full): 0-13 (cnt=14, max=13)
1042 - input (half): (cnt=0, max=0)
1043 - input (full): 2-5 (cnt=4, max=5)
1044 - max const: 52
1045
1046 - output (half): (cnt=0, max=0) (estimated)
1047 - output (full): 6-13 (cnt=8, max=13) (estimated)
1048 - shaderdb: 74 instructions, 38 nops, 36 non-nops, (61 instlen), 0 half, 4 full
1049 - shaderdb: 1 (ss), 0 (sy)
1050 109ce66c: 0000: c0813000 01200000 00000000 10000002 40700000 10030002 40700001 00001004
1051 109ce68c: 0020: 63818000 00011007 63818001 00001008 63820000 0001100b 63820001 0000100c
1052 109ce6ac: 0040: 63828006 10010002 40700000 0001100f 63828009 00001005 63818000 00000010
1053 109ce6cc: 0060: 20244001 00001009 63820000 00000000 00000000 0000100d 63828007 10020002
1054 109ce6ec: 0080: 40700000 00000015 20244002 00001006 63818000 00000016 20244003 0000100a
1055 109ce70c: 00a0: 63820000 00000017 20244004 0000100e 63828008 00000011 20244000 00021021
1056 109ce72c: 00c0: 40100002 00041017 4050040d 00031022 40100003 00001011 40700000 00000000
1057 109ce74c: 00e0: 00000000 00001010 63808000 00000012 20244001 00000000 00000200 00001012
1058 109ce76c: 0100: 63808000 00000014 20244001 00000000 00000200 00011020 40100001 00000000
1059 109ce78c: 0120: 00000000 00000000 80300000 00001011 40701004 00000000 00000200 10190004
1060 109ce7ac: 0140: 40700004 00001010 40700005 00000000 00000200 00041018 63828004 00001012
1061 109ce7cc: 0160: 40700000 00000000 00000200 0004101a 63800000 00000000 00000200 00001034
1062 109ce7ec: 0180: 40b00004 00001034 40500000 00000000 00000100 00000004 200c4004 00011024
1063 109ce80c: 01a0: 63800001 00021025 63800002 00031026 63800000 00011028 6382040a 00021029
1064 109ce82c: 01c0: 6382040b 0000102a 6382040c 00000000 03000000 00000000 00000000 00000000
1065 *
1066 t3 opcode: CP_LOAD_STATE4 (30) (35 dwords)
1067 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 }
1068 { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 }
1069 :0:0000:0000[00000000x_00000000x] nop
1070 :6:0001:0001[c7c60000x_01c00000x] ldlv.u32 r0.x, l[0], 1
1071 :6:0002:0002[c7c60001x_01c00002x] ldlv.u32 r0.y, l[1], 1
1072 :6:0003:0003[c7c60002x_01c00004x] ldlv.u32 r0.z, l[2], 1
1073 :6:0004:0004[c7c60003x_01c00006x] ldlv.u32 r0.w, l[3], 1
1074 :2:0005:0005[473090fcx_00002000x] (ss)bary.f (ei)r63.x, 0, r0.x
1075 :0:0006:0006[03000000x_00000000x] end
1076 :0:0007:0007[00000000x_00000000x] nop
1077 :0:0008:0008[00000000x_00000000x] nop
1078 :0:0009:0009[00000000x_00000000x] nop
1079 :0:0010:0010[00000000x_00000000x] nop
1080 Register Stats:
1081 - used (half): (cnt=0, max=0)
1082 - used (full): 0-3 (cnt=4, max=3)
1083 - input (half): (cnt=0, max=0)
1084 - input (full): 0-3 (cnt=4, max=3)
1085 - max const: 0
1086
1087 - output (half): (cnt=0, max=0) (estimated)
1088 - output (full): (cnt=0, max=0) (estimated)
1089 - shaderdb: 11 instructions, 5 nops, 6 non-nops, (11 instlen), 0 half, 1 full
1090 - shaderdb: 1 (ss), 0 (sy)
1091 109ce878: 0000: c0213000 00700000 00000000 00000000 00000000 01c00000 c7c60000 01c00002
1092 109ce898: 0020: c7c60001 01c00004 c7c60002 01c00006 c7c60003 00002000 473090fc 00000000
1093 109ce8b8: 0040: 03000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
1094 *
1095 t3 opcode: CP_LOAD_STATE4 (30) (51 dwords)
1096 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 }
1097 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 }
1098 109ce910: 4.330127 0.855050 0.555273 0.469846 0.000000 4.698463 -0.404206 -0.342020
1099 109ce930: 2.500000 -1.480991 -0.961761 -0.813798 -12.990380 -11.962078 35.506226 39.274502
1100 109ce950: 0.000000 0.000000 1.000000 1.000000 0.160000 0.020000 0.000000 1.000000
1101 109ce970: 0.039740 0.662886 0.747665 0.000000 1.000000 0.000000 0.000000 0.000000
1102 109ce990: 0.000000 0.000000 0.000000 1.000000 0.800000 0.100000 0.000000 1.000000
1103 109ce9b0: 0.000000 0.000000 0.000000 1.000000 0.000000 0.000000 0.000000 1.000000
1104 109ce910: 0000: 408a9066 3f5ae494 3f0e265d 3ef08fb2 00000000 409659cf becef409 beaf1d43
1105 109ce930: 0020: 40200000 bfbd9119 bf7635f5 bf50550b c14fd899 c13f64ac 420e0660 421d1917
1106 109ce950: 0040: 00000000 00000000 3f800000 3f800000 3e23d70b 3ca3d70b 00000000 3f800000
1107 109ce970: 0060: 3d22c66e 3f29b2e7 3f3f66f5 00000000 3f800000 00000000 00000000 00000000
1108 109ce990: 0080: 00000000 00000000 00000000 3f800000 3f4ccccd 3dcccccd 00000000 3f800000
1109 109ce9b0: 00a0: 00000000 00000000 00000000 3f800000 00000000 00000000 00000000 3f800000
1110 109ce904: 0000: c0313000 03200000 00000001 408a9066 3f5ae494 3f0e265d 3ef08fb2 00000000
1111 109ce924: 0020: 409659cf becef409 beaf1d43 40200000 bfbd9119 bf7635f5 bf50550b c14fd899
1112 109ce944: 0040: c13f64ac 420e0660 421d1917 00000000 00000000 3f800000 3f800000 3e23d70b
1113 109ce964: 0060: 3ca3d70b 00000000 3f800000 3d22c66e 3f29b2e7 3f3f66f5 00000000 3f800000
1114 109ce984: 0080: 00000000 00000000 00000000 00000000 00000000 00000000 3f800000 3f4ccccd
1115 109ce9a4: 00a0: 3dcccccd 00000000 3f800000 00000000 00000000 00000000 3f800000 00000000
1116 109ce9c4: 00c0: 00000000 00000000 3f800000
1117 t3 opcode: CP_LOAD_STATE4 (30) (7 dwords)
1118 { DST_OFF = 13 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 }
1119 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 }
1120 109ce9dc: 0.000000 -28026765312.000000 -28026765312.000000 -28026765312.000000
1121 109ce9dc: 0000: 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0
1122 109ce9d0: 0000: c0053000 0060000d 00000001 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0
1123 t0 write RB_MRT[0].CONTROL (20a4)
1124 RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf }
1125 109ce9ec: 0000: 000020a4 0f000c00
1126 t0 write RB_MRT[0].BLEND_CONTROL (20a8)
1127 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
1128 109ce9f4: 0000: 000020a8 00000000
1129 t0 write RB_MRT[0x1].CONTROL (20a9)
1130 RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf }
1131 109ce9fc: 0000: 000020a9 0f000c00
1132 t0 write RB_MRT[0x1].BLEND_CONTROL (20ad)
1133 RB_MRT[0x1].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
1134 109cea04: 0000: 000020ad 00000000
1135 t0 write RB_MRT[0x2].CONTROL (20ae)
1136 RB_MRT[0x2].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf }
1137 109cea0c: 0000: 000020ae 0f000c00
1138 t0 write RB_MRT[0x2].BLEND_CONTROL (20b2)
1139 RB_MRT[0x2].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
1140 109cea14: 0000: 000020b2 00000000
1141 t0 write RB_MRT[0x3].CONTROL (20b3)
1142 RB_MRT[0x3].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf }
1143 109cea1c: 0000: 000020b3 0f000c00
1144 t0 write RB_MRT[0x3].BLEND_CONTROL (20b7)
1145 RB_MRT[0x3].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
1146 109cea24: 0000: 000020b7 00000000
1147 t0 write RB_MRT[0x4].CONTROL (20b8)
1148 RB_MRT[0x4].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf }
1149 109cea2c: 0000: 000020b8 0f000c00
1150 t0 write RB_MRT[0x4].BLEND_CONTROL (20bc)
1151 RB_MRT[0x4].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
1152 109cea34: 0000: 000020bc 00000000
1153 t0 write RB_MRT[0x5].CONTROL (20bd)
1154 RB_MRT[0x5].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf }
1155 109cea3c: 0000: 000020bd 0f000c00
1156 t0 write RB_MRT[0x5].BLEND_CONTROL (20c1)
1157 RB_MRT[0x5].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
1158 109cea44: 0000: 000020c1 00000000
1159 t0 write RB_MRT[0x6].CONTROL (20c2)
1160 RB_MRT[0x6].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf }
1161 109cea4c: 0000: 000020c2 0f000c00
1162 t0 write RB_MRT[0x6].BLEND_CONTROL (20c6)
1163 RB_MRT[0x6].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
1164 109cea54: 0000: 000020c6 00000000
1165 t0 write RB_MRT[0x7].CONTROL (20c7)
1166 RB_MRT[0x7].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf }
1167 109cea5c: 0000: 000020c7 0f000c00
1168 t0 write RB_MRT[0x7].BLEND_CONTROL (20cb)
1169 RB_MRT[0x7].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
1170 109cea64: 0000: 000020cb 00000000
1171 t0 write RB_FS_OUTPUT (20f9)
1172 RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff }
1173 109cea6c: 0000: 000020f9 ffff0000
1174 t0 write VFD_FETCH[0].INSTR_0 (220a)
1175 VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 12 }
1176 VFD_FETCH[0].INSTR_1: 0x107cb000
1177 VFD_FETCH[0].INSTR_2: { SIZE = 0x100000 }
1178 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 }
1179 109cea74: 0000: 0003220a 0000060b 107cb000 00100000 00000001
1180 t0 write VFD_DECODE[0].INSTR (228a)
1181 VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID }
1182 109cea88: 0000: 0000228a 2c0020df
1183 t0 write VFD_CONTROL_0 (2200)
1184 VFD_CONTROL_0: { TOTALATTRTOVS = 4 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 | 0xa0000 }
1185 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x }
1186 VFD_CONTROL_2: 0
1187 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x }
1188 VFD_CONTROL_4: 0
1189 109cea90: 0000: 00042200 041a0004 fcfc0081 00000000 0000fc00 00000000
1190 t0 write UCHE_INVALIDATE0 (0e8a)
1191 UCHE_INVALIDATE0: 0
1192 UCHE_INVALIDATE1: 0x12
1193 109ceaa8: 0000: 00010e8a 00000000 00000012
1194 t0 write VFD_INDEX_OFFSET (2208)
1195 VFD_INDEX_OFFSET: 0
1196 UNKNOWN_2209: 0
1197 109ceab4: 0000: 00012208 00000000 00000000
1198 t0 write PC_RESTART_INDEX (21c6)
1199 PC_RESTART_INDEX: 0xffffffff
1200 109ceac0: 0000: 000021c6 ffffffff
1201 t0 write CP_SCRATCH[0x7].REG (057f)
1202 CP_SCRATCH[0x7].REG: 0x8
1203 :0,7,115,8
1204 109ceac8: 0000: 0000057f 00000008
1205 t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
1206 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS }
1207 { NUM_INSTANCES = 1 }
1208 { NUM_INDICES = 240 }
1209 { FIRST_INDX = 0 }
1210 { INDX_BASE = 0x10bd0000 }
1211 { INDX_SIZE = 480 }
1212 draw[1] register values
1213 !+ 00000007 CP_SCRATCH[0x5].REG: 0x7
1214 :0,7,115,8
1215 !+ 00000008 CP_SCRATCH[0x7].REG: 0x8
1216 :0,7,115,8
1217 + 00000000 UCHE_INVALIDATE0: 0
1218 + 00000012 UCHE_INVALIDATE1: 0x12
1219 + 00080000 GRAS_CL_CLIP_CNTL: { 0x80000 }
1220 + 00000000 GRAS_CNTL: { 0 }
1221 + 43160000 GRAS_CL_VPORT_XOFFSET_0: 150.000000
1222 + 43160000 GRAS_CL_VPORT_XSCALE_0: 150.000000
1223 + 43160000 GRAS_CL_VPORT_YOFFSET_0: 150.000000
1224 + c3160000 GRAS_CL_VPORT_YSCALE_0: -150.000000
1225 !+ 3f000000 GRAS_CL_VPORT_ZOFFSET_0: 0.500000
1226 !+ 3f000000 GRAS_CL_VPORT_ZSCALE_0: 0.500000
1227 !+ 00100010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 }
1228 !+ 00000010 GRAS_SU_POINT_SIZE: 1.000000
1229 + 00000000 GRAS_ALPHA_CONTROL: { 0 }
1230 + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000
1231 + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000
1232 + 00000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000
1233 !+ 00100012 GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 | RENDERING_PASS }
1234 + 012b012b GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 }
1235 + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
1236 + 00000000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 }
1237 + 0f000c00 RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf }
1238 + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
1239 !+ 0f000c00 RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf }
1240 + 00000000 RB_MRT[0x1].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
1241 !+ 0f000c00 RB_MRT[0x2].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf }
1242 + 00000000 RB_MRT[0x2].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
1243 !+ 0f000c00 RB_MRT[0x3].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf }
1244 + 00000000 RB_MRT[0x3].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
1245 !+ 0f000c00 RB_MRT[0x4].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf }
1246 + 00000000 RB_MRT[0x4].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
1247 !+ 0f000c00 RB_MRT[0x5].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf }
1248 + 00000000 RB_MRT[0x5].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
1249 !+ 0f000c00 RB_MRT[0x6].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf }
1250 + 00000000 RB_MRT[0x6].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
1251 !+ 0f000c00 RB_MRT[0x7].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf }
1252 + 00000000 RB_MRT[0x7].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO }
1253 + 00000000 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_NEVER }
1254 !+ ffff0000 RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff }
1255 + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 }
1256 !+ 80000016 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE }
1257 + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP }
1258 + 00000000 RB_STENCIL_CONTROL2: { 0 }
1259 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
1260 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
1261 + 00000000 RB_VPORT_Z_CLAMP[0].MIN: 0
1262 + 00ffffff RB_VPORT_Z_CLAMP[0].MAX: 0xffffff
1263 !+ 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 }
1264 !+ 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 }
1265 !+ 00000055 VPC_VARYING_INTERP[0].MODE: 0x55
1266 + 00000000 VPC_VARYING_INTERP[0x1].MODE: 0
1267 + 00000000 VPC_VARYING_INTERP[0x2].MODE: 0
1268 + 00000000 VPC_VARYING_INTERP[0x3].MODE: 0
1269 + 00000000 VPC_VARYING_INTERP[0x4].MODE: 0
1270 + 00000000 VPC_VARYING_INTERP[0x5].MODE: 0
1271 + 00000000 VPC_VARYING_INTERP[0x6].MODE: 0
1272 + 00000000 VPC_VARYING_INTERP[0x7].MODE: 0
1273 + 00000000 VPC_VARYING_PS_REPL[0].MODE: 0
1274 + 00000000 VPC_VARYING_PS_REPL[0x1].MODE: 0
1275 + 00000000 VPC_VARYING_PS_REPL[0x2].MODE: 0
1276 + 00000000 VPC_VARYING_PS_REPL[0x3].MODE: 0
1277 + 00000000 VPC_VARYING_PS_REPL[0x4].MODE: 0
1278 + 00000000 VPC_VARYING_PS_REPL[0x5].MODE: 0
1279 + 00000000 VPC_VARYING_PS_REPL[0x6].MODE: 0
1280 + 00000000 VPC_VARYING_PS_REPL[0x7].MODE: 0
1281 !+ 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
1282 + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
1283 + ffffffff PC_RESTART_INDEX: 0xffffffff
1284 + 041a0004 VFD_CONTROL_0: { TOTALATTRTOVS = 4 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 | 0xa0000 }
1285 + fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x }
1286 + 00000000 VFD_CONTROL_2: 0
1287 + 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x }
1288 + 00000000 VFD_CONTROL_4: 0
1289 + 00000000 VFD_INDEX_OFFSET: 0
1290 + 00000000 UNKNOWN_2209: 0
1291 + 0000060b VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 12 }
1292 !+ 107cb000 VFD_FETCH[0].INSTR_1: 0x107cb000
1293 !+ 00100000 VFD_FETCH[0].INSTR_2: { SIZE = 0x100000 }
1294 + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 }
1295 !+ 2c0020df VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID }
1296 + 00140010 SP_SP_CTRL_REG: { 0x140010 }
1297 + 000005ff SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f }
1298 !+ 00201000 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 4 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE }
1299 + 04000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 4 }
1300 !+ 0010fc06 SP_VS_PARAM_REG: { POSREGID = r1.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 }
1301 !+ 00001e0a SP_VS_OUT[0].REG: { A_REGID = r2.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 }
1302 !+ 08080808 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 }
1303 + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 }
1304 !+ 10cd0000 SP_VS_OBJ_START: 0x10cd0000
1305 !+ 00000004 SP_VS_LENGTH_REG: 4
1306 !+ 00340402 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE }
1307 !+ 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 }
1308 + 7e420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
1309 !+ 10cd2000 SP_FS_OBJ_START: 0x10cd2000
1310 + 00000001 SP_FS_LENGTH_REG: 1
1311 + 0000fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x }
1312 + 0001a000 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM }
1313 + 00000000 SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 }
1314 + 00000000 SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 }
1315 + 00000000 SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 }
1316 + 00000000 SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 }
1317 + 00000000 SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 }
1318 + 00000000 SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 }
1319 + 00000000 SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 }
1320 + 7e420000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
1321 + 7e420000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
1322 + 7e420000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
1323 + 28000250 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE }
1324 + fcfc0100 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x }
1325 + fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x }
1326 + fcfcfcfc HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
1327 + 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 }
1328 !+ 04000042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 }
1329 + 017e423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 }
1330 + 007e4200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
1331 + 007e4200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
1332 + 007e4200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
1333 + 00000003 HLSQ_UPDATE_CONTROL: 0x3
1334 109cead0: 0000: c0053800 00000404 00000001 000000f0 00000000 10bd0000 000001e0
1335 t0 write CP_SCRATCH[0x7].REG (057f)
1336 CP_SCRATCH[0x7].REG: 0x9
1337 :0,7,115,9
1338 109ceaec: 0000: 0000057f 00000009
1339 t0 write CP_SCRATCH[0x5].REG (057d)
1340 CP_SCRATCH[0x5].REG: 0xd
1341 :0,13,115,9
1342 109ceaf4: 0000: 0000057d 0000000d
1343 t0 write PC_PRIM_VTX_CNTL (21c4)
1344 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
1345 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
1346 109ceafc: 0000: 000121c4 02000001 00000012
1347 t0 write VFD_INDEX_OFFSET (2208)
1348 VFD_INDEX_OFFSET: 0
1349 UNKNOWN_2209: 0
1350 109ceb08: 0000: 00012208 00000000 00000000
1351 t0 write PC_RESTART_INDEX (21c6)
1352 PC_RESTART_INDEX: 0xffffffff
1353 109ceb14: 0000: 000021c6 ffffffff
1354 t0 write CP_SCRATCH[0x7].REG (057f)
1355 CP_SCRATCH[0x7].REG: 0xe
1356 :0,13,115,14
1357 109ceb1c: 0000: 0000057f 0000000e
1358 t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
1359 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS }
1360 { NUM_INSTANCES = 1 }
1361 { NUM_INDICES = 120 }
1362 { FIRST_INDX = 0 }
1363 { INDX_BASE = 0x10bd01e0 }
1364 { INDX_SIZE = 240 }
1365 draw[2] register values
1366 !+ 0000000d CP_SCRATCH[0x5].REG: 0xd
1367 :0,13,115,14
1368 !+ 0000000e CP_SCRATCH[0x7].REG: 0xe
1369 :0,13,115,14
1370 + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
1371 + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
1372 + ffffffff PC_RESTART_INDEX: 0xffffffff
1373 + 00000000 VFD_INDEX_OFFSET: 0
1374 + 00000000 UNKNOWN_2209: 0
1375 109ceb24: 0000: c0053800 00000404 00000001 00000078 00000000 10bd01e0 000000f0
1376 t0 write CP_SCRATCH[0x7].REG (057f)
1377 CP_SCRATCH[0x7].REG: 0xf
1378 :0,13,115,15
1379 109ceb40: 0000: 0000057f 0000000f
1380 t0 write CP_SCRATCH[0x5].REG (057d)
1381 CP_SCRATCH[0x5].REG: 0x13
1382 :0,19,115,15
1383 109ceb48: 0000: 0000057d 00000013
1384 t0 write PC_PRIM_VTX_CNTL (21c4)
1385 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
1386 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
1387 109ceb50: 0000: 000121c4 02000001 00000012
1388 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
1389 109ceb5c: 0000: c0002600 00000000
1390 t3 opcode: CP_LOAD_STATE4 (30) (51 dwords)
1391 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 }
1392 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 }
1393 109ceb70: 4.330127 0.855050 0.555273 0.469846 0.000000 4.698463 -0.404206 -0.342020
1394 109ceb90: 2.500000 -1.480991 -0.961761 -0.813798 -12.990380 -11.962078 35.506226 39.274502
1395 109cebb0: 0.000000 0.000000 -1.000000 1.000000 0.160000 0.020000 0.000000 1.000000
1396 109cebd0: 0.039740 0.662886 0.747665 0.000000 1.000000 0.000000 0.000000 0.000000
1397 109cebf0: 0.000000 0.000000 0.000000 1.000000 0.800000 0.100000 0.000000 1.000000
1398 109cec10: 0.000000 0.000000 0.000000 1.000000 0.000000 0.000000 0.000000 1.000000
1399 109ceb70: 0000: 408a9066 3f5ae494 3f0e265d 3ef08fb2 00000000 409659cf becef409 beaf1d43
1400 109ceb90: 0020: 40200000 bfbd9119 bf7635f5 bf50550b c14fd899 c13f64ac 420e0660 421d1917
1401 109cebb0: 0040: 00000000 00000000 bf800000 3f800000 3e23d70b 3ca3d70b 00000000 3f800000
1402 109cebd0: 0060: 3d22c66e 3f29b2e7 3f3f66f5 00000000 3f800000 00000000 00000000 00000000
1403 109cebf0: 0080: 00000000 00000000 00000000 3f800000 3f4ccccd 3dcccccd 00000000 3f800000
1404 109cec10: 00a0: 00000000 00000000 00000000 3f800000 00000000 00000000 00000000 3f800000
1405 109ceb64: 0000: c0313000 03200000 00000001 408a9066 3f5ae494 3f0e265d 3ef08fb2 00000000
1406 109ceb84: 0020: 409659cf becef409 beaf1d43 40200000 bfbd9119 bf7635f5 bf50550b c14fd899
1407 109ceba4: 0040: c13f64ac 420e0660 421d1917 00000000 00000000 bf800000 3f800000 3e23d70b
1408 109cebc4: 0060: 3ca3d70b 00000000 3f800000 3d22c66e 3f29b2e7 3f3f66f5 00000000 3f800000
1409 109cebe4: 0080: 00000000 00000000 00000000 00000000 00000000 00000000 3f800000 3f4ccccd
1410 109cec04: 00a0: 3dcccccd 00000000 3f800000 00000000 00000000 00000000 3f800000 00000000
1411 109cec24: 00c0: 00000000 00000000 3f800000
1412 t0 write VFD_INDEX_OFFSET (2208)
1413 VFD_INDEX_OFFSET: 0
1414 UNKNOWN_2209: 0
1415 109cec30: 0000: 00012208 00000000 00000000
1416 t0 write PC_RESTART_INDEX (21c6)
1417 PC_RESTART_INDEX: 0xffffffff
1418 109cec3c: 0000: 000021c6 ffffffff
1419 t0 write CP_SCRATCH[0x7].REG (057f)
1420 CP_SCRATCH[0x7].REG: 0x14
1421 :0,19,115,20
1422 109cec44: 0000: 0000057f 00000014
1423 t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
1424 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS }
1425 { NUM_INSTANCES = 1 }
1426 { NUM_INDICES = 240 }
1427 { FIRST_INDX = 0 }
1428 { INDX_BASE = 0x10bd02d0 }
1429 { INDX_SIZE = 480 }
1430 draw[3] register values
1431 !+ 00000013 CP_SCRATCH[0x5].REG: 0x13
1432 :0,19,115,20
1433 !+ 00000014 CP_SCRATCH[0x7].REG: 0x14
1434 :0,19,115,20
1435 + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
1436 + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
1437 + ffffffff PC_RESTART_INDEX: 0xffffffff
1438 + 00000000 VFD_INDEX_OFFSET: 0
1439 + 00000000 UNKNOWN_2209: 0
1440 109cec4c: 0000: c0053800 00000404 00000001 000000f0 00000000 10bd02d0 000001e0
1441 t0 write CP_SCRATCH[0x7].REG (057f)
1442 CP_SCRATCH[0x7].REG: 0x15
1443 :0,19,115,21
1444 109cec68: 0000: 0000057f 00000015
1445 t0 write CP_SCRATCH[0x5].REG (057d)
1446 CP_SCRATCH[0x5].REG: 0x19
1447 :0,25,115,21
1448 109cec70: 0000: 0000057d 00000019
1449 t0 write PC_PRIM_VTX_CNTL (21c4)
1450 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
1451 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
1452 109cec78: 0000: 000121c4 02000001 00000012
1453 t0 write VFD_INDEX_OFFSET (2208)
1454 VFD_INDEX_OFFSET: 0
1455 UNKNOWN_2209: 0
1456 109cec84: 0000: 00012208 00000000 00000000
1457 t0 write PC_RESTART_INDEX (21c6)
1458 PC_RESTART_INDEX: 0xffffffff
1459 109cec90: 0000: 000021c6 ffffffff
1460 t0 write CP_SCRATCH[0x7].REG (057f)
1461 CP_SCRATCH[0x7].REG: 0x1a
1462 :0,25,115,26
1463 109cec98: 0000: 0000057f 0000001a
1464 t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
1465 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS }
1466 { NUM_INSTANCES = 1 }
1467 { NUM_INDICES = 120 }
1468 { FIRST_INDX = 0 }
1469 { INDX_BASE = 0x10bd04b0 }
1470 { INDX_SIZE = 240 }
1471 draw[4] register values
1472 !+ 00000019 CP_SCRATCH[0x5].REG: 0x19
1473 :0,25,115,26
1474 !+ 0000001a CP_SCRATCH[0x7].REG: 0x1a
1475 :0,25,115,26
1476 + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
1477 + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
1478 + ffffffff PC_RESTART_INDEX: 0xffffffff
1479 + 00000000 VFD_INDEX_OFFSET: 0
1480 + 00000000 UNKNOWN_2209: 0
1481 109ceca0: 0000: c0053800 00000404 00000001 00000078 00000000 10bd04b0 000000f0
1482 t0 write CP_SCRATCH[0x7].REG (057f)
1483 CP_SCRATCH[0x7].REG: 0x1b
1484 :0,25,115,27
1485 109cecbc: 0000: 0000057f 0000001b
1486 t0 write CP_SCRATCH[0x5].REG (057d)
1487 CP_SCRATCH[0x5].REG: 0x1f
1488 :0,31,115,27
1489 109cecc4: 0000: 0000057d 0000001f
1490 t0 write RB_DEPTH_CONTROL (2101)
1491 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE }
1492 109ceccc: 0000: 00002101 80000016
1493 t0 write GRAS_ALPHA_CONTROL (2073)
1494 GRAS_ALPHA_CONTROL: { 0 }
1495 109cecd4: 0000: 00002073 00000000
1496 t0 write PC_PRIM_VTX_CNTL (21c4)
1497 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
1498 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
1499 109cecdc: 0000: 000121c4 02000001 00000012
1500 t0 write HLSQ_UPDATE_CONTROL (23db)
1501 HLSQ_UPDATE_CONTROL: 0x3
1502 109cece8: 0000: 000023db 00000003
1503 t0 write HLSQ_CONTROL_0_REG (23c0)
1504 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE }
1505 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x }
1506 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x }
1507 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
1508 HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 }
1509 109cecf0: 0000: 000423c0 28000250 fcfc0100 fff3f3f0 fcfcfcfc 00fcfcfc
1510 t0 write HLSQ_VS_CONTROL_REG (23c5)
1511 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 }
1512 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 }
1513 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
1514 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
1515 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
1516 109ced08: 0000: 000423c5 04000042 017e423e 007e4200 007e4200 007e4200
1517 t0 write SP_SP_CTRL_REG (22c0)
1518 SP_SP_CTRL_REG: { 0x140010 }
1519 109ced20: 0000: 000022c0 00140010
1520 t0 write SP_INSTR_CACHE_CTRL (22c1)
1521 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f }
1522 109ced28: 0000: 000022c1 000005ff
1523 t0 write SP_VS_LENGTH_REG (22e5)
1524 SP_VS_LENGTH_REG: 4
1525 109ced30: 0000: 000022e5 00000004
1526 t0 write SP_VS_CTRL_REG0 (22c4)
1527 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE }
1528 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 8 }
1529 SP_VS_PARAM_REG: { POSREGID = r2.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 }
1530 109ced38: 0000: 000222c4 00201400 08000042 0010fc0a
1531 t0 write SP_VS_OUT[0].REG (22c7)
1532 SP_VS_OUT[0].REG: { A_REGID = r3.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 }
1533 109ced48: 0000: 000022c7 00001e0e
1534 t0 write SP_VS_VPC_DST[0].REG (22d8)
1535 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 }
1536 109ced50: 0000: 000022d8 08080808
1537 t0 write SP_VS_OBJ_OFFSET_REG (22e0)
1538 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 }
1539 SP_VS_OBJ_START: 0x10cd5000
1540 109ced58: 0000: 000122e0 00000000 10cd5000
1541 t0 write SP_FS_LENGTH_REG (22ef)
1542 SP_FS_LENGTH_REG: 1
1543 109ced64: 0000: 000022ef 00000001
1544 t0 write SP_FS_CTRL_REG0 (22e8)
1545 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE }
1546 SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 }
1547 109ced6c: 0000: 000122e8 00340402 8010003e
1548 t0 write SP_FS_OBJ_OFFSET_REG (22ea)
1549 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
1550 SP_FS_OBJ_START: 0x10cd2000
1551 109ced78: 0000: 000122ea 7e420000 10cd2000
1552 t0 write SP_HS_OBJ_OFFSET_REG (230d)
1553 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
1554 109ced84: 0000: 0000230d 7e420000
1555 t0 write SP_DS_OBJ_OFFSET_REG (2334)
1556 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
1557 109ced8c: 0000: 00002334 7e420000
1558 t0 write SP_GS_OBJ_OFFSET_REG (235b)
1559 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
1560 109ced94: 0000: 0000235b 7e420000
1561 t0 write GRAS_CNTL (2003)
1562 GRAS_CNTL: { 0 }
1563 109ced9c: 0000: 00002003 00000000
1564 t0 write RB_RENDER_CONTROL2 (20a3)
1565 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 }
1566 109ceda4: 0000: 000020a3 00000000
1567 t0 write RB_FS_OUTPUT_REG (2100)
1568 RB_FS_OUTPUT_REG: { MRT = 1 }
1569 109cedac: 0000: 00002100 00000001
1570 t0 write SP_FS_OUTPUT_REG (22f0)
1571 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x }
1572 109cedb4: 0000: 000022f0 0000fc01
1573 t0 write SP_FS_MRT[0].REG (22f1)
1574 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM }
1575 SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 }
1576 SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 }
1577 SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 }
1578 SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 }
1579 SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 }
1580 SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 }
1581 SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 }
1582 109cedbc: 0000: 000722f1 0001a000 00000000 00000000 00000000 00000000 00000000 00000000
1583 *
1584 t0 write VPC_ATTR (2140)
1585 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 }
1586 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 }
1587 109cede0: 0000: 00012140 42001004 00040400
1588 t0 write VPC_VARYING_INTERP[0].MODE (2142)
1589 VPC_VARYING_INTERP[0].MODE: 0x55
1590 VPC_VARYING_INTERP[0x1].MODE: 0
1591 VPC_VARYING_INTERP[0x2].MODE: 0
1592 VPC_VARYING_INTERP[0x3].MODE: 0
1593 VPC_VARYING_INTERP[0x4].MODE: 0
1594 VPC_VARYING_INTERP[0x5].MODE: 0
1595 VPC_VARYING_INTERP[0x6].MODE: 0
1596 VPC_VARYING_INTERP[0x7].MODE: 0
1597 109cedec: 0000: 00072142 00000055 00000000 00000000 00000000 00000000 00000000 00000000
1598 *
1599 t0 write VPC_VARYING_PS_REPL[0].MODE (214a)
1600 VPC_VARYING_PS_REPL[0].MODE: 0
1601 VPC_VARYING_PS_REPL[0x1].MODE: 0
1602 VPC_VARYING_PS_REPL[0x2].MODE: 0
1603 VPC_VARYING_PS_REPL[0x3].MODE: 0
1604 VPC_VARYING_PS_REPL[0x4].MODE: 0
1605 VPC_VARYING_PS_REPL[0x5].MODE: 0
1606 VPC_VARYING_PS_REPL[0x6].MODE: 0
1607 VPC_VARYING_PS_REPL[0x7].MODE: 0
1608 109cee10: 0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000
1609 *
1610 t3 opcode: CP_LOAD_STATE4 (30) (131 dwords)
1611 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 }
1612 { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 }
1613 :2:0000:0000[40700000x_10000002x] mul.f r0.x, r0.z, c0.x
1614 :2:0001:0001[40700001x_10030002x] mul.f r0.y, r0.z, c0.w
1615 :3:0002:0002[63818000x_00001004x] mad.f32 r0.x, c1.x, r0.w, r0.x
1616 :3:0003:0003[63818001x_00011007x] mad.f32 r0.y, c1.w, r0.w, r0.y
1617 :3:0004:0004[63820000x_00001008x] mad.f32 r0.x, c2.x, r1.x, r0.x
1618 :3:0005:0005[63820001x_0001100bx] mad.f32 r0.y, c2.w, r1.x, r0.y
1619 :3:0006:0006[6382800ax_0000100cx] mad.f32 r2.z, c3.x, r1.y, r0.x
1620 :2:0007:0007[40700000x_10010002x] mul.f r0.x, r0.z, c0.y
1621 :3:0008:0008[6382800dx_0001100fx] mad.f32 r3.y, c3.w, r1.y, r0.y
1622 :3:0009:0009[63818000x_00001005x] mad.f32 r0.x, c1.y, r0.w, r0.x
1623 :1:0010:0010[20244001x_00000010x] mov.f32f32 r0.y, c4.x
1624 :3:0011:0011[63820000x_00001009x] mad.f32 r0.x, c2.y, r1.x, r0.x
1625 :0:0012:0012[00000000x_00000000x] nop
1626 :3:0013:0013[6382800bx_0000100dx] mad.f32 r2.w, c3.y, r1.y, r0.x
1627 :2:0014:0014[40700000x_10020002x] mul.f r0.x, r0.z, c0.z
1628 :2:0015:0015[40100001x_0001101cx] add.f r0.y, c7.x, r0.y
1629 :3:0016:0016[63818000x_00001006x] mad.f32 r0.x, c1.z, r0.w, r0.x
1630 :1:0017:0017[20244002x_00000011x] mov.f32f32 r0.z, c4.y
1631 :3:0018:0018[63820000x_0000100ax] mad.f32 r0.x, c2.z, r1.x, r0.x
1632 :1:0019:0019[20244004x_00000013x] mov.f32f32 r1.x, c4.w
1633 :3:0020:0020[6382800cx_0000100ex] mad.f32 r3.x, c3.z, r1.y, r0.x
1634 :2:0021:0021[40700000x_00070007x] mul.f r0.x, r1.w, r1.w
1635 :2:0022:0022[40100002x_0002101dx] add.f r0.z, c7.y, r0.z
1636 :3:0023:0023[63830000x_00000006x] mad.f32 r0.x, r1.z, r1.z, r0.x
1637 :2:0024:0024[40500411x_00041013x] (sat)max.f r4.y, c4.w, r1.x
1638 :3:0025:0025[63840000x_00000008x] mad.f32 r0.x, r2.x, r2.x, r0.x
1639 :1:0026:0026[20244003x_00000012x] mov.f32f32 r0.w, c4.z
1640 :0:0027:0027[00000200x_00000000x] (rpt2)nop
1641 :2:0028:0030[40100003x_0003101ex] add.f r0.w, c7.z, r0.w
1642 :0:0029:0031[00000000x_00000000x] nop
1643 :4:0030:0032[80300000x_00000000x] rsq r0.x, r0.x
1644 :2:0031:0033[40701004x_00000007x] (ss)mul.f r1.x, r1.w, r0.x
1645 :0:0032:0034[00000200x_00000000x] (rpt2)nop
1646 :2:0033:0037[40700004x_10150004x] mul.f r1.x, r1.x, c5.y
1647 :2:0034:0038[40700005x_00000006x] mul.f r1.y, r1.z, r0.x
1648 :0:0035:0039[00000200x_00000000x] (rpt2)nop
1649 :3:0036:0042[63828004x_00041014x] mad.f32 r1.x, c5.x, r1.y, r1.x
1650 :2:0037:0043[40700000x_00000008x] mul.f r0.x, r2.x, r0.x
1651 :0:0038:0044[00000200x_00000000x] (rpt2)nop
1652 :3:0039:0047[63800000x_00041016x] mad.f32 r0.x, c5.z, r0.x, r1.x
1653 :0:0040:0048[00000200x_00000000x] (rpt2)nop
1654 :2:0041:0051[40b00004x_00001034x] cmps.f.lt r1.x, c13.x, r0.x
1655 :2:0042:0052[40500000x_00001034x] max.f r0.x, c13.x, r0.x
1656 :0:0043:0053[00000100x_00000000x] (rpt1)nop
1657 :1:0044:0055[200c4004x_00000004x] cov.u32f32 r1.x, r1.x
1658 :3:0045:0056[63800001x_00011020x] mad.f32 r0.y, c8.x, r0.x, r0.y
1659 :3:0046:0057[63800002x_00021021x] mad.f32 r0.z, c8.y, r0.x, r0.z
1660 :3:0047:0058[63800000x_00031022x] mad.f32 r0.x, c8.z, r0.x, r0.w
1661 :3:0048:0059[6382040ex_00011024x] (sat)mad.f32 r3.z, c9.x, r1.x, r0.y
1662 :3:0049:0060[6382040fx_00021025x] (sat)mad.f32 r3.w, c9.y, r1.x, r0.z
1663 :3:0050:0061[63820410x_00001026x] (sat)mad.f32 r4.x, c9.z, r1.x, r0.x
1664 :0:0051:0062[03000000x_00000000x] end
1665 :0:0052:0063[00000000x_00000000x] nop
1666 :0:0053:0064[00000000x_00000000x] nop
1667 :0:0054:0065[00000000x_00000000x] nop
1668 :0:0055:0066[00000000x_00000000x] nop
1669 Register Stats:
1670 - used (half): (cnt=0, max=0)
1671 - used (full): 0-8 10-17 (cnt=17, max=17)
1672 - input (half): (cnt=0, max=0)
1673 - input (full): 2-8 (cnt=7, max=8)
1674 - max const: 52
1675
1676 - output (half): (cnt=0, max=0) (estimated)
1677 - output (full): 10-17 (cnt=8, max=17) (estimated)
1678 - shaderdb: 67 instructions, 31 nops, 36 non-nops, (56 instlen), 0 half, 5 full
1679 - shaderdb: 1 (ss), 0 (sy)
1680 109cee34: 0000: c0813000 01200000 00000000 10000002 40700000 10030002 40700001 00001004
1681 109cee54: 0020: 63818000 00011007 63818001 00001008 63820000 0001100b 63820001 0000100c
1682 109cee74: 0040: 6382800a 10010002 40700000 0001100f 6382800d 00001005 63818000 00000010
1683 109cee94: 0060: 20244001 00001009 63820000 00000000 00000000 0000100d 6382800b 10020002
1684 109ceeb4: 0080: 40700000 0001101c 40100001 00001006 63818000 00000011 20244002 0000100a
1685 109ceed4: 00a0: 63820000 00000013 20244004 0000100e 6382800c 00070007 40700000 0002101d
1686 109ceef4: 00c0: 40100002 00000006 63830000 00041013 40500411 00000008 63840000 00000012
1687 109cef14: 00e0: 20244003 00000000 00000200 0003101e 40100003 00000000 00000000 00000000
1688 109cef34: 0100: 80300000 00000007 40701004 00000000 00000200 10150004 40700004 00000006
1689 109cef54: 0120: 40700005 00000000 00000200 00041014 63828004 00000008 40700000 00000000
1690 109cef74: 0140: 00000200 00041016 63800000 00000000 00000200 00001034 40b00004 00001034
1691 109cef94: 0160: 40500000 00000000 00000100 00000004 200c4004 00011020 63800001 00021021
1692 109cefb4: 0180: 63800002 00031022 63800000 00011024 6382040e 00021025 6382040f 00001026
1693 109cefd4: 01a0: 63820410 00000000 03000000 00000000 00000000 00000000 00000000 00000000
1694 *
1695 t3 opcode: CP_LOAD_STATE4 (30) (35 dwords)
1696 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 }
1697 { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 }
1698 :0:0000:0000[00000000x_00000000x] nop
1699 :6:0001:0001[c7c60000x_01c00000x] ldlv.u32 r0.x, l[0], 1
1700 :6:0002:0002[c7c60001x_01c00002x] ldlv.u32 r0.y, l[1], 1
1701 :6:0003:0003[c7c60002x_01c00004x] ldlv.u32 r0.z, l[2], 1
1702 :6:0004:0004[c7c60003x_01c00006x] ldlv.u32 r0.w, l[3], 1
1703 :2:0005:0005[473090fcx_00002000x] (ss)bary.f (ei)r63.x, 0, r0.x
1704 :0:0006:0006[03000000x_00000000x] end
1705 :0:0007:0007[00000000x_00000000x] nop
1706 :0:0008:0008[00000000x_00000000x] nop
1707 :0:0009:0009[00000000x_00000000x] nop
1708 :0:0010:0010[00000000x_00000000x] nop
1709 Register Stats:
1710 - used (half): (cnt=0, max=0)
1711 - used (full): 0-3 (cnt=4, max=3)
1712 - input (half): (cnt=0, max=0)
1713 - input (full): 0-3 (cnt=4, max=3)
1714 - max const: 0
1715
1716 - output (half): (cnt=0, max=0) (estimated)
1717 - output (full): (cnt=0, max=0) (estimated)
1718 - shaderdb: 11 instructions, 5 nops, 6 non-nops, (11 instlen), 0 half, 1 full
1719 - shaderdb: 1 (ss), 0 (sy)
1720 109cf040: 0000: c0213000 00700000 00000000 00000000 00000000 01c00000 c7c60000 01c00002
1721 109cf060: 0020: c7c60001 01c00004 c7c60002 01c00006 c7c60003 00002000 473090fc 00000000
1722 109cf080: 0040: 03000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
1723 *
1724 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
1725 109cf0cc: 0000: c0002600 00000000
1726 t3 opcode: CP_LOAD_STATE4 (30) (51 dwords)
1727 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 }
1728 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 }
1729 109cf0e0: 4.330127 0.855050 0.555273 0.469846 0.000000 4.698463 -0.404206 -0.342020
1730 109cf100: 2.500000 -1.480991 -0.961761 -0.813798 -12.990380 -11.962078 35.506226 39.274502
1731 109cf120: 0.160000 0.020000 0.000000 1.000000 0.039740 0.662886 0.747665 0.000000
1732 109cf140: 1.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 1.000000
1733 109cf160: 0.800000 0.100000 0.000000 1.000000 0.000000 0.000000 0.000000 1.000000
1734 109cf180: 0.000000 0.000000 0.000000 1.000000 0.000000 0.000000 0.000000 0.000000
1735 109cf0e0: 0000: 408a9066 3f5ae494 3f0e265d 3ef08fb2 00000000 409659cf becef409 beaf1d43
1736 109cf100: 0020: 40200000 bfbd9119 bf7635f5 bf50550b c14fd899 c13f64ac 420e0660 421d1917
1737 109cf120: 0040: 3e23d70b 3ca3d70b 00000000 3f800000 3d22c66e 3f29b2e7 3f3f66f5 00000000
1738 109cf140: 0060: 3f800000 00000000 00000000 00000000 00000000 00000000 00000000 3f800000
1739 109cf160: 0080: 3f4ccccd 3dcccccd 00000000 3f800000 00000000 00000000 00000000 3f800000
1740 109cf180: 00a0: 00000000 00000000 00000000 3f800000 02020000 02020202 02020202 00000202
1741 109cf0d4: 0000: c0313000 03200000 00000001 408a9066 3f5ae494 3f0e265d 3ef08fb2 00000000
1742 109cf0f4: 0020: 409659cf becef409 beaf1d43 40200000 bfbd9119 bf7635f5 bf50550b c14fd899
1743 109cf114: 0040: c13f64ac 420e0660 421d1917 3e23d70b 3ca3d70b 00000000 3f800000 3d22c66e
1744 109cf134: 0060: 3f29b2e7 3f3f66f5 00000000 3f800000 00000000 00000000 00000000 00000000
1745 109cf154: 0080: 00000000 00000000 3f800000 3f4ccccd 3dcccccd 00000000 3f800000 00000000
1746 109cf174: 00a0: 00000000 00000000 3f800000 00000000 00000000 00000000 3f800000 02020000
1747 109cf194: 00c0: 02020202 02020202 00000202
1748 t3 opcode: CP_LOAD_STATE4 (30) (7 dwords)
1749 { DST_OFF = 13 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 }
1750 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 }
1751 109cf1ac: 0.000000 -28026765312.000000 -28026765312.000000 -28026765312.000000
1752 109cf1ac: 0000: 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0
1753 109cf1a0: 0000: c0053000 0060000d 00000001 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0
1754 t0 write VFD_FETCH[0].INSTR_0 (220a)
1755 VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 | SWITCHNEXT }
1756 VFD_FETCH[0].INSTR_1: 0x107cb000
1757 VFD_FETCH[0].INSTR_2: { SIZE = 0x100000 }
1758 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 }
1759 109cf1bc: 0000: 0003220a 00080c0b 107cb000 00100000 00000001
1760 t0 write VFD_DECODE[0].INSTR (228a)
1761 VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID | SWITCHNEXT }
1762 109cf1d0: 0000: 0000228a 6c0020df
1763 t0 write VFD_FETCH[0x1].INSTR_0 (220e)
1764 VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 }
1765 VFD_FETCH[0x1].INSTR_1: 0x107cb00c
1766 VFD_FETCH[0x1].INSTR_2: { SIZE = 0xffff4 }
1767 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 }
1768 109cf1d8: 0000: 0003220e 00000c0b 107cb00c 000ffff4 00000001
1769 t0 write VFD_DECODE[0x1].INSTR (228b)
1770 VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r1.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID }
1771 109cf1ec: 0000: 0000228b 2c0060df
1772 t0 write VFD_CONTROL_0 (2200)
1773 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 }
1774 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x }
1775 VFD_CONTROL_2: 0
1776 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x }
1777 VFD_CONTROL_4: 0
1778 109cf1f4: 0000: 00042200 082a0008 fcfc0081 00000000 0000fc00 00000000
1779 t0 write UCHE_INVALIDATE0 (0e8a)
1780 UCHE_INVALIDATE0: 0
1781 UCHE_INVALIDATE1: 0x12
1782 109cf20c: 0000: 00010e8a 00000000 00000012
1783 t0 write VFD_INDEX_OFFSET (2208)
1784 VFD_INDEX_OFFSET: 0
1785 UNKNOWN_2209: 0
1786 109cf218: 0000: 00012208 00000000 00000000
1787 t0 write PC_RESTART_INDEX (21c6)
1788 PC_RESTART_INDEX: 0xffffffff
1789 109cf224: 0000: 000021c6 ffffffff
1790 t0 write CP_SCRATCH[0x7].REG (057f)
1791 CP_SCRATCH[0x7].REG: 0x20
1792 :0,31,115,32
1793 109cf22c: 0000: 0000057f 00000020
1794 t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
1795 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS }
1796 { NUM_INSTANCES = 1 }
1797 { NUM_INDICES = 480 }
1798 { FIRST_INDX = 0 }
1799 { INDX_BASE = 0x10bd05a0 }
1800 { INDX_SIZE = 960 }
1801 draw[5] register values
1802 !+ 0000001f CP_SCRATCH[0x5].REG: 0x1f
1803 :0,31,115,32
1804 !+ 00000020 CP_SCRATCH[0x7].REG: 0x20
1805 :0,31,115,32
1806 + 00000000 UCHE_INVALIDATE0: 0
1807 + 00000012 UCHE_INVALIDATE1: 0x12
1808 + 00000000 GRAS_CNTL: { 0 }
1809 + 00000000 GRAS_ALPHA_CONTROL: { 0 }
1810 + 00000000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 }
1811 + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 }
1812 + 80000016 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE }
1813 + 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 }
1814 + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 }
1815 + 00000055 VPC_VARYING_INTERP[0].MODE: 0x55
1816 + 00000000 VPC_VARYING_INTERP[0x1].MODE: 0
1817 + 00000000 VPC_VARYING_INTERP[0x2].MODE: 0
1818 + 00000000 VPC_VARYING_INTERP[0x3].MODE: 0
1819 + 00000000 VPC_VARYING_INTERP[0x4].MODE: 0
1820 + 00000000 VPC_VARYING_INTERP[0x5].MODE: 0
1821 + 00000000 VPC_VARYING_INTERP[0x6].MODE: 0
1822 + 00000000 VPC_VARYING_INTERP[0x7].MODE: 0
1823 + 00000000 VPC_VARYING_PS_REPL[0].MODE: 0
1824 + 00000000 VPC_VARYING_PS_REPL[0x1].MODE: 0
1825 + 00000000 VPC_VARYING_PS_REPL[0x2].MODE: 0
1826 + 00000000 VPC_VARYING_PS_REPL[0x3].MODE: 0
1827 + 00000000 VPC_VARYING_PS_REPL[0x4].MODE: 0
1828 + 00000000 VPC_VARYING_PS_REPL[0x5].MODE: 0
1829 + 00000000 VPC_VARYING_PS_REPL[0x6].MODE: 0
1830 + 00000000 VPC_VARYING_PS_REPL[0x7].MODE: 0
1831 + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
1832 + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
1833 + ffffffff PC_RESTART_INDEX: 0xffffffff
1834 !+ 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 }
1835 + fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x }
1836 + 00000000 VFD_CONTROL_2: 0
1837 + 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x }
1838 + 00000000 VFD_CONTROL_4: 0
1839 + 00000000 VFD_INDEX_OFFSET: 0
1840 + 00000000 UNKNOWN_2209: 0
1841 !+ 00080c0b VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 | SWITCHNEXT }
1842 + 107cb000 VFD_FETCH[0].INSTR_1: 0x107cb000
1843 + 00100000 VFD_FETCH[0].INSTR_2: { SIZE = 0x100000 }
1844 + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 }
1845 !+ 00000c0b VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 }
1846 !+ 107cb00c VFD_FETCH[0x1].INSTR_1: 0x107cb00c
1847 !+ 000ffff4 VFD_FETCH[0x1].INSTR_2: { SIZE = 0xffff4 }
1848 !+ 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 }
1849 !+ 6c0020df VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID | SWITCHNEXT }
1850 !+ 2c0060df VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r1.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID }
1851 + 00140010 SP_SP_CTRL_REG: { 0x140010 }
1852 + 000005ff SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f }
1853 !+ 00201400 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE }
1854 !+ 08000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 8 }
1855 !+ 0010fc0a SP_VS_PARAM_REG: { POSREGID = r2.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 }
1856 !+ 00001e0e SP_VS_OUT[0].REG: { A_REGID = r3.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 }
1857 + 08080808 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 }
1858 + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 }
1859 !+ 10cd5000 SP_VS_OBJ_START: 0x10cd5000
1860 + 00000004 SP_VS_LENGTH_REG: 4
1861 + 00340402 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE }
1862 + 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 }
1863 + 7e420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
1864 + 10cd2000 SP_FS_OBJ_START: 0x10cd2000
1865 + 00000001 SP_FS_LENGTH_REG: 1
1866 + 0000fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x }
1867 + 0001a000 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM }
1868 + 00000000 SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 }
1869 + 00000000 SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 }
1870 + 00000000 SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 }
1871 + 00000000 SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 }
1872 + 00000000 SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 }
1873 + 00000000 SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 }
1874 + 00000000 SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 }
1875 + 7e420000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
1876 + 7e420000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
1877 + 7e420000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
1878 + 28000250 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE }
1879 + fcfc0100 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x }
1880 + fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x }
1881 + fcfcfcfc HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
1882 + 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 }
1883 + 04000042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 }
1884 + 017e423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 }
1885 + 007e4200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
1886 + 007e4200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
1887 + 007e4200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
1888 + 00000003 HLSQ_UPDATE_CONTROL: 0x3
1889 109cf234: 0000: c0053800 00000404 00000001 000001e0 00000000 10bd05a0 000003c0
1890 t0 write CP_SCRATCH[0x7].REG (057f)
1891 CP_SCRATCH[0x7].REG: 0x21
1892 :0,31,115,33
1893 109cf250: 0000: 0000057f 00000021
1894 t0 write CP_SCRATCH[0x5].REG (057d)
1895 CP_SCRATCH[0x5].REG: 0x25
1896 :0,37,115,33
1897 109cf258: 0000: 0000057d 00000025
1898 t0 write RB_DEPTH_CONTROL (2101)
1899 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE }
1900 109cf260: 0000: 00002101 80000016
1901 t0 write GRAS_ALPHA_CONTROL (2073)
1902 GRAS_ALPHA_CONTROL: { 0 }
1903 109cf268: 0000: 00002073 00000000
1904 t0 write GRAS_SU_MODE_CONTROL (2078)
1905 GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 | RENDERING_PASS }
1906 109cf270: 0000: 00002078 00100012
1907 t0 write GRAS_SU_POINT_MINMAX (2070)
1908 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 }
1909 GRAS_SU_POINT_SIZE: 1.000000
1910 109cf278: 0000: 00012070 00100010 00000010
1911 t0 write GRAS_SU_POLY_OFFSET_SCALE (2074)
1912 GRAS_SU_POLY_OFFSET_SCALE: 0.000000
1913 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000
1914 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000
1915 109cf284: 0000: 00022074 00000000 00000000 00000000
1916 t0 write GRAS_CL_CLIP_CNTL (2000)
1917 GRAS_CL_CLIP_CNTL: { 0x80000 }
1918 109cf294: 0000: 00002000 00080000
1919 t0 write PC_PRIM_VTX_CNTL (21c4)
1920 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
1921 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
1922 109cf29c: 0000: 000121c4 02000001 00000012
1923 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c)
1924 GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 }
1925 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
1926 109cf2a8: 0000: 0001209c 012b012b 00000000
1927 t0 write RB_VPORT_Z_CLAMP[0].MIN (2120)
1928 RB_VPORT_Z_CLAMP[0].MIN: 0
1929 RB_VPORT_Z_CLAMP[0].MAX: 0xffffff
1930 109cf2b4: 0000: 00012120 00000000 00ffffff
1931 t0 write HLSQ_UPDATE_CONTROL (23db)
1932 HLSQ_UPDATE_CONTROL: 0x3
1933 109cf2c0: 0000: 000023db 00000003
1934 t0 write HLSQ_CONTROL_0_REG (23c0)
1935 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE }
1936 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x }
1937 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x }
1938 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
1939 HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 }
1940 109cf2c8: 0000: 000423c0 28000250 fcfc0100 fff3f3f0 fcfcfc00 00fcfcfc
1941 t0 write HLSQ_VS_CONTROL_REG (23c5)
1942 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 }
1943 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 }
1944 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
1945 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
1946 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
1947 109cf2e0: 0000: 000423c5 04000042 017e423e 007e4200 007e4200 007e4200
1948 t0 write SP_SP_CTRL_REG (22c0)
1949 SP_SP_CTRL_REG: { 0x140010 }
1950 109cf2f8: 0000: 000022c0 00140010
1951 t0 write SP_INSTR_CACHE_CTRL (22c1)
1952 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f }
1953 109cf300: 0000: 000022c1 000005ff
1954 t0 write SP_VS_LENGTH_REG (22e5)
1955 SP_VS_LENGTH_REG: 4
1956 109cf308: 0000: 000022e5 00000004
1957 t0 write SP_VS_CTRL_REG0 (22c4)
1958 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE }
1959 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 8 }
1960 SP_VS_PARAM_REG: { POSREGID = r2.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 }
1961 109cf310: 0000: 000222c4 00201400 08000042 0010fc0a
1962 t0 write SP_VS_OUT[0].REG (22c7)
1963 SP_VS_OUT[0].REG: { A_REGID = r3.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 }
1964 109cf320: 0000: 000022c7 00001e0e
1965 t0 write SP_VS_VPC_DST[0].REG (22d8)
1966 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 }
1967 109cf328: 0000: 000022d8 08080808
1968 t0 write SP_VS_OBJ_OFFSET_REG (22e0)
1969 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 }
1970 SP_VS_OBJ_START: 0x10cd5000
1971 109cf330: 0000: 000122e0 00000000 10cd5000
1972 t0 write SP_FS_LENGTH_REG (22ef)
1973 SP_FS_LENGTH_REG: 1
1974 109cf33c: 0000: 000022ef 00000001
1975 t0 write SP_FS_CTRL_REG0 (22e8)
1976 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE }
1977 SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 }
1978 109cf344: 0000: 000122e8 00340802 8010003e
1979 t0 write SP_FS_OBJ_OFFSET_REG (22ea)
1980 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
1981 SP_FS_OBJ_START: 0x108cb000
1982 109cf350: 0000: 000122ea 7e420000 108cb000
1983 t0 write SP_HS_OBJ_OFFSET_REG (230d)
1984 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
1985 109cf35c: 0000: 0000230d 7e420000
1986 t0 write SP_DS_OBJ_OFFSET_REG (2334)
1987 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
1988 109cf364: 0000: 00002334 7e420000
1989 t0 write SP_GS_OBJ_OFFSET_REG (235b)
1990 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
1991 109cf36c: 0000: 0000235b 7e420000
1992 t0 write GRAS_CNTL (2003)
1993 GRAS_CNTL: { IJ_PERSP }
1994 109cf374: 0000: 00002003 00000001
1995 t0 write RB_RENDER_CONTROL2 (20a3)
1996 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL }
1997 109cf37c: 0000: 000020a3 00001000
1998 t0 write RB_FS_OUTPUT_REG (2100)
1999 RB_FS_OUTPUT_REG: { MRT = 1 }
2000 109cf384: 0000: 00002100 00000001
2001 t0 write SP_FS_OUTPUT_REG (22f0)
2002 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x }
2003 109cf38c: 0000: 000022f0 0000fc01
2004 t0 write SP_FS_MRT[0].REG (22f1)
2005 SP_FS_MRT[0].REG: { REGID = r0.z | MRTFORMAT = RB4_R8G8B8A8_UNORM }
2006 SP_FS_MRT[0x1].REG: { REGID = r0.z | MRTFORMAT = 0 }
2007 SP_FS_MRT[0x2].REG: { REGID = r0.z | MRTFORMAT = 0 }
2008 SP_FS_MRT[0x3].REG: { REGID = r0.z | MRTFORMAT = 0 }
2009 SP_FS_MRT[0x4].REG: { REGID = r0.z | MRTFORMAT = 0 }
2010 SP_FS_MRT[0x5].REG: { REGID = r0.z | MRTFORMAT = 0 }
2011 SP_FS_MRT[0x6].REG: { REGID = r0.z | MRTFORMAT = 0 }
2012 SP_FS_MRT[0x7].REG: { REGID = r0.z | MRTFORMAT = 0 }
2013 109cf394: 0000: 000722f1 0001a002 00000002 00000002 00000002 00000002 00000002 00000002
2014 109cf3b4: 0020: 00000002
2015 t0 write VPC_ATTR (2140)
2016 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 }
2017 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 }
2018 109cf3b8: 0000: 00012140 42001004 00040400
2019 t0 write VPC_VARYING_INTERP[0].MODE (2142)
2020 VPC_VARYING_INTERP[0].MODE: 0
2021 VPC_VARYING_INTERP[0x1].MODE: 0
2022 VPC_VARYING_INTERP[0x2].MODE: 0
2023 VPC_VARYING_INTERP[0x3].MODE: 0
2024 VPC_VARYING_INTERP[0x4].MODE: 0
2025 VPC_VARYING_INTERP[0x5].MODE: 0
2026 VPC_VARYING_INTERP[0x6].MODE: 0
2027 VPC_VARYING_INTERP[0x7].MODE: 0
2028 109cf3c4: 0000: 00072142 00000000 00000000 00000000 00000000 00000000 00000000 00000000
2029 *
2030 t0 write VPC_VARYING_PS_REPL[0].MODE (214a)
2031 VPC_VARYING_PS_REPL[0].MODE: 0
2032 VPC_VARYING_PS_REPL[0x1].MODE: 0
2033 VPC_VARYING_PS_REPL[0x2].MODE: 0
2034 VPC_VARYING_PS_REPL[0x3].MODE: 0
2035 VPC_VARYING_PS_REPL[0x4].MODE: 0
2036 VPC_VARYING_PS_REPL[0x5].MODE: 0
2037 VPC_VARYING_PS_REPL[0x6].MODE: 0
2038 VPC_VARYING_PS_REPL[0x7].MODE: 0
2039 109cf3e8: 0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000
2040 *
2041 t3 opcode: CP_LOAD_STATE4 (30) (131 dwords)
2042 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 }
2043 { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 }
2044 :2:0000:0000[40700000x_10000002x] mul.f r0.x, r0.z, c0.x
2045 :2:0001:0001[40700001x_10030002x] mul.f r0.y, r0.z, c0.w
2046 :3:0002:0002[63818000x_00001004x] mad.f32 r0.x, c1.x, r0.w, r0.x
2047 :3:0003:0003[63818001x_00011007x] mad.f32 r0.y, c1.w, r0.w, r0.y
2048 :3:0004:0004[63820000x_00001008x] mad.f32 r0.x, c2.x, r1.x, r0.x
2049 :3:0005:0005[63820001x_0001100bx] mad.f32 r0.y, c2.w, r1.x, r0.y
2050 :3:0006:0006[6382800ax_0000100cx] mad.f32 r2.z, c3.x, r1.y, r0.x
2051 :2:0007:0007[40700000x_10010002x] mul.f r0.x, r0.z, c0.y
2052 :3:0008:0008[6382800dx_0001100fx] mad.f32 r3.y, c3.w, r1.y, r0.y
2053 :3:0009:0009[63818000x_00001005x] mad.f32 r0.x, c1.y, r0.w, r0.x
2054 :1:0010:0010[20244001x_00000010x] mov.f32f32 r0.y, c4.x
2055 :3:0011:0011[63820000x_00001009x] mad.f32 r0.x, c2.y, r1.x, r0.x
2056 :0:0012:0012[00000000x_00000000x] nop
2057 :3:0013:0013[6382800bx_0000100dx] mad.f32 r2.w, c3.y, r1.y, r0.x
2058 :2:0014:0014[40700000x_10020002x] mul.f r0.x, r0.z, c0.z
2059 :2:0015:0015[40100001x_0001101cx] add.f r0.y, c7.x, r0.y
2060 :3:0016:0016[63818000x_00001006x] mad.f32 r0.x, c1.z, r0.w, r0.x
2061 :1:0017:0017[20244002x_00000011x] mov.f32f32 r0.z, c4.y
2062 :3:0018:0018[63820000x_0000100ax] mad.f32 r0.x, c2.z, r1.x, r0.x
2063 :1:0019:0019[20244004x_00000013x] mov.f32f32 r1.x, c4.w
2064 :3:0020:0020[6382800cx_0000100ex] mad.f32 r3.x, c3.z, r1.y, r0.x
2065 :2:0021:0021[40700000x_00070007x] mul.f r0.x, r1.w, r1.w
2066 :2:0022:0022[40100002x_0002101dx] add.f r0.z, c7.y, r0.z
2067 :3:0023:0023[63830000x_00000006x] mad.f32 r0.x, r1.z, r1.z, r0.x
2068 :2:0024:0024[40500411x_00041013x] (sat)max.f r4.y, c4.w, r1.x
2069 :3:0025:0025[63840000x_00000008x] mad.f32 r0.x, r2.x, r2.x, r0.x
2070 :1:0026:0026[20244003x_00000012x] mov.f32f32 r0.w, c4.z
2071 :0:0027:0027[00000200x_00000000x] (rpt2)nop
2072 :2:0028:0030[40100003x_0003101ex] add.f r0.w, c7.z, r0.w
2073 :0:0029:0031[00000000x_00000000x] nop
2074 :4:0030:0032[80300000x_00000000x] rsq r0.x, r0.x
2075 :2:0031:0033[40701004x_00000007x] (ss)mul.f r1.x, r1.w, r0.x
2076 :0:0032:0034[00000200x_00000000x] (rpt2)nop
2077 :2:0033:0037[40700004x_10150004x] mul.f r1.x, r1.x, c5.y
2078 :2:0034:0038[40700005x_00000006x] mul.f r1.y, r1.z, r0.x
2079 :0:0035:0039[00000200x_00000000x] (rpt2)nop
2080 :3:0036:0042[63828004x_00041014x] mad.f32 r1.x, c5.x, r1.y, r1.x
2081 :2:0037:0043[40700000x_00000008x] mul.f r0.x, r2.x, r0.x
2082 :0:0038:0044[00000200x_00000000x] (rpt2)nop
2083 :3:0039:0047[63800000x_00041016x] mad.f32 r0.x, c5.z, r0.x, r1.x
2084 :0:0040:0048[00000200x_00000000x] (rpt2)nop
2085 :2:0041:0051[40b00004x_00001034x] cmps.f.lt r1.x, c13.x, r0.x
2086 :2:0042:0052[40500000x_00001034x] max.f r0.x, c13.x, r0.x
2087 :0:0043:0053[00000100x_00000000x] (rpt1)nop
2088 :1:0044:0055[200c4004x_00000004x] cov.u32f32 r1.x, r1.x
2089 :3:0045:0056[63800001x_00011020x] mad.f32 r0.y, c8.x, r0.x, r0.y
2090 :3:0046:0057[63800002x_00021021x] mad.f32 r0.z, c8.y, r0.x, r0.z
2091 :3:0047:0058[63800000x_00031022x] mad.f32 r0.x, c8.z, r0.x, r0.w
2092 :3:0048:0059[6382040ex_00011024x] (sat)mad.f32 r3.z, c9.x, r1.x, r0.y
2093 :3:0049:0060[6382040fx_00021025x] (sat)mad.f32 r3.w, c9.y, r1.x, r0.z
2094 :3:0050:0061[63820410x_00001026x] (sat)mad.f32 r4.x, c9.z, r1.x, r0.x
2095 :0:0051:0062[03000000x_00000000x] end
2096 :0:0052:0063[00000000x_00000000x] nop
2097 :0:0053:0064[00000000x_00000000x] nop
2098 :0:0054:0065[00000000x_00000000x] nop
2099 :0:0055:0066[00000000x_00000000x] nop
2100 Register Stats:
2101 - used (half): (cnt=0, max=0)
2102 - used (full): 0-8 10-17 (cnt=17, max=17)
2103 - input (half): (cnt=0, max=0)
2104 - input (full): 2-8 (cnt=7, max=8)
2105 - max const: 52
2106
2107 - output (half): (cnt=0, max=0) (estimated)
2108 - output (full): 10-17 (cnt=8, max=17) (estimated)
2109 - shaderdb: 67 instructions, 31 nops, 36 non-nops, (56 instlen), 0 half, 5 full
2110 - shaderdb: 1 (ss), 0 (sy)
2111 109cf40c: 0000: c0813000 01200000 00000000 10000002 40700000 10030002 40700001 00001004
2112 109cf42c: 0020: 63818000 00011007 63818001 00001008 63820000 0001100b 63820001 0000100c
2113 109cf44c: 0040: 6382800a 10010002 40700000 0001100f 6382800d 00001005 63818000 00000010
2114 109cf46c: 0060: 20244001 00001009 63820000 00000000 00000000 0000100d 6382800b 10020002
2115 109cf48c: 0080: 40700000 0001101c 40100001 00001006 63818000 00000011 20244002 0000100a
2116 109cf4ac: 00a0: 63820000 00000013 20244004 0000100e 6382800c 00070007 40700000 0002101d
2117 109cf4cc: 00c0: 40100002 00000006 63830000 00041013 40500411 00000008 63840000 00000012
2118 109cf4ec: 00e0: 20244003 00000000 00000200 0003101e 40100003 00000000 00000000 00000000
2119 109cf50c: 0100: 80300000 00000007 40701004 00000000 00000200 10150004 40700004 00000006
2120 109cf52c: 0120: 40700005 00000000 00000200 00041014 63828004 00000008 40700000 00000000
2121 109cf54c: 0140: 00000200 00041016 63800000 00000000 00000200 00001034 40b00004 00001034
2122 109cf56c: 0160: 40500000 00000000 00000100 00000004 200c4004 00011020 63800001 00021021
2123 109cf58c: 0180: 63800002 00031022 63800000 00011024 6382040e 00021025 6382040f 00001026
2124 109cf5ac: 01a0: 63820410 00000000 03000000 00000000 00000000 00000000 00000000 00000000
2125 *
2126 t3 opcode: CP_LOAD_STATE4 (30) (35 dwords)
2127 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 }
2128 { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 }
2129 :2:0000:0000[47300002x_00002000x] bary.f r0.z, 0, r0.x
2130 :2:0001:0001[47300003x_00002001x] bary.f r0.w, 1, r0.x
2131 :2:0002:0002[47300004x_00002002x] bary.f r1.x, 2, r0.x
2132 :2:0003:0003[47308005x_00002003x] bary.f (ei)r1.y, 3, r0.x
2133 :0:0004:0004[03000000x_00000000x] end
2134 :0:0005:0005[00000000x_00000000x] nop
2135 :0:0006:0006[00000000x_00000000x] nop
2136 :0:0007:0007[00000000x_00000000x] nop
2137 :0:0008:0008[00000000x_00000000x] nop
2138 Register Stats:
2139 - used (half): (cnt=0, max=0)
2140 - used (full): 0 2-5 (cnt=5, max=5)
2141 - input (half): (cnt=0, max=0)
2142 - input (full): 0 (cnt=1, max=0)
2143 - max const: 0
2144
2145 - output (half): (cnt=0, max=0) (estimated)
2146 - output (full): 2-5 (cnt=4, max=5) (estimated)
2147 - shaderdb: 9 instructions, 4 nops, 5 non-nops, (9 instlen), 0 half, 2 full
2148 - shaderdb: 0 (ss), 0 (sy)
2149 109cf618: 0000: c0213000 00700000 00000000 00002000 47300002 00002001 47300003 00002002
2150 109cf638: 0020: 47300004 00002003 47308005 00000000 03000000 00000000 00000000 00000000
2151 *
2152 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
2153 109cf6a4: 0000: c0002600 00000000
2154 t3 opcode: CP_LOAD_STATE4 (30) (51 dwords)
2155 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 }
2156 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 }
2157 109cf6b8: 4.330127 0.855050 0.555273 0.469846 0.000000 4.698463 -0.404206 -0.342020
2158 109cf6d8: 2.500000 -1.480991 -0.961761 -0.813798 -12.990380 -11.962078 35.506226 39.274502
2159 109cf6f8: 0.160000 0.020000 0.000000 1.000000 0.039740 0.662886 0.747665 0.000000
2160 109cf718: 1.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 1.000000
2161 109cf738: 0.800000 0.100000 0.000000 1.000000 0.000000 0.000000 0.000000 1.000000
2162 109cf758: 0.000000 0.000000 0.000000 1.000000 0.000000 0.000000 0.000000 0.000000
2163 109cf6b8: 0000: 408a9066 3f5ae494 3f0e265d 3ef08fb2 00000000 409659cf becef409 beaf1d43
2164 109cf6d8: 0020: 40200000 bfbd9119 bf7635f5 bf50550b c14fd899 c13f64ac 420e0660 421d1917
2165 109cf6f8: 0040: 3e23d70b 3ca3d70b 00000000 3f800000 3d22c66e 3f29b2e7 3f3f66f5 00000000
2166 109cf718: 0060: 3f800000 00000000 00000000 00000000 00000000 00000000 00000000 3f800000
2167 109cf738: 0080: 3f4ccccd 3dcccccd 00000000 3f800000 00000000 00000000 00000000 3f800000
2168 109cf758: 00a0: 00000000 00000000 00000000 3f800000 02020000 02020202 02020202 00000202
2169 109cf6ac: 0000: c0313000 03200000 00000001 408a9066 3f5ae494 3f0e265d 3ef08fb2 00000000
2170 109cf6cc: 0020: 409659cf becef409 beaf1d43 40200000 bfbd9119 bf7635f5 bf50550b c14fd899
2171 109cf6ec: 0040: c13f64ac 420e0660 421d1917 3e23d70b 3ca3d70b 00000000 3f800000 3d22c66e
2172 109cf70c: 0060: 3f29b2e7 3f3f66f5 00000000 3f800000 00000000 00000000 00000000 00000000
2173 109cf72c: 0080: 00000000 00000000 3f800000 3f4ccccd 3dcccccd 00000000 3f800000 00000000
2174 109cf74c: 00a0: 00000000 00000000 3f800000 00000000 00000000 00000000 3f800000 02020000
2175 109cf76c: 00c0: 02020202 02020202 00000202
2176 t0 write VFD_INDEX_OFFSET (2208)
2177 VFD_INDEX_OFFSET: 0
2178 UNKNOWN_2209: 0
2179 109cf778: 0000: 00012208 00000000 00000000
2180 t0 write PC_RESTART_INDEX (21c6)
2181 PC_RESTART_INDEX: 0xffffffff
2182 109cf784: 0000: 000021c6 ffffffff
2183 t0 write CP_SCRATCH[0x7].REG (057f)
2184 CP_SCRATCH[0x7].REG: 0x26
2185 :0,37,115,38
2186 109cf78c: 0000: 0000057f 00000026
2187 t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
2188 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS }
2189 { NUM_INSTANCES = 1 }
2190 { NUM_INDICES = 120 }
2191 { FIRST_INDX = 0 }
2192 { INDX_BASE = 0x10bd0960 }
2193 { INDX_SIZE = 240 }
2194 draw[6] register values
2195 !+ 00000025 CP_SCRATCH[0x5].REG: 0x25
2196 :0,37,115,38
2197 !+ 00000026 CP_SCRATCH[0x7].REG: 0x26
2198 :0,37,115,38
2199 + 00080000 GRAS_CL_CLIP_CNTL: { 0x80000 }
2200 !+ 00000001 GRAS_CNTL: { IJ_PERSP }
2201 + 00100010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 }
2202 + 00000010 GRAS_SU_POINT_SIZE: 1.000000
2203 + 00000000 GRAS_ALPHA_CONTROL: { 0 }
2204 + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000
2205 + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000
2206 + 00000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000
2207 + 00100012 GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 | RENDERING_PASS }
2208 + 012b012b GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 }
2209 + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
2210 !+ 00001000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL }
2211 + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 }
2212 + 80000016 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE }
2213 + 00000000 RB_VPORT_Z_CLAMP[0].MIN: 0
2214 + 00ffffff RB_VPORT_Z_CLAMP[0].MAX: 0xffffff
2215 + 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 }
2216 + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 }
2217 !+ 00000000 VPC_VARYING_INTERP[0].MODE: 0
2218 + 00000000 VPC_VARYING_INTERP[0x1].MODE: 0
2219 + 00000000 VPC_VARYING_INTERP[0x2].MODE: 0
2220 + 00000000 VPC_VARYING_INTERP[0x3].MODE: 0
2221 + 00000000 VPC_VARYING_INTERP[0x4].MODE: 0
2222 + 00000000 VPC_VARYING_INTERP[0x5].MODE: 0
2223 + 00000000 VPC_VARYING_INTERP[0x6].MODE: 0
2224 + 00000000 VPC_VARYING_INTERP[0x7].MODE: 0
2225 + 00000000 VPC_VARYING_PS_REPL[0].MODE: 0
2226 + 00000000 VPC_VARYING_PS_REPL[0x1].MODE: 0
2227 + 00000000 VPC_VARYING_PS_REPL[0x2].MODE: 0
2228 + 00000000 VPC_VARYING_PS_REPL[0x3].MODE: 0
2229 + 00000000 VPC_VARYING_PS_REPL[0x4].MODE: 0
2230 + 00000000 VPC_VARYING_PS_REPL[0x5].MODE: 0
2231 + 00000000 VPC_VARYING_PS_REPL[0x6].MODE: 0
2232 + 00000000 VPC_VARYING_PS_REPL[0x7].MODE: 0
2233 + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
2234 + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
2235 + ffffffff PC_RESTART_INDEX: 0xffffffff
2236 + 00000000 VFD_INDEX_OFFSET: 0
2237 + 00000000 UNKNOWN_2209: 0
2238 + 00140010 SP_SP_CTRL_REG: { 0x140010 }
2239 + 000005ff SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f }
2240 + 00201400 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE }
2241 + 08000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 8 }
2242 + 0010fc0a SP_VS_PARAM_REG: { POSREGID = r2.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 }
2243 + 00001e0e SP_VS_OUT[0].REG: { A_REGID = r3.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 }
2244 + 08080808 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 }
2245 + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 }
2246 + 10cd5000 SP_VS_OBJ_START: 0x10cd5000
2247 + 00000004 SP_VS_LENGTH_REG: 4
2248 !+ 00340802 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE }
2249 + 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 }
2250 + 7e420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
2251 !+ 108cb000 SP_FS_OBJ_START: 0x108cb000
2252 + 00000001 SP_FS_LENGTH_REG: 1
2253 + 0000fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x }
2254 !+ 0001a002 SP_FS_MRT[0].REG: { REGID = r0.z | MRTFORMAT = RB4_R8G8B8A8_UNORM }
2255 !+ 00000002 SP_FS_MRT[0x1].REG: { REGID = r0.z | MRTFORMAT = 0 }
2256 !+ 00000002 SP_FS_MRT[0x2].REG: { REGID = r0.z | MRTFORMAT = 0 }
2257 !+ 00000002 SP_FS_MRT[0x3].REG: { REGID = r0.z | MRTFORMAT = 0 }
2258 !+ 00000002 SP_FS_MRT[0x4].REG: { REGID = r0.z | MRTFORMAT = 0 }
2259 !+ 00000002 SP_FS_MRT[0x5].REG: { REGID = r0.z | MRTFORMAT = 0 }
2260 !+ 00000002 SP_FS_MRT[0x6].REG: { REGID = r0.z | MRTFORMAT = 0 }
2261 !+ 00000002 SP_FS_MRT[0x7].REG: { REGID = r0.z | MRTFORMAT = 0 }
2262 + 7e420000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
2263 + 7e420000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
2264 + 7e420000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
2265 + 28000250 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE }
2266 + fcfc0100 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x }
2267 + fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x }
2268 !+ fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
2269 + 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 }
2270 + 04000042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 }
2271 + 017e423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 }
2272 + 007e4200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
2273 + 007e4200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
2274 + 007e4200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
2275 + 00000003 HLSQ_UPDATE_CONTROL: 0x3
2276 109cf794: 0000: c0053800 00000404 00000001 00000078 00000000 10bd0960 000000f0
2277 t0 write CP_SCRATCH[0x7].REG (057f)
2278 CP_SCRATCH[0x7].REG: 0x27
2279 :0,37,115,39
2280 109cf7b0: 0000: 0000057f 00000027
2281 t0 write CP_SCRATCH[0x5].REG (057d)
2282 CP_SCRATCH[0x5].REG: 0x2b
2283 :0,43,115,39
2284 109cf7b8: 0000: 0000057d 0000002b
2285 t0 write RB_DEPTH_CONTROL (2101)
2286 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE }
2287 109cf7c0: 0000: 00002101 80000016
2288 t0 write GRAS_ALPHA_CONTROL (2073)
2289 GRAS_ALPHA_CONTROL: { 0 }
2290 109cf7c8: 0000: 00002073 00000000
2291 t0 write GRAS_SU_MODE_CONTROL (2078)
2292 GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 | RENDERING_PASS }
2293 109cf7d0: 0000: 00002078 00100012
2294 t0 write GRAS_SU_POINT_MINMAX (2070)
2295 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 }
2296 GRAS_SU_POINT_SIZE: 1.000000
2297 109cf7d8: 0000: 00012070 00100010 00000010
2298 t0 write GRAS_SU_POLY_OFFSET_SCALE (2074)
2299 GRAS_SU_POLY_OFFSET_SCALE: 0.000000
2300 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000
2301 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000
2302 109cf7e4: 0000: 00022074 00000000 00000000 00000000
2303 t0 write GRAS_CL_CLIP_CNTL (2000)
2304 GRAS_CL_CLIP_CNTL: { 0x80000 }
2305 109cf7f4: 0000: 00002000 00080000
2306 t0 write PC_PRIM_VTX_CNTL (21c4)
2307 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
2308 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
2309 109cf7fc: 0000: 000121c4 02000001 00000012
2310 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c)
2311 GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 }
2312 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
2313 109cf808: 0000: 0001209c 012b012b 00000000
2314 t0 write RB_VPORT_Z_CLAMP[0].MIN (2120)
2315 RB_VPORT_Z_CLAMP[0].MIN: 0
2316 RB_VPORT_Z_CLAMP[0].MAX: 0xffffff
2317 109cf814: 0000: 00012120 00000000 00ffffff
2318 t0 write HLSQ_UPDATE_CONTROL (23db)
2319 HLSQ_UPDATE_CONTROL: 0x3
2320 109cf820: 0000: 000023db 00000003
2321 t0 write HLSQ_CONTROL_0_REG (23c0)
2322 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE }
2323 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x }
2324 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x }
2325 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
2326 HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 }
2327 109cf828: 0000: 000423c0 28000250 fcfc0100 fff3f3f0 fcfcfcfc 00fcfcfc
2328 t0 write HLSQ_VS_CONTROL_REG (23c5)
2329 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 }
2330 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 }
2331 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
2332 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
2333 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
2334 109cf840: 0000: 000423c5 04000042 017e423e 007e4200 007e4200 007e4200
2335 t0 write SP_SP_CTRL_REG (22c0)
2336 SP_SP_CTRL_REG: { 0x140010 }
2337 109cf858: 0000: 000022c0 00140010
2338 t0 write SP_INSTR_CACHE_CTRL (22c1)
2339 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f }
2340 109cf860: 0000: 000022c1 000005ff
2341 t0 write SP_VS_LENGTH_REG (22e5)
2342 SP_VS_LENGTH_REG: 4
2343 109cf868: 0000: 000022e5 00000004
2344 t0 write SP_VS_CTRL_REG0 (22c4)
2345 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 4 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE }
2346 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 4 }
2347 SP_VS_PARAM_REG: { POSREGID = r1.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 }
2348 109cf870: 0000: 000222c4 00201000 04000042 0010fc06
2349 t0 write SP_VS_OUT[0].REG (22c7)
2350 SP_VS_OUT[0].REG: { A_REGID = r2.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 }
2351 109cf880: 0000: 000022c7 00001e0a
2352 t0 write SP_VS_VPC_DST[0].REG (22d8)
2353 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 }
2354 109cf888: 0000: 000022d8 08080808
2355 t0 write SP_VS_OBJ_OFFSET_REG (22e0)
2356 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 }
2357 SP_VS_OBJ_START: 0x10cd0000
2358 109cf890: 0000: 000122e0 00000000 10cd0000
2359 t0 write SP_FS_LENGTH_REG (22ef)
2360 SP_FS_LENGTH_REG: 1
2361 109cf89c: 0000: 000022ef 00000001
2362 t0 write SP_FS_CTRL_REG0 (22e8)
2363 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE }
2364 SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 }
2365 109cf8a4: 0000: 000122e8 00340402 8010003e
2366 t0 write SP_FS_OBJ_OFFSET_REG (22ea)
2367 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
2368 SP_FS_OBJ_START: 0x10cd2000
2369 109cf8b0: 0000: 000122ea 7e420000 10cd2000
2370 t0 write SP_HS_OBJ_OFFSET_REG (230d)
2371 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
2372 109cf8bc: 0000: 0000230d 7e420000
2373 t0 write SP_DS_OBJ_OFFSET_REG (2334)
2374 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
2375 109cf8c4: 0000: 00002334 7e420000
2376 t0 write SP_GS_OBJ_OFFSET_REG (235b)
2377 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
2378 109cf8cc: 0000: 0000235b 7e420000
2379 t0 write GRAS_CNTL (2003)
2380 GRAS_CNTL: { 0 }
2381 109cf8d4: 0000: 00002003 00000000
2382 t0 write RB_RENDER_CONTROL2 (20a3)
2383 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 }
2384 109cf8dc: 0000: 000020a3 00000000
2385 t0 write RB_FS_OUTPUT_REG (2100)
2386 RB_FS_OUTPUT_REG: { MRT = 1 }
2387 109cf8e4: 0000: 00002100 00000001
2388 t0 write SP_FS_OUTPUT_REG (22f0)
2389 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x }
2390 109cf8ec: 0000: 000022f0 0000fc01
2391 t0 write SP_FS_MRT[0].REG (22f1)
2392 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM }
2393 SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 }
2394 SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 }
2395 SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 }
2396 SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 }
2397 SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 }
2398 SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 }
2399 SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 }
2400 109cf8f4: 0000: 000722f1 0001a000 00000000 00000000 00000000 00000000 00000000 00000000
2401 *
2402 t0 write VPC_ATTR (2140)
2403 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 }
2404 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 }
2405 109cf918: 0000: 00012140 42001004 00040400
2406 t0 write VPC_VARYING_INTERP[0].MODE (2142)
2407 VPC_VARYING_INTERP[0].MODE: 0x55
2408 VPC_VARYING_INTERP[0x1].MODE: 0
2409 VPC_VARYING_INTERP[0x2].MODE: 0
2410 VPC_VARYING_INTERP[0x3].MODE: 0
2411 VPC_VARYING_INTERP[0x4].MODE: 0
2412 VPC_VARYING_INTERP[0x5].MODE: 0
2413 VPC_VARYING_INTERP[0x6].MODE: 0
2414 VPC_VARYING_INTERP[0x7].MODE: 0
2415 109cf924: 0000: 00072142 00000055 00000000 00000000 00000000 00000000 00000000 00000000
2416 *
2417 t0 write VPC_VARYING_PS_REPL[0].MODE (214a)
2418 VPC_VARYING_PS_REPL[0].MODE: 0
2419 VPC_VARYING_PS_REPL[0x1].MODE: 0
2420 VPC_VARYING_PS_REPL[0x2].MODE: 0
2421 VPC_VARYING_PS_REPL[0x3].MODE: 0
2422 VPC_VARYING_PS_REPL[0x4].MODE: 0
2423 VPC_VARYING_PS_REPL[0x5].MODE: 0
2424 VPC_VARYING_PS_REPL[0x6].MODE: 0
2425 VPC_VARYING_PS_REPL[0x7].MODE: 0
2426 109cf948: 0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000
2427 *
2428 t3 opcode: CP_LOAD_STATE4 (30) (131 dwords)
2429 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 }
2430 { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 }
2431 :2:0000:0000[40700000x_10000002x] mul.f r0.x, r0.z, c0.x
2432 :2:0001:0001[40700001x_10030002x] mul.f r0.y, r0.z, c0.w
2433 :3:0002:0002[63818000x_00001004x] mad.f32 r0.x, c1.x, r0.w, r0.x
2434 :3:0003:0003[63818001x_00011007x] mad.f32 r0.y, c1.w, r0.w, r0.y
2435 :3:0004:0004[63820000x_00001008x] mad.f32 r0.x, c2.x, r1.x, r0.x
2436 :3:0005:0005[63820001x_0001100bx] mad.f32 r0.y, c2.w, r1.x, r0.y
2437 :3:0006:0006[63828006x_0000100cx] mad.f32 r1.z, c3.x, r1.y, r0.x
2438 :2:0007:0007[40700000x_10010002x] mul.f r0.x, r0.z, c0.y
2439 :3:0008:0008[63828009x_0001100fx] mad.f32 r2.y, c3.w, r1.y, r0.y
2440 :3:0009:0009[63818000x_00001005x] mad.f32 r0.x, c1.y, r0.w, r0.x
2441 :1:0010:0010[20244001x_00000010x] mov.f32f32 r0.y, c4.x
2442 :3:0011:0011[63820000x_00001009x] mad.f32 r0.x, c2.y, r1.x, r0.x
2443 :0:0012:0012[00000000x_00000000x] nop
2444 :3:0013:0013[63828007x_0000100dx] mad.f32 r1.w, c3.y, r1.y, r0.x
2445 :2:0014:0014[40700000x_10020002x] mul.f r0.x, r0.z, c0.z
2446 :1:0015:0015[20244002x_00000015x] mov.f32f32 r0.z, c5.y
2447 :3:0016:0016[63818000x_00001006x] mad.f32 r0.x, c1.z, r0.w, r0.x
2448 :1:0017:0017[20244003x_00000016x] mov.f32f32 r0.w, c5.z
2449 :3:0018:0018[63820000x_0000100ax] mad.f32 r0.x, c2.z, r1.x, r0.x
2450 :1:0019:0019[20244004x_00000017x] mov.f32f32 r1.x, c5.w
2451 :3:0020:0020[63828008x_0000100ex] mad.f32 r2.x, c3.z, r1.y, r0.x
2452 :1:0021:0021[20244000x_00000011x] mov.f32f32 r0.x, c4.y
2453 :2:0022:0022[40100002x_00021021x] add.f r0.z, c8.y, r0.z
2454 :2:0023:0023[4050040dx_00041017x] (sat)max.f r3.y, c5.w, r1.x
2455 :2:0024:0024[40100003x_00031022x] add.f r0.w, c8.z, r0.w
2456 :2:0025:0025[40700000x_00001011x] mul.f r0.x, c4.y, r0.x
2457 :0:0026:0026[00000000x_00000000x] nop
2458 :3:0027:0027[63808000x_00001010x] mad.f32 r0.x, c4.x, r0.y, r0.x
2459 :1:0028:0028[20244001x_00000012x] mov.f32f32 r0.y, c4.z
2460 :0:0029:0029[00000200x_00000000x] (rpt2)nop
2461 :3:0030:0032[63808000x_00001012x] mad.f32 r0.x, c4.z, r0.y, r0.x
2462 :1:0031:0033[20244001x_00000014x] mov.f32f32 r0.y, c5.x
2463 :0:0032:0034[00000200x_00000000x] (rpt2)nop
2464 :2:0033:0037[40100001x_00011020x] add.f r0.y, c8.x, r0.y
2465 :0:0034:0038[00000000x_00000000x] nop
2466 :4:0035:0039[80300000x_00000000x] rsq r0.x, r0.x
2467 :2:0036:0040[40701004x_00001011x] (ss)mul.f r1.x, c4.y, r0.x
2468 :0:0037:0041[00000200x_00000000x] (rpt2)nop
2469 :2:0038:0044[40700004x_10190004x] mul.f r1.x, r1.x, c6.y
2470 :2:0039:0045[40700005x_00001010x] mul.f r1.y, c4.x, r0.x
2471 :0:0040:0046[00000200x_00000000x] (rpt2)nop
2472 :3:0041:0049[63828004x_00041018x] mad.f32 r1.x, c6.x, r1.y, r1.x
2473 :2:0042:0050[40700000x_00001012x] mul.f r0.x, c4.z, r0.x
2474 :0:0043:0051[00000200x_00000000x] (rpt2)nop
2475 :3:0044:0054[63800000x_0004101ax] mad.f32 r0.x, c6.z, r0.x, r1.x
2476 :0:0045:0055[00000200x_00000000x] (rpt2)nop
2477 :2:0046:0058[40b00004x_00001034x] cmps.f.lt r1.x, c13.x, r0.x
2478 :2:0047:0059[40500000x_00001034x] max.f r0.x, c13.x, r0.x
2479 :0:0048:0060[00000100x_00000000x] (rpt1)nop
2480 :1:0049:0062[200c4004x_00000004x] cov.u32f32 r1.x, r1.x
2481 :3:0050:0063[63800001x_00011024x] mad.f32 r0.y, c9.x, r0.x, r0.y
2482 :3:0051:0064[63800002x_00021025x] mad.f32 r0.z, c9.y, r0.x, r0.z
2483 :3:0052:0065[63800000x_00031026x] mad.f32 r0.x, c9.z, r0.x, r0.w
2484 :3:0053:0066[6382040ax_00011028x] (sat)mad.f32 r2.z, c10.x, r1.x, r0.y
2485 :3:0054:0067[6382040bx_00021029x] (sat)mad.f32 r2.w, c10.y, r1.x, r0.z
2486 :3:0055:0068[6382040cx_0000102ax] (sat)mad.f32 r3.x, c10.z, r1.x, r0.x
2487 :0:0056:0069[03000000x_00000000x] end
2488 :0:0057:0070[00000000x_00000000x] nop
2489 :0:0058:0071[00000000x_00000000x] nop
2490 :0:0059:0072[00000000x_00000000x] nop
2491 :0:0060:0073[00000000x_00000000x] nop
2492 Register Stats:
2493 - used (half): (cnt=0, max=0)
2494 - used (full): 0-13 (cnt=14, max=13)
2495 - input (half): (cnt=0, max=0)
2496 - input (full): 2-5 (cnt=4, max=5)
2497 - max const: 52
2498
2499 - output (half): (cnt=0, max=0) (estimated)
2500 - output (full): 6-13 (cnt=8, max=13) (estimated)
2501 - shaderdb: 74 instructions, 38 nops, 36 non-nops, (61 instlen), 0 half, 4 full
2502 - shaderdb: 1 (ss), 0 (sy)
2503 109cf96c: 0000: c0813000 01200000 00000000 10000002 40700000 10030002 40700001 00001004
2504 109cf98c: 0020: 63818000 00011007 63818001 00001008 63820000 0001100b 63820001 0000100c
2505 109cf9ac: 0040: 63828006 10010002 40700000 0001100f 63828009 00001005 63818000 00000010
2506 109cf9cc: 0060: 20244001 00001009 63820000 00000000 00000000 0000100d 63828007 10020002
2507 109cf9ec: 0080: 40700000 00000015 20244002 00001006 63818000 00000016 20244003 0000100a
2508 109cfa0c: 00a0: 63820000 00000017 20244004 0000100e 63828008 00000011 20244000 00021021
2509 109cfa2c: 00c0: 40100002 00041017 4050040d 00031022 40100003 00001011 40700000 00000000
2510 109cfa4c: 00e0: 00000000 00001010 63808000 00000012 20244001 00000000 00000200 00001012
2511 109cfa6c: 0100: 63808000 00000014 20244001 00000000 00000200 00011020 40100001 00000000
2512 109cfa8c: 0120: 00000000 00000000 80300000 00001011 40701004 00000000 00000200 10190004
2513 109cfaac: 0140: 40700004 00001010 40700005 00000000 00000200 00041018 63828004 00001012
2514 109cfacc: 0160: 40700000 00000000 00000200 0004101a 63800000 00000000 00000200 00001034
2515 109cfaec: 0180: 40b00004 00001034 40500000 00000000 00000100 00000004 200c4004 00011024
2516 109cfb0c: 01a0: 63800001 00021025 63800002 00031026 63800000 00011028 6382040a 00021029
2517 109cfb2c: 01c0: 6382040b 0000102a 6382040c 00000000 03000000 00000000 00000000 00000000
2518 *
2519 t3 opcode: CP_LOAD_STATE4 (30) (35 dwords)
2520 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 }
2521 { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 }
2522 :0:0000:0000[00000000x_00000000x] nop
2523 :6:0001:0001[c7c60000x_01c00000x] ldlv.u32 r0.x, l[0], 1
2524 :6:0002:0002[c7c60001x_01c00002x] ldlv.u32 r0.y, l[1], 1
2525 :6:0003:0003[c7c60002x_01c00004x] ldlv.u32 r0.z, l[2], 1
2526 :6:0004:0004[c7c60003x_01c00006x] ldlv.u32 r0.w, l[3], 1
2527 :2:0005:0005[473090fcx_00002000x] (ss)bary.f (ei)r63.x, 0, r0.x
2528 :0:0006:0006[03000000x_00000000x] end
2529 :0:0007:0007[00000000x_00000000x] nop
2530 :0:0008:0008[00000000x_00000000x] nop
2531 :0:0009:0009[00000000x_00000000x] nop
2532 :0:0010:0010[00000000x_00000000x] nop
2533 Register Stats:
2534 - used (half): (cnt=0, max=0)
2535 - used (full): 0-3 (cnt=4, max=3)
2536 - input (half): (cnt=0, max=0)
2537 - input (full): 0-3 (cnt=4, max=3)
2538 - max const: 0
2539
2540 - output (half): (cnt=0, max=0) (estimated)
2541 - output (full): (cnt=0, max=0) (estimated)
2542 - shaderdb: 11 instructions, 5 nops, 6 non-nops, (11 instlen), 0 half, 1 full
2543 - shaderdb: 1 (ss), 0 (sy)
2544 109cfb78: 0000: c0213000 00700000 00000000 00000000 00000000 01c00000 c7c60000 01c00002
2545 109cfb98: 0020: c7c60001 01c00004 c7c60002 01c00006 c7c60003 00002000 473090fc 00000000
2546 109cfbb8: 0040: 03000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
2547 *
2548 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
2549 109cfc04: 0000: c0002600 00000000
2550 t3 opcode: CP_LOAD_STATE4 (30) (51 dwords)
2551 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 }
2552 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 }
2553 109cfc18: 4.276816 0.109522 0.611668 0.517565 0.677381 4.774377 -0.312365 -0.264309
2554 109cfc38: 2.500000 -1.480991 -0.961761 -0.813798 13.423393 -6.746271 38.893391 42.140564
2555 109cfc58: 0.000000 0.000000 1.000000 1.000000 0.000000 0.160000 0.040000 1.000000
2556 109cfc78: -0.064448 0.660942 0.747665 0.000000 1.000000 0.000000 0.000000 0.000000
2557 109cfc98: 0.000000 0.000000 0.000000 1.000000 0.000000 0.800000 0.200000 1.000000
2558 109cfcb8: 0.000000 0.000000 0.000000 1.000000 0.000000 0.000000 0.000000 1.000000
2559 109cfc18: 0000: 4088dbad 3de04cdc 3f1c964b 3f047f2c 3f2d68da 4098c7b2 be9fee59 be875387
2560 109cfc38: 0020: 40200000 bfbd9119 bf7635f5 bf50550b 4156c638 c0d7e173 421b92d5 42288ff0
2561 109cfc58: 0040: 00000000 00000000 3f800000 3f800000 00000000 3e23d70b 3d23d70b 3f800000
2562 109cfc78: 0060: bd83fd0e 3f293379 3f3f66f5 00000000 3f800000 00000000 00000000 00000000
2563 109cfc98: 0080: 00000000 00000000 00000000 3f800000 00000000 3f4ccccd 3e4ccccd 3f800000
2564 109cfcb8: 00a0: 00000000 00000000 00000000 3f800000 00000000 00000000 00000000 3f800000
2565 109cfc0c: 0000: c0313000 03200000 00000001 4088dbad 3de04cdc 3f1c964b 3f047f2c 3f2d68da
2566 109cfc2c: 0020: 4098c7b2 be9fee59 be875387 40200000 bfbd9119 bf7635f5 bf50550b 4156c638
2567 109cfc4c: 0040: c0d7e173 421b92d5 42288ff0 00000000 00000000 3f800000 3f800000 00000000
2568 109cfc6c: 0060: 3e23d70b 3d23d70b 3f800000 bd83fd0e 3f293379 3f3f66f5 00000000 3f800000
2569 109cfc8c: 0080: 00000000 00000000 00000000 00000000 00000000 00000000 3f800000 00000000
2570 109cfcac: 00a0: 3f4ccccd 3e4ccccd 3f800000 00000000 00000000 00000000 3f800000 00000000
2571 109cfccc: 00c0: 00000000 00000000 3f800000
2572 t3 opcode: CP_LOAD_STATE4 (30) (7 dwords)
2573 { DST_OFF = 13 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 }
2574 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 }
2575 109cfce4: 0.000000 -28026765312.000000 -28026765312.000000 -28026765312.000000
2576 109cfce4: 0000: 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0
2577 109cfcd8: 0000: c0053000 0060000d 00000001 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0
2578 t0 write VFD_FETCH[0].INSTR_0 (220a)
2579 VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 12 }
2580 VFD_FETCH[0].INSTR_1: 0x107cb000
2581 VFD_FETCH[0].INSTR_2: { SIZE = 0x100000 }
2582 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 }
2583 109cfcf4: 0000: 0003220a 0000060b 107cb000 00100000 00000001
2584 t0 write VFD_DECODE[0].INSTR (228a)
2585 VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID }
2586 109cfd08: 0000: 0000228a 2c0020df
2587 t0 write VFD_CONTROL_0 (2200)
2588 VFD_CONTROL_0: { TOTALATTRTOVS = 4 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 | 0xa0000 }
2589 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x }
2590 VFD_CONTROL_2: 0
2591 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x }
2592 VFD_CONTROL_4: 0
2593 109cfd10: 0000: 00042200 041a0004 fcfc0081 00000000 0000fc00 00000000
2594 t0 write UCHE_INVALIDATE0 (0e8a)
2595 UCHE_INVALIDATE0: 0
2596 UCHE_INVALIDATE1: 0x12
2597 109cfd28: 0000: 00010e8a 00000000 00000012
2598 t0 write VFD_INDEX_OFFSET (2208)
2599 VFD_INDEX_OFFSET: 0
2600 UNKNOWN_2209: 0
2601 109cfd34: 0000: 00012208 00000000 00000000
2602 t0 write PC_RESTART_INDEX (21c6)
2603 PC_RESTART_INDEX: 0xffffffff
2604 109cfd40: 0000: 000021c6 ffffffff
2605 t0 write CP_SCRATCH[0x7].REG (057f)
2606 CP_SCRATCH[0x7].REG: 0x2c
2607 :0,43,115,44
2608 109cfd48: 0000: 0000057f 0000002c
2609 t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
2610 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS }
2611 { NUM_INSTANCES = 1 }
2612 { NUM_INDICES = 120 }
2613 { FIRST_INDX = 0 }
2614 { INDX_BASE = 0x10bd0a50 }
2615 { INDX_SIZE = 240 }
2616 draw[7] register values
2617 !+ 0000002b CP_SCRATCH[0x5].REG: 0x2b
2618 :0,43,115,44
2619 !+ 0000002c CP_SCRATCH[0x7].REG: 0x2c
2620 :0,43,115,44
2621 + 00000000 UCHE_INVALIDATE0: 0
2622 + 00000012 UCHE_INVALIDATE1: 0x12
2623 + 00080000 GRAS_CL_CLIP_CNTL: { 0x80000 }
2624 !+ 00000000 GRAS_CNTL: { 0 }
2625 + 00100010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 }
2626 + 00000010 GRAS_SU_POINT_SIZE: 1.000000
2627 + 00000000 GRAS_ALPHA_CONTROL: { 0 }
2628 + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000
2629 + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000
2630 + 00000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000
2631 + 00100012 GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 | RENDERING_PASS }
2632 + 012b012b GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 }
2633 + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
2634 !+ 00000000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 }
2635 + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 }
2636 + 80000016 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE }
2637 + 00000000 RB_VPORT_Z_CLAMP[0].MIN: 0
2638 + 00ffffff RB_VPORT_Z_CLAMP[0].MAX: 0xffffff
2639 + 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 }
2640 + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 }
2641 !+ 00000055 VPC_VARYING_INTERP[0].MODE: 0x55
2642 + 00000000 VPC_VARYING_INTERP[0x1].MODE: 0
2643 + 00000000 VPC_VARYING_INTERP[0x2].MODE: 0
2644 + 00000000 VPC_VARYING_INTERP[0x3].MODE: 0
2645 + 00000000 VPC_VARYING_INTERP[0x4].MODE: 0
2646 + 00000000 VPC_VARYING_INTERP[0x5].MODE: 0
2647 + 00000000 VPC_VARYING_INTERP[0x6].MODE: 0
2648 + 00000000 VPC_VARYING_INTERP[0x7].MODE: 0
2649 + 00000000 VPC_VARYING_PS_REPL[0].MODE: 0
2650 + 00000000 VPC_VARYING_PS_REPL[0x1].MODE: 0
2651 + 00000000 VPC_VARYING_PS_REPL[0x2].MODE: 0
2652 + 00000000 VPC_VARYING_PS_REPL[0x3].MODE: 0
2653 + 00000000 VPC_VARYING_PS_REPL[0x4].MODE: 0
2654 + 00000000 VPC_VARYING_PS_REPL[0x5].MODE: 0
2655 + 00000000 VPC_VARYING_PS_REPL[0x6].MODE: 0
2656 + 00000000 VPC_VARYING_PS_REPL[0x7].MODE: 0
2657 + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
2658 + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
2659 + ffffffff PC_RESTART_INDEX: 0xffffffff
2660 !+ 041a0004 VFD_CONTROL_0: { TOTALATTRTOVS = 4 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 | 0xa0000 }
2661 + fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x }
2662 + 00000000 VFD_CONTROL_2: 0
2663 + 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x }
2664 + 00000000 VFD_CONTROL_4: 0
2665 + 00000000 VFD_INDEX_OFFSET: 0
2666 + 00000000 UNKNOWN_2209: 0
2667 !+ 0000060b VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 12 }
2668 + 107cb000 VFD_FETCH[0].INSTR_1: 0x107cb000
2669 + 00100000 VFD_FETCH[0].INSTR_2: { SIZE = 0x100000 }
2670 + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 }
2671 !+ 2c0020df VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID }
2672 + 00140010 SP_SP_CTRL_REG: { 0x140010 }
2673 + 000005ff SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f }
2674 !+ 00201000 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 4 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE }
2675 !+ 04000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 4 }
2676 !+ 0010fc06 SP_VS_PARAM_REG: { POSREGID = r1.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 }
2677 !+ 00001e0a SP_VS_OUT[0].REG: { A_REGID = r2.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 }
2678 + 08080808 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 }
2679 + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 }
2680 !+ 10cd0000 SP_VS_OBJ_START: 0x10cd0000
2681 + 00000004 SP_VS_LENGTH_REG: 4
2682 !+ 00340402 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE }
2683 + 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 }
2684 + 7e420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
2685 !+ 10cd2000 SP_FS_OBJ_START: 0x10cd2000
2686 + 00000001 SP_FS_LENGTH_REG: 1
2687 + 0000fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x }
2688 !+ 0001a000 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM }
2689 !+ 00000000 SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 }
2690 !+ 00000000 SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 }
2691 !+ 00000000 SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 }
2692 !+ 00000000 SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 }
2693 !+ 00000000 SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 }
2694 !+ 00000000 SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 }
2695 !+ 00000000 SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 }
2696 + 7e420000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
2697 + 7e420000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
2698 + 7e420000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
2699 + 28000250 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE }
2700 + fcfc0100 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x }
2701 + fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x }
2702 !+ fcfcfcfc HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
2703 + 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 }
2704 + 04000042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 }
2705 + 017e423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 }
2706 + 007e4200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
2707 + 007e4200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
2708 + 007e4200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
2709 + 00000003 HLSQ_UPDATE_CONTROL: 0x3
2710 109cfd50: 0000: c0053800 00000404 00000001 00000078 00000000 10bd0a50 000000f0
2711 t0 write CP_SCRATCH[0x7].REG (057f)
2712 CP_SCRATCH[0x7].REG: 0x2d
2713 :0,43,115,45
2714 109cfd6c: 0000: 0000057f 0000002d
2715 t0 write CP_SCRATCH[0x5].REG (057d)
2716 CP_SCRATCH[0x5].REG: 0x31
2717 :0,49,115,45
2718 109cfd74: 0000: 0000057d 00000031
2719 t0 write PC_PRIM_VTX_CNTL (21c4)
2720 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
2721 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
2722 109cfd7c: 0000: 000121c4 02000001 00000012
2723 t0 write VFD_INDEX_OFFSET (2208)
2724 VFD_INDEX_OFFSET: 0
2725 UNKNOWN_2209: 0
2726 109cfd88: 0000: 00012208 00000000 00000000
2727 t0 write PC_RESTART_INDEX (21c6)
2728 PC_RESTART_INDEX: 0xffffffff
2729 109cfd94: 0000: 000021c6 ffffffff
2730 t0 write CP_SCRATCH[0x7].REG (057f)
2731 CP_SCRATCH[0x7].REG: 0x32
2732 :0,49,115,50
2733 109cfd9c: 0000: 0000057f 00000032
2734 t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
2735 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS }
2736 { NUM_INSTANCES = 1 }
2737 { NUM_INDICES = 60 }
2738 { FIRST_INDX = 0 }
2739 { INDX_BASE = 0x10bd0b40 }
2740 { INDX_SIZE = 120 }
2741 draw[8] register values
2742 !+ 00000031 CP_SCRATCH[0x5].REG: 0x31
2743 :0,49,115,50
2744 !+ 00000032 CP_SCRATCH[0x7].REG: 0x32
2745 :0,49,115,50
2746 + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
2747 + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
2748 + ffffffff PC_RESTART_INDEX: 0xffffffff
2749 + 00000000 VFD_INDEX_OFFSET: 0
2750 + 00000000 UNKNOWN_2209: 0
2751 109cfda4: 0000: c0053800 00000404 00000001 0000003c 00000000 10bd0b40 00000078
2752 t0 write CP_SCRATCH[0x7].REG (057f)
2753 CP_SCRATCH[0x7].REG: 0x33
2754 :0,49,115,51
2755 109cfdc0: 0000: 0000057f 00000033
2756 t0 write CP_SCRATCH[0x5].REG (057d)
2757 CP_SCRATCH[0x5].REG: 0x37
2758 :0,55,115,51
2759 109cfdc8: 0000: 0000057d 00000037
2760 t0 write PC_PRIM_VTX_CNTL (21c4)
2761 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
2762 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
2763 109cfdd0: 0000: 000121c4 02000001 00000012
2764 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
2765 109cfddc: 0000: c0002600 00000000
2766 t3 opcode: CP_LOAD_STATE4 (30) (51 dwords)
2767 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 }
2768 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 }
2769 109cfdf0: 4.276816 0.109522 0.611668 0.517565 0.677381 4.774377 -0.312365 -0.264309
2770 109cfe10: 2.500000 -1.480991 -0.961761 -0.813798 13.423393 -6.746271 38.893391 42.140564
2771 109cfe30: 0.000000 0.000000 -1.000000 1.000000 0.000000 0.160000 0.040000 1.000000
2772 109cfe50: -0.064448 0.660942 0.747665 0.000000 1.000000 0.000000 0.000000 0.000000
2773 109cfe70: 0.000000 0.000000 0.000000 1.000000 0.000000 0.800000 0.200000 1.000000
2774 109cfe90: 0.000000 0.000000 0.000000 1.000000 0.000000 0.000000 0.000000 1.000000
2775 109cfdf0: 0000: 4088dbad 3de04cdc 3f1c964b 3f047f2c 3f2d68da 4098c7b2 be9fee59 be875387
2776 109cfe10: 0020: 40200000 bfbd9119 bf7635f5 bf50550b 4156c638 c0d7e173 421b92d5 42288ff0
2777 109cfe30: 0040: 00000000 00000000 bf800000 3f800000 00000000 3e23d70b 3d23d70b 3f800000
2778 109cfe50: 0060: bd83fd0e 3f293379 3f3f66f5 00000000 3f800000 00000000 00000000 00000000
2779 109cfe70: 0080: 00000000 00000000 00000000 3f800000 00000000 3f4ccccd 3e4ccccd 3f800000
2780 109cfe90: 00a0: 00000000 00000000 00000000 3f800000 00000000 00000000 00000000 3f800000
2781 109cfde4: 0000: c0313000 03200000 00000001 4088dbad 3de04cdc 3f1c964b 3f047f2c 3f2d68da
2782 109cfe04: 0020: 4098c7b2 be9fee59 be875387 40200000 bfbd9119 bf7635f5 bf50550b 4156c638
2783 109cfe24: 0040: c0d7e173 421b92d5 42288ff0 00000000 00000000 bf800000 3f800000 00000000
2784 109cfe44: 0060: 3e23d70b 3d23d70b 3f800000 bd83fd0e 3f293379 3f3f66f5 00000000 3f800000
2785 109cfe64: 0080: 00000000 00000000 00000000 00000000 00000000 00000000 3f800000 00000000
2786 109cfe84: 00a0: 3f4ccccd 3e4ccccd 3f800000 00000000 00000000 00000000 3f800000 00000000
2787 109cfea4: 00c0: 00000000 00000000 3f800000
2788 t0 write VFD_INDEX_OFFSET (2208)
2789 VFD_INDEX_OFFSET: 0
2790 UNKNOWN_2209: 0
2791 109cfeb0: 0000: 00012208 00000000 00000000
2792 t0 write PC_RESTART_INDEX (21c6)
2793 PC_RESTART_INDEX: 0xffffffff
2794 109cfebc: 0000: 000021c6 ffffffff
2795 t0 write CP_SCRATCH[0x7].REG (057f)
2796 CP_SCRATCH[0x7].REG: 0x38
2797 :0,55,115,56
2798 109cfec4: 0000: 0000057f 00000038
2799 t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
2800 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS }
2801 { NUM_INSTANCES = 1 }
2802 { NUM_INDICES = 120 }
2803 { FIRST_INDX = 0 }
2804 { INDX_BASE = 0x10bd0bb8 }
2805 { INDX_SIZE = 240 }
2806 draw[9] register values
2807 !+ 00000037 CP_SCRATCH[0x5].REG: 0x37
2808 :0,55,115,56
2809 !+ 00000038 CP_SCRATCH[0x7].REG: 0x38
2810 :0,55,115,56
2811 + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
2812 + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
2813 + ffffffff PC_RESTART_INDEX: 0xffffffff
2814 + 00000000 VFD_INDEX_OFFSET: 0
2815 + 00000000 UNKNOWN_2209: 0
2816 109cfecc: 0000: c0053800 00000404 00000001 00000078 00000000 10bd0bb8 000000f0
2817 t0 write CP_SCRATCH[0x7].REG (057f)
2818 CP_SCRATCH[0x7].REG: 0x39
2819 :0,55,115,57
2820 109cfee8: 0000: 0000057f 00000039
2821 t0 write CP_SCRATCH[0x5].REG (057d)
2822 CP_SCRATCH[0x5].REG: 0x3d
2823 :0,61,115,57
2824 109cfef0: 0000: 0000057d 0000003d
2825 t0 write PC_PRIM_VTX_CNTL (21c4)
2826 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
2827 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
2828 109cfef8: 0000: 000121c4 02000001 00000012
2829 t0 write VFD_INDEX_OFFSET (2208)
2830 VFD_INDEX_OFFSET: 0
2831 UNKNOWN_2209: 0
2832 109cff04: 0000: 00012208 00000000 00000000
2833 t0 write PC_RESTART_INDEX (21c6)
2834 PC_RESTART_INDEX: 0xffffffff
2835 109cff10: 0000: 000021c6 ffffffff
2836 t0 write CP_SCRATCH[0x7].REG (057f)
2837 CP_SCRATCH[0x7].REG: 0x3e
2838 :0,61,115,62
2839 109cff18: 0000: 0000057f 0000003e
2840 t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
2841 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS }
2842 { NUM_INSTANCES = 1 }
2843 { NUM_INDICES = 60 }
2844 { FIRST_INDX = 0 }
2845 { INDX_BASE = 0x10bd0ca8 }
2846 { INDX_SIZE = 120 }
2847 draw[10] register values
2848 !+ 0000003d CP_SCRATCH[0x5].REG: 0x3d
2849 :0,61,115,62
2850 !+ 0000003e CP_SCRATCH[0x7].REG: 0x3e
2851 :0,61,115,62
2852 + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
2853 + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
2854 + ffffffff PC_RESTART_INDEX: 0xffffffff
2855 + 00000000 VFD_INDEX_OFFSET: 0
2856 + 00000000 UNKNOWN_2209: 0
2857 109cff20: 0000: c0053800 00000404 00000001 0000003c 00000000 10bd0ca8 00000078
2858 t0 write CP_SCRATCH[0x7].REG (057f)
2859 CP_SCRATCH[0x7].REG: 0x3f
2860 :0,61,115,63
2861 109cff3c: 0000: 0000057f 0000003f
2862 t0 write CP_SCRATCH[0x5].REG (057d)
2863 CP_SCRATCH[0x5].REG: 0x43
2864 :0,67,115,63
2865 109cff44: 0000: 0000057d 00000043
2866 t0 write RB_DEPTH_CONTROL (2101)
2867 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE }
2868 109cff4c: 0000: 00002101 80000016
2869 t0 write GRAS_ALPHA_CONTROL (2073)
2870 GRAS_ALPHA_CONTROL: { 0 }
2871 109cff54: 0000: 00002073 00000000
2872 t0 write PC_PRIM_VTX_CNTL (21c4)
2873 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
2874 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
2875 109cff5c: 0000: 000121c4 02000001 00000012
2876 t0 write HLSQ_UPDATE_CONTROL (23db)
2877 HLSQ_UPDATE_CONTROL: 0x3
2878 109cff68: 0000: 000023db 00000003
2879 t0 write HLSQ_CONTROL_0_REG (23c0)
2880 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE }
2881 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x }
2882 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x }
2883 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
2884 HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 }
2885 109cff70: 0000: 000423c0 28000250 fcfc0100 fff3f3f0 fcfcfcfc 00fcfcfc
2886 t0 write HLSQ_VS_CONTROL_REG (23c5)
2887 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 }
2888 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 }
2889 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
2890 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
2891 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
2892 109cff88: 0000: 000423c5 04000042 017e423e 007e4200 007e4200 007e4200
2893 t0 write SP_SP_CTRL_REG (22c0)
2894 SP_SP_CTRL_REG: { 0x140010 }
2895 109cffa0: 0000: 000022c0 00140010
2896 t0 write SP_INSTR_CACHE_CTRL (22c1)
2897 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f }
2898 109cffa8: 0000: 000022c1 000005ff
2899 t0 write SP_VS_LENGTH_REG (22e5)
2900 SP_VS_LENGTH_REG: 4
2901 109cffb0: 0000: 000022e5 00000004
2902 t0 write SP_VS_CTRL_REG0 (22c4)
2903 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE }
2904 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 8 }
2905 SP_VS_PARAM_REG: { POSREGID = r2.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 }
2906 109cffb8: 0000: 000222c4 00201400 08000042 0010fc0a
2907 t0 write SP_VS_OUT[0].REG (22c7)
2908 SP_VS_OUT[0].REG: { A_REGID = r3.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 }
2909 109cffc8: 0000: 000022c7 00001e0e
2910 t0 write SP_VS_VPC_DST[0].REG (22d8)
2911 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 }
2912 109cffd0: 0000: 000022d8 08080808
2913 t0 write SP_VS_OBJ_OFFSET_REG (22e0)
2914 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 }
2915 SP_VS_OBJ_START: 0x10cd5000
2916 109cffd8: 0000: 000122e0 00000000 10cd5000
2917 t0 write SP_FS_LENGTH_REG (22ef)
2918 SP_FS_LENGTH_REG: 1
2919 109cffe4: 0000: 000022ef 00000001
2920 t0 write SP_FS_CTRL_REG0 (22e8)
2921 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE }
2922 SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 }
2923 109cffec: 0000: 000122e8 00340402 8010003e
2924 t0 write SP_FS_OBJ_OFFSET_REG (22ea)
2925 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
2926 SP_FS_OBJ_START: 0x10cd2000
2927 109cfff8: 0000: 000122ea 7e420000 10cd2000
2928 t0 write SP_HS_OBJ_OFFSET_REG (230d)
2929 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
2930 109d0004: 0000: 0000230d 7e420000
2931 t0 write SP_DS_OBJ_OFFSET_REG (2334)
2932 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
2933 109d000c: 0000: 00002334 7e420000
2934 t0 write SP_GS_OBJ_OFFSET_REG (235b)
2935 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
2936 109d0014: 0000: 0000235b 7e420000
2937 t0 write GRAS_CNTL (2003)
2938 GRAS_CNTL: { 0 }
2939 109d001c: 0000: 00002003 00000000
2940 t0 write RB_RENDER_CONTROL2 (20a3)
2941 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 }
2942 109d0024: 0000: 000020a3 00000000
2943 t0 write RB_FS_OUTPUT_REG (2100)
2944 RB_FS_OUTPUT_REG: { MRT = 1 }
2945 109d002c: 0000: 00002100 00000001
2946 t0 write SP_FS_OUTPUT_REG (22f0)
2947 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x }
2948 109d0034: 0000: 000022f0 0000fc01
2949 t0 write SP_FS_MRT[0].REG (22f1)
2950 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM }
2951 SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 }
2952 SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 }
2953 SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 }
2954 SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 }
2955 SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 }
2956 SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 }
2957 SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 }
2958 109d003c: 0000: 000722f1 0001a000 00000000 00000000 00000000 00000000 00000000 00000000
2959 *
2960 t0 write VPC_ATTR (2140)
2961 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 }
2962 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 }
2963 109d0060: 0000: 00012140 42001004 00040400
2964 t0 write VPC_VARYING_INTERP[0].MODE (2142)
2965 VPC_VARYING_INTERP[0].MODE: 0x55
2966 VPC_VARYING_INTERP[0x1].MODE: 0
2967 VPC_VARYING_INTERP[0x2].MODE: 0
2968 VPC_VARYING_INTERP[0x3].MODE: 0
2969 VPC_VARYING_INTERP[0x4].MODE: 0
2970 VPC_VARYING_INTERP[0x5].MODE: 0
2971 VPC_VARYING_INTERP[0x6].MODE: 0
2972 VPC_VARYING_INTERP[0x7].MODE: 0
2973 109d006c: 0000: 00072142 00000055 00000000 00000000 00000000 00000000 00000000 00000000
2974 *
2975 t0 write VPC_VARYING_PS_REPL[0].MODE (214a)
2976 VPC_VARYING_PS_REPL[0].MODE: 0
2977 VPC_VARYING_PS_REPL[0x1].MODE: 0
2978 VPC_VARYING_PS_REPL[0x2].MODE: 0
2979 VPC_VARYING_PS_REPL[0x3].MODE: 0
2980 VPC_VARYING_PS_REPL[0x4].MODE: 0
2981 VPC_VARYING_PS_REPL[0x5].MODE: 0
2982 VPC_VARYING_PS_REPL[0x6].MODE: 0
2983 VPC_VARYING_PS_REPL[0x7].MODE: 0
2984 109d0090: 0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000
2985 *
2986 t3 opcode: CP_LOAD_STATE4 (30) (131 dwords)
2987 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 }
2988 { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 }
2989 :2:0000:0000[40700000x_10000002x] mul.f r0.x, r0.z, c0.x
2990 :2:0001:0001[40700001x_10030002x] mul.f r0.y, r0.z, c0.w
2991 :3:0002:0002[63818000x_00001004x] mad.f32 r0.x, c1.x, r0.w, r0.x
2992 :3:0003:0003[63818001x_00011007x] mad.f32 r0.y, c1.w, r0.w, r0.y
2993 :3:0004:0004[63820000x_00001008x] mad.f32 r0.x, c2.x, r1.x, r0.x
2994 :3:0005:0005[63820001x_0001100bx] mad.f32 r0.y, c2.w, r1.x, r0.y
2995 :3:0006:0006[6382800ax_0000100cx] mad.f32 r2.z, c3.x, r1.y, r0.x
2996 :2:0007:0007[40700000x_10010002x] mul.f r0.x, r0.z, c0.y
2997 :3:0008:0008[6382800dx_0001100fx] mad.f32 r3.y, c3.w, r1.y, r0.y
2998 :3:0009:0009[63818000x_00001005x] mad.f32 r0.x, c1.y, r0.w, r0.x
2999 :1:0010:0010[20244001x_00000010x] mov.f32f32 r0.y, c4.x
3000 :3:0011:0011[63820000x_00001009x] mad.f32 r0.x, c2.y, r1.x, r0.x
3001 :0:0012:0012[00000000x_00000000x] nop
3002 :3:0013:0013[6382800bx_0000100dx] mad.f32 r2.w, c3.y, r1.y, r0.x
3003 :2:0014:0014[40700000x_10020002x] mul.f r0.x, r0.z, c0.z
3004 :2:0015:0015[40100001x_0001101cx] add.f r0.y, c7.x, r0.y
3005 :3:0016:0016[63818000x_00001006x] mad.f32 r0.x, c1.z, r0.w, r0.x
3006 :1:0017:0017[20244002x_00000011x] mov.f32f32 r0.z, c4.y
3007 :3:0018:0018[63820000x_0000100ax] mad.f32 r0.x, c2.z, r1.x, r0.x
3008 :1:0019:0019[20244004x_00000013x] mov.f32f32 r1.x, c4.w
3009 :3:0020:0020[6382800cx_0000100ex] mad.f32 r3.x, c3.z, r1.y, r0.x
3010 :2:0021:0021[40700000x_00070007x] mul.f r0.x, r1.w, r1.w
3011 :2:0022:0022[40100002x_0002101dx] add.f r0.z, c7.y, r0.z
3012 :3:0023:0023[63830000x_00000006x] mad.f32 r0.x, r1.z, r1.z, r0.x
3013 :2:0024:0024[40500411x_00041013x] (sat)max.f r4.y, c4.w, r1.x
3014 :3:0025:0025[63840000x_00000008x] mad.f32 r0.x, r2.x, r2.x, r0.x
3015 :1:0026:0026[20244003x_00000012x] mov.f32f32 r0.w, c4.z
3016 :0:0027:0027[00000200x_00000000x] (rpt2)nop
3017 :2:0028:0030[40100003x_0003101ex] add.f r0.w, c7.z, r0.w
3018 :0:0029:0031[00000000x_00000000x] nop
3019 :4:0030:0032[80300000x_00000000x] rsq r0.x, r0.x
3020 :2:0031:0033[40701004x_00000007x] (ss)mul.f r1.x, r1.w, r0.x
3021 :0:0032:0034[00000200x_00000000x] (rpt2)nop
3022 :2:0033:0037[40700004x_10150004x] mul.f r1.x, r1.x, c5.y
3023 :2:0034:0038[40700005x_00000006x] mul.f r1.y, r1.z, r0.x
3024 :0:0035:0039[00000200x_00000000x] (rpt2)nop
3025 :3:0036:0042[63828004x_00041014x] mad.f32 r1.x, c5.x, r1.y, r1.x
3026 :2:0037:0043[40700000x_00000008x] mul.f r0.x, r2.x, r0.x
3027 :0:0038:0044[00000200x_00000000x] (rpt2)nop
3028 :3:0039:0047[63800000x_00041016x] mad.f32 r0.x, c5.z, r0.x, r1.x
3029 :0:0040:0048[00000200x_00000000x] (rpt2)nop
3030 :2:0041:0051[40b00004x_00001034x] cmps.f.lt r1.x, c13.x, r0.x
3031 :2:0042:0052[40500000x_00001034x] max.f r0.x, c13.x, r0.x
3032 :0:0043:0053[00000100x_00000000x] (rpt1)nop
3033 :1:0044:0055[200c4004x_00000004x] cov.u32f32 r1.x, r1.x
3034 :3:0045:0056[63800001x_00011020x] mad.f32 r0.y, c8.x, r0.x, r0.y
3035 :3:0046:0057[63800002x_00021021x] mad.f32 r0.z, c8.y, r0.x, r0.z
3036 :3:0047:0058[63800000x_00031022x] mad.f32 r0.x, c8.z, r0.x, r0.w
3037 :3:0048:0059[6382040ex_00011024x] (sat)mad.f32 r3.z, c9.x, r1.x, r0.y
3038 :3:0049:0060[6382040fx_00021025x] (sat)mad.f32 r3.w, c9.y, r1.x, r0.z
3039 :3:0050:0061[63820410x_00001026x] (sat)mad.f32 r4.x, c9.z, r1.x, r0.x
3040 :0:0051:0062[03000000x_00000000x] end
3041 :0:0052:0063[00000000x_00000000x] nop
3042 :0:0053:0064[00000000x_00000000x] nop
3043 :0:0054:0065[00000000x_00000000x] nop
3044 :0:0055:0066[00000000x_00000000x] nop
3045 Register Stats:
3046 - used (half): (cnt=0, max=0)
3047 - used (full): 0-8 10-17 (cnt=17, max=17)
3048 - input (half): (cnt=0, max=0)
3049 - input (full): 2-8 (cnt=7, max=8)
3050 - max const: 52
3051
3052 - output (half): (cnt=0, max=0) (estimated)
3053 - output (full): 10-17 (cnt=8, max=17) (estimated)
3054 - shaderdb: 67 instructions, 31 nops, 36 non-nops, (56 instlen), 0 half, 5 full
3055 - shaderdb: 1 (ss), 0 (sy)
3056 109d00b4: 0000: c0813000 01200000 00000000 10000002 40700000 10030002 40700001 00001004
3057 109d00d4: 0020: 63818000 00011007 63818001 00001008 63820000 0001100b 63820001 0000100c
3058 109d00f4: 0040: 6382800a 10010002 40700000 0001100f 6382800d 00001005 63818000 00000010
3059 109d0114: 0060: 20244001 00001009 63820000 00000000 00000000 0000100d 6382800b 10020002
3060 109d0134: 0080: 40700000 0001101c 40100001 00001006 63818000 00000011 20244002 0000100a
3061 109d0154: 00a0: 63820000 00000013 20244004 0000100e 6382800c 00070007 40700000 0002101d
3062 109d0174: 00c0: 40100002 00000006 63830000 00041013 40500411 00000008 63840000 00000012
3063 109d0194: 00e0: 20244003 00000000 00000200 0003101e 40100003 00000000 00000000 00000000
3064 109d01b4: 0100: 80300000 00000007 40701004 00000000 00000200 10150004 40700004 00000006
3065 109d01d4: 0120: 40700005 00000000 00000200 00041014 63828004 00000008 40700000 00000000
3066 109d01f4: 0140: 00000200 00041016 63800000 00000000 00000200 00001034 40b00004 00001034
3067 109d0214: 0160: 40500000 00000000 00000100 00000004 200c4004 00011020 63800001 00021021
3068 109d0234: 0180: 63800002 00031022 63800000 00011024 6382040e 00021025 6382040f 00001026
3069 109d0254: 01a0: 63820410 00000000 03000000 00000000 00000000 00000000 00000000 00000000
3070 *
3071 t3 opcode: CP_LOAD_STATE4 (30) (35 dwords)
3072 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 }
3073 { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 }
3074 :0:0000:0000[00000000x_00000000x] nop
3075 :6:0001:0001[c7c60000x_01c00000x] ldlv.u32 r0.x, l[0], 1
3076 :6:0002:0002[c7c60001x_01c00002x] ldlv.u32 r0.y, l[1], 1
3077 :6:0003:0003[c7c60002x_01c00004x] ldlv.u32 r0.z, l[2], 1
3078 :6:0004:0004[c7c60003x_01c00006x] ldlv.u32 r0.w, l[3], 1
3079 :2:0005:0005[473090fcx_00002000x] (ss)bary.f (ei)r63.x, 0, r0.x
3080 :0:0006:0006[03000000x_00000000x] end
3081 :0:0007:0007[00000000x_00000000x] nop
3082 :0:0008:0008[00000000x_00000000x] nop
3083 :0:0009:0009[00000000x_00000000x] nop
3084 :0:0010:0010[00000000x_00000000x] nop
3085 Register Stats:
3086 - used (half): (cnt=0, max=0)
3087 - used (full): 0-3 (cnt=4, max=3)
3088 - input (half): (cnt=0, max=0)
3089 - input (full): 0-3 (cnt=4, max=3)
3090 - max const: 0
3091
3092 - output (half): (cnt=0, max=0) (estimated)
3093 - output (full): (cnt=0, max=0) (estimated)
3094 - shaderdb: 11 instructions, 5 nops, 6 non-nops, (11 instlen), 0 half, 1 full
3095 - shaderdb: 1 (ss), 0 (sy)
3096 109d02c0: 0000: c0213000 00700000 00000000 00000000 00000000 01c00000 c7c60000 01c00002
3097 109d02e0: 0020: c7c60001 01c00004 c7c60002 01c00006 c7c60003 00002000 473090fc 00000000
3098 109d0300: 0040: 03000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
3099 *
3100 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
3101 109d034c: 0000: c0002600 00000000
3102 t3 opcode: CP_LOAD_STATE4 (30) (51 dwords)
3103 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 }
3104 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 }
3105 109d0360: 4.276816 0.109522 0.611668 0.517565 0.677381 4.774377 -0.312365 -0.264309
3106 109d0380: 2.500000 -1.480991 -0.961761 -0.813798 13.423393 -6.746271 38.893391 42.140564
3107 109d03a0: 0.000000 0.160000 0.040000 1.000000 -0.064448 0.660942 0.747665 0.000000
3108 109d03c0: 1.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 1.000000
3109 109d03e0: 0.000000 0.800000 0.200000 1.000000 0.000000 0.000000 0.000000 1.000000
3110 109d0400: 0.000000 0.000000 0.000000 1.000000 0.000000 0.000000 0.000000 0.000000
3111 109d0360: 0000: 4088dbad 3de04cdc 3f1c964b 3f047f2c 3f2d68da 4098c7b2 be9fee59 be875387
3112 109d0380: 0020: 40200000 bfbd9119 bf7635f5 bf50550b 4156c638 c0d7e173 421b92d5 42288ff0
3113 109d03a0: 0040: 00000000 3e23d70b 3d23d70b 3f800000 bd83fd0e 3f293379 3f3f66f5 00000000
3114 109d03c0: 0060: 3f800000 00000000 00000000 00000000 00000000 00000000 00000000 3f800000
3115 109d03e0: 0080: 00000000 3f4ccccd 3e4ccccd 3f800000 00000000 00000000 00000000 3f800000
3116 109d0400: 00a0: 00000000 00000000 00000000 3f800000 02020000 02020202 02020202 00000202
3117 109d0354: 0000: c0313000 03200000 00000001 4088dbad 3de04cdc 3f1c964b 3f047f2c 3f2d68da
3118 109d0374: 0020: 4098c7b2 be9fee59 be875387 40200000 bfbd9119 bf7635f5 bf50550b 4156c638
3119 109d0394: 0040: c0d7e173 421b92d5 42288ff0 00000000 3e23d70b 3d23d70b 3f800000 bd83fd0e
3120 109d03b4: 0060: 3f293379 3f3f66f5 00000000 3f800000 00000000 00000000 00000000 00000000
3121 109d03d4: 0080: 00000000 00000000 3f800000 00000000 3f4ccccd 3e4ccccd 3f800000 00000000
3122 109d03f4: 00a0: 00000000 00000000 3f800000 00000000 00000000 00000000 3f800000 02020000
3123 109d0414: 00c0: 02020202 02020202 00000202
3124 t3 opcode: CP_LOAD_STATE4 (30) (7 dwords)
3125 { DST_OFF = 13 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 }
3126 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 }
3127 109d042c: 0.000000 -28026765312.000000 -28026765312.000000 -28026765312.000000
3128 109d042c: 0000: 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0
3129 109d0420: 0000: c0053000 0060000d 00000001 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0
3130 t0 write VFD_FETCH[0].INSTR_0 (220a)
3131 VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 | SWITCHNEXT }
3132 VFD_FETCH[0].INSTR_1: 0x107cb000
3133 VFD_FETCH[0].INSTR_2: { SIZE = 0x100000 }
3134 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 }
3135 109d043c: 0000: 0003220a 00080c0b 107cb000 00100000 00000001
3136 t0 write VFD_DECODE[0].INSTR (228a)
3137 VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID | SWITCHNEXT }
3138 109d0450: 0000: 0000228a 6c0020df
3139 t0 write VFD_FETCH[0x1].INSTR_0 (220e)
3140 VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 }
3141 VFD_FETCH[0x1].INSTR_1: 0x107cb00c
3142 VFD_FETCH[0x1].INSTR_2: { SIZE = 0xffff4 }
3143 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 }
3144 109d0458: 0000: 0003220e 00000c0b 107cb00c 000ffff4 00000001
3145 t0 write VFD_DECODE[0x1].INSTR (228b)
3146 VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r1.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID }
3147 109d046c: 0000: 0000228b 2c0060df
3148 t0 write VFD_CONTROL_0 (2200)
3149 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 }
3150 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x }
3151 VFD_CONTROL_2: 0
3152 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x }
3153 VFD_CONTROL_4: 0
3154 109d0474: 0000: 00042200 082a0008 fcfc0081 00000000 0000fc00 00000000
3155 t0 write UCHE_INVALIDATE0 (0e8a)
3156 UCHE_INVALIDATE0: 0
3157 UCHE_INVALIDATE1: 0x12
3158 109d048c: 0000: 00010e8a 00000000 00000012
3159 t0 write VFD_INDEX_OFFSET (2208)
3160 VFD_INDEX_OFFSET: 0
3161 UNKNOWN_2209: 0
3162 109d0498: 0000: 00012208 00000000 00000000
3163 t0 write PC_RESTART_INDEX (21c6)
3164 PC_RESTART_INDEX: 0xffffffff
3165 109d04a4: 0000: 000021c6 ffffffff
3166 t0 write CP_SCRATCH[0x7].REG (057f)
3167 CP_SCRATCH[0x7].REG: 0x44
3168 :0,67,115,68
3169 109d04ac: 0000: 0000057f 00000044
3170 t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
3171 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS }
3172 { NUM_INSTANCES = 1 }
3173 { NUM_INDICES = 240 }
3174 { FIRST_INDX = 0 }
3175 { INDX_BASE = 0x10bd0d20 }
3176 { INDX_SIZE = 480 }
3177 draw[11] register values
3178 !+ 00000043 CP_SCRATCH[0x5].REG: 0x43
3179 :0,67,115,68
3180 !+ 00000044 CP_SCRATCH[0x7].REG: 0x44
3181 :0,67,115,68
3182 + 00000000 UCHE_INVALIDATE0: 0
3183 + 00000012 UCHE_INVALIDATE1: 0x12
3184 + 00000000 GRAS_CNTL: { 0 }
3185 + 00000000 GRAS_ALPHA_CONTROL: { 0 }
3186 + 00000000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 }
3187 + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 }
3188 + 80000016 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE }
3189 + 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 }
3190 + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 }
3191 + 00000055 VPC_VARYING_INTERP[0].MODE: 0x55
3192 + 00000000 VPC_VARYING_INTERP[0x1].MODE: 0
3193 + 00000000 VPC_VARYING_INTERP[0x2].MODE: 0
3194 + 00000000 VPC_VARYING_INTERP[0x3].MODE: 0
3195 + 00000000 VPC_VARYING_INTERP[0x4].MODE: 0
3196 + 00000000 VPC_VARYING_INTERP[0x5].MODE: 0
3197 + 00000000 VPC_VARYING_INTERP[0x6].MODE: 0
3198 + 00000000 VPC_VARYING_INTERP[0x7].MODE: 0
3199 + 00000000 VPC_VARYING_PS_REPL[0].MODE: 0
3200 + 00000000 VPC_VARYING_PS_REPL[0x1].MODE: 0
3201 + 00000000 VPC_VARYING_PS_REPL[0x2].MODE: 0
3202 + 00000000 VPC_VARYING_PS_REPL[0x3].MODE: 0
3203 + 00000000 VPC_VARYING_PS_REPL[0x4].MODE: 0
3204 + 00000000 VPC_VARYING_PS_REPL[0x5].MODE: 0
3205 + 00000000 VPC_VARYING_PS_REPL[0x6].MODE: 0
3206 + 00000000 VPC_VARYING_PS_REPL[0x7].MODE: 0
3207 + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
3208 + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
3209 + ffffffff PC_RESTART_INDEX: 0xffffffff
3210 !+ 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 }
3211 + fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x }
3212 + 00000000 VFD_CONTROL_2: 0
3213 + 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x }
3214 + 00000000 VFD_CONTROL_4: 0
3215 + 00000000 VFD_INDEX_OFFSET: 0
3216 + 00000000 UNKNOWN_2209: 0
3217 !+ 00080c0b VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 | SWITCHNEXT }
3218 + 107cb000 VFD_FETCH[0].INSTR_1: 0x107cb000
3219 + 00100000 VFD_FETCH[0].INSTR_2: { SIZE = 0x100000 }
3220 + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 }
3221 + 00000c0b VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 }
3222 + 107cb00c VFD_FETCH[0x1].INSTR_1: 0x107cb00c
3223 + 000ffff4 VFD_FETCH[0x1].INSTR_2: { SIZE = 0xffff4 }
3224 + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 }
3225 !+ 6c0020df VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID | SWITCHNEXT }
3226 + 2c0060df VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r1.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID }
3227 + 00140010 SP_SP_CTRL_REG: { 0x140010 }
3228 + 000005ff SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f }
3229 !+ 00201400 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE }
3230 !+ 08000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 8 }
3231 !+ 0010fc0a SP_VS_PARAM_REG: { POSREGID = r2.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 }
3232 !+ 00001e0e SP_VS_OUT[0].REG: { A_REGID = r3.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 }
3233 + 08080808 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 }
3234 + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 }
3235 !+ 10cd5000 SP_VS_OBJ_START: 0x10cd5000
3236 + 00000004 SP_VS_LENGTH_REG: 4
3237 + 00340402 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE }
3238 + 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 }
3239 + 7e420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
3240 + 10cd2000 SP_FS_OBJ_START: 0x10cd2000
3241 + 00000001 SP_FS_LENGTH_REG: 1
3242 + 0000fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x }
3243 + 0001a000 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM }
3244 + 00000000 SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 }
3245 + 00000000 SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 }
3246 + 00000000 SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 }
3247 + 00000000 SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 }
3248 + 00000000 SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 }
3249 + 00000000 SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 }
3250 + 00000000 SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 }
3251 + 7e420000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
3252 + 7e420000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
3253 + 7e420000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
3254 + 28000250 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE }
3255 + fcfc0100 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x }
3256 + fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x }
3257 + fcfcfcfc HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
3258 + 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 }
3259 + 04000042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 }
3260 + 017e423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 }
3261 + 007e4200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
3262 + 007e4200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
3263 + 007e4200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
3264 + 00000003 HLSQ_UPDATE_CONTROL: 0x3
3265 109d04b4: 0000: c0053800 00000404 00000001 000000f0 00000000 10bd0d20 000001e0
3266 t0 write CP_SCRATCH[0x7].REG (057f)
3267 CP_SCRATCH[0x7].REG: 0x45
3268 :0,67,115,69
3269 109d04d0: 0000: 0000057f 00000045
3270 t0 write CP_SCRATCH[0x5].REG (057d)
3271 CP_SCRATCH[0x5].REG: 0x49
3272 :0,73,115,69
3273 109d04d8: 0000: 0000057d 00000049
3274 t0 write RB_DEPTH_CONTROL (2101)
3275 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE }
3276 109d04e0: 0000: 00002101 80000016
3277 t0 write GRAS_ALPHA_CONTROL (2073)
3278 GRAS_ALPHA_CONTROL: { 0 }
3279 109d04e8: 0000: 00002073 00000000
3280 t0 write GRAS_SU_MODE_CONTROL (2078)
3281 GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 | RENDERING_PASS }
3282 109d04f0: 0000: 00002078 00100012
3283 t0 write GRAS_SU_POINT_MINMAX (2070)
3284 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 }
3285 GRAS_SU_POINT_SIZE: 1.000000
3286 109d04f8: 0000: 00012070 00100010 00000010
3287 t0 write GRAS_SU_POLY_OFFSET_SCALE (2074)
3288 GRAS_SU_POLY_OFFSET_SCALE: 0.000000
3289 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000
3290 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000
3291 109d0504: 0000: 00022074 00000000 00000000 00000000
3292 t0 write GRAS_CL_CLIP_CNTL (2000)
3293 GRAS_CL_CLIP_CNTL: { 0x80000 }
3294 109d0514: 0000: 00002000 00080000
3295 t0 write PC_PRIM_VTX_CNTL (21c4)
3296 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
3297 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
3298 109d051c: 0000: 000121c4 02000001 00000012
3299 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c)
3300 GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 }
3301 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
3302 109d0528: 0000: 0001209c 012b012b 00000000
3303 t0 write RB_VPORT_Z_CLAMP[0].MIN (2120)
3304 RB_VPORT_Z_CLAMP[0].MIN: 0
3305 RB_VPORT_Z_CLAMP[0].MAX: 0xffffff
3306 109d0534: 0000: 00012120 00000000 00ffffff
3307 t0 write HLSQ_UPDATE_CONTROL (23db)
3308 HLSQ_UPDATE_CONTROL: 0x3
3309 109d0540: 0000: 000023db 00000003
3310 t0 write HLSQ_CONTROL_0_REG (23c0)
3311 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE }
3312 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x }
3313 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x }
3314 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
3315 HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 }
3316 109d0548: 0000: 000423c0 28000250 fcfc0100 fff3f3f0 fcfcfc00 00fcfcfc
3317 t0 write HLSQ_VS_CONTROL_REG (23c5)
3318 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 }
3319 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 }
3320 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
3321 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
3322 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
3323 109d0560: 0000: 000423c5 04000042 017e423e 007e4200 007e4200 007e4200
3324 t0 write SP_SP_CTRL_REG (22c0)
3325 SP_SP_CTRL_REG: { 0x140010 }
3326 109d0578: 0000: 000022c0 00140010
3327 t0 write SP_INSTR_CACHE_CTRL (22c1)
3328 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f }
3329 109d0580: 0000: 000022c1 000005ff
3330 t0 write SP_VS_LENGTH_REG (22e5)
3331 SP_VS_LENGTH_REG: 4
3332 109d0588: 0000: 000022e5 00000004
3333 t0 write SP_VS_CTRL_REG0 (22c4)
3334 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE }
3335 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 8 }
3336 SP_VS_PARAM_REG: { POSREGID = r2.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 }
3337 109d0590: 0000: 000222c4 00201400 08000042 0010fc0a
3338 t0 write SP_VS_OUT[0].REG (22c7)
3339 SP_VS_OUT[0].REG: { A_REGID = r3.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 }
3340 109d05a0: 0000: 000022c7 00001e0e
3341 t0 write SP_VS_VPC_DST[0].REG (22d8)
3342 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 }
3343 109d05a8: 0000: 000022d8 08080808
3344 t0 write SP_VS_OBJ_OFFSET_REG (22e0)
3345 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 }
3346 SP_VS_OBJ_START: 0x10cd5000
3347 109d05b0: 0000: 000122e0 00000000 10cd5000
3348 t0 write SP_FS_LENGTH_REG (22ef)
3349 SP_FS_LENGTH_REG: 1
3350 109d05bc: 0000: 000022ef 00000001
3351 t0 write SP_FS_CTRL_REG0 (22e8)
3352 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE }
3353 SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 }
3354 109d05c4: 0000: 000122e8 00340802 8010003e
3355 t0 write SP_FS_OBJ_OFFSET_REG (22ea)
3356 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
3357 SP_FS_OBJ_START: 0x108cb000
3358 109d05d0: 0000: 000122ea 7e420000 108cb000
3359 t0 write SP_HS_OBJ_OFFSET_REG (230d)
3360 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
3361 109d05dc: 0000: 0000230d 7e420000
3362 t0 write SP_DS_OBJ_OFFSET_REG (2334)
3363 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
3364 109d05e4: 0000: 00002334 7e420000
3365 t0 write SP_GS_OBJ_OFFSET_REG (235b)
3366 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
3367 109d05ec: 0000: 0000235b 7e420000
3368 t0 write GRAS_CNTL (2003)
3369 GRAS_CNTL: { IJ_PERSP }
3370 109d05f4: 0000: 00002003 00000001
3371 t0 write RB_RENDER_CONTROL2 (20a3)
3372 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL }
3373 109d05fc: 0000: 000020a3 00001000
3374 t0 write RB_FS_OUTPUT_REG (2100)
3375 RB_FS_OUTPUT_REG: { MRT = 1 }
3376 109d0604: 0000: 00002100 00000001
3377 t0 write SP_FS_OUTPUT_REG (22f0)
3378 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x }
3379 109d060c: 0000: 000022f0 0000fc01
3380 t0 write SP_FS_MRT[0].REG (22f1)
3381 SP_FS_MRT[0].REG: { REGID = r0.z | MRTFORMAT = RB4_R8G8B8A8_UNORM }
3382 SP_FS_MRT[0x1].REG: { REGID = r0.z | MRTFORMAT = 0 }
3383 SP_FS_MRT[0x2].REG: { REGID = r0.z | MRTFORMAT = 0 }
3384 SP_FS_MRT[0x3].REG: { REGID = r0.z | MRTFORMAT = 0 }
3385 SP_FS_MRT[0x4].REG: { REGID = r0.z | MRTFORMAT = 0 }
3386 SP_FS_MRT[0x5].REG: { REGID = r0.z | MRTFORMAT = 0 }
3387 SP_FS_MRT[0x6].REG: { REGID = r0.z | MRTFORMAT = 0 }
3388 SP_FS_MRT[0x7].REG: { REGID = r0.z | MRTFORMAT = 0 }
3389 109d0614: 0000: 000722f1 0001a002 00000002 00000002 00000002 00000002 00000002 00000002
3390 109d0634: 0020: 00000002
3391 t0 write VPC_ATTR (2140)
3392 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 }
3393 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 }
3394 109d0638: 0000: 00012140 42001004 00040400
3395 t0 write VPC_VARYING_INTERP[0].MODE (2142)
3396 VPC_VARYING_INTERP[0].MODE: 0
3397 VPC_VARYING_INTERP[0x1].MODE: 0
3398 VPC_VARYING_INTERP[0x2].MODE: 0
3399 VPC_VARYING_INTERP[0x3].MODE: 0
3400 VPC_VARYING_INTERP[0x4].MODE: 0
3401 VPC_VARYING_INTERP[0x5].MODE: 0
3402 VPC_VARYING_INTERP[0x6].MODE: 0
3403 VPC_VARYING_INTERP[0x7].MODE: 0
3404 109d0644: 0000: 00072142 00000000 00000000 00000000 00000000 00000000 00000000 00000000
3405 *
3406 t0 write VPC_VARYING_PS_REPL[0].MODE (214a)
3407 VPC_VARYING_PS_REPL[0].MODE: 0
3408 VPC_VARYING_PS_REPL[0x1].MODE: 0
3409 VPC_VARYING_PS_REPL[0x2].MODE: 0
3410 VPC_VARYING_PS_REPL[0x3].MODE: 0
3411 VPC_VARYING_PS_REPL[0x4].MODE: 0
3412 VPC_VARYING_PS_REPL[0x5].MODE: 0
3413 VPC_VARYING_PS_REPL[0x6].MODE: 0
3414 VPC_VARYING_PS_REPL[0x7].MODE: 0
3415 109d0668: 0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000
3416 *
3417 t3 opcode: CP_LOAD_STATE4 (30) (131 dwords)
3418 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 }
3419 { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 }
3420 :2:0000:0000[40700000x_10000002x] mul.f r0.x, r0.z, c0.x
3421 :2:0001:0001[40700001x_10030002x] mul.f r0.y, r0.z, c0.w
3422 :3:0002:0002[63818000x_00001004x] mad.f32 r0.x, c1.x, r0.w, r0.x
3423 :3:0003:0003[63818001x_00011007x] mad.f32 r0.y, c1.w, r0.w, r0.y
3424 :3:0004:0004[63820000x_00001008x] mad.f32 r0.x, c2.x, r1.x, r0.x
3425 :3:0005:0005[63820001x_0001100bx] mad.f32 r0.y, c2.w, r1.x, r0.y
3426 :3:0006:0006[6382800ax_0000100cx] mad.f32 r2.z, c3.x, r1.y, r0.x
3427 :2:0007:0007[40700000x_10010002x] mul.f r0.x, r0.z, c0.y
3428 :3:0008:0008[6382800dx_0001100fx] mad.f32 r3.y, c3.w, r1.y, r0.y
3429 :3:0009:0009[63818000x_00001005x] mad.f32 r0.x, c1.y, r0.w, r0.x
3430 :1:0010:0010[20244001x_00000010x] mov.f32f32 r0.y, c4.x
3431 :3:0011:0011[63820000x_00001009x] mad.f32 r0.x, c2.y, r1.x, r0.x
3432 :0:0012:0012[00000000x_00000000x] nop
3433 :3:0013:0013[6382800bx_0000100dx] mad.f32 r2.w, c3.y, r1.y, r0.x
3434 :2:0014:0014[40700000x_10020002x] mul.f r0.x, r0.z, c0.z
3435 :2:0015:0015[40100001x_0001101cx] add.f r0.y, c7.x, r0.y
3436 :3:0016:0016[63818000x_00001006x] mad.f32 r0.x, c1.z, r0.w, r0.x
3437 :1:0017:0017[20244002x_00000011x] mov.f32f32 r0.z, c4.y
3438 :3:0018:0018[63820000x_0000100ax] mad.f32 r0.x, c2.z, r1.x, r0.x
3439 :1:0019:0019[20244004x_00000013x] mov.f32f32 r1.x, c4.w
3440 :3:0020:0020[6382800cx_0000100ex] mad.f32 r3.x, c3.z, r1.y, r0.x
3441 :2:0021:0021[40700000x_00070007x] mul.f r0.x, r1.w, r1.w
3442 :2:0022:0022[40100002x_0002101dx] add.f r0.z, c7.y, r0.z
3443 :3:0023:0023[63830000x_00000006x] mad.f32 r0.x, r1.z, r1.z, r0.x
3444 :2:0024:0024[40500411x_00041013x] (sat)max.f r4.y, c4.w, r1.x
3445 :3:0025:0025[63840000x_00000008x] mad.f32 r0.x, r2.x, r2.x, r0.x
3446 :1:0026:0026[20244003x_00000012x] mov.f32f32 r0.w, c4.z
3447 :0:0027:0027[00000200x_00000000x] (rpt2)nop
3448 :2:0028:0030[40100003x_0003101ex] add.f r0.w, c7.z, r0.w
3449 :0:0029:0031[00000000x_00000000x] nop
3450 :4:0030:0032[80300000x_00000000x] rsq r0.x, r0.x
3451 :2:0031:0033[40701004x_00000007x] (ss)mul.f r1.x, r1.w, r0.x
3452 :0:0032:0034[00000200x_00000000x] (rpt2)nop
3453 :2:0033:0037[40700004x_10150004x] mul.f r1.x, r1.x, c5.y
3454 :2:0034:0038[40700005x_00000006x] mul.f r1.y, r1.z, r0.x
3455 :0:0035:0039[00000200x_00000000x] (rpt2)nop
3456 :3:0036:0042[63828004x_00041014x] mad.f32 r1.x, c5.x, r1.y, r1.x
3457 :2:0037:0043[40700000x_00000008x] mul.f r0.x, r2.x, r0.x
3458 :0:0038:0044[00000200x_00000000x] (rpt2)nop
3459 :3:0039:0047[63800000x_00041016x] mad.f32 r0.x, c5.z, r0.x, r1.x
3460 :0:0040:0048[00000200x_00000000x] (rpt2)nop
3461 :2:0041:0051[40b00004x_00001034x] cmps.f.lt r1.x, c13.x, r0.x
3462 :2:0042:0052[40500000x_00001034x] max.f r0.x, c13.x, r0.x
3463 :0:0043:0053[00000100x_00000000x] (rpt1)nop
3464 :1:0044:0055[200c4004x_00000004x] cov.u32f32 r1.x, r1.x
3465 :3:0045:0056[63800001x_00011020x] mad.f32 r0.y, c8.x, r0.x, r0.y
3466 :3:0046:0057[63800002x_00021021x] mad.f32 r0.z, c8.y, r0.x, r0.z
3467 :3:0047:0058[63800000x_00031022x] mad.f32 r0.x, c8.z, r0.x, r0.w
3468 :3:0048:0059[6382040ex_00011024x] (sat)mad.f32 r3.z, c9.x, r1.x, r0.y
3469 :3:0049:0060[6382040fx_00021025x] (sat)mad.f32 r3.w, c9.y, r1.x, r0.z
3470 :3:0050:0061[63820410x_00001026x] (sat)mad.f32 r4.x, c9.z, r1.x, r0.x
3471 :0:0051:0062[03000000x_00000000x] end
3472 :0:0052:0063[00000000x_00000000x] nop
3473 :0:0053:0064[00000000x_00000000x] nop
3474 :0:0054:0065[00000000x_00000000x] nop
3475 :0:0055:0066[00000000x_00000000x] nop
3476 Register Stats:
3477 - used (half): (cnt=0, max=0)
3478 - used (full): 0-8 10-17 (cnt=17, max=17)
3479 - input (half): (cnt=0, max=0)
3480 - input (full): 2-8 (cnt=7, max=8)
3481 - max const: 52
3482
3483 - output (half): (cnt=0, max=0) (estimated)
3484 - output (full): 10-17 (cnt=8, max=17) (estimated)
3485 - shaderdb: 67 instructions, 31 nops, 36 non-nops, (56 instlen), 0 half, 5 full
3486 - shaderdb: 1 (ss), 0 (sy)
3487 109d068c: 0000: c0813000 01200000 00000000 10000002 40700000 10030002 40700001 00001004
3488 109d06ac: 0020: 63818000 00011007 63818001 00001008 63820000 0001100b 63820001 0000100c
3489 109d06cc: 0040: 6382800a 10010002 40700000 0001100f 6382800d 00001005 63818000 00000010
3490 109d06ec: 0060: 20244001 00001009 63820000 00000000 00000000 0000100d 6382800b 10020002
3491 109d070c: 0080: 40700000 0001101c 40100001 00001006 63818000 00000011 20244002 0000100a
3492 109d072c: 00a0: 63820000 00000013 20244004 0000100e 6382800c 00070007 40700000 0002101d
3493 109d074c: 00c0: 40100002 00000006 63830000 00041013 40500411 00000008 63840000 00000012
3494 109d076c: 00e0: 20244003 00000000 00000200 0003101e 40100003 00000000 00000000 00000000
3495 109d078c: 0100: 80300000 00000007 40701004 00000000 00000200 10150004 40700004 00000006
3496 109d07ac: 0120: 40700005 00000000 00000200 00041014 63828004 00000008 40700000 00000000
3497 109d07cc: 0140: 00000200 00041016 63800000 00000000 00000200 00001034 40b00004 00001034
3498 109d07ec: 0160: 40500000 00000000 00000100 00000004 200c4004 00011020 63800001 00021021
3499 109d080c: 0180: 63800002 00031022 63800000 00011024 6382040e 00021025 6382040f 00001026
3500 109d082c: 01a0: 63820410 00000000 03000000 00000000 00000000 00000000 00000000 00000000
3501 *
3502 t3 opcode: CP_LOAD_STATE4 (30) (35 dwords)
3503 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 }
3504 { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 }
3505 :2:0000:0000[47300002x_00002000x] bary.f r0.z, 0, r0.x
3506 :2:0001:0001[47300003x_00002001x] bary.f r0.w, 1, r0.x
3507 :2:0002:0002[47300004x_00002002x] bary.f r1.x, 2, r0.x
3508 :2:0003:0003[47308005x_00002003x] bary.f (ei)r1.y, 3, r0.x
3509 :0:0004:0004[03000000x_00000000x] end
3510 :0:0005:0005[00000000x_00000000x] nop
3511 :0:0006:0006[00000000x_00000000x] nop
3512 :0:0007:0007[00000000x_00000000x] nop
3513 :0:0008:0008[00000000x_00000000x] nop
3514 Register Stats:
3515 - used (half): (cnt=0, max=0)
3516 - used (full): 0 2-5 (cnt=5, max=5)
3517 - input (half): (cnt=0, max=0)
3518 - input (full): 0 (cnt=1, max=0)
3519 - max const: 0
3520
3521 - output (half): (cnt=0, max=0) (estimated)
3522 - output (full): 2-5 (cnt=4, max=5) (estimated)
3523 - shaderdb: 9 instructions, 4 nops, 5 non-nops, (9 instlen), 0 half, 2 full
3524 - shaderdb: 0 (ss), 0 (sy)
3525 109d0898: 0000: c0213000 00700000 00000000 00002000 47300002 00002001 47300003 00002002
3526 109d08b8: 0020: 47300004 00002003 47308005 00000000 03000000 00000000 00000000 00000000
3527 *
3528 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
3529 109d0924: 0000: c0002600 00000000
3530 t3 opcode: CP_LOAD_STATE4 (30) (51 dwords)
3531 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 }
3532 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 }
3533 109d0938: 4.276816 0.109522 0.611668 0.517565 0.677381 4.774377 -0.312365 -0.264309
3534 109d0958: 2.500000 -1.480991 -0.961761 -0.813798 13.423393 -6.746271 38.893391 42.140564
3535 109d0978: 0.000000 0.160000 0.040000 1.000000 -0.064448 0.660942 0.747665 0.000000
3536 109d0998: 1.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 1.000000
3537 109d09b8: 0.000000 0.800000 0.200000 1.000000 0.000000 0.000000 0.000000 1.000000
3538 109d09d8: 0.000000 0.000000 0.000000 1.000000 0.000000 0.000000 0.000000 0.000000
3539 109d0938: 0000: 4088dbad 3de04cdc 3f1c964b 3f047f2c 3f2d68da 4098c7b2 be9fee59 be875387
3540 109d0958: 0020: 40200000 bfbd9119 bf7635f5 bf50550b 4156c638 c0d7e173 421b92d5 42288ff0
3541 109d0978: 0040: 00000000 3e23d70b 3d23d70b 3f800000 bd83fd0e 3f293379 3f3f66f5 00000000
3542 109d0998: 0060: 3f800000 00000000 00000000 00000000 00000000 00000000 00000000 3f800000
3543 109d09b8: 0080: 00000000 3f4ccccd 3e4ccccd 3f800000 00000000 00000000 00000000 3f800000
3544 109d09d8: 00a0: 00000000 00000000 00000000 3f800000 02020000 02020202 02020202 00000202
3545 109d092c: 0000: c0313000 03200000 00000001 4088dbad 3de04cdc 3f1c964b 3f047f2c 3f2d68da
3546 109d094c: 0020: 4098c7b2 be9fee59 be875387 40200000 bfbd9119 bf7635f5 bf50550b 4156c638
3547 109d096c: 0040: c0d7e173 421b92d5 42288ff0 00000000 3e23d70b 3d23d70b 3f800000 bd83fd0e
3548 109d098c: 0060: 3f293379 3f3f66f5 00000000 3f800000 00000000 00000000 00000000 00000000
3549 109d09ac: 0080: 00000000 00000000 3f800000 00000000 3f4ccccd 3e4ccccd 3f800000 00000000
3550 109d09cc: 00a0: 00000000 00000000 3f800000 00000000 00000000 00000000 3f800000 02020000
3551 109d09ec: 00c0: 02020202 02020202 00000202
3552 t0 write VFD_INDEX_OFFSET (2208)
3553 VFD_INDEX_OFFSET: 0
3554 UNKNOWN_2209: 0
3555 109d09f8: 0000: 00012208 00000000 00000000
3556 t0 write PC_RESTART_INDEX (21c6)
3557 PC_RESTART_INDEX: 0xffffffff
3558 109d0a04: 0000: 000021c6 ffffffff
3559 t0 write CP_SCRATCH[0x7].REG (057f)
3560 CP_SCRATCH[0x7].REG: 0x4a
3561 :0,73,115,74
3562 109d0a0c: 0000: 0000057f 0000004a
3563 t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
3564 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS }
3565 { NUM_INSTANCES = 1 }
3566 { NUM_INDICES = 60 }
3567 { FIRST_INDX = 0 }
3568 { INDX_BASE = 0x10bd0f00 }
3569 { INDX_SIZE = 120 }
3570 draw[12] register values
3571 !+ 00000049 CP_SCRATCH[0x5].REG: 0x49
3572 :0,73,115,74
3573 !+ 0000004a CP_SCRATCH[0x7].REG: 0x4a
3574 :0,73,115,74
3575 + 00080000 GRAS_CL_CLIP_CNTL: { 0x80000 }
3576 !+ 00000001 GRAS_CNTL: { IJ_PERSP }
3577 + 00100010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 }
3578 + 00000010 GRAS_SU_POINT_SIZE: 1.000000
3579 + 00000000 GRAS_ALPHA_CONTROL: { 0 }
3580 + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000
3581 + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000
3582 + 00000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000
3583 + 00100012 GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 | RENDERING_PASS }
3584 + 012b012b GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 }
3585 + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
3586 !+ 00001000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL }
3587 + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 }
3588 + 80000016 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE }
3589 + 00000000 RB_VPORT_Z_CLAMP[0].MIN: 0
3590 + 00ffffff RB_VPORT_Z_CLAMP[0].MAX: 0xffffff
3591 + 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 }
3592 + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 }
3593 !+ 00000000 VPC_VARYING_INTERP[0].MODE: 0
3594 + 00000000 VPC_VARYING_INTERP[0x1].MODE: 0
3595 + 00000000 VPC_VARYING_INTERP[0x2].MODE: 0
3596 + 00000000 VPC_VARYING_INTERP[0x3].MODE: 0
3597 + 00000000 VPC_VARYING_INTERP[0x4].MODE: 0
3598 + 00000000 VPC_VARYING_INTERP[0x5].MODE: 0
3599 + 00000000 VPC_VARYING_INTERP[0x6].MODE: 0
3600 + 00000000 VPC_VARYING_INTERP[0x7].MODE: 0
3601 + 00000000 VPC_VARYING_PS_REPL[0].MODE: 0
3602 + 00000000 VPC_VARYING_PS_REPL[0x1].MODE: 0
3603 + 00000000 VPC_VARYING_PS_REPL[0x2].MODE: 0
3604 + 00000000 VPC_VARYING_PS_REPL[0x3].MODE: 0
3605 + 00000000 VPC_VARYING_PS_REPL[0x4].MODE: 0
3606 + 00000000 VPC_VARYING_PS_REPL[0x5].MODE: 0
3607 + 00000000 VPC_VARYING_PS_REPL[0x6].MODE: 0
3608 + 00000000 VPC_VARYING_PS_REPL[0x7].MODE: 0
3609 + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
3610 + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
3611 + ffffffff PC_RESTART_INDEX: 0xffffffff
3612 + 00000000 VFD_INDEX_OFFSET: 0
3613 + 00000000 UNKNOWN_2209: 0
3614 + 00140010 SP_SP_CTRL_REG: { 0x140010 }
3615 + 000005ff SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f }
3616 + 00201400 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE }
3617 + 08000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 8 }
3618 + 0010fc0a SP_VS_PARAM_REG: { POSREGID = r2.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 }
3619 + 00001e0e SP_VS_OUT[0].REG: { A_REGID = r3.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 }
3620 + 08080808 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 }
3621 + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 }
3622 + 10cd5000 SP_VS_OBJ_START: 0x10cd5000
3623 + 00000004 SP_VS_LENGTH_REG: 4
3624 !+ 00340802 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE }
3625 + 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 }
3626 + 7e420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
3627 !+ 108cb000 SP_FS_OBJ_START: 0x108cb000
3628 + 00000001 SP_FS_LENGTH_REG: 1
3629 + 0000fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x }
3630 !+ 0001a002 SP_FS_MRT[0].REG: { REGID = r0.z | MRTFORMAT = RB4_R8G8B8A8_UNORM }
3631 !+ 00000002 SP_FS_MRT[0x1].REG: { REGID = r0.z | MRTFORMAT = 0 }
3632 !+ 00000002 SP_FS_MRT[0x2].REG: { REGID = r0.z | MRTFORMAT = 0 }
3633 !+ 00000002 SP_FS_MRT[0x3].REG: { REGID = r0.z | MRTFORMAT = 0 }
3634 !+ 00000002 SP_FS_MRT[0x4].REG: { REGID = r0.z | MRTFORMAT = 0 }
3635 !+ 00000002 SP_FS_MRT[0x5].REG: { REGID = r0.z | MRTFORMAT = 0 }
3636 !+ 00000002 SP_FS_MRT[0x6].REG: { REGID = r0.z | MRTFORMAT = 0 }
3637 !+ 00000002 SP_FS_MRT[0x7].REG: { REGID = r0.z | MRTFORMAT = 0 }
3638 + 7e420000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
3639 + 7e420000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
3640 + 7e420000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
3641 + 28000250 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE }
3642 + fcfc0100 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x }
3643 + fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x }
3644 !+ fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
3645 + 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 }
3646 + 04000042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 }
3647 + 017e423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 }
3648 + 007e4200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
3649 + 007e4200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
3650 + 007e4200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
3651 + 00000003 HLSQ_UPDATE_CONTROL: 0x3
3652 109d0a14: 0000: c0053800 00000404 00000001 0000003c 00000000 10bd0f00 00000078
3653 t0 write CP_SCRATCH[0x7].REG (057f)
3654 CP_SCRATCH[0x7].REG: 0x4b
3655 :0,73,115,75
3656 109d0a30: 0000: 0000057f 0000004b
3657 t0 write CP_SCRATCH[0x5].REG (057d)
3658 CP_SCRATCH[0x5].REG: 0x4f
3659 :0,79,115,75
3660 109d0a38: 0000: 0000057d 0000004f
3661 t0 write RB_DEPTH_CONTROL (2101)
3662 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE }
3663 109d0a40: 0000: 00002101 80000016
3664 t0 write GRAS_ALPHA_CONTROL (2073)
3665 GRAS_ALPHA_CONTROL: { 0 }
3666 109d0a48: 0000: 00002073 00000000
3667 t0 write GRAS_SU_MODE_CONTROL (2078)
3668 GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 | RENDERING_PASS }
3669 109d0a50: 0000: 00002078 00100012
3670 t0 write GRAS_SU_POINT_MINMAX (2070)
3671 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 }
3672 GRAS_SU_POINT_SIZE: 1.000000
3673 109d0a58: 0000: 00012070 00100010 00000010
3674 t0 write GRAS_SU_POLY_OFFSET_SCALE (2074)
3675 GRAS_SU_POLY_OFFSET_SCALE: 0.000000
3676 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000
3677 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000
3678 109d0a64: 0000: 00022074 00000000 00000000 00000000
3679 t0 write GRAS_CL_CLIP_CNTL (2000)
3680 GRAS_CL_CLIP_CNTL: { 0x80000 }
3681 109d0a74: 0000: 00002000 00080000
3682 t0 write PC_PRIM_VTX_CNTL (21c4)
3683 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
3684 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
3685 109d0a7c: 0000: 000121c4 02000001 00000012
3686 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c)
3687 GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 }
3688 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
3689 109d0a88: 0000: 0001209c 012b012b 00000000
3690 t0 write RB_VPORT_Z_CLAMP[0].MIN (2120)
3691 RB_VPORT_Z_CLAMP[0].MIN: 0
3692 RB_VPORT_Z_CLAMP[0].MAX: 0xffffff
3693 109d0a94: 0000: 00012120 00000000 00ffffff
3694 t0 write HLSQ_UPDATE_CONTROL (23db)
3695 HLSQ_UPDATE_CONTROL: 0x3
3696 109d0aa0: 0000: 000023db 00000003
3697 t0 write HLSQ_CONTROL_0_REG (23c0)
3698 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE }
3699 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x }
3700 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x }
3701 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
3702 HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 }
3703 109d0aa8: 0000: 000423c0 28000250 fcfc0100 fff3f3f0 fcfcfcfc 00fcfcfc
3704 t0 write HLSQ_VS_CONTROL_REG (23c5)
3705 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 }
3706 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 }
3707 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
3708 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
3709 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
3710 109d0ac0: 0000: 000423c5 04000042 017e423e 007e4200 007e4200 007e4200
3711 t0 write SP_SP_CTRL_REG (22c0)
3712 SP_SP_CTRL_REG: { 0x140010 }
3713 109d0ad8: 0000: 000022c0 00140010
3714 t0 write SP_INSTR_CACHE_CTRL (22c1)
3715 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f }
3716 109d0ae0: 0000: 000022c1 000005ff
3717 t0 write SP_VS_LENGTH_REG (22e5)
3718 SP_VS_LENGTH_REG: 4
3719 109d0ae8: 0000: 000022e5 00000004
3720 t0 write SP_VS_CTRL_REG0 (22c4)
3721 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 4 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE }
3722 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 4 }
3723 SP_VS_PARAM_REG: { POSREGID = r1.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 }
3724 109d0af0: 0000: 000222c4 00201000 04000042 0010fc06
3725 t0 write SP_VS_OUT[0].REG (22c7)
3726 SP_VS_OUT[0].REG: { A_REGID = r2.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 }
3727 109d0b00: 0000: 000022c7 00001e0a
3728 t0 write SP_VS_VPC_DST[0].REG (22d8)
3729 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 }
3730 109d0b08: 0000: 000022d8 08080808
3731 t0 write SP_VS_OBJ_OFFSET_REG (22e0)
3732 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 }
3733 SP_VS_OBJ_START: 0x10cd0000
3734 109d0b10: 0000: 000122e0 00000000 10cd0000
3735 t0 write SP_FS_LENGTH_REG (22ef)
3736 SP_FS_LENGTH_REG: 1
3737 109d0b1c: 0000: 000022ef 00000001
3738 t0 write SP_FS_CTRL_REG0 (22e8)
3739 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE }
3740 SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 }
3741 109d0b24: 0000: 000122e8 00340402 8010003e
3742 t0 write SP_FS_OBJ_OFFSET_REG (22ea)
3743 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
3744 SP_FS_OBJ_START: 0x10cd2000
3745 109d0b30: 0000: 000122ea 7e420000 10cd2000
3746 t0 write SP_HS_OBJ_OFFSET_REG (230d)
3747 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
3748 109d0b3c: 0000: 0000230d 7e420000
3749 t0 write SP_DS_OBJ_OFFSET_REG (2334)
3750 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
3751 109d0b44: 0000: 00002334 7e420000
3752 t0 write SP_GS_OBJ_OFFSET_REG (235b)
3753 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
3754 109d0b4c: 0000: 0000235b 7e420000
3755 t0 write GRAS_CNTL (2003)
3756 GRAS_CNTL: { 0 }
3757 109d0b54: 0000: 00002003 00000000
3758 t0 write RB_RENDER_CONTROL2 (20a3)
3759 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 }
3760 109d0b5c: 0000: 000020a3 00000000
3761 t0 write RB_FS_OUTPUT_REG (2100)
3762 RB_FS_OUTPUT_REG: { MRT = 1 }
3763 109d0b64: 0000: 00002100 00000001
3764 t0 write SP_FS_OUTPUT_REG (22f0)
3765 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x }
3766 109d0b6c: 0000: 000022f0 0000fc01
3767 t0 write SP_FS_MRT[0].REG (22f1)
3768 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM }
3769 SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 }
3770 SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 }
3771 SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 }
3772 SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 }
3773 SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 }
3774 SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 }
3775 SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 }
3776 109d0b74: 0000: 000722f1 0001a000 00000000 00000000 00000000 00000000 00000000 00000000
3777 *
3778 t0 write VPC_ATTR (2140)
3779 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 }
3780 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 }
3781 109d0b98: 0000: 00012140 42001004 00040400
3782 t0 write VPC_VARYING_INTERP[0].MODE (2142)
3783 VPC_VARYING_INTERP[0].MODE: 0x55
3784 VPC_VARYING_INTERP[0x1].MODE: 0
3785 VPC_VARYING_INTERP[0x2].MODE: 0
3786 VPC_VARYING_INTERP[0x3].MODE: 0
3787 VPC_VARYING_INTERP[0x4].MODE: 0
3788 VPC_VARYING_INTERP[0x5].MODE: 0
3789 VPC_VARYING_INTERP[0x6].MODE: 0
3790 VPC_VARYING_INTERP[0x7].MODE: 0
3791 109d0ba4: 0000: 00072142 00000055 00000000 00000000 00000000 00000000 00000000 00000000
3792 *
3793 t0 write VPC_VARYING_PS_REPL[0].MODE (214a)
3794 VPC_VARYING_PS_REPL[0].MODE: 0
3795 VPC_VARYING_PS_REPL[0x1].MODE: 0
3796 VPC_VARYING_PS_REPL[0x2].MODE: 0
3797 VPC_VARYING_PS_REPL[0x3].MODE: 0
3798 VPC_VARYING_PS_REPL[0x4].MODE: 0
3799 VPC_VARYING_PS_REPL[0x5].MODE: 0
3800 VPC_VARYING_PS_REPL[0x6].MODE: 0
3801 VPC_VARYING_PS_REPL[0x7].MODE: 0
3802 109d0bc8: 0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000
3803 *
3804 t3 opcode: CP_LOAD_STATE4 (30) (131 dwords)
3805 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 }
3806 { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 }
3807 :2:0000:0000[40700000x_10000002x] mul.f r0.x, r0.z, c0.x
3808 :2:0001:0001[40700001x_10030002x] mul.f r0.y, r0.z, c0.w
3809 :3:0002:0002[63818000x_00001004x] mad.f32 r0.x, c1.x, r0.w, r0.x
3810 :3:0003:0003[63818001x_00011007x] mad.f32 r0.y, c1.w, r0.w, r0.y
3811 :3:0004:0004[63820000x_00001008x] mad.f32 r0.x, c2.x, r1.x, r0.x
3812 :3:0005:0005[63820001x_0001100bx] mad.f32 r0.y, c2.w, r1.x, r0.y
3813 :3:0006:0006[63828006x_0000100cx] mad.f32 r1.z, c3.x, r1.y, r0.x
3814 :2:0007:0007[40700000x_10010002x] mul.f r0.x, r0.z, c0.y
3815 :3:0008:0008[63828009x_0001100fx] mad.f32 r2.y, c3.w, r1.y, r0.y
3816 :3:0009:0009[63818000x_00001005x] mad.f32 r0.x, c1.y, r0.w, r0.x
3817 :1:0010:0010[20244001x_00000010x] mov.f32f32 r0.y, c4.x
3818 :3:0011:0011[63820000x_00001009x] mad.f32 r0.x, c2.y, r1.x, r0.x
3819 :0:0012:0012[00000000x_00000000x] nop
3820 :3:0013:0013[63828007x_0000100dx] mad.f32 r1.w, c3.y, r1.y, r0.x
3821 :2:0014:0014[40700000x_10020002x] mul.f r0.x, r0.z, c0.z
3822 :1:0015:0015[20244002x_00000015x] mov.f32f32 r0.z, c5.y
3823 :3:0016:0016[63818000x_00001006x] mad.f32 r0.x, c1.z, r0.w, r0.x
3824 :1:0017:0017[20244003x_00000016x] mov.f32f32 r0.w, c5.z
3825 :3:0018:0018[63820000x_0000100ax] mad.f32 r0.x, c2.z, r1.x, r0.x
3826 :1:0019:0019[20244004x_00000017x] mov.f32f32 r1.x, c5.w
3827 :3:0020:0020[63828008x_0000100ex] mad.f32 r2.x, c3.z, r1.y, r0.x
3828 :1:0021:0021[20244000x_00000011x] mov.f32f32 r0.x, c4.y
3829 :2:0022:0022[40100002x_00021021x] add.f r0.z, c8.y, r0.z
3830 :2:0023:0023[4050040dx_00041017x] (sat)max.f r3.y, c5.w, r1.x
3831 :2:0024:0024[40100003x_00031022x] add.f r0.w, c8.z, r0.w
3832 :2:0025:0025[40700000x_00001011x] mul.f r0.x, c4.y, r0.x
3833 :0:0026:0026[00000000x_00000000x] nop
3834 :3:0027:0027[63808000x_00001010x] mad.f32 r0.x, c4.x, r0.y, r0.x
3835 :1:0028:0028[20244001x_00000012x] mov.f32f32 r0.y, c4.z
3836 :0:0029:0029[00000200x_00000000x] (rpt2)nop
3837 :3:0030:0032[63808000x_00001012x] mad.f32 r0.x, c4.z, r0.y, r0.x
3838 :1:0031:0033[20244001x_00000014x] mov.f32f32 r0.y, c5.x
3839 :0:0032:0034[00000200x_00000000x] (rpt2)nop
3840 :2:0033:0037[40100001x_00011020x] add.f r0.y, c8.x, r0.y
3841 :0:0034:0038[00000000x_00000000x] nop
3842 :4:0035:0039[80300000x_00000000x] rsq r0.x, r0.x
3843 :2:0036:0040[40701004x_00001011x] (ss)mul.f r1.x, c4.y, r0.x
3844 :0:0037:0041[00000200x_00000000x] (rpt2)nop
3845 :2:0038:0044[40700004x_10190004x] mul.f r1.x, r1.x, c6.y
3846 :2:0039:0045[40700005x_00001010x] mul.f r1.y, c4.x, r0.x
3847 :0:0040:0046[00000200x_00000000x] (rpt2)nop
3848 :3:0041:0049[63828004x_00041018x] mad.f32 r1.x, c6.x, r1.y, r1.x
3849 :2:0042:0050[40700000x_00001012x] mul.f r0.x, c4.z, r0.x
3850 :0:0043:0051[00000200x_00000000x] (rpt2)nop
3851 :3:0044:0054[63800000x_0004101ax] mad.f32 r0.x, c6.z, r0.x, r1.x
3852 :0:0045:0055[00000200x_00000000x] (rpt2)nop
3853 :2:0046:0058[40b00004x_00001034x] cmps.f.lt r1.x, c13.x, r0.x
3854 :2:0047:0059[40500000x_00001034x] max.f r0.x, c13.x, r0.x
3855 :0:0048:0060[00000100x_00000000x] (rpt1)nop
3856 :1:0049:0062[200c4004x_00000004x] cov.u32f32 r1.x, r1.x
3857 :3:0050:0063[63800001x_00011024x] mad.f32 r0.y, c9.x, r0.x, r0.y
3858 :3:0051:0064[63800002x_00021025x] mad.f32 r0.z, c9.y, r0.x, r0.z
3859 :3:0052:0065[63800000x_00031026x] mad.f32 r0.x, c9.z, r0.x, r0.w
3860 :3:0053:0066[6382040ax_00011028x] (sat)mad.f32 r2.z, c10.x, r1.x, r0.y
3861 :3:0054:0067[6382040bx_00021029x] (sat)mad.f32 r2.w, c10.y, r1.x, r0.z
3862 :3:0055:0068[6382040cx_0000102ax] (sat)mad.f32 r3.x, c10.z, r1.x, r0.x
3863 :0:0056:0069[03000000x_00000000x] end
3864 :0:0057:0070[00000000x_00000000x] nop
3865 :0:0058:0071[00000000x_00000000x] nop
3866 :0:0059:0072[00000000x_00000000x] nop
3867 :0:0060:0073[00000000x_00000000x] nop
3868 Register Stats:
3869 - used (half): (cnt=0, max=0)
3870 - used (full): 0-13 (cnt=14, max=13)
3871 - input (half): (cnt=0, max=0)
3872 - input (full): 2-5 (cnt=4, max=5)
3873 - max const: 52
3874
3875 - output (half): (cnt=0, max=0) (estimated)
3876 - output (full): 6-13 (cnt=8, max=13) (estimated)
3877 - shaderdb: 74 instructions, 38 nops, 36 non-nops, (61 instlen), 0 half, 4 full
3878 - shaderdb: 1 (ss), 0 (sy)
3879 109d0bec: 0000: c0813000 01200000 00000000 10000002 40700000 10030002 40700001 00001004
3880 109d0c0c: 0020: 63818000 00011007 63818001 00001008 63820000 0001100b 63820001 0000100c
3881 109d0c2c: 0040: 63828006 10010002 40700000 0001100f 63828009 00001005 63818000 00000010
3882 109d0c4c: 0060: 20244001 00001009 63820000 00000000 00000000 0000100d 63828007 10020002
3883 109d0c6c: 0080: 40700000 00000015 20244002 00001006 63818000 00000016 20244003 0000100a
3884 109d0c8c: 00a0: 63820000 00000017 20244004 0000100e 63828008 00000011 20244000 00021021
3885 109d0cac: 00c0: 40100002 00041017 4050040d 00031022 40100003 00001011 40700000 00000000
3886 109d0ccc: 00e0: 00000000 00001010 63808000 00000012 20244001 00000000 00000200 00001012
3887 109d0cec: 0100: 63808000 00000014 20244001 00000000 00000200 00011020 40100001 00000000
3888 109d0d0c: 0120: 00000000 00000000 80300000 00001011 40701004 00000000 00000200 10190004
3889 109d0d2c: 0140: 40700004 00001010 40700005 00000000 00000200 00041018 63828004 00001012
3890 109d0d4c: 0160: 40700000 00000000 00000200 0004101a 63800000 00000000 00000200 00001034
3891 109d0d6c: 0180: 40b00004 00001034 40500000 00000000 00000100 00000004 200c4004 00011024
3892 109d0d8c: 01a0: 63800001 00021025 63800002 00031026 63800000 00011028 6382040a 00021029
3893 109d0dac: 01c0: 6382040b 0000102a 6382040c 00000000 03000000 00000000 00000000 00000000
3894 *
3895 t3 opcode: CP_LOAD_STATE4 (30) (35 dwords)
3896 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 }
3897 { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 }
3898 :0:0000:0000[00000000x_00000000x] nop
3899 :6:0001:0001[c7c60000x_01c00000x] ldlv.u32 r0.x, l[0], 1
3900 :6:0002:0002[c7c60001x_01c00002x] ldlv.u32 r0.y, l[1], 1
3901 :6:0003:0003[c7c60002x_01c00004x] ldlv.u32 r0.z, l[2], 1
3902 :6:0004:0004[c7c60003x_01c00006x] ldlv.u32 r0.w, l[3], 1
3903 :2:0005:0005[473090fcx_00002000x] (ss)bary.f (ei)r63.x, 0, r0.x
3904 :0:0006:0006[03000000x_00000000x] end
3905 :0:0007:0007[00000000x_00000000x] nop
3906 :0:0008:0008[00000000x_00000000x] nop
3907 :0:0009:0009[00000000x_00000000x] nop
3908 :0:0010:0010[00000000x_00000000x] nop
3909 Register Stats:
3910 - used (half): (cnt=0, max=0)
3911 - used (full): 0-3 (cnt=4, max=3)
3912 - input (half): (cnt=0, max=0)
3913 - input (full): 0-3 (cnt=4, max=3)
3914 - max const: 0
3915
3916 - output (half): (cnt=0, max=0) (estimated)
3917 - output (full): (cnt=0, max=0) (estimated)
3918 - shaderdb: 11 instructions, 5 nops, 6 non-nops, (11 instlen), 0 half, 1 full
3919 - shaderdb: 1 (ss), 0 (sy)
3920 109d0df8: 0000: c0213000 00700000 00000000 00000000 00000000 01c00000 c7c60000 01c00002
3921 109d0e18: 0020: c7c60001 01c00004 c7c60002 01c00006 c7c60003 00002000 473090fc 00000000
3922 109d0e38: 0040: 03000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
3923 *
3924 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
3925 109d0e84: 0000: c0002600 00000000
3926 t3 opcode: CP_LOAD_STATE4 (30) (51 dwords)
3927 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 }
3928 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 }
3929 109d0e98: 3.924428 -1.210718 0.674073 0.570369 1.829991 4.619613 -0.131666 -0.111410
3930 109d0eb8: 2.500000 -1.480991 -0.961761 -0.813798 -13.423393 17.082890 32.944622 37.106991
3931 109d0ed8: 0.000000 0.000000 1.000000 1.000000 0.040000 0.040000 0.200000 1.000000
3932 109d0ef8: -0.244131 0.617574 0.747665 0.000000 1.000000 0.000000 0.000000 0.000000
3933 109d0f18: 0.000000 0.000000 0.000000 1.000000 0.200000 0.200000 1.000000 1.000000
3934 109d0f38: 0.000000 0.000000 0.000000 1.000000 0.000000 0.000000 0.000000 1.000000
3935 109d0e98: 0000: 407b29d2 bf9af8cb 3f2c9009 3f1203b9 3fea3d23 4093d3df be06d382 bde42adc
3936 109d0eb8: 0020: 40200000 bfbd9119 bf7635f5 bf50550b c156c638 4188a9c2 4203c74b 42146d8f
3937 109d0ed8: 0040: 00000000 00000000 3f800000 3f800000 3d23d70b 3d23d70b 3e4ccccd 3f800000
3938 109d0ef8: 0060: be79fd80 3f1e194f 3f3f66f5 00000000 3f800000 00000000 00000000 00000000
3939 109d0f18: 0080: 00000000 00000000 00000000 3f800000 3e4ccccd 3e4ccccd 3f800000 3f800000
3940 109d0f38: 00a0: 00000000 00000000 00000000 3f800000 00000000 00000000 00000000 3f800000
3941 109d0e8c: 0000: c0313000 03200000 00000001 407b29d2 bf9af8cb 3f2c9009 3f1203b9 3fea3d23
3942 109d0eac: 0020: 4093d3df be06d382 bde42adc 40200000 bfbd9119 bf7635f5 bf50550b c156c638
3943 109d0ecc: 0040: 4188a9c2 4203c74b 42146d8f 00000000 00000000 3f800000 3f800000 3d23d70b
3944 109d0eec: 0060: 3d23d70b 3e4ccccd 3f800000 be79fd80 3f1e194f 3f3f66f5 00000000 3f800000
3945 109d0f0c: 0080: 00000000 00000000 00000000 00000000 00000000 00000000 3f800000 3e4ccccd
3946 109d0f2c: 00a0: 3e4ccccd 3f800000 3f800000 00000000 00000000 00000000 3f800000 00000000
3947 109d0f4c: 00c0: 00000000 00000000 3f800000
3948 t3 opcode: CP_LOAD_STATE4 (30) (7 dwords)
3949 { DST_OFF = 13 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 }
3950 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 }
3951 109d0f64: 0.000000 -28026765312.000000 -28026765312.000000 -28026765312.000000
3952 109d0f64: 0000: 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0
3953 109d0f58: 0000: c0053000 0060000d 00000001 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0
3954 t0 write VFD_FETCH[0].INSTR_0 (220a)
3955 VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 12 }
3956 VFD_FETCH[0].INSTR_1: 0x107cb000
3957 VFD_FETCH[0].INSTR_2: { SIZE = 0x100000 }
3958 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 }
3959 109d0f74: 0000: 0003220a 0000060b 107cb000 00100000 00000001
3960 t0 write VFD_DECODE[0].INSTR (228a)
3961 VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID }
3962 109d0f88: 0000: 0000228a 2c0020df
3963 t0 write VFD_CONTROL_0 (2200)
3964 VFD_CONTROL_0: { TOTALATTRTOVS = 4 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 | 0xa0000 }
3965 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x }
3966 VFD_CONTROL_2: 0
3967 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x }
3968 VFD_CONTROL_4: 0
3969 109d0f90: 0000: 00042200 041a0004 fcfc0081 00000000 0000fc00 00000000
3970 t0 write UCHE_INVALIDATE0 (0e8a)
3971 UCHE_INVALIDATE0: 0
3972 UCHE_INVALIDATE1: 0x12
3973 109d0fa8: 0000: 00010e8a 00000000 00000012
3974 t0 write VFD_INDEX_OFFSET (2208)
3975 VFD_INDEX_OFFSET: 0
3976 UNKNOWN_2209: 0
3977 109d0fb4: 0000: 00012208 00000000 00000000
3978 t0 write PC_RESTART_INDEX (21c6)
3979 PC_RESTART_INDEX: 0xffffffff
3980 109d0fc0: 0000: 000021c6 ffffffff
3981 t0 write CP_SCRATCH[0x7].REG (057f)
3982 CP_SCRATCH[0x7].REG: 0x50
3983 :0,79,115,80
3984 109d0fc8: 0000: 0000057f 00000050
3985 t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
3986 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS }
3987 { NUM_INSTANCES = 1 }
3988 { NUM_INDICES = 120 }
3989 { FIRST_INDX = 0 }
3990 { INDX_BASE = 0x10bd0f78 }
3991 { INDX_SIZE = 240 }
3992 draw[13] register values
3993 !+ 0000004f CP_SCRATCH[0x5].REG: 0x4f
3994 :0,79,115,80
3995 !+ 00000050 CP_SCRATCH[0x7].REG: 0x50
3996 :0,79,115,80
3997 + 00000000 UCHE_INVALIDATE0: 0
3998 + 00000012 UCHE_INVALIDATE1: 0x12
3999 + 00080000 GRAS_CL_CLIP_CNTL: { 0x80000 }
4000 !+ 00000000 GRAS_CNTL: { 0 }
4001 + 00100010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 }
4002 + 00000010 GRAS_SU_POINT_SIZE: 1.000000
4003 + 00000000 GRAS_ALPHA_CONTROL: { 0 }
4004 + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000
4005 + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000
4006 + 00000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000
4007 + 00100012 GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 | RENDERING_PASS }
4008 + 012b012b GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 }
4009 + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
4010 !+ 00000000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 }
4011 + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 }
4012 + 80000016 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE }
4013 + 00000000 RB_VPORT_Z_CLAMP[0].MIN: 0
4014 + 00ffffff RB_VPORT_Z_CLAMP[0].MAX: 0xffffff
4015 + 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 }
4016 + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 }
4017 !+ 00000055 VPC_VARYING_INTERP[0].MODE: 0x55
4018 + 00000000 VPC_VARYING_INTERP[0x1].MODE: 0
4019 + 00000000 VPC_VARYING_INTERP[0x2].MODE: 0
4020 + 00000000 VPC_VARYING_INTERP[0x3].MODE: 0
4021 + 00000000 VPC_VARYING_INTERP[0x4].MODE: 0
4022 + 00000000 VPC_VARYING_INTERP[0x5].MODE: 0
4023 + 00000000 VPC_VARYING_INTERP[0x6].MODE: 0
4024 + 00000000 VPC_VARYING_INTERP[0x7].MODE: 0
4025 + 00000000 VPC_VARYING_PS_REPL[0].MODE: 0
4026 + 00000000 VPC_VARYING_PS_REPL[0x1].MODE: 0
4027 + 00000000 VPC_VARYING_PS_REPL[0x2].MODE: 0
4028 + 00000000 VPC_VARYING_PS_REPL[0x3].MODE: 0
4029 + 00000000 VPC_VARYING_PS_REPL[0x4].MODE: 0
4030 + 00000000 VPC_VARYING_PS_REPL[0x5].MODE: 0
4031 + 00000000 VPC_VARYING_PS_REPL[0x6].MODE: 0
4032 + 00000000 VPC_VARYING_PS_REPL[0x7].MODE: 0
4033 + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
4034 + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
4035 + ffffffff PC_RESTART_INDEX: 0xffffffff
4036 !+ 041a0004 VFD_CONTROL_0: { TOTALATTRTOVS = 4 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 | 0xa0000 }
4037 + fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x }
4038 + 00000000 VFD_CONTROL_2: 0
4039 + 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x }
4040 + 00000000 VFD_CONTROL_4: 0
4041 + 00000000 VFD_INDEX_OFFSET: 0
4042 + 00000000 UNKNOWN_2209: 0
4043 !+ 0000060b VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 12 }
4044 + 107cb000 VFD_FETCH[0].INSTR_1: 0x107cb000
4045 + 00100000 VFD_FETCH[0].INSTR_2: { SIZE = 0x100000 }
4046 + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 }
4047 !+ 2c0020df VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID }
4048 + 00140010 SP_SP_CTRL_REG: { 0x140010 }
4049 + 000005ff SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f }
4050 !+ 00201000 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 4 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE }
4051 !+ 04000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 4 }
4052 !+ 0010fc06 SP_VS_PARAM_REG: { POSREGID = r1.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 }
4053 !+ 00001e0a SP_VS_OUT[0].REG: { A_REGID = r2.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 }
4054 + 08080808 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 }
4055 + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 }
4056 !+ 10cd0000 SP_VS_OBJ_START: 0x10cd0000
4057 + 00000004 SP_VS_LENGTH_REG: 4
4058 !+ 00340402 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE }
4059 + 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 }
4060 + 7e420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
4061 !+ 10cd2000 SP_FS_OBJ_START: 0x10cd2000
4062 + 00000001 SP_FS_LENGTH_REG: 1
4063 + 0000fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x }
4064 !+ 0001a000 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM }
4065 !+ 00000000 SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 }
4066 !+ 00000000 SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 }
4067 !+ 00000000 SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 }
4068 !+ 00000000 SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 }
4069 !+ 00000000 SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 }
4070 !+ 00000000 SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 }
4071 !+ 00000000 SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 }
4072 + 7e420000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
4073 + 7e420000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
4074 + 7e420000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
4075 + 28000250 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE }
4076 + fcfc0100 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x }
4077 + fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x }
4078 !+ fcfcfcfc HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
4079 + 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 }
4080 + 04000042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 }
4081 + 017e423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 }
4082 + 007e4200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
4083 + 007e4200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
4084 + 007e4200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
4085 + 00000003 HLSQ_UPDATE_CONTROL: 0x3
4086 109d0fd0: 0000: c0053800 00000404 00000001 00000078 00000000 10bd0f78 000000f0
4087 t0 write CP_SCRATCH[0x7].REG (057f)
4088 CP_SCRATCH[0x7].REG: 0x51
4089 :0,79,115,81
4090 109d0fec: 0000: 0000057f 00000051
4091 t0 write CP_SCRATCH[0x5].REG (057d)
4092 CP_SCRATCH[0x5].REG: 0x55
4093 :0,85,115,81
4094 109d0ff4: 0000: 0000057d 00000055
4095 t0 write PC_PRIM_VTX_CNTL (21c4)
4096 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
4097 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
4098 109d0ffc: 0000: 000121c4 02000001 00000012
4099 t0 write VFD_INDEX_OFFSET (2208)
4100 VFD_INDEX_OFFSET: 0
4101 UNKNOWN_2209: 0
4102 109d1008: 0000: 00012208 00000000 00000000
4103 t0 write PC_RESTART_INDEX (21c6)
4104 PC_RESTART_INDEX: 0xffffffff
4105 109d1014: 0000: 000021c6 ffffffff
4106 t0 write CP_SCRATCH[0x7].REG (057f)
4107 CP_SCRATCH[0x7].REG: 0x56
4108 :0,85,115,86
4109 109d101c: 0000: 0000057f 00000056
4110 t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
4111 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS }
4112 { NUM_INSTANCES = 1 }
4113 { NUM_INDICES = 60 }
4114 { FIRST_INDX = 0 }
4115 { INDX_BASE = 0x10bd1068 }
4116 { INDX_SIZE = 120 }
4117 draw[14] register values
4118 !+ 00000055 CP_SCRATCH[0x5].REG: 0x55
4119 :0,85,115,86
4120 !+ 00000056 CP_SCRATCH[0x7].REG: 0x56
4121 :0,85,115,86
4122 + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
4123 + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
4124 + ffffffff PC_RESTART_INDEX: 0xffffffff
4125 + 00000000 VFD_INDEX_OFFSET: 0
4126 + 00000000 UNKNOWN_2209: 0
4127 109d1024: 0000: c0053800 00000404 00000001 0000003c 00000000 10bd1068 00000078
4128 t0 write CP_SCRATCH[0x7].REG (057f)
4129 CP_SCRATCH[0x7].REG: 0x57
4130 :0,85,115,87
4131 109d1040: 0000: 0000057f 00000057
4132 t0 write CP_SCRATCH[0x5].REG (057d)
4133 CP_SCRATCH[0x5].REG: 0x5b
4134 :0,91,115,87
4135 109d1048: 0000: 0000057d 0000005b
4136 t0 write PC_PRIM_VTX_CNTL (21c4)
4137 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
4138 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
4139 109d1050: 0000: 000121c4 02000001 00000012
4140 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
4141 109d105c: 0000: c0002600 00000000
4142 t3 opcode: CP_LOAD_STATE4 (30) (51 dwords)
4143 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 }
4144 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 }
4145 109d1070: 3.924428 -1.210718 0.674073 0.570369 1.829991 4.619613 -0.131666 -0.111410
4146 109d1090: 2.500000 -1.480991 -0.961761 -0.813798 -13.423393 17.082890 32.944622 37.106991
4147 109d10b0: 0.000000 0.000000 -1.000000 1.000000 0.040000 0.040000 0.200000 1.000000
4148 109d10d0: -0.244131 0.617574 0.747665 0.000000 1.000000 0.000000 0.000000 0.000000
4149 109d10f0: 0.000000 0.000000 0.000000 1.000000 0.200000 0.200000 1.000000 1.000000
4150 109d1110: 0.000000 0.000000 0.000000 1.000000 0.000000 0.000000 0.000000 1.000000
4151 109d1070: 0000: 407b29d2 bf9af8cb 3f2c9009 3f1203b9 3fea3d23 4093d3df be06d382 bde42adc
4152 109d1090: 0020: 40200000 bfbd9119 bf7635f5 bf50550b c156c638 4188a9c2 4203c74b 42146d8f
4153 109d10b0: 0040: 00000000 00000000 bf800000 3f800000 3d23d70b 3d23d70b 3e4ccccd 3f800000
4154 109d10d0: 0060: be79fd80 3f1e194f 3f3f66f5 00000000 3f800000 00000000 00000000 00000000
4155 109d10f0: 0080: 00000000 00000000 00000000 3f800000 3e4ccccd 3e4ccccd 3f800000 3f800000
4156 109d1110: 00a0: 00000000 00000000 00000000 3f800000 00000000 00000000 00000000 3f800000
4157 109d1064: 0000: c0313000 03200000 00000001 407b29d2 bf9af8cb 3f2c9009 3f1203b9 3fea3d23
4158 109d1084: 0020: 4093d3df be06d382 bde42adc 40200000 bfbd9119 bf7635f5 bf50550b c156c638
4159 109d10a4: 0040: 4188a9c2 4203c74b 42146d8f 00000000 00000000 bf800000 3f800000 3d23d70b
4160 109d10c4: 0060: 3d23d70b 3e4ccccd 3f800000 be79fd80 3f1e194f 3f3f66f5 00000000 3f800000
4161 109d10e4: 0080: 00000000 00000000 00000000 00000000 00000000 00000000 3f800000 3e4ccccd
4162 109d1104: 00a0: 3e4ccccd 3f800000 3f800000 00000000 00000000 00000000 3f800000 00000000
4163 109d1124: 00c0: 00000000 00000000 3f800000
4164 t0 write VFD_INDEX_OFFSET (2208)
4165 VFD_INDEX_OFFSET: 0
4166 UNKNOWN_2209: 0
4167 109d1130: 0000: 00012208 00000000 00000000
4168 t0 write PC_RESTART_INDEX (21c6)
4169 PC_RESTART_INDEX: 0xffffffff
4170 109d113c: 0000: 000021c6 ffffffff
4171 t0 write CP_SCRATCH[0x7].REG (057f)
4172 CP_SCRATCH[0x7].REG: 0x5c
4173 :0,91,115,92
4174 109d1144: 0000: 0000057f 0000005c
4175 t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
4176 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS }
4177 { NUM_INSTANCES = 1 }
4178 { NUM_INDICES = 120 }
4179 { FIRST_INDX = 0 }
4180 { INDX_BASE = 0x10bd10e0 }
4181 { INDX_SIZE = 240 }
4182 draw[15] register values
4183 !+ 0000005b CP_SCRATCH[0x5].REG: 0x5b
4184 :0,91,115,92
4185 !+ 0000005c CP_SCRATCH[0x7].REG: 0x5c
4186 :0,91,115,92
4187 + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
4188 + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
4189 + ffffffff PC_RESTART_INDEX: 0xffffffff
4190 + 00000000 VFD_INDEX_OFFSET: 0
4191 + 00000000 UNKNOWN_2209: 0
4192 109d114c: 0000: c0053800 00000404 00000001 00000078 00000000 10bd10e0 000000f0
4193 t0 write CP_SCRATCH[0x7].REG (057f)
4194 CP_SCRATCH[0x7].REG: 0x5d
4195 :0,91,115,93
4196 109d1168: 0000: 0000057f 0000005d
4197 t0 write CP_SCRATCH[0x5].REG (057d)
4198 CP_SCRATCH[0x5].REG: 0x61
4199 :0,97,115,93
4200 109d1170: 0000: 0000057d 00000061
4201 t0 write PC_PRIM_VTX_CNTL (21c4)
4202 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
4203 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
4204 109d1178: 0000: 000121c4 02000001 00000012
4205 t0 write VFD_INDEX_OFFSET (2208)
4206 VFD_INDEX_OFFSET: 0
4207 UNKNOWN_2209: 0
4208 109d1184: 0000: 00012208 00000000 00000000
4209 t0 write PC_RESTART_INDEX (21c6)
4210 PC_RESTART_INDEX: 0xffffffff
4211 109d1190: 0000: 000021c6 ffffffff
4212 t0 write CP_SCRATCH[0x7].REG (057f)
4213 CP_SCRATCH[0x7].REG: 0x62
4214 :0,97,115,98
4215 109d1198: 0000: 0000057f 00000062
4216 t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
4217 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS }
4218 { NUM_INSTANCES = 1 }
4219 { NUM_INDICES = 60 }
4220 { FIRST_INDX = 0 }
4221 { INDX_BASE = 0x10bd11d0 }
4222 { INDX_SIZE = 120 }
4223 draw[16] register values
4224 !+ 00000061 CP_SCRATCH[0x5].REG: 0x61
4225 :0,97,115,98
4226 !+ 00000062 CP_SCRATCH[0x7].REG: 0x62
4227 :0,97,115,98
4228 + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
4229 + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
4230 + ffffffff PC_RESTART_INDEX: 0xffffffff
4231 + 00000000 VFD_INDEX_OFFSET: 0
4232 + 00000000 UNKNOWN_2209: 0
4233 109d11a0: 0000: c0053800 00000404 00000001 0000003c 00000000 10bd11d0 00000078
4234 t0 write CP_SCRATCH[0x7].REG (057f)
4235 CP_SCRATCH[0x7].REG: 0x63
4236 :0,97,115,99
4237 109d11bc: 0000: 0000057f 00000063
4238 t0 write CP_SCRATCH[0x5].REG (057d)
4239 CP_SCRATCH[0x5].REG: 0x67
4240 :0,103,115,99
4241 109d11c4: 0000: 0000057d 00000067
4242 t0 write RB_DEPTH_CONTROL (2101)
4243 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE }
4244 109d11cc: 0000: 00002101 80000016
4245 t0 write GRAS_ALPHA_CONTROL (2073)
4246 GRAS_ALPHA_CONTROL: { 0 }
4247 109d11d4: 0000: 00002073 00000000
4248 t0 write PC_PRIM_VTX_CNTL (21c4)
4249 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
4250 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
4251 109d11dc: 0000: 000121c4 02000001 00000012
4252 t0 write HLSQ_UPDATE_CONTROL (23db)
4253 HLSQ_UPDATE_CONTROL: 0x3
4254 109d11e8: 0000: 000023db 00000003
4255 t0 write HLSQ_CONTROL_0_REG (23c0)
4256 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE }
4257 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x }
4258 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x }
4259 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
4260 HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 }
4261 109d11f0: 0000: 000423c0 28000250 fcfc0100 fff3f3f0 fcfcfcfc 00fcfcfc
4262 t0 write HLSQ_VS_CONTROL_REG (23c5)
4263 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 }
4264 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 }
4265 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
4266 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
4267 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
4268 109d1208: 0000: 000423c5 04000042 017e423e 007e4200 007e4200 007e4200
4269 t0 write SP_SP_CTRL_REG (22c0)
4270 SP_SP_CTRL_REG: { 0x140010 }
4271 109d1220: 0000: 000022c0 00140010
4272 t0 write SP_INSTR_CACHE_CTRL (22c1)
4273 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f }
4274 109d1228: 0000: 000022c1 000005ff
4275 t0 write SP_VS_LENGTH_REG (22e5)
4276 SP_VS_LENGTH_REG: 4
4277 109d1230: 0000: 000022e5 00000004
4278 t0 write SP_VS_CTRL_REG0 (22c4)
4279 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE }
4280 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 8 }
4281 SP_VS_PARAM_REG: { POSREGID = r2.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 }
4282 109d1238: 0000: 000222c4 00201400 08000042 0010fc0a
4283 t0 write SP_VS_OUT[0].REG (22c7)
4284 SP_VS_OUT[0].REG: { A_REGID = r3.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 }
4285 109d1248: 0000: 000022c7 00001e0e
4286 t0 write SP_VS_VPC_DST[0].REG (22d8)
4287 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 }
4288 109d1250: 0000: 000022d8 08080808
4289 t0 write SP_VS_OBJ_OFFSET_REG (22e0)
4290 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 }
4291 SP_VS_OBJ_START: 0x10cd5000
4292 109d1258: 0000: 000122e0 00000000 10cd5000
4293 t0 write SP_FS_LENGTH_REG (22ef)
4294 SP_FS_LENGTH_REG: 1
4295 109d1264: 0000: 000022ef 00000001
4296 t0 write SP_FS_CTRL_REG0 (22e8)
4297 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE }
4298 SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 }
4299 109d126c: 0000: 000122e8 00340402 8010003e
4300 t0 write SP_FS_OBJ_OFFSET_REG (22ea)
4301 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
4302 SP_FS_OBJ_START: 0x10cd2000
4303 109d1278: 0000: 000122ea 7e420000 10cd2000
4304 t0 write SP_HS_OBJ_OFFSET_REG (230d)
4305 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
4306 109d1284: 0000: 0000230d 7e420000
4307 t0 write SP_DS_OBJ_OFFSET_REG (2334)
4308 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
4309 109d128c: 0000: 00002334 7e420000
4310 t0 write SP_GS_OBJ_OFFSET_REG (235b)
4311 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
4312 109d1294: 0000: 0000235b 7e420000
4313 t0 write GRAS_CNTL (2003)
4314 GRAS_CNTL: { 0 }
4315 109d129c: 0000: 00002003 00000000
4316 t0 write RB_RENDER_CONTROL2 (20a3)
4317 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 }
4318 109d12a4: 0000: 000020a3 00000000
4319 t0 write RB_FS_OUTPUT_REG (2100)
4320 RB_FS_OUTPUT_REG: { MRT = 1 }
4321 109d12ac: 0000: 00002100 00000001
4322 t0 write SP_FS_OUTPUT_REG (22f0)
4323 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x }
4324 109d12b4: 0000: 000022f0 0000fc01
4325 t0 write SP_FS_MRT[0].REG (22f1)
4326 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM }
4327 SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 }
4328 SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 }
4329 SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 }
4330 SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 }
4331 SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 }
4332 SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 }
4333 SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 }
4334 109d12bc: 0000: 000722f1 0001a000 00000000 00000000 00000000 00000000 00000000 00000000
4335 *
4336 t0 write VPC_ATTR (2140)
4337 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 }
4338 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 }
4339 109d12e0: 0000: 00012140 42001004 00040400
4340 t0 write VPC_VARYING_INTERP[0].MODE (2142)
4341 VPC_VARYING_INTERP[0].MODE: 0x55
4342 VPC_VARYING_INTERP[0x1].MODE: 0
4343 VPC_VARYING_INTERP[0x2].MODE: 0
4344 VPC_VARYING_INTERP[0x3].MODE: 0
4345 VPC_VARYING_INTERP[0x4].MODE: 0
4346 VPC_VARYING_INTERP[0x5].MODE: 0
4347 VPC_VARYING_INTERP[0x6].MODE: 0
4348 VPC_VARYING_INTERP[0x7].MODE: 0
4349 109d12ec: 0000: 00072142 00000055 00000000 00000000 00000000 00000000 00000000 00000000
4350 *
4351 t0 write VPC_VARYING_PS_REPL[0].MODE (214a)
4352 VPC_VARYING_PS_REPL[0].MODE: 0
4353 VPC_VARYING_PS_REPL[0x1].MODE: 0
4354 VPC_VARYING_PS_REPL[0x2].MODE: 0
4355 VPC_VARYING_PS_REPL[0x3].MODE: 0
4356 VPC_VARYING_PS_REPL[0x4].MODE: 0
4357 VPC_VARYING_PS_REPL[0x5].MODE: 0
4358 VPC_VARYING_PS_REPL[0x6].MODE: 0
4359 VPC_VARYING_PS_REPL[0x7].MODE: 0
4360 109d1310: 0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000
4361 *
4362 t3 opcode: CP_LOAD_STATE4 (30) (131 dwords)
4363 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 }
4364 { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 }
4365 :2:0000:0000[40700000x_10000002x] mul.f r0.x, r0.z, c0.x
4366 :2:0001:0001[40700001x_10030002x] mul.f r0.y, r0.z, c0.w
4367 :3:0002:0002[63818000x_00001004x] mad.f32 r0.x, c1.x, r0.w, r0.x
4368 :3:0003:0003[63818001x_00011007x] mad.f32 r0.y, c1.w, r0.w, r0.y
4369 :3:0004:0004[63820000x_00001008x] mad.f32 r0.x, c2.x, r1.x, r0.x
4370 :3:0005:0005[63820001x_0001100bx] mad.f32 r0.y, c2.w, r1.x, r0.y
4371 :3:0006:0006[6382800ax_0000100cx] mad.f32 r2.z, c3.x, r1.y, r0.x
4372 :2:0007:0007[40700000x_10010002x] mul.f r0.x, r0.z, c0.y
4373 :3:0008:0008[6382800dx_0001100fx] mad.f32 r3.y, c3.w, r1.y, r0.y
4374 :3:0009:0009[63818000x_00001005x] mad.f32 r0.x, c1.y, r0.w, r0.x
4375 :1:0010:0010[20244001x_00000010x] mov.f32f32 r0.y, c4.x
4376 :3:0011:0011[63820000x_00001009x] mad.f32 r0.x, c2.y, r1.x, r0.x
4377 :0:0012:0012[00000000x_00000000x] nop
4378 :3:0013:0013[6382800bx_0000100dx] mad.f32 r2.w, c3.y, r1.y, r0.x
4379 :2:0014:0014[40700000x_10020002x] mul.f r0.x, r0.z, c0.z
4380 :2:0015:0015[40100001x_0001101cx] add.f r0.y, c7.x, r0.y
4381 :3:0016:0016[63818000x_00001006x] mad.f32 r0.x, c1.z, r0.w, r0.x
4382 :1:0017:0017[20244002x_00000011x] mov.f32f32 r0.z, c4.y
4383 :3:0018:0018[63820000x_0000100ax] mad.f32 r0.x, c2.z, r1.x, r0.x
4384 :1:0019:0019[20244004x_00000013x] mov.f32f32 r1.x, c4.w
4385 :3:0020:0020[6382800cx_0000100ex] mad.f32 r3.x, c3.z, r1.y, r0.x
4386 :2:0021:0021[40700000x_00070007x] mul.f r0.x, r1.w, r1.w
4387 :2:0022:0022[40100002x_0002101dx] add.f r0.z, c7.y, r0.z
4388 :3:0023:0023[63830000x_00000006x] mad.f32 r0.x, r1.z, r1.z, r0.x
4389 :2:0024:0024[40500411x_00041013x] (sat)max.f r4.y, c4.w, r1.x
4390 :3:0025:0025[63840000x_00000008x] mad.f32 r0.x, r2.x, r2.x, r0.x
4391 :1:0026:0026[20244003x_00000012x] mov.f32f32 r0.w, c4.z
4392 :0:0027:0027[00000200x_00000000x] (rpt2)nop
4393 :2:0028:0030[40100003x_0003101ex] add.f r0.w, c7.z, r0.w
4394 :0:0029:0031[00000000x_00000000x] nop
4395 :4:0030:0032[80300000x_00000000x] rsq r0.x, r0.x
4396 :2:0031:0033[40701004x_00000007x] (ss)mul.f r1.x, r1.w, r0.x
4397 :0:0032:0034[00000200x_00000000x] (rpt2)nop
4398 :2:0033:0037[40700004x_10150004x] mul.f r1.x, r1.x, c5.y
4399 :2:0034:0038[40700005x_00000006x] mul.f r1.y, r1.z, r0.x
4400 :0:0035:0039[00000200x_00000000x] (rpt2)nop
4401 :3:0036:0042[63828004x_00041014x] mad.f32 r1.x, c5.x, r1.y, r1.x
4402 :2:0037:0043[40700000x_00000008x] mul.f r0.x, r2.x, r0.x
4403 :0:0038:0044[00000200x_00000000x] (rpt2)nop
4404 :3:0039:0047[63800000x_00041016x] mad.f32 r0.x, c5.z, r0.x, r1.x
4405 :0:0040:0048[00000200x_00000000x] (rpt2)nop
4406 :2:0041:0051[40b00004x_00001034x] cmps.f.lt r1.x, c13.x, r0.x
4407 :2:0042:0052[40500000x_00001034x] max.f r0.x, c13.x, r0.x
4408 :0:0043:0053[00000100x_00000000x] (rpt1)nop
4409 :1:0044:0055[200c4004x_00000004x] cov.u32f32 r1.x, r1.x
4410 :3:0045:0056[63800001x_00011020x] mad.f32 r0.y, c8.x, r0.x, r0.y
4411 :3:0046:0057[63800002x_00021021x] mad.f32 r0.z, c8.y, r0.x, r0.z
4412 :3:0047:0058[63800000x_00031022x] mad.f32 r0.x, c8.z, r0.x, r0.w
4413 :3:0048:0059[6382040ex_00011024x] (sat)mad.f32 r3.z, c9.x, r1.x, r0.y
4414 :3:0049:0060[6382040fx_00021025x] (sat)mad.f32 r3.w, c9.y, r1.x, r0.z
4415 :3:0050:0061[63820410x_00001026x] (sat)mad.f32 r4.x, c9.z, r1.x, r0.x
4416 :0:0051:0062[03000000x_00000000x] end
4417 :0:0052:0063[00000000x_00000000x] nop
4418 :0:0053:0064[00000000x_00000000x] nop
4419 :0:0054:0065[00000000x_00000000x] nop
4420 :0:0055:0066[00000000x_00000000x] nop
4421 Register Stats:
4422 - used (half): (cnt=0, max=0)
4423 - used (full): 0-8 10-17 (cnt=17, max=17)
4424 - input (half): (cnt=0, max=0)
4425 - input (full): 2-8 (cnt=7, max=8)
4426 - max const: 52
4427
4428 - output (half): (cnt=0, max=0) (estimated)
4429 - output (full): 10-17 (cnt=8, max=17) (estimated)
4430 - shaderdb: 67 instructions, 31 nops, 36 non-nops, (56 instlen), 0 half, 5 full
4431 - shaderdb: 1 (ss), 0 (sy)
4432 109d1334: 0000: c0813000 01200000 00000000 10000002 40700000 10030002 40700001 00001004
4433 109d1354: 0020: 63818000 00011007 63818001 00001008 63820000 0001100b 63820001 0000100c
4434 109d1374: 0040: 6382800a 10010002 40700000 0001100f 6382800d 00001005 63818000 00000010
4435 109d1394: 0060: 20244001 00001009 63820000 00000000 00000000 0000100d 6382800b 10020002
4436 109d13b4: 0080: 40700000 0001101c 40100001 00001006 63818000 00000011 20244002 0000100a
4437 109d13d4: 00a0: 63820000 00000013 20244004 0000100e 6382800c 00070007 40700000 0002101d
4438 109d13f4: 00c0: 40100002 00000006 63830000 00041013 40500411 00000008 63840000 00000012
4439 109d1414: 00e0: 20244003 00000000 00000200 0003101e 40100003 00000000 00000000 00000000
4440 109d1434: 0100: 80300000 00000007 40701004 00000000 00000200 10150004 40700004 00000006
4441 109d1454: 0120: 40700005 00000000 00000200 00041014 63828004 00000008 40700000 00000000
4442 109d1474: 0140: 00000200 00041016 63800000 00000000 00000200 00001034 40b00004 00001034
4443 109d1494: 0160: 40500000 00000000 00000100 00000004 200c4004 00011020 63800001 00021021
4444 109d14b4: 0180: 63800002 00031022 63800000 00011024 6382040e 00021025 6382040f 00001026
4445 109d14d4: 01a0: 63820410 00000000 03000000 00000000 00000000 00000000 00000000 00000000
4446 *
4447 t3 opcode: CP_LOAD_STATE4 (30) (35 dwords)
4448 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 }
4449 { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 }
4450 :0:0000:0000[00000000x_00000000x] nop
4451 :6:0001:0001[c7c60000x_01c00000x] ldlv.u32 r0.x, l[0], 1
4452 :6:0002:0002[c7c60001x_01c00002x] ldlv.u32 r0.y, l[1], 1
4453 :6:0003:0003[c7c60002x_01c00004x] ldlv.u32 r0.z, l[2], 1
4454 :6:0004:0004[c7c60003x_01c00006x] ldlv.u32 r0.w, l[3], 1
4455 :2:0005:0005[473090fcx_00002000x] (ss)bary.f (ei)r63.x, 0, r0.x
4456 :0:0006:0006[03000000x_00000000x] end
4457 :0:0007:0007[00000000x_00000000x] nop
4458 :0:0008:0008[00000000x_00000000x] nop
4459 :0:0009:0009[00000000x_00000000x] nop
4460 :0:0010:0010[00000000x_00000000x] nop
4461 Register Stats:
4462 - used (half): (cnt=0, max=0)
4463 - used (full): 0-3 (cnt=4, max=3)
4464 - input (half): (cnt=0, max=0)
4465 - input (full): 0-3 (cnt=4, max=3)
4466 - max const: 0
4467
4468 - output (half): (cnt=0, max=0) (estimated)
4469 - output (full): (cnt=0, max=0) (estimated)
4470 - shaderdb: 11 instructions, 5 nops, 6 non-nops, (11 instlen), 0 half, 1 full
4471 - shaderdb: 1 (ss), 0 (sy)
4472 109d1540: 0000: c0213000 00700000 00000000 00000000 00000000 01c00000 c7c60000 01c00002
4473 109d1560: 0020: c7c60001 01c00004 c7c60002 01c00006 c7c60003 00002000 473090fc 00000000
4474 109d1580: 0040: 03000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
4475 *
4476 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
4477 109d15cc: 0000: c0002600 00000000
4478 t3 opcode: CP_LOAD_STATE4 (30) (51 dwords)
4479 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 }
4480 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 }
4481 109d15e0: 3.924428 -1.210718 0.674073 0.570369 1.829991 4.619613 -0.131666 -0.111410
4482 109d1600: 2.500000 -1.480991 -0.961761 -0.813798 -13.423393 17.082890 32.944622 37.106991
4483 109d1620: 0.040000 0.040000 0.200000 1.000000 -0.244131 0.617574 0.747665 0.000000
4484 109d1640: 1.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 1.000000
4485 109d1660: 0.200000 0.200000 1.000000 1.000000 0.000000 0.000000 0.000000 1.000000
4486 109d1680: 0.000000 0.000000 0.000000 1.000000 0.000000 0.000000 0.000000 0.000000
4487 109d15e0: 0000: 407b29d2 bf9af8cb 3f2c9009 3f1203b9 3fea3d23 4093d3df be06d382 bde42adc
4488 109d1600: 0020: 40200000 bfbd9119 bf7635f5 bf50550b c156c638 4188a9c2 4203c74b 42146d8f
4489 109d1620: 0040: 3d23d70b 3d23d70b 3e4ccccd 3f800000 be79fd80 3f1e194f 3f3f66f5 00000000
4490 109d1640: 0060: 3f800000 00000000 00000000 00000000 00000000 00000000 00000000 3f800000
4491 109d1660: 0080: 3e4ccccd 3e4ccccd 3f800000 3f800000 00000000 00000000 00000000 3f800000
4492 109d1680: 00a0: 00000000 00000000 00000000 3f800000 02020000 02020202 02020202 00000202
4493 109d15d4: 0000: c0313000 03200000 00000001 407b29d2 bf9af8cb 3f2c9009 3f1203b9 3fea3d23
4494 109d15f4: 0020: 4093d3df be06d382 bde42adc 40200000 bfbd9119 bf7635f5 bf50550b c156c638
4495 109d1614: 0040: 4188a9c2 4203c74b 42146d8f 3d23d70b 3d23d70b 3e4ccccd 3f800000 be79fd80
4496 109d1634: 0060: 3f1e194f 3f3f66f5 00000000 3f800000 00000000 00000000 00000000 00000000
4497 109d1654: 0080: 00000000 00000000 3f800000 3e4ccccd 3e4ccccd 3f800000 3f800000 00000000
4498 109d1674: 00a0: 00000000 00000000 3f800000 00000000 00000000 00000000 3f800000 02020000
4499 109d1694: 00c0: 02020202 02020202 00000202
4500 t3 opcode: CP_LOAD_STATE4 (30) (7 dwords)
4501 { DST_OFF = 13 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 }
4502 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 }
4503 109d16ac: 0.000000 -28026765312.000000 -28026765312.000000 -28026765312.000000
4504 109d16ac: 0000: 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0
4505 109d16a0: 0000: c0053000 0060000d 00000001 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0
4506 t0 write VFD_FETCH[0].INSTR_0 (220a)
4507 VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 | SWITCHNEXT }
4508 VFD_FETCH[0].INSTR_1: 0x107cb000
4509 VFD_FETCH[0].INSTR_2: { SIZE = 0x100000 }
4510 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 }
4511 109d16bc: 0000: 0003220a 00080c0b 107cb000 00100000 00000001
4512 t0 write VFD_DECODE[0].INSTR (228a)
4513 VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID | SWITCHNEXT }
4514 109d16d0: 0000: 0000228a 6c0020df
4515 t0 write VFD_FETCH[0x1].INSTR_0 (220e)
4516 VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 }
4517 VFD_FETCH[0x1].INSTR_1: 0x107cb00c
4518 VFD_FETCH[0x1].INSTR_2: { SIZE = 0xffff4 }
4519 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 }
4520 109d16d8: 0000: 0003220e 00000c0b 107cb00c 000ffff4 00000001
4521 t0 write VFD_DECODE[0x1].INSTR (228b)
4522 VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r1.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID }
4523 109d16ec: 0000: 0000228b 2c0060df
4524 t0 write VFD_CONTROL_0 (2200)
4525 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 }
4526 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x }
4527 VFD_CONTROL_2: 0
4528 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x }
4529 VFD_CONTROL_4: 0
4530 109d16f4: 0000: 00042200 082a0008 fcfc0081 00000000 0000fc00 00000000
4531 t0 write UCHE_INVALIDATE0 (0e8a)
4532 UCHE_INVALIDATE0: 0
4533 UCHE_INVALIDATE1: 0x12
4534 109d170c: 0000: 00010e8a 00000000 00000012
4535 t0 write VFD_INDEX_OFFSET (2208)
4536 VFD_INDEX_OFFSET: 0
4537 UNKNOWN_2209: 0
4538 109d1718: 0000: 00012208 00000000 00000000
4539 t0 write PC_RESTART_INDEX (21c6)
4540 PC_RESTART_INDEX: 0xffffffff
4541 109d1724: 0000: 000021c6 ffffffff
4542 t0 write CP_SCRATCH[0x7].REG (057f)
4543 CP_SCRATCH[0x7].REG: 0x68
4544 :0,103,115,104
4545 109d172c: 0000: 0000057f 00000068
4546 t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
4547 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS }
4548 { NUM_INSTANCES = 1 }
4549 { NUM_INDICES = 240 }
4550 { FIRST_INDX = 0 }
4551 { INDX_BASE = 0x10bd1248 }
4552 { INDX_SIZE = 480 }
4553 draw[17] register values
4554 !+ 00000067 CP_SCRATCH[0x5].REG: 0x67
4555 :0,103,115,104
4556 !+ 00000068 CP_SCRATCH[0x7].REG: 0x68
4557 :0,103,115,104
4558 + 00000000 UCHE_INVALIDATE0: 0
4559 + 00000012 UCHE_INVALIDATE1: 0x12
4560 + 00000000 GRAS_CNTL: { 0 }
4561 + 00000000 GRAS_ALPHA_CONTROL: { 0 }
4562 + 00000000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 }
4563 + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 }
4564 + 80000016 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE }
4565 + 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 }
4566 + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 }
4567 + 00000055 VPC_VARYING_INTERP[0].MODE: 0x55
4568 + 00000000 VPC_VARYING_INTERP[0x1].MODE: 0
4569 + 00000000 VPC_VARYING_INTERP[0x2].MODE: 0
4570 + 00000000 VPC_VARYING_INTERP[0x3].MODE: 0
4571 + 00000000 VPC_VARYING_INTERP[0x4].MODE: 0
4572 + 00000000 VPC_VARYING_INTERP[0x5].MODE: 0
4573 + 00000000 VPC_VARYING_INTERP[0x6].MODE: 0
4574 + 00000000 VPC_VARYING_INTERP[0x7].MODE: 0
4575 + 00000000 VPC_VARYING_PS_REPL[0].MODE: 0
4576 + 00000000 VPC_VARYING_PS_REPL[0x1].MODE: 0
4577 + 00000000 VPC_VARYING_PS_REPL[0x2].MODE: 0
4578 + 00000000 VPC_VARYING_PS_REPL[0x3].MODE: 0
4579 + 00000000 VPC_VARYING_PS_REPL[0x4].MODE: 0
4580 + 00000000 VPC_VARYING_PS_REPL[0x5].MODE: 0
4581 + 00000000 VPC_VARYING_PS_REPL[0x6].MODE: 0
4582 + 00000000 VPC_VARYING_PS_REPL[0x7].MODE: 0
4583 + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
4584 + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
4585 + ffffffff PC_RESTART_INDEX: 0xffffffff
4586 !+ 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 }
4587 + fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x }
4588 + 00000000 VFD_CONTROL_2: 0
4589 + 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x }
4590 + 00000000 VFD_CONTROL_4: 0
4591 + 00000000 VFD_INDEX_OFFSET: 0
4592 + 00000000 UNKNOWN_2209: 0
4593 !+ 00080c0b VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 | SWITCHNEXT }
4594 + 107cb000 VFD_FETCH[0].INSTR_1: 0x107cb000
4595 + 00100000 VFD_FETCH[0].INSTR_2: { SIZE = 0x100000 }
4596 + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 }
4597 + 00000c0b VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 }
4598 + 107cb00c VFD_FETCH[0x1].INSTR_1: 0x107cb00c
4599 + 000ffff4 VFD_FETCH[0x1].INSTR_2: { SIZE = 0xffff4 }
4600 + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 }
4601 !+ 6c0020df VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID | SWITCHNEXT }
4602 + 2c0060df VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r1.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID }
4603 + 00140010 SP_SP_CTRL_REG: { 0x140010 }
4604 + 000005ff SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f }
4605 !+ 00201400 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE }
4606 !+ 08000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 8 }
4607 !+ 0010fc0a SP_VS_PARAM_REG: { POSREGID = r2.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 }
4608 !+ 00001e0e SP_VS_OUT[0].REG: { A_REGID = r3.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 }
4609 + 08080808 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 }
4610 + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 }
4611 !+ 10cd5000 SP_VS_OBJ_START: 0x10cd5000
4612 + 00000004 SP_VS_LENGTH_REG: 4
4613 + 00340402 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE }
4614 + 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 }
4615 + 7e420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
4616 + 10cd2000 SP_FS_OBJ_START: 0x10cd2000
4617 + 00000001 SP_FS_LENGTH_REG: 1
4618 + 0000fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x }
4619 + 0001a000 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM }
4620 + 00000000 SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 }
4621 + 00000000 SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 }
4622 + 00000000 SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 }
4623 + 00000000 SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 }
4624 + 00000000 SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 }
4625 + 00000000 SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 }
4626 + 00000000 SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 }
4627 + 7e420000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
4628 + 7e420000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
4629 + 7e420000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
4630 + 28000250 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE }
4631 + fcfc0100 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x }
4632 + fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x }
4633 + fcfcfcfc HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
4634 + 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 }
4635 + 04000042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 }
4636 + 017e423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 }
4637 + 007e4200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
4638 + 007e4200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
4639 + 007e4200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
4640 + 00000003 HLSQ_UPDATE_CONTROL: 0x3
4641 109d1734: 0000: c0053800 00000404 00000001 000000f0 00000000 10bd1248 000001e0
4642 t0 write CP_SCRATCH[0x7].REG (057f)
4643 CP_SCRATCH[0x7].REG: 0x69
4644 :0,103,115,105
4645 109d1750: 0000: 0000057f 00000069
4646 t0 write CP_SCRATCH[0x5].REG (057d)
4647 CP_SCRATCH[0x5].REG: 0x6d
4648 :0,109,115,105
4649 109d1758: 0000: 0000057d 0000006d
4650 t0 write RB_DEPTH_CONTROL (2101)
4651 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE }
4652 109d1760: 0000: 00002101 80000016
4653 t0 write GRAS_ALPHA_CONTROL (2073)
4654 GRAS_ALPHA_CONTROL: { 0 }
4655 109d1768: 0000: 00002073 00000000
4656 t0 write GRAS_SU_MODE_CONTROL (2078)
4657 GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 | RENDERING_PASS }
4658 109d1770: 0000: 00002078 00100012
4659 t0 write GRAS_SU_POINT_MINMAX (2070)
4660 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 }
4661 GRAS_SU_POINT_SIZE: 1.000000
4662 109d1778: 0000: 00012070 00100010 00000010
4663 t0 write GRAS_SU_POLY_OFFSET_SCALE (2074)
4664 GRAS_SU_POLY_OFFSET_SCALE: 0.000000
4665 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000
4666 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000
4667 109d1784: 0000: 00022074 00000000 00000000 00000000
4668 t0 write GRAS_CL_CLIP_CNTL (2000)
4669 GRAS_CL_CLIP_CNTL: { 0x80000 }
4670 109d1794: 0000: 00002000 00080000
4671 t0 write PC_PRIM_VTX_CNTL (21c4)
4672 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
4673 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
4674 109d179c: 0000: 000121c4 02000001 00000012
4675 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c)
4676 GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 }
4677 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
4678 109d17a8: 0000: 0001209c 012b012b 00000000
4679 t0 write RB_VPORT_Z_CLAMP[0].MIN (2120)
4680 RB_VPORT_Z_CLAMP[0].MIN: 0
4681 RB_VPORT_Z_CLAMP[0].MAX: 0xffffff
4682 109d17b4: 0000: 00012120 00000000 00ffffff
4683 t0 write HLSQ_UPDATE_CONTROL (23db)
4684 HLSQ_UPDATE_CONTROL: 0x3
4685 109d17c0: 0000: 000023db 00000003
4686 t0 write HLSQ_CONTROL_0_REG (23c0)
4687 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE }
4688 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x }
4689 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x }
4690 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
4691 HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 }
4692 109d17c8: 0000: 000423c0 28000250 fcfc0100 fff3f3f0 fcfcfc00 00fcfcfc
4693 t0 write HLSQ_VS_CONTROL_REG (23c5)
4694 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 }
4695 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 }
4696 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
4697 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
4698 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
4699 109d17e0: 0000: 000423c5 04000042 017e423e 007e4200 007e4200 007e4200
4700 t0 write SP_SP_CTRL_REG (22c0)
4701 SP_SP_CTRL_REG: { 0x140010 }
4702 109d17f8: 0000: 000022c0 00140010
4703 t0 write SP_INSTR_CACHE_CTRL (22c1)
4704 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f }
4705 109d1800: 0000: 000022c1 000005ff
4706 t0 write SP_VS_LENGTH_REG (22e5)
4707 SP_VS_LENGTH_REG: 4
4708 109d1808: 0000: 000022e5 00000004
4709 t0 write SP_VS_CTRL_REG0 (22c4)
4710 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE }
4711 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 8 }
4712 SP_VS_PARAM_REG: { POSREGID = r2.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 }
4713 109d1810: 0000: 000222c4 00201400 08000042 0010fc0a
4714 t0 write SP_VS_OUT[0].REG (22c7)
4715 SP_VS_OUT[0].REG: { A_REGID = r3.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 }
4716 109d1820: 0000: 000022c7 00001e0e
4717 t0 write SP_VS_VPC_DST[0].REG (22d8)
4718 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 }
4719 109d1828: 0000: 000022d8 08080808
4720 t0 write SP_VS_OBJ_OFFSET_REG (22e0)
4721 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 }
4722 SP_VS_OBJ_START: 0x10cd5000
4723 109d1830: 0000: 000122e0 00000000 10cd5000
4724 t0 write SP_FS_LENGTH_REG (22ef)
4725 SP_FS_LENGTH_REG: 1
4726 109d183c: 0000: 000022ef 00000001
4727 t0 write SP_FS_CTRL_REG0 (22e8)
4728 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE }
4729 SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 }
4730 109d1844: 0000: 000122e8 00340802 8010003e
4731 t0 write SP_FS_OBJ_OFFSET_REG (22ea)
4732 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
4733 SP_FS_OBJ_START: 0x108cb000
4734 109d1850: 0000: 000122ea 7e420000 108cb000
4735 t0 write SP_HS_OBJ_OFFSET_REG (230d)
4736 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
4737 109d185c: 0000: 0000230d 7e420000
4738 t0 write SP_DS_OBJ_OFFSET_REG (2334)
4739 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
4740 109d1864: 0000: 00002334 7e420000
4741 t0 write SP_GS_OBJ_OFFSET_REG (235b)
4742 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
4743 109d186c: 0000: 0000235b 7e420000
4744 t0 write GRAS_CNTL (2003)
4745 GRAS_CNTL: { IJ_PERSP }
4746 109d1874: 0000: 00002003 00000001
4747 t0 write RB_RENDER_CONTROL2 (20a3)
4748 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL }
4749 109d187c: 0000: 000020a3 00001000
4750 t0 write RB_FS_OUTPUT_REG (2100)
4751 RB_FS_OUTPUT_REG: { MRT = 1 }
4752 109d1884: 0000: 00002100 00000001
4753 t0 write SP_FS_OUTPUT_REG (22f0)
4754 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x }
4755 109d188c: 0000: 000022f0 0000fc01
4756 t0 write SP_FS_MRT[0].REG (22f1)
4757 SP_FS_MRT[0].REG: { REGID = r0.z | MRTFORMAT = RB4_R8G8B8A8_UNORM }
4758 SP_FS_MRT[0x1].REG: { REGID = r0.z | MRTFORMAT = 0 }
4759 SP_FS_MRT[0x2].REG: { REGID = r0.z | MRTFORMAT = 0 }
4760 SP_FS_MRT[0x3].REG: { REGID = r0.z | MRTFORMAT = 0 }
4761 SP_FS_MRT[0x4].REG: { REGID = r0.z | MRTFORMAT = 0 }
4762 SP_FS_MRT[0x5].REG: { REGID = r0.z | MRTFORMAT = 0 }
4763 SP_FS_MRT[0x6].REG: { REGID = r0.z | MRTFORMAT = 0 }
4764 SP_FS_MRT[0x7].REG: { REGID = r0.z | MRTFORMAT = 0 }
4765 109d1894: 0000: 000722f1 0001a002 00000002 00000002 00000002 00000002 00000002 00000002
4766 109d18b4: 0020: 00000002
4767 t0 write VPC_ATTR (2140)
4768 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 }
4769 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 }
4770 109d18b8: 0000: 00012140 42001004 00040400
4771 t0 write VPC_VARYING_INTERP[0].MODE (2142)
4772 VPC_VARYING_INTERP[0].MODE: 0
4773 VPC_VARYING_INTERP[0x1].MODE: 0
4774 VPC_VARYING_INTERP[0x2].MODE: 0
4775 VPC_VARYING_INTERP[0x3].MODE: 0
4776 VPC_VARYING_INTERP[0x4].MODE: 0
4777 VPC_VARYING_INTERP[0x5].MODE: 0
4778 VPC_VARYING_INTERP[0x6].MODE: 0
4779 VPC_VARYING_INTERP[0x7].MODE: 0
4780 109d18c4: 0000: 00072142 00000000 00000000 00000000 00000000 00000000 00000000 00000000
4781 *
4782 t0 write VPC_VARYING_PS_REPL[0].MODE (214a)
4783 VPC_VARYING_PS_REPL[0].MODE: 0
4784 VPC_VARYING_PS_REPL[0x1].MODE: 0
4785 VPC_VARYING_PS_REPL[0x2].MODE: 0
4786 VPC_VARYING_PS_REPL[0x3].MODE: 0
4787 VPC_VARYING_PS_REPL[0x4].MODE: 0
4788 VPC_VARYING_PS_REPL[0x5].MODE: 0
4789 VPC_VARYING_PS_REPL[0x6].MODE: 0
4790 VPC_VARYING_PS_REPL[0x7].MODE: 0
4791 109d18e8: 0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000
4792 *
4793 t3 opcode: CP_LOAD_STATE4 (30) (131 dwords)
4794 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 }
4795 { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 }
4796 :2:0000:0000[40700000x_10000002x] mul.f r0.x, r0.z, c0.x
4797 :2:0001:0001[40700001x_10030002x] mul.f r0.y, r0.z, c0.w
4798 :3:0002:0002[63818000x_00001004x] mad.f32 r0.x, c1.x, r0.w, r0.x
4799 :3:0003:0003[63818001x_00011007x] mad.f32 r0.y, c1.w, r0.w, r0.y
4800 :3:0004:0004[63820000x_00001008x] mad.f32 r0.x, c2.x, r1.x, r0.x
4801 :3:0005:0005[63820001x_0001100bx] mad.f32 r0.y, c2.w, r1.x, r0.y
4802 :3:0006:0006[6382800ax_0000100cx] mad.f32 r2.z, c3.x, r1.y, r0.x
4803 :2:0007:0007[40700000x_10010002x] mul.f r0.x, r0.z, c0.y
4804 :3:0008:0008[6382800dx_0001100fx] mad.f32 r3.y, c3.w, r1.y, r0.y
4805 :3:0009:0009[63818000x_00001005x] mad.f32 r0.x, c1.y, r0.w, r0.x
4806 :1:0010:0010[20244001x_00000010x] mov.f32f32 r0.y, c4.x
4807 :3:0011:0011[63820000x_00001009x] mad.f32 r0.x, c2.y, r1.x, r0.x
4808 :0:0012:0012[00000000x_00000000x] nop
4809 :3:0013:0013[6382800bx_0000100dx] mad.f32 r2.w, c3.y, r1.y, r0.x
4810 :2:0014:0014[40700000x_10020002x] mul.f r0.x, r0.z, c0.z
4811 :2:0015:0015[40100001x_0001101cx] add.f r0.y, c7.x, r0.y
4812 :3:0016:0016[63818000x_00001006x] mad.f32 r0.x, c1.z, r0.w, r0.x
4813 :1:0017:0017[20244002x_00000011x] mov.f32f32 r0.z, c4.y
4814 :3:0018:0018[63820000x_0000100ax] mad.f32 r0.x, c2.z, r1.x, r0.x
4815 :1:0019:0019[20244004x_00000013x] mov.f32f32 r1.x, c4.w
4816 :3:0020:0020[6382800cx_0000100ex] mad.f32 r3.x, c3.z, r1.y, r0.x
4817 :2:0021:0021[40700000x_00070007x] mul.f r0.x, r1.w, r1.w
4818 :2:0022:0022[40100002x_0002101dx] add.f r0.z, c7.y, r0.z
4819 :3:0023:0023[63830000x_00000006x] mad.f32 r0.x, r1.z, r1.z, r0.x
4820 :2:0024:0024[40500411x_00041013x] (sat)max.f r4.y, c4.w, r1.x
4821 :3:0025:0025[63840000x_00000008x] mad.f32 r0.x, r2.x, r2.x, r0.x
4822 :1:0026:0026[20244003x_00000012x] mov.f32f32 r0.w, c4.z
4823 :0:0027:0027[00000200x_00000000x] (rpt2)nop
4824 :2:0028:0030[40100003x_0003101ex] add.f r0.w, c7.z, r0.w
4825 :0:0029:0031[00000000x_00000000x] nop
4826 :4:0030:0032[80300000x_00000000x] rsq r0.x, r0.x
4827 :2:0031:0033[40701004x_00000007x] (ss)mul.f r1.x, r1.w, r0.x
4828 :0:0032:0034[00000200x_00000000x] (rpt2)nop
4829 :2:0033:0037[40700004x_10150004x] mul.f r1.x, r1.x, c5.y
4830 :2:0034:0038[40700005x_00000006x] mul.f r1.y, r1.z, r0.x
4831 :0:0035:0039[00000200x_00000000x] (rpt2)nop
4832 :3:0036:0042[63828004x_00041014x] mad.f32 r1.x, c5.x, r1.y, r1.x
4833 :2:0037:0043[40700000x_00000008x] mul.f r0.x, r2.x, r0.x
4834 :0:0038:0044[00000200x_00000000x] (rpt2)nop
4835 :3:0039:0047[63800000x_00041016x] mad.f32 r0.x, c5.z, r0.x, r1.x
4836 :0:0040:0048[00000200x_00000000x] (rpt2)nop
4837 :2:0041:0051[40b00004x_00001034x] cmps.f.lt r1.x, c13.x, r0.x
4838 :2:0042:0052[40500000x_00001034x] max.f r0.x, c13.x, r0.x
4839 :0:0043:0053[00000100x_00000000x] (rpt1)nop
4840 :1:0044:0055[200c4004x_00000004x] cov.u32f32 r1.x, r1.x
4841 :3:0045:0056[63800001x_00011020x] mad.f32 r0.y, c8.x, r0.x, r0.y
4842 :3:0046:0057[63800002x_00021021x] mad.f32 r0.z, c8.y, r0.x, r0.z
4843 :3:0047:0058[63800000x_00031022x] mad.f32 r0.x, c8.z, r0.x, r0.w
4844 :3:0048:0059[6382040ex_00011024x] (sat)mad.f32 r3.z, c9.x, r1.x, r0.y
4845 :3:0049:0060[6382040fx_00021025x] (sat)mad.f32 r3.w, c9.y, r1.x, r0.z
4846 :3:0050:0061[63820410x_00001026x] (sat)mad.f32 r4.x, c9.z, r1.x, r0.x
4847 :0:0051:0062[03000000x_00000000x] end
4848 :0:0052:0063[00000000x_00000000x] nop
4849 :0:0053:0064[00000000x_00000000x] nop
4850 :0:0054:0065[00000000x_00000000x] nop
4851 :0:0055:0066[00000000x_00000000x] nop
4852 Register Stats:
4853 - used (half): (cnt=0, max=0)
4854 - used (full): 0-8 10-17 (cnt=17, max=17)
4855 - input (half): (cnt=0, max=0)
4856 - input (full): 2-8 (cnt=7, max=8)
4857 - max const: 52
4858
4859 - output (half): (cnt=0, max=0) (estimated)
4860 - output (full): 10-17 (cnt=8, max=17) (estimated)
4861 - shaderdb: 67 instructions, 31 nops, 36 non-nops, (56 instlen), 0 half, 5 full
4862 - shaderdb: 1 (ss), 0 (sy)
4863 109d190c: 0000: c0813000 01200000 00000000 10000002 40700000 10030002 40700001 00001004
4864 109d192c: 0020: 63818000 00011007 63818001 00001008 63820000 0001100b 63820001 0000100c
4865 109d194c: 0040: 6382800a 10010002 40700000 0001100f 6382800d 00001005 63818000 00000010
4866 109d196c: 0060: 20244001 00001009 63820000 00000000 00000000 0000100d 6382800b 10020002
4867 109d198c: 0080: 40700000 0001101c 40100001 00001006 63818000 00000011 20244002 0000100a
4868 109d19ac: 00a0: 63820000 00000013 20244004 0000100e 6382800c 00070007 40700000 0002101d
4869 109d19cc: 00c0: 40100002 00000006 63830000 00041013 40500411 00000008 63840000 00000012
4870 109d19ec: 00e0: 20244003 00000000 00000200 0003101e 40100003 00000000 00000000 00000000
4871 109d1a0c: 0100: 80300000 00000007 40701004 00000000 00000200 10150004 40700004 00000006
4872 109d1a2c: 0120: 40700005 00000000 00000200 00041014 63828004 00000008 40700000 00000000
4873 109d1a4c: 0140: 00000200 00041016 63800000 00000000 00000200 00001034 40b00004 00001034
4874 109d1a6c: 0160: 40500000 00000000 00000100 00000004 200c4004 00011020 63800001 00021021
4875 109d1a8c: 0180: 63800002 00031022 63800000 00011024 6382040e 00021025 6382040f 00001026
4876 109d1aac: 01a0: 63820410 00000000 03000000 00000000 00000000 00000000 00000000 00000000
4877 *
4878 t3 opcode: CP_LOAD_STATE4 (30) (35 dwords)
4879 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 }
4880 { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 }
4881 :2:0000:0000[47300002x_00002000x] bary.f r0.z, 0, r0.x
4882 :2:0001:0001[47300003x_00002001x] bary.f r0.w, 1, r0.x
4883 :2:0002:0002[47300004x_00002002x] bary.f r1.x, 2, r0.x
4884 :2:0003:0003[47308005x_00002003x] bary.f (ei)r1.y, 3, r0.x
4885 :0:0004:0004[03000000x_00000000x] end
4886 :0:0005:0005[00000000x_00000000x] nop
4887 :0:0006:0006[00000000x_00000000x] nop
4888 :0:0007:0007[00000000x_00000000x] nop
4889 :0:0008:0008[00000000x_00000000x] nop
4890 Register Stats:
4891 - used (half): (cnt=0, max=0)
4892 - used (full): 0 2-5 (cnt=5, max=5)
4893 - input (half): (cnt=0, max=0)
4894 - input (full): 0 (cnt=1, max=0)
4895 - max const: 0
4896
4897 - output (half): (cnt=0, max=0) (estimated)
4898 - output (full): 2-5 (cnt=4, max=5) (estimated)
4899 - shaderdb: 9 instructions, 4 nops, 5 non-nops, (9 instlen), 0 half, 2 full
4900 - shaderdb: 0 (ss), 0 (sy)
4901 109d1b18: 0000: c0213000 00700000 00000000 00002000 47300002 00002001 47300003 00002002
4902 109d1b38: 0020: 47300004 00002003 47308005 00000000 03000000 00000000 00000000 00000000
4903 *
4904 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
4905 109d1ba4: 0000: c0002600 00000000
4906 t3 opcode: CP_LOAD_STATE4 (30) (51 dwords)
4907 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 }
4908 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 }
4909 109d1bb8: 3.924428 -1.210718 0.674073 0.570369 1.829991 4.619613 -0.131666 -0.111410
4910 109d1bd8: 2.500000 -1.480991 -0.961761 -0.813798 -13.423393 17.082890 32.944622 37.106991
4911 109d1bf8: 0.040000 0.040000 0.200000 1.000000 -0.244131 0.617574 0.747665 0.000000
4912 109d1c18: 1.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 1.000000
4913 109d1c38: 0.200000 0.200000 1.000000 1.000000 0.000000 0.000000 0.000000 1.000000
4914 109d1c58: 0.000000 0.000000 0.000000 1.000000 0.000000 0.000000 0.000000 0.000000
4915 109d1bb8: 0000: 407b29d2 bf9af8cb 3f2c9009 3f1203b9 3fea3d23 4093d3df be06d382 bde42adc
4916 109d1bd8: 0020: 40200000 bfbd9119 bf7635f5 bf50550b c156c638 4188a9c2 4203c74b 42146d8f
4917 109d1bf8: 0040: 3d23d70b 3d23d70b 3e4ccccd 3f800000 be79fd80 3f1e194f 3f3f66f5 00000000
4918 109d1c18: 0060: 3f800000 00000000 00000000 00000000 00000000 00000000 00000000 3f800000
4919 109d1c38: 0080: 3e4ccccd 3e4ccccd 3f800000 3f800000 00000000 00000000 00000000 3f800000
4920 109d1c58: 00a0: 00000000 00000000 00000000 3f800000 02020000 02020202 02020202 00000202
4921 109d1bac: 0000: c0313000 03200000 00000001 407b29d2 bf9af8cb 3f2c9009 3f1203b9 3fea3d23
4922 109d1bcc: 0020: 4093d3df be06d382 bde42adc 40200000 bfbd9119 bf7635f5 bf50550b c156c638
4923 109d1bec: 0040: 4188a9c2 4203c74b 42146d8f 3d23d70b 3d23d70b 3e4ccccd 3f800000 be79fd80
4924 109d1c0c: 0060: 3f1e194f 3f3f66f5 00000000 3f800000 00000000 00000000 00000000 00000000
4925 109d1c2c: 0080: 00000000 00000000 3f800000 3e4ccccd 3e4ccccd 3f800000 3f800000 00000000
4926 109d1c4c: 00a0: 00000000 00000000 3f800000 00000000 00000000 00000000 3f800000 02020000
4927 109d1c6c: 00c0: 02020202 02020202 00000202
4928 t0 write VFD_INDEX_OFFSET (2208)
4929 VFD_INDEX_OFFSET: 0
4930 UNKNOWN_2209: 0
4931 109d1c78: 0000: 00012208 00000000 00000000
4932 t0 write PC_RESTART_INDEX (21c6)
4933 PC_RESTART_INDEX: 0xffffffff
4934 109d1c84: 0000: 000021c6 ffffffff
4935 t0 write CP_SCRATCH[0x7].REG (057f)
4936 CP_SCRATCH[0x7].REG: 0x6e
4937 :0,109,115,110
4938 109d1c8c: 0000: 0000057f 0000006e
4939 t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
4940 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS }
4941 { NUM_INSTANCES = 1 }
4942 { NUM_INDICES = 60 }
4943 { FIRST_INDX = 0 }
4944 { INDX_BASE = 0x10bd1428 }
4945 { INDX_SIZE = 120 }
4946 draw[18] register values
4947 !+ 0000006d CP_SCRATCH[0x5].REG: 0x6d
4948 :0,109,115,110
4949 !+ 0000006e CP_SCRATCH[0x7].REG: 0x6e
4950 :0,109,115,110
4951 + 00080000 GRAS_CL_CLIP_CNTL: { 0x80000 }
4952 !+ 00000001 GRAS_CNTL: { IJ_PERSP }
4953 + 00100010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 }
4954 + 00000010 GRAS_SU_POINT_SIZE: 1.000000
4955 + 00000000 GRAS_ALPHA_CONTROL: { 0 }
4956 + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000
4957 + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000
4958 + 00000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000
4959 + 00100012 GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 | RENDERING_PASS }
4960 + 012b012b GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 }
4961 + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
4962 !+ 00001000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL }
4963 + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 }
4964 + 80000016 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE }
4965 + 00000000 RB_VPORT_Z_CLAMP[0].MIN: 0
4966 + 00ffffff RB_VPORT_Z_CLAMP[0].MAX: 0xffffff
4967 + 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 }
4968 + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 }
4969 !+ 00000000 VPC_VARYING_INTERP[0].MODE: 0
4970 + 00000000 VPC_VARYING_INTERP[0x1].MODE: 0
4971 + 00000000 VPC_VARYING_INTERP[0x2].MODE: 0
4972 + 00000000 VPC_VARYING_INTERP[0x3].MODE: 0
4973 + 00000000 VPC_VARYING_INTERP[0x4].MODE: 0
4974 + 00000000 VPC_VARYING_INTERP[0x5].MODE: 0
4975 + 00000000 VPC_VARYING_INTERP[0x6].MODE: 0
4976 + 00000000 VPC_VARYING_INTERP[0x7].MODE: 0
4977 + 00000000 VPC_VARYING_PS_REPL[0].MODE: 0
4978 + 00000000 VPC_VARYING_PS_REPL[0x1].MODE: 0
4979 + 00000000 VPC_VARYING_PS_REPL[0x2].MODE: 0
4980 + 00000000 VPC_VARYING_PS_REPL[0x3].MODE: 0
4981 + 00000000 VPC_VARYING_PS_REPL[0x4].MODE: 0
4982 + 00000000 VPC_VARYING_PS_REPL[0x5].MODE: 0
4983 + 00000000 VPC_VARYING_PS_REPL[0x6].MODE: 0
4984 + 00000000 VPC_VARYING_PS_REPL[0x7].MODE: 0
4985 + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST }
4986 + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES }
4987 + ffffffff PC_RESTART_INDEX: 0xffffffff
4988 + 00000000 VFD_INDEX_OFFSET: 0
4989 + 00000000 UNKNOWN_2209: 0
4990 + 00140010 SP_SP_CTRL_REG: { 0x140010 }
4991 + 000005ff SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f }
4992 + 00201400 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE }
4993 + 08000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 8 }
4994 + 0010fc0a SP_VS_PARAM_REG: { POSREGID = r2.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 }
4995 + 00001e0e SP_VS_OUT[0].REG: { A_REGID = r3.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 }
4996 + 08080808 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 }
4997 + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 }
4998 + 10cd5000 SP_VS_OBJ_START: 0x10cd5000
4999 + 00000004 SP_VS_LENGTH_REG: 4
5000 !+ 00340802 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE }
5001 + 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 }
5002 + 7e420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
5003 !+ 108cb000 SP_FS_OBJ_START: 0x108cb000
5004 + 00000001 SP_FS_LENGTH_REG: 1
5005 + 0000fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x }
5006 !+ 0001a002 SP_FS_MRT[0].REG: { REGID = r0.z | MRTFORMAT = RB4_R8G8B8A8_UNORM }
5007 !+ 00000002 SP_FS_MRT[0x1].REG: { REGID = r0.z | MRTFORMAT = 0 }
5008 !+ 00000002 SP_FS_MRT[0x2].REG: { REGID = r0.z | MRTFORMAT = 0 }
5009 !+ 00000002 SP_FS_MRT[0x3].REG: { REGID = r0.z | MRTFORMAT = 0 }
5010 !+ 00000002 SP_FS_MRT[0x4].REG: { REGID = r0.z | MRTFORMAT = 0 }
5011 !+ 00000002 SP_FS_MRT[0x5].REG: { REGID = r0.z | MRTFORMAT = 0 }
5012 !+ 00000002 SP_FS_MRT[0x6].REG: { REGID = r0.z | MRTFORMAT = 0 }
5013 !+ 00000002 SP_FS_MRT[0x7].REG: { REGID = r0.z | MRTFORMAT = 0 }
5014 + 7e420000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
5015 + 7e420000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
5016 + 7e420000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
5017 + 28000250 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE }
5018 + fcfc0100 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x }
5019 + fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x }
5020 !+ fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
5021 + 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 }
5022 + 04000042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 }
5023 + 017e423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 }
5024 + 007e4200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
5025 + 007e4200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
5026 + 007e4200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
5027 + 00000003 HLSQ_UPDATE_CONTROL: 0x3
5028 109d1c94: 0000: c0053800 00000404 00000001 0000003c 00000000 10bd1428 00000078
5029 t0 write CP_SCRATCH[0x7].REG (057f)
5030 CP_SCRATCH[0x7].REG: 0x6f
5031 :0,109,115,111
5032 109d1cb0: 0000: 0000057f 0000006f
5033 108ce2d0: 0000: c0013f00 109ce000 00000f2e
5034 t2 nop
5035 t0 write RB_DEPTH_CONTROL (2101)
5036 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER }
5037 108ce2e8: 0000: 00002101 00000000
5038 t0 write RB_STENCIL_CONTROL (2106)
5039 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP }
5040 RB_STENCIL_CONTROL2: { 0 }
5041 108ce2f0: 0000: 00012106 00000000 00000000
5042 t0 write RB_STENCILREFMASK (210b)
5043 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 }
5044 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 }
5045 108ce2fc: 0000: 0001210b ffff0000 ffff0000
5046 t0 write GRAS_SU_MODE_CONTROL (2078)
5047 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 }
5048 108ce308: 0000: 00002078 00000000
5049 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
5050 108ce310: 0000: c0002600 00000000
5051 t0 write GRAS_CL_CLIP_CNTL (2000)
5052 GRAS_CL_CLIP_CNTL: { 0x80000 }
5053 108ce318: 0000: 00002000 00080000
5054 t0 write GRAS_CL_VPORT_XOFFSET_0 (2008)
5055 GRAS_CL_VPORT_XOFFSET_0: 150.000000
5056 GRAS_CL_VPORT_XSCALE_0: 150.000000
5057 GRAS_CL_VPORT_YOFFSET_0: 150.000000
5058 GRAS_CL_VPORT_YSCALE_0: -150.000000
5059 GRAS_CL_VPORT_ZOFFSET_0: 0.000000
5060 GRAS_CL_VPORT_ZSCALE_0: 1.000000
5061 108ce320: 0000: 00052008 43160000 43160000 43160000 c3160000 00000000 3f800000
5062 t0 write RB_RENDER_CONTROL (20a1)
5063 RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0xa }
5064 108ce33c: 0000: 000020a1 0000002a
5065 t0 write GRAS_SC_CONTROL (207b)
5066 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0x1 }
5067 108ce344: 0000: 0000207b 00001808
5068 t0 write PC_PRIM_VTX_CNTL (21c4)
5069 PC_PRIM_VTX_CNTL: { VAROUT = 0 | PROVOKING_VTX_LAST }
5070 108ce34c: 0000: 000021c4 02000000
5071 t0 write GRAS_ALPHA_CONTROL (2073)
5072 GRAS_ALPHA_CONTROL: { 0x2 }
5073 108ce354: 0000: 00002073 00000002
5074 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c)
5075 GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 }
5076 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
5077 108ce35c: 0000: 0001209c 012b012b 00000000
5078 t0 write VFD_INDEX_OFFSET (2208)
5079 VFD_INDEX_OFFSET: 0
5080 UNKNOWN_2209: 0
5081 108ce368: 0000: 00012208 00000000 00000000
5082 t0 write HLSQ_UPDATE_CONTROL (23db)
5083 HLSQ_UPDATE_CONTROL: 0x3
5084 108ce374: 0000: 000023db 00000003
5085 t0 write HLSQ_CONTROL_0_REG (23c0)
5086 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE }
5087 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x }
5088 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x }
5089 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
5090 HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 }
5091 108ce37c: 0000: 000423c0 28000250 fcfc0100 fff3f3f0 fcfcfcfc 00fcfcfc
5092 t0 write HLSQ_VS_CONTROL_REG (23c5)
5093 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 }
5094 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 }
5095 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
5096 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
5097 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
5098 108ce394: 0000: 000423c5 01000042 017e423e 007e4200 007e4200 007e4200
5099 t0 write SP_SP_CTRL_REG (22c0)
5100 SP_SP_CTRL_REG: { 0x140010 }
5101 108ce3ac: 0000: 000022c0 00140010
5102 t0 write SP_INSTR_CACHE_CTRL (22c1)
5103 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f }
5104 108ce3b4: 0000: 000022c1 000005ff
5105 t0 write SP_VS_LENGTH_REG (22e5)
5106 SP_VS_LENGTH_REG: 1
5107 108ce3bc: 0000: 000022e5 00000001
5108 t0 write SP_VS_CTRL_REG0 (22c4)
5109 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE }
5110 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 4 }
5111 SP_VS_PARAM_REG: { POSREGID = r0.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 0 }
5112 108ce3c4: 0000: 000222c4 00200400 04000042 0000fc00
5113 t0 write SP_VS_OBJ_OFFSET_REG (22e0)
5114 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 }
5115 SP_VS_OBJ_START: 0x1073c000
5116 108ce3d4: 0000: 000122e0 00000000 1073c000
5117 t0 write SP_FS_LENGTH_REG (22ef)
5118 SP_FS_LENGTH_REG: 1
5119 108ce3e0: 0000: 000022ef 00000001
5120 t0 write SP_FS_CTRL_REG0 (22e8)
5121 SP_FS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE }
5122 SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | 0x80000000 }
5123 108ce3e8: 0000: 000122e8 00340400 8000003e
5124 t0 write SP_FS_OBJ_OFFSET_REG (22ea)
5125 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
5126 SP_FS_OBJ_START: 0x1073b000
5127 108ce3f4: 0000: 000122ea 7e420000 1073b000
5128 t0 write SP_HS_OBJ_OFFSET_REG (230d)
5129 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
5130 108ce400: 0000: 0000230d 7e420000
5131 t0 write SP_DS_OBJ_OFFSET_REG (2334)
5132 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
5133 108ce408: 0000: 00002334 7e420000
5134 t0 write SP_GS_OBJ_OFFSET_REG (235b)
5135 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
5136 108ce410: 0000: 0000235b 7e420000
5137 t0 write GRAS_CNTL (2003)
5138 GRAS_CNTL: { 0 }
5139 108ce418: 0000: 00002003 00000000
5140 t0 write RB_RENDER_CONTROL2 (20a3)
5141 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 }
5142 108ce420: 0000: 000020a3 00000000
5143 t0 write RB_FS_OUTPUT_REG (2100)
5144 RB_FS_OUTPUT_REG: { MRT = 0 }
5145 108ce428: 0000: 00002100 00000000
5146 t0 write SP_FS_OUTPUT_REG (22f0)
5147 SP_FS_OUTPUT_REG: { MRT = 0 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x }
5148 108ce430: 0000: 000022f0 0000fc00
5149 t0 write SP_FS_MRT[0].REG (22f1)
5150 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = 0 }
5151 SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 }
5152 SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 }
5153 SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 }
5154 SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 }
5155 SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 }
5156 SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 }
5157 SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 }
5158 108ce438: 0000: 000722f1 00000000 00000000 00000000 00000000 00000000 00000000 00000000
5159 *
5160 t0 write VPC_ATTR (2140)
5161 VPC_ATTR: { TOTALATTR = 0 | THRDASSIGN = 1 | 0x40000000 }
5162 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 0 | NUMNONPOSVSVAR = 0 }
5163 108ce45c: 0000: 00012140 40001000 00000000
5164 t0 write VPC_VARYING_INTERP[0].MODE (2142)
5165 VPC_VARYING_INTERP[0].MODE: 0
5166 VPC_VARYING_INTERP[0x1].MODE: 0
5167 VPC_VARYING_INTERP[0x2].MODE: 0
5168 VPC_VARYING_INTERP[0x3].MODE: 0
5169 VPC_VARYING_INTERP[0x4].MODE: 0
5170 VPC_VARYING_INTERP[0x5].MODE: 0
5171 VPC_VARYING_INTERP[0x6].MODE: 0
5172 VPC_VARYING_INTERP[0x7].MODE: 0
5173 108ce468: 0000: 00072142 00000000 00000000 00000000 00000000 00000000 00000000 00000000
5174 *
5175 t0 write VPC_VARYING_PS_REPL[0].MODE (214a)
5176 VPC_VARYING_PS_REPL[0].MODE: 0
5177 VPC_VARYING_PS_REPL[0x1].MODE: 0
5178 VPC_VARYING_PS_REPL[0x2].MODE: 0
5179 VPC_VARYING_PS_REPL[0x3].MODE: 0
5180 VPC_VARYING_PS_REPL[0x4].MODE: 0
5181 VPC_VARYING_PS_REPL[0x5].MODE: 0
5182 VPC_VARYING_PS_REPL[0x6].MODE: 0
5183 VPC_VARYING_PS_REPL[0x7].MODE: 0
5184 108ce48c: 0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000
5185 *
5186 t3 opcode: CP_LOAD_STATE4 (30) (35 dwords)
5187 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 }
5188 { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 }
5189 :0:0000:0000[03000000x_00000000x] end
5190 :0:0001:0001[00000000x_00000000x] nop
5191 :0:0002:0002[00000000x_00000000x] nop
5192 :0:0003:0003[00000000x_00000000x] nop
5193 :0:0004:0004[00000000x_00000000x] nop
5194 Register Stats:
5195 - used (half): (cnt=0, max=0)
5196 - used (full): (cnt=0, max=0)
5197 - input (half): (cnt=0, max=0)
5198 - input (full): (cnt=0, max=0)
5199 - max const: 0
5200
5201 - output (half): (cnt=0, max=0) (estimated)
5202 - output (full): (cnt=0, max=0) (estimated)
5203 - shaderdb: 5 instructions, 4 nops, 1 non-nops, (5 instlen), 0 half, 0 full
5204 - shaderdb: 0 (ss), 0 (sy)
5205 108ce4b0: 0000: c0213000 00600000 00000000 00000000 03000000 00000000 00000000 00000000
5206 *
5207 t3 opcode: CP_LOAD_STATE4 (30) (35 dwords)
5208 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 }
5209 { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 }
5210 :1:0000:0000[20244000x_00000000x] mov.f32f32 r0.x, c0.x
5211 :1:0001:0001[20244001x_00000001x] mov.f32f32 r0.y, c0.y
5212 :1:0002:0002[20244002x_00000002x] mov.f32f32 r0.z, c0.z
5213 :1:0003:0003[20244003x_00000003x] mov.f32f32 r0.w, c0.w
5214 :0:0004:0004[03000000x_00000000x] end
5215 :0:0005:0005[00000000x_00000000x] nop
5216 :0:0006:0006[00000000x_00000000x] nop
5217 :0:0007:0007[00000000x_00000000x] nop
5218 :0:0008:0008[00000000x_00000000x] nop
5219 Register Stats:
5220 - used (half): (cnt=0, max=0)
5221 - used (full): 0-3 (cnt=4, max=3)
5222 - input (half): (cnt=0, max=0)
5223 - input (full): (cnt=0, max=0)
5224 - max const: 3
5225
5226 - output (half): (cnt=0, max=0) (estimated)
5227 - output (full): 0-3 (cnt=4, max=3) (estimated)
5228 - shaderdb: 9 instructions, 8 nops, 1 non-nops, (9 instlen), 0 half, 1 full
5229 - shaderdb: 0 (ss), 0 (sy)
5230 108ce53c: 0000: c0213000 00700000 00000000 00000000 20244000 00000001 20244001 00000002
5231 108ce55c: 0020: 20244002 00000003 20244003 00000000 03000000 00000000 00000000 00000000
5232 *
5233 t0 write VFD_FETCH[0].INSTR_0 (220a)
5234 VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 12 }
5235 VFD_FETCH[0].INSTR_1: 0x1074a000
5236 VFD_FETCH[0].INSTR_2: { SIZE = 0x1000 }
5237 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 }
5238 108ce5c8: 0000: 0003220a 0000060b 1074a000 00001000 00000001
5239 t0 write VFD_DECODE[0].INSTR (228a)
5240 VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID }
5241 108ce5dc: 0000: 0000228a 2c0000df
5242 t0 write VFD_CONTROL_0 (2200)
5243 VFD_CONTROL_0: { TOTALATTRTOVS = 4 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 | 0xa0000 }
5244 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x }
5245 VFD_CONTROL_2: 0
5246 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x }
5247 VFD_CONTROL_4: 0
5248 108ce5e4: 0000: 00042200 041a0004 fcfc0081 00000000 0000fc00 00000000
5249 t0 write UCHE_INVALIDATE0 (0e8a)
5250 UCHE_INVALIDATE0: 0
5251 UCHE_INVALIDATE1: 0x12
5252 108ce5fc: 0000: 00010e8a 00000000 00000012
5253 t0 write RB_COPY_CONTROL (20fc)
5254 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_ONE | MODE = RB_COPY_RESOLVE | FASTCLEAR = 0 | GMEM_BASE = 0x64000 }
5255 RB_COPY_DEST_BASE: { BASE = 0x10edc000 }
5256 RB_COPY_DEST_PITCH: { PITCH = 1280 }
5257 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_LINEAR }
5258 108ce608: 0000: 000320fc 00064010 10edc000 00000028 0003c068
5259 t0 write CP_SCRATCH[0x7].REG (057f)
5260 CP_SCRATCH[0x7].REG: 0x75
5261 :0,109,115,117
5262 108ce61c: 0000: 0000057f 00000075
5263 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
5264 { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_8_BIT | PATCH_TYPE = TESS_QUADS }
5265 { NUM_INSTANCES = 1 }
5266 { NUM_INDICES = 2 }
5267 draw[19] register values
5268 !+ 00000075 CP_SCRATCH[0x7].REG: 0x75
5269 :0,109,115,117
5270 + 00000000 UCHE_INVALIDATE0: 0
5271 + 00000012 UCHE_INVALIDATE1: 0x12
5272 + 00080000 GRAS_CL_CLIP_CNTL: { 0x80000 }
5273 !+ 00000000 GRAS_CNTL: { 0 }
5274 + 43160000 GRAS_CL_VPORT_XOFFSET_0: 150.000000
5275 + 43160000 GRAS_CL_VPORT_XSCALE_0: 150.000000
5276 + 43160000 GRAS_CL_VPORT_YOFFSET_0: 150.000000
5277 + c3160000 GRAS_CL_VPORT_YSCALE_0: -150.000000
5278 !+ 00000000 GRAS_CL_VPORT_ZOFFSET_0: 0.000000
5279 !+ 3f800000 GRAS_CL_VPORT_ZSCALE_0: 1.000000
5280 !+ 00000002 GRAS_ALPHA_CONTROL: { 0x2 }
5281 !+ 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 }
5282 !+ 00001808 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0x1 }
5283 + 012b012b GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 }
5284 + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
5285 !+ 0000002a RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0xa }
5286 !+ 00000000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 }
5287 !+ 00064010 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_ONE | MODE = RB_COPY_RESOLVE | FASTCLEAR = 0 | GMEM_BASE = 0x64000 }
5288 !+ 10edc000 RB_COPY_DEST_BASE: { BASE = 0x10edc000 }
5289 !+ 00000028 RB_COPY_DEST_PITCH: { PITCH = 1280 }
5290 !+ 0003c068 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_LINEAR }
5291 !+ 00000000 RB_FS_OUTPUT_REG: { MRT = 0 }
5292 !+ 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER }
5293 + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP }
5294 + 00000000 RB_STENCIL_CONTROL2: { 0 }
5295 !+ ffff0000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 }
5296 !+ ffff0000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 }
5297 !+ 40001000 VPC_ATTR: { TOTALATTR = 0 | THRDASSIGN = 1 | 0x40000000 }
5298 !+ 00000000 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 0 | NUMNONPOSVSVAR = 0 }
5299 + 00000000 VPC_VARYING_INTERP[0].MODE: 0
5300 + 00000000 VPC_VARYING_INTERP[0x1].MODE: 0
5301 + 00000000 VPC_VARYING_INTERP[0x2].MODE: 0
5302 + 00000000 VPC_VARYING_INTERP[0x3].MODE: 0
5303 + 00000000 VPC_VARYING_INTERP[0x4].MODE: 0
5304 + 00000000 VPC_VARYING_INTERP[0x5].MODE: 0
5305 + 00000000 VPC_VARYING_INTERP[0x6].MODE: 0
5306 + 00000000 VPC_VARYING_INTERP[0x7].MODE: 0
5307 + 00000000 VPC_VARYING_PS_REPL[0].MODE: 0
5308 + 00000000 VPC_VARYING_PS_REPL[0x1].MODE: 0
5309 + 00000000 VPC_VARYING_PS_REPL[0x2].MODE: 0
5310 + 00000000 VPC_VARYING_PS_REPL[0x3].MODE: 0
5311 + 00000000 VPC_VARYING_PS_REPL[0x4].MODE: 0
5312 + 00000000 VPC_VARYING_PS_REPL[0x5].MODE: 0
5313 + 00000000 VPC_VARYING_PS_REPL[0x6].MODE: 0
5314 + 00000000 VPC_VARYING_PS_REPL[0x7].MODE: 0
5315 !+ 02000000 PC_PRIM_VTX_CNTL: { VAROUT = 0 | PROVOKING_VTX_LAST }
5316 !+ 041a0004 VFD_CONTROL_0: { TOTALATTRTOVS = 4 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 | 0xa0000 }
5317 + fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x }
5318 + 00000000 VFD_CONTROL_2: 0
5319 + 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x }
5320 + 00000000 VFD_CONTROL_4: 0
5321 + 00000000 VFD_INDEX_OFFSET: 0
5322 + 00000000 UNKNOWN_2209: 0
5323 !+ 0000060b VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 12 }
5324 !+ 1074a000 VFD_FETCH[0].INSTR_1: 0x1074a000
5325 !+ 00001000 VFD_FETCH[0].INSTR_2: { SIZE = 0x1000 }
5326 + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 }
5327 !+ 2c0000df VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID }
5328 + 00140010 SP_SP_CTRL_REG: { 0x140010 }
5329 + 000005ff SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f }
5330 !+ 00200400 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE }
5331 !+ 04000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 4 }
5332 !+ 0000fc00 SP_VS_PARAM_REG: { POSREGID = r0.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 0 }
5333 + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 }
5334 !+ 1073c000 SP_VS_OBJ_START: 0x1073c000
5335 !+ 00000001 SP_VS_LENGTH_REG: 1
5336 !+ 00340400 SP_FS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE }
5337 !+ 8000003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | 0x80000000 }
5338 + 7e420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
5339 !+ 1073b000 SP_FS_OBJ_START: 0x1073b000
5340 + 00000001 SP_FS_LENGTH_REG: 1
5341 !+ 0000fc00 SP_FS_OUTPUT_REG: { MRT = 0 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x }
5342 !+ 00000000 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = 0 }
5343 !+ 00000000 SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 }
5344 !+ 00000000 SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 }
5345 !+ 00000000 SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 }
5346 !+ 00000000 SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 }
5347 !+ 00000000 SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 }
5348 !+ 00000000 SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 }
5349 !+ 00000000 SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 }
5350 + 7e420000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
5351 + 7e420000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
5352 + 7e420000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 }
5353 + 28000250 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE }
5354 + fcfc0100 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x }
5355 + fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x }
5356 !+ fcfcfcfc HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
5357 + 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 }
5358 !+ 01000042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 }
5359 + 017e423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 }
5360 + 007e4200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
5361 + 007e4200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
5362 + 007e4200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 }
5363 + 00000003 HLSQ_UPDATE_CONTROL: 0x3
5364 108ce624: 0000: c0023800 00000088 00000001 00000002
5365 t0 write CP_SCRATCH[0x7].REG (057f)
5366 CP_SCRATCH[0x7].REG: 0x76
5367 :0,109,115,118
5368 108ce634: 0000: 0000057f 00000076
5369 t0 write RB_COPY_CONTROL (20fc)
5370 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_ONE | MODE = RB_COPY_RESOLVE | FASTCLEAR = 0 | GMEM_BASE = 0 }
5371 RB_COPY_DEST_BASE: { BASE = 0x10f3c000 }
5372 RB_COPY_DEST_PITCH: { PITCH = 1280 }
5373 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WXYZ | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_LINEAR }
5374 108ce63c: 0000: 000320fc 00000010 10f3c000 00000028 0003c168
5375 t0 write CP_SCRATCH[0x7].REG (057f)
5376 CP_SCRATCH[0x7].REG: 0x77
5377 :0,109,115,119
5378 108ce650: 0000: 0000057f 00000077
5379 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
5380 { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_8_BIT | PATCH_TYPE = TESS_QUADS }
5381 { NUM_INSTANCES = 1 }
5382 { NUM_INDICES = 2 }
5383 draw[20] register values
5384 !+ 00000077 CP_SCRATCH[0x7].REG: 0x77
5385 :0,109,115,119
5386 !+ 00000010 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_ONE | MODE = RB_COPY_RESOLVE | FASTCLEAR = 0 | GMEM_BASE = 0 }
5387 !+ 10f3c000 RB_COPY_DEST_BASE: { BASE = 0x10f3c000 }
5388 + 00000028 RB_COPY_DEST_PITCH: { PITCH = 1280 }
5389 !+ 0003c168 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WXYZ | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_LINEAR }
5390 108ce658: 0000: c0023800 00000088 00000001 00000002
5391 t0 write CP_SCRATCH[0x7].REG (057f)
5392 CP_SCRATCH[0x7].REG: 0x78
5393 :0,109,115,120
5394 108ce668: 0000: 0000057f 00000078
5395 t0 write GRAS_SC_CONTROL (207b)
5396 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 }
5397 108ce670: 0000: 0000207b 00000800
5398 ############################################################
5399 vertices: 0
5400 cmd: glxgears/23375: fence=1029605
5401 cmd: glxgears/23375: fence=1029606
5402 cmd: glxgears/23375: fence=1029607
5403 cmd: glxgears/23375: fence=1029608
5404 cmd: glxgears/23375: fence=1029609
5405 cmd: glxgears/23375: fence=1029610
5406 cmd: glxgears/23375: fence=1029611
5407 cmd: glxgears/23375: fence=1029612
5408 cmd: glxgears/23375: fence=1029613
5409 cmd: glxgears/23375: fence=1029614
5410 cmd: glxgears/23375: fence=1029615
5411 cmd: glxgears/23375: fence=1029616
5412 cmd: glxgears/23375: fence=1029617
5413 cmd: glxgears/23375: fence=1029618
5414 cmd: glxgears/23375: fence=1029619
5415 cmd: glxgears/23375: fence=1029620
5416 cmd: glxgears/23375: fence=1029621
5417 cmd: glxgears/23375: fence=1029622
5418 cmd: glxgears/23375: fence=1029623
5419 cmd: glxgears/23375: fence=1029624
5420 cmd: glxgears/23375: fence=1029625
5421 cmd: glxgears/23375: fence=1029626
5422 cmd: glxgears/23375: fence=1029627
5423 cmd: glxgears/23375: fence=1029628
5424 cmd: glxgears/23375: fence=1029629
5425 cmd: glxgears/23375: fence=1029630
5426 cmd: glxgears/23375: fence=1029631
5427 cmd: glxgears/23375: fence=1029632
5428 cmd: glxgears/23375: fence=1029633
5429 cmd: glxgears/23375: fence=1029634
5430 cmd: glxgears/23375: fence=1029635
5431 cmd: glxgears/23375: fence=1029636
5432 cmd: glxgears/23375: fence=1029637
5433 cmd: glxgears/23375: fence=1029638
5434 cmd: glxgears/23375: fence=1029639
5435 cmd: glxgears/23375: fence=1029640
5436 cmd: glxgears/23375: fence=1029641
5437 cmd: glxgears/23375: fence=1029642
5438 cmd: glxgears/23375: fence=1029643
5439 cmd: glxgears/23375: fence=1029644
5440 cmd: glxgears/23375: fence=1029645
5441 cmd: glxgears/23375: fence=1029646
5442 cmd: glxgears/23375: fence=1029647
5443 cmd: glxgears/23375: fence=1029648
5444 cmd: glxgears/23375: fence=1029649
5445 cmd: glxgears/23375: fence=1029650
5446 cmd: glxgears/23375: fence=1029651
5447 cmd: glxgears/23375: fence=1029652
5448 cmd: glxgears/23375: fence=1029653
5449 cmd: glxgears/23375: fence=1029654
5450 cmd: glxgears/23375: fence=1029655
5451 cmd: glxgears/23375: fence=1029656
5452 cmd: glxgears/23375: fence=1029657
5453 cmd: glxgears/23375: fence=1029658
5454 cmd: glxgears/23375: fence=1029659
5455 cmd: glxgears/23375: fence=1029660
5456 cmd: glxgears/23375: fence=1029661
5457 cmd: glxgears/23375: fence=1029662
5458 cmd: glxgears/23375: fence=1029663
5459 cmd: glxgears/23375: fence=1029664
5460 cmd: glxgears/23375: fence=1029665
5461 cmd: glxgears/23375: fence=1029666
5462 cmd: glxgears/23375: fence=1029667
5463 cmd: glxgears/23375: fence=1029668
5464 cmd: glxgears/23375: fence=1029669
5465 cmd: glxgears/23375: fence=1029670
5466 cmd: glxgears/23375: fence=1029671
5467 cmd: glxgears/23375: fence=1029672
5468 cmd: glxgears/23375: fence=1029673
5469 cmd: glxgears/23375: fence=1029674
5470 cmd: glxgears/23375: fence=1029675
5471 cmd: glxgears/23375: fence=1029676
5472 cmd: glxgears/23375: fence=1029677
5473 cmd: glxgears/23375: fence=1029678
5474 cmd: glxgears/23375: fence=1029679
5475 cmd: glxgears/23375: fence=1029680
5476 cmd: glxgears/23375: fence=1029681
5477 cmd: glxgears/23375: fence=1029682
5478 cmd: glxgears/23375: fence=1029683
5479 cmd: glxgears/23375: fence=1029684
5480 cmd: glxgears/23375: fence=1029685
5481 cmd: glxgears/23375: fence=1029686
5482 cmd: glxgears/23375: fence=1029687
5483 cmd: glxgears/23375: fence=1029688
5484 cmd: glxgears/23375: fence=1029689
5485 cmd: glxgears/23375: fence=1029690
5486 cmd: glxgears/23375: fence=1029691
5487 cmd: glxgears/23375: fence=1029692
5488 cmd: glxgears/23375: fence=1029693
5489 cmd: glxgears/23375: fence=1029694
5490 cmd: glxgears/23375: fence=1029695
5491 cmd: glxgears/23375: fence=1029696
5492 cmd: glxgears/23375: fence=1029697
5493 cmd: glxgears/23375: fence=1029698
5494 cmd: glxgears/23375: fence=1029699
5495 cmd: glxgears/23375: fence=1029700
5496 cmd: glxgears/23375: fence=1029701
5497 cmd: glxgears/23375: fence=1029702
5498 cmd: glxgears/23375: fence=1029703
5499 cmd: glxgears/23375: fence=1029704
5500 cmd: glxgears/23375: fence=1029705
5501 cmd: glxgears/23375: fence=1029706
5502 cmd: glxgears/23375: fence=1029707
5503 cmd: glxgears/23375: fence=1029708
5504 cmd: glxgears/23375: fence=1029709
5505 cmd: glxgears/23375: fence=1029710
5506 cmd: glxgears/23375: fence=1029711
5507 cmd: glxgears/23375: fence=1029712
5508 cmd: glxgears/23375: fence=1029713
5509 cmd: glxgears/23375: fence=1029714
5510 cmd: glxgears/23375: fence=1029715
5511 cmd: glxgears/23375: fence=1029716
5512 cmd: glxgears/23375: fence=1029717
5513 cmd: glxgears/23375: fence=1029718
5514 cmd: glxgears/23375: fence=1029719
5515 cmd: glxgears/23375: fence=1029720
5516 cmd: glxgears/23375: fence=1029721
5517 cmd: glxgears/23375: fence=1029722
5518 cmd: glxgears/23375: fence=1029723
5519 cmd: glxgears/23375: fence=1029724
5520 cmd: glxgears/23375: fence=1029725
5521 cmd: glxgears/23375: fence=1029726
5522 cmd: glxgears/23375: fence=1029727
5523 cmd: glxgears/23375: fence=1029728
5524 cmd: glxgears/23375: fence=1029729
5525 cmd: glxgears/23375: fence=1029730
5526 cmd: glxgears/23375: fence=1029731
5527 cmd: glxgears/23375: fence=1029732
5528 cmd: glxgears/23375: fence=1029733
5529 cmd: glxgears/23375: fence=1029734
5530 cmd: glxgears/23375: fence=1029735
5531 cmd: glxgears/23375: fence=1029736
5532 cmd: glxgears/23375: fence=1029737
5533 cmd: glxgears/23375: fence=1029738
5534 cmd: glxgears/23375: fence=1029739
5535 cmd: glxgears/23375: fence=1029740
5536 cmd: glxgears/23375: fence=1029741
5537 cmd: glxgears/23375: fence=1029742
5538 cmd: glxgears/23375: fence=1029743
5539 cmd: glxgears/23375: fence=1029744
5540 cmd: glxgears/23375: fence=1029745
5541 cmd: glxgears/23375: fence=1029746
5542 cmd: glxgears/23375: fence=1029747
5543 cmd: glxgears/23375: fence=1029748
5544 cmd: glxgears/23375: fence=1029749
5545 cmd: glxgears/23375: fence=1029750
5546 cmd: glxgears/23375: fence=1029751
5547 cmd: glxgears/23375: fence=1029752
5548 cmd: glxgears/23375: fence=1029753
5549 cmd: glxgears/23375: fence=1029754
5550 cmd: glxgears/23375: fence=1029755
5551 cmd: glxgears/23375: fence=1029756
5552 cmd: glxgears/23375: fence=1029757
5553 cmd: glxgears/23375: fence=1029758
5554 cmd: glxgears/23375: fence=1029759
5555 cmd: glxgears/23375: fence=1029760
5556 cmd: glxgears/23375: fence=1029761
5557 cmd: glxgears/23375: fence=1029762
5558 cmd: glxgears/23375: fence=1029763
5559 cmd: glxgears/23375: fence=1029764
5560 cmd: glxgears/23375: fence=1029765
5561 cmd: glxgears/23375: fence=1029766
5562 cmd: glxgears/23375: fence=1029767
5563 cmd: glxgears/23375: fence=1029768
5564 cmd: glxgears/23375: fence=1029769
5565 cmd: glxgears/23375: fence=1029770
5566 cmd: glxgears/23375: fence=1029771
5567 cmd: glxgears/23375: fence=1029772
5568 cmd: glxgears/23375: fence=1029773
5569 cmd: glxgears/23375: fence=1029774
5570 cmd: glxgears/23375: fence=1029775
5571 cmd: glxgears/23375: fence=1029776
5572 cmd: glxgears/23375: fence=1029777
5573 cmd: glxgears/23375: fence=1029778
5574 cmd: glxgears/23375: fence=1029779
5575 cmd: glxgears/23375: fence=1029780
5576 cmd: glxgears/23375: fence=1029781
5577 cmd: glxgears/23375: fence=1029782
5578 cmd: glxgears/23375: fence=1029783
5579 cmd: glxgears/23375: fence=1029784
5580 cmd: glxgears/23375: fence=1029785
5581 cmd: glxgears/23375: fence=1029786
5582 cmd: glxgears/23375: fence=1029787
5583 cmd: glxgears/23375: fence=1029788
5584 cmd: glxgears/23375: fence=1029789
5585 cmd: glxgears/23375: fence=1029790
5586 cmd: glxgears/23375: fence=1029791
5587 cmd: glxgears/23375: fence=1029792
5588 cmd: glxgears/23375: fence=1029793
5589 cmd: glxgears/23375: fence=1029794
5590 cmd: glxgears/23375: fence=1029795
5591 cmd: glxgears/23375: fence=1029796
5592 cmd: glxgears/23375: fence=1029797
5593 cmd: glxgears/23375: fence=1029798
5594 cmd: glxgears/23375: fence=1029799
5595 cmd: glxgears/23375: fence=1029800
5596 cmd: glxgears/23375: fence=1029801
5597 cmd: glxgears/23375: fence=1029802
5598 cmd: glxgears/23375: fence=1029803
5599 cmd: glxgears/23375: fence=1029804
5600 cmd: glxgears/23375: fence=1029805
5601 cmd: glxgears/23375: fence=1029806
5602 cmd: glxgears/23375: fence=1029807
5603 cmd: glxgears/23375: fence=1029808
5604 cmd: glxgears/23375: fence=1029809
5605 cmd: glxgears/23375: fence=1029810
5606 cmd: glxgears/23375: fence=1029811
5607 cmd: glxgears/23375: fence=1029812
5608 cmd: glxgears/23375: fence=1029813
5609 cmd: glxgears/23375: fence=1029814
5610 cmd: glxgears/23375: fence=1029815
5611 cmd: glxgears/23375: fence=1029816
5612 cmd: glxgears/23375: fence=1029817
5613 cmd: glxgears/23375: fence=1029818
5614 cmd: glxgears/23375: fence=1029819
5615 cmd: glxgears/23375: fence=1029820
5616 cmd: glxgears/23375: fence=1029821
5617 cmd: glxgears/23375: fence=1029822
5618 cmd: glxgears/23375: fence=1029823
5619 cmd: glxgears/23375: fence=1029824
5620 cmd: glxgears/23375: fence=1029825
5621 cmd: glxgears/23375: fence=1029826
5622 cmd: glxgears/23375: fence=1029827
5623 cmd: glxgears/23375: fence=1029828
5624 cmd: X/23360: fence=1029829
5625 cmd: glxgears/23375: fence=1029830
5626 cmd: glxgears/23375: fence=1029831
5627 cmd: X/23360: fence=1029832
5628 cmd: glxgears/23375: fence=1029833
5629 cmd: glxgears/23375: fence=1029834
5630 cmd: X/23360: fence=1029835
5631 cmd: glxgears/23375: fence=1029836
5632 cmd: glxgears/23375: fence=1029837
5633 cmd: X/23360: fence=1029838
5634 cmd: glxgears/23375: fence=1029839
5635 cmd: glxgears/23375: fence=1029840
5636 cmd: X/23360: fence=1029841
5637 cmd: glxgears/23375: fence=1029842
5638 cmd: glxgears/23375: fence=1029843
5639 cmd: X/23360: fence=1029844
5640 cmd: glxgears/23375: fence=1029845
5641 cmd: glxgears/23375: fence=1029846
5642 cmd: X/23360: fence=1029847