src/freedreno/.gitlab-ci/traces/afuc_test.asm

   1 ; Copyright (c) 2020 Valve Corporation
   2 ;
   3 ; Permission is hereby granted, free of charge, to any person obtaining a
   4 ; copy of this software and associated documentation files (the "Software"),
   5 ; to deal in the Software without restriction, including without limitation
   6 ; the rights to use, copy, modify, merge, publish, distribute, sublicense,
   7 ; and/or sell copies of the Software, and to permit persons to whom the
   8 ; Software is furnished to do so, subject to the following conditions:
   9 ;
  10 ; The above copyright notice and this permission notice (including the next
  11 ; paragraph) shall be included in all copies or substantial portions of the
  12 ; Software.
  13 ;
  14 ; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 ; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 ; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 ; THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18 ; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  19 ; OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20 ; SOFTWARE.
  21 ;
  22 ;
  23 ; This file is the source for a simple mock firmware used to regression test
  24 ; the afuc assembler/disassembler. Note, it won't actually work if you try to
  25 ; load it on the GPU! First this is assembled, compared to the reference
  26 ; binary, then disassambled and compared to the reference disassembly. We do
  27 ; this to avoid having to host the actual firmware, especially the disassembled
  28 ; version, in Mesa.
  29 [01000001]
  30 [01000000]
  31 loc02:
  32 mov $02, 0x883
  33 mov $03, 0xbeef
  34 mov $04, 0xdead << 16
  35 or $03, $03, $04
  36 cwrite $02, [$00 + @REG_WRITE_ADDR], 0x0
  37 cwrite $03, [$00 + @REG_WRITE], 0x0
  38 waitin
  39 mov $01, $data
  40
  41 CP_ME_INIT:
  42 ; test label-as-immediate feature
  43 mov $02, #loc02 ; should be 0x0002
  44 waitin
  45 mov $01, $data
  46
  47 CP_MEM_WRITE:
  48 ; test $addr + (rep) + (xmovN) with ALU
  49 mov $addr, 0xa0 << 24
  50 mov $02, 4
  51 (xmov1)add $data, $02, $data
  52 mov $addr, 0xa204 << 16
  53 (rep)(xmov3)mov $data, $data
  54 waitin
  55 mov $01, $data
  56
  57 CP_SCRATCH_WRITE:
  58 ; test (rep) + flags + non-zero offset with cwrite
  59 ; TODO: 0x4 flag is actually pre-increment addressing, handle it as such
  60 mov $02, 0xff
  61 (rep)cwrite $data, [$02 + 0x001], 0x4
  62 waitin
  63 mov $01, $data
  64
  65 CP_SET_SECURE_MODE:
  66 ; test setsecure
  67 mov $02, $data
  68 setsecure $02, #setsecure_success
  69 err:
  70 jump #err
  71 nop
  72 setsecure_success:
  73 waitin
  74 mov $01, $data
  75
  76 euclid:
  77 ; Euclid's algorithm in afuc: https://en.wikipedia.org/wiki/Euclidean_algorithm
  78 ; Since afuc doesn't do modulo, we implement the subtraction-based version.
  79 ;
  80 ; Demonstrates/tests comparisons and conditional branches. This also
  81 ; demonstrates the common trick of branching in a delay slot. Note that if a
  82 ; branch is taken and its delay slot includes another branch, the second
  83 ; branch cannot also be taken, which is why the last branch in the sequence
  84 ; cannot be unconditional.
  85 ;
  86 ; Inputs are in $02 and $03, and output is in $02.
  87 cmp $04, $02, $03
  88 breq $04, b0, #euclid_exit
  89 brne $04, b1, #euclid_gt
  90 breq $04, b2, #euclid
  91 sub $03, $03, $02
  92 euclid_gt:
  93 jump #euclid
  94 sub $02, $02, $03
  95 euclid_exit:
  96 ret
  97 nop
  98
  99 CP_REG_RMW:
 100 ; Test various ALU instructions, and read/write $addr2
 101 cwrite $data, [$00 + @REG_READ_ADDR], 0x0
 102 add $02, $addr2, 0x42
 103 addhi $03, $00, $addr2
 104 sub $02, $02, $addr2
 105 call #euclid
 106 subhi $03, $03, $addr2
 107 and $02, $02, $addr2
 108 or $02, $02, 0x1
 109 xor $02, $02, 0x1
 110 not $02, $02
 111 shl $02, $02, $addr2
 112 ushr $02, $02, $addr2
 113 ishr $02, $02, $addr2
 114 rot $02, $02, $addr2
 115 min $02, $02, $addr2
 116 max $02, $02, $addr2
 117 mul8 $02, $02, $addr2
 118 msb $02, $02
 119 mov $addr2, $data
 120 mov $data, $02
 121 waitin
 122 mov $01, $data
 123
 124 CP_MEMCPY:
 125 ; implement CP_MEMCPY using load/store instructions
 126 mov $02, $data
 127 mov $03, $data
 128 mov $04, $data
 129 mov $05, $data
 130 mov $06, $data
 131 cpy_header:
 132 breq $06, 0, #cpy_exit
 133 cwrite $03, [$00 + @LOAD_STORE_HI], 0x0
 134 load $07, [$02 + 0x004], 0x4
 135 cwrite $05, [$00 + @LOAD_STORE_HI], 0x0
 136 jump #cpy_header
 137 store $07, [$04 + 0x004], 0x4
 138 cpy_exit:
 139 waitin
 140 mov $01, $data
 141
 142 CP_MEM_TO_MEM:
 143 ; implement CP_MEMCPY using mem read control regs
 144 ; tests @FOO+0x1 for 64-bit control regs, and reading/writing $rem
 145 cwrite $data, [$00 + @MEM_READ_ADDR], 0x0
 146 cwrite $data, [$00 + @MEM_READ_ADDR+1], 0x0
 147 mov $02, $data
 148 cwrite $data, [$00 + @LOAD_STORE_HI], 0x0
 149 mov $rem, $data
 150 cwrite $rem, [$00 + @MEM_READ_DWORDS], 0x0
 151 (rep)store $addr, [$02 + 0x004], 0x4
 152 waitin
 153 mov $01, $data
 154
 155 UNKN15:
 156 ; test preemptleave + iret + conditional branch w/ immed
 157 cread $02, [$00 + 0x101], 0x0
 158 brne $02, 0x0001, #exit_iret
 159 nop
 160 preemptleave #err
 161 nop
 162 nop
 163 nop
 164 waitin
 165 mov $01, $data
 166 exit_iret:
 167 iret
 168 nop
 169
 170 UNKN0:
 171 UNKN1:
 172 UNKN2:
 173 UNKN3:
 174 PKT4:
 175 UNKN5:
 176 UNKN6:
 177 UNKN7:
 178 UNKN8:
 179 UNKN9:
 180 UNKN10:
 181 UNKN11:
 182 UNKN12:
 183 UNKN13:
 184 UNKN14:
 185 CP_NOP:
 186 CP_RECORD_PFP_TIMESTAMP:
 187 CP_WAIT_MEM_WRITES:
 188 CP_WAIT_FOR_ME:
 189 CP_WAIT_MEM_GTE:
 190 UNKN21:
 191 UNKN22:
 192 UNKN23:
 193 UNKN24:
 194 CP_DRAW_PRED_ENABLE_GLOBAL:
 195 CP_DRAW_PRED_ENABLE_LOCAL:
 196 UNKN27:
 197 CP_PREEMPT_ENABLE:
 198 CP_SKIP_IB2_ENABLE_GLOBAL:
 199 CP_PREEMPT_TOKEN:
 200 UNKN31:
 201 UNKN32:
 202 CP_DRAW_INDX:
 203 CP_SKIP_IB2_ENABLE_LOCAL:
 204 CP_DRAW_AUTO:
 205 CP_SET_STATE:
 206 CP_WAIT_FOR_IDLE:
 207 CP_IM_LOAD:
 208 CP_DRAW_INDIRECT:
 209 CP_DRAW_INDX_INDIRECT:
 210 CP_DRAW_INDIRECT_MULTI:
 211 CP_IM_LOAD_IMMEDIATE:
 212 CP_BLIT:
 213 CP_SET_CONSTANT:
 214 CP_SET_BIN_DATA5_OFFSET:
 215 CP_SET_BIN_DATA5:
 216 UNKN48:
 217 CP_RUN_OPENCL:
 218 CP_LOAD_STATE6_GEOM:
 219 CP_EXEC_CS:
 220 CP_LOAD_STATE6_FRAG:
 221 CP_SET_SUBDRAW_SIZE:
 222 CP_LOAD_STATE6:
 223 CP_INDIRECT_BUFFER_PFD:
 224 CP_DRAW_INDX_OFFSET:
 225 CP_REG_TEST:
 226 CP_COND_INDIRECT_BUFFER_PFE:
 227 CP_INVALIDATE_STATE:
 228 CP_WAIT_REG_MEM:
 229 CP_REG_TO_MEM:
 230 CP_INDIRECT_BUFFER:
 231 CP_INTERRUPT:
 232 CP_EXEC_CS_INDIRECT:
 233 CP_MEM_TO_REG:
 234 CP_SET_DRAW_STATE:
 235 CP_COND_EXEC:
 236 CP_COND_WRITE5:
 237 CP_EVENT_WRITE:
 238 CP_COND_REG_EXEC:
 239 UNKN73:
 240 CP_REG_TO_SCRATCH:
 241 CP_SET_DRAW_INIT_FLAGS:
 242 CP_SCRATCH_TO_REG:
 243 CP_DRAW_PRED_SET:
 244 CP_MEM_WRITE_CNTR:
 245 UNKN80:
 246 CP_SET_BIN_SELECT:
 247 CP_WAIT_REG_EQ:
 248 CP_SMMU_TABLE_UPDATE:
 249 UNKN84:
 250 CP_SET_CTXSWITCH_IB:
 251 CP_SET_PSEUDO_REG:
 252 CP_INDIRECT_BUFFER_CHAIN:
 253 CP_EVENT_WRITE_SHD:
 254 CP_EVENT_WRITE_CFL:
 255 UNKN90:
 256 CP_EVENT_WRITE_ZPD:
 257 CP_CONTEXT_REG_BUNCH:
 258 CP_WAIT_IB_PFD_COMPLETE:
 259 CP_CONTEXT_UPDATE:
 260 CP_SET_PROTECTED_MODE:
 261 UNKN96:
 262 UNKN97:
 263 UNKN98:
 264 CP_SET_MODE:
 265 CP_SET_VISIBILITY_OVERRIDE:
 266 CP_SET_MARKER:
 267 UNKN103:
 268 UNKN104:
 269 UNKN105:
 270 UNKN106:
 271 UNKN107:
 272 UNKN108:
 273 CP_REG_WRITE:
 274 UNKN110:
 275 CP_BOOTSTRAP_UCODE:
 276 CP_WAIT_TWO_REGS:
 277 CP_TEST_TWO_MEMS:
 278 CP_REG_TO_MEM_OFFSET_REG:
 279 CP_REG_TO_MEM_OFFSET_MEM:
 280 UNKN118:
 281 UNKN119:
 282 CP_REG_WR_NO_CTXT:
 283 UNKN121:
 284 UNKN122:
 285 UNKN123:
 286 UNKN124:
 287 UNKN125:
 288 UNKN126:
 289 UNKN127:
 290         waitin
 291         mov $01, $data