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23 ; This file is the source for a simple mock firmware used to regression test
24 ; the afuc assembler/disassembler. Note, it won't actually work if you try to
25 ; load it on the GPU! First this is assembled, compared to the reference
26 ; binary, then disassambled and compared to the reference disassembly. We do
27 ; this to avoid having to host the actual firmware, especially the disassembled
36 cwrite $02, [$00 + @REG_WRITE_ADDR], 0x0
37 cwrite $03, [$00 + @REG_WRITE], 0x0
42 ; test label-as-immediate feature
43 mov $02, #loc02 ; should be 0x0002
48 ; test $addr + (rep) + (xmovN) with ALU
51 (xmov1)add $data, $02, $data
52 mov $addr, 0xa204 << 16
53 (rep)(xmov3)mov $data, $data
58 ; test (rep) + flags + non-zero offset with cwrite
59 ; TODO: 0x4 flag is actually pre-increment addressing, handle it as such
61 (rep)cwrite $data, [$02 + 0x001], 0x4
68 setsecure $02, #setsecure_success
77 ; Euclid's algorithm in afuc: https://en.wikipedia.org/wiki/Euclidean_algorithm
78 ; Since afuc doesn't do modulo, we implement the subtraction-based version.
80 ; Demonstrates/tests comparisons and conditional branches. This also
81 ; demonstrates the common trick of branching in a delay slot. Note that if a
82 ; branch is taken and its delay slot includes another branch, the second
83 ; branch cannot also be taken, which is why the last branch in the sequence
84 ; cannot be unconditional.
86 ; Inputs are in $02 and $03, and output is in $02.
88 breq $04, b0, #euclid_exit
89 brne $04, b1, #euclid_gt
100 ; Test various ALU instructions, and read/write $addr2
101 cwrite $data, [$00 + @REG_READ_ADDR], 0x0
102 add $02, $addr2, 0x42
103 addhi $03, $00, $addr2
106 subhi $03, $03, $addr2
112 ushr $02, $02, $addr2
113 ishr $02, $02, $addr2
117 mul8 $02, $02, $addr2
125 ; implement CP_MEMCPY using load/store instructions
132 breq $06, 0, #cpy_exit
133 cwrite $03, [$00 + @LOAD_STORE_HI], 0x0
134 load $07, [$02 + 0x004], 0x4
135 cwrite $05, [$00 + @LOAD_STORE_HI], 0x0
137 store $07, [$04 + 0x004], 0x4
143 ; implement CP_MEMCPY using mem read control regs
144 ; tests @FOO+0x1 for 64-bit control regs, and reading/writing $rem
145 cwrite $data, [$00 + @MEM_READ_ADDR], 0x0
146 cwrite $data, [$00 + @MEM_READ_ADDR+1], 0x0
148 cwrite $data, [$00 + @LOAD_STORE_HI], 0x0
150 cwrite $rem, [$00 + @MEM_READ_DWORDS], 0x0
151 (rep)store $addr, [$02 + 0x004], 0x4
156 ; test preemptleave + iret + conditional branch w/ immed
157 cread $02, [$00 + 0x101], 0x0
158 brne $02, 0x0001, #exit_iret
186 CP_RECORD_PFP_TIMESTAMP:
194 CP_DRAW_PRED_ENABLE_GLOBAL:
195 CP_DRAW_PRED_ENABLE_LOCAL:
198 CP_SKIP_IB2_ENABLE_GLOBAL:
203 CP_SKIP_IB2_ENABLE_LOCAL:
209 CP_DRAW_INDX_INDIRECT:
210 CP_DRAW_INDIRECT_MULTI:
211 CP_IM_LOAD_IMMEDIATE:
214 CP_SET_BIN_DATA5_OFFSET:
223 CP_INDIRECT_BUFFER_PFD:
226 CP_COND_INDIRECT_BUFFER_PFE:
241 CP_SET_DRAW_INIT_FLAGS:
248 CP_SMMU_TABLE_UPDATE:
252 CP_INDIRECT_BUFFER_CHAIN:
257 CP_CONTEXT_REG_BUNCH:
258 CP_WAIT_IB_PFD_COMPLETE:
260 CP_SET_PROTECTED_MODE:
265 CP_SET_VISIBILITY_OVERRIDE:
278 CP_REG_TO_MEM_OFFSET_REG:
279 CP_REG_TO_MEM_OFFSET_MEM: