2 * Copyright © 2020 Google, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include "ir3/ir3_compiler.h"
26 #include "util/u_math.h"
28 #include "registers/adreno_pm4.xml.h"
29 #include "registers/adreno_common.xml.h"
30 #include "registers/a6xx.xml.h"
38 struct ir3_compiler
*compiler
;
39 struct fd_device
*dev
;
42 struct fd_bo
*control_mem
;
44 struct fd_bo
*query_mem
;
45 const struct perfcntr
*perfcntrs
;
46 unsigned num_perfcntrs
;
48 define_cast(backend
, a6xx_backend
);
51 * Data structures shared with GPU:
54 /* This struct defines the layout of the fd6_context::control buffer: */
56 uint32_t seqno
; /* seqno for async CP_EVENT_WRITE, etc */
58 volatile uint32_t vsc_overflow
;
60 /* flag set from cmdstream when VSC overflow detected: */
66 /* scratch space for VPC_SO[i].FLUSH_BASE_LO/HI, start on 32 byte boundary. */
73 #define control_ptr(a6xx_backend, member) \
74 (a6xx_backend)->control_mem, offsetof(struct fd6_control, member), 0, 0
77 struct PACKED fd6_query_sample
{
84 /* offset of a single field of an array of fd6_query_sample: */
85 #define query_sample_idx(a6xx_backend, idx, field) \
86 (a6xx_backend)->query_mem, \
87 (idx * sizeof(struct fd6_query_sample)) + \
88 offsetof(struct fd6_query_sample, field), \
93 * Backend implementation:
96 static struct kernel
*
97 a6xx_assemble(struct backend
*b
, FILE *in
)
99 struct a6xx_backend
*a6xx_backend
= to_a6xx_backend(b
);
100 struct ir3_kernel
*ir3_kernel
=
101 ir3_asm_assemble(a6xx_backend
->compiler
, in
);
102 ir3_kernel
->backend
= b
;
103 return &ir3_kernel
->base
;
107 a6xx_disassemble(struct kernel
*kernel
, FILE *out
)
109 ir3_asm_disassemble(to_ir3_kernel(kernel
), out
);
113 cs_program_emit(struct fd_ringbuffer
*ring
, struct kernel
*kernel
)
115 struct ir3_kernel
*ir3_kernel
= to_ir3_kernel(kernel
);
116 struct ir3_shader_variant
*v
= ir3_kernel
->v
;
117 const struct ir3_info
*i
= &v
->info
;
118 enum a3xx_threadsize thrsz
= FOUR_QUADS
;
120 OUT_PKT4(ring
, REG_A6XX_HLSQ_UPDATE_CNTL
, 1);
121 OUT_RING(ring
, 0xff);
123 unsigned constlen
= align(v
->constlen
, 4);
124 OUT_PKT4(ring
, REG_A6XX_HLSQ_CS_CNTL
, 1);
125 OUT_RING(ring
, A6XX_HLSQ_CS_CNTL_CONSTLEN(constlen
) |
126 A6XX_HLSQ_CS_CNTL_ENABLED
);
128 OUT_PKT4(ring
, REG_A6XX_SP_CS_CONFIG
, 2);
129 OUT_RING(ring
, A6XX_SP_CS_CONFIG_ENABLED
|
130 A6XX_SP_CS_CONFIG_NIBO(kernel
->num_bufs
) |
131 A6XX_SP_CS_CONFIG_NTEX(v
->num_samp
) |
132 A6XX_SP_CS_CONFIG_NSAMP(v
->num_samp
)); /* SP_VS_CONFIG */
133 OUT_RING(ring
, v
->instrlen
); /* SP_VS_INSTRLEN */
135 OUT_PKT4(ring
, REG_A6XX_SP_CS_CTRL_REG0
, 1);
136 OUT_RING(ring
, A6XX_SP_CS_CTRL_REG0_THREADSIZE(thrsz
) |
137 A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(i
->max_reg
+ 1) |
138 A6XX_SP_CS_CTRL_REG0_MERGEDREGS
|
139 A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(v
->branchstack
) |
140 COND(v
->need_pixlod
, A6XX_SP_CS_CTRL_REG0_PIXLODENABLE
));
142 OUT_PKT4(ring
, REG_A6XX_SP_CS_UNKNOWN_A9B1
, 1);
143 OUT_RING(ring
, 0x41);
145 uint32_t local_invocation_id
, work_group_id
;
146 local_invocation_id
= ir3_find_sysval_regid(v
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
);
147 work_group_id
= ir3_find_sysval_regid(v
, SYSTEM_VALUE_WORK_GROUP_ID
);
149 OUT_PKT4(ring
, REG_A6XX_HLSQ_CS_CNTL_0
, 2);
150 OUT_RING(ring
, A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id
) |
151 A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
152 A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
153 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id
));
154 OUT_RING(ring
, 0x2fc); /* HLSQ_CS_UNKNOWN_B998 */
156 OUT_PKT4(ring
, REG_A6XX_SP_CS_OBJ_START_LO
, 2);
157 OUT_RELOC(ring
, v
->bo
, 0, 0, 0); /* SP_CS_OBJ_START_LO/HI */
159 OUT_PKT4(ring
, REG_A6XX_SP_CS_INSTRLEN
, 1);
160 OUT_RING(ring
, v
->instrlen
);
162 OUT_PKT4(ring
, REG_A6XX_SP_CS_OBJ_START_LO
, 2);
163 OUT_RELOC(ring
, v
->bo
, 0, 0, 0);
165 OUT_PKT7(ring
, CP_LOAD_STATE6_FRAG
, 3);
166 OUT_RING(ring
, CP_LOAD_STATE6_0_DST_OFF(0) |
167 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER
) |
168 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
169 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_CS_SHADER
) |
170 CP_LOAD_STATE6_0_NUM_UNIT(v
->instrlen
));
171 OUT_RELOCD(ring
, v
->bo
, 0, 0, 0);
175 emit_const(struct fd_ringbuffer
*ring
, uint32_t regid
,
176 uint32_t sizedwords
, const uint32_t *dwords
)
180 debug_assert((regid
% 4) == 0);
182 align_sz
= align(sizedwords
, 4);
184 OUT_PKT7(ring
, CP_LOAD_STATE6_FRAG
, 3 + align_sz
);
185 OUT_RING(ring
, CP_LOAD_STATE6_0_DST_OFF(regid
/4) |
186 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
187 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
188 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_CS_SHADER
) |
189 CP_LOAD_STATE6_0_NUM_UNIT(DIV_ROUND_UP(sizedwords
, 4)));
190 OUT_RING(ring
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
191 OUT_RING(ring
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
193 for (uint32_t i
= 0; i
< sizedwords
; i
++) {
194 OUT_RING(ring
, dwords
[i
]);
197 /* Zero-pad to multiple of 4 dwords */
198 for (uint32_t i
= sizedwords
; i
< align_sz
; i
++) {
205 cs_const_emit(struct fd_ringbuffer
*ring
, struct kernel
*kernel
, uint32_t grid
[3])
207 struct ir3_kernel
*ir3_kernel
= to_ir3_kernel(kernel
);
208 struct ir3_shader_variant
*v
= ir3_kernel
->v
;
210 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
211 uint32_t base
= const_state
->offsets
.immediate
;
212 int size
= const_state
->immediates_count
;
214 if (ir3_kernel
->info
.numwg
!= INVALID_REG
) {
215 assert((ir3_kernel
->info
.numwg
& 0x3) == 0);
216 int idx
= ir3_kernel
->info
.numwg
>> 2;
217 const_state
->immediates
[idx
].val
[0] = grid
[0];
218 const_state
->immediates
[idx
].val
[1] = grid
[1];
219 const_state
->immediates
[idx
].val
[2] = grid
[2];
222 /* truncate size to avoid writing constants that shader
225 size
= MIN2(size
+ base
, v
->constlen
) - base
;
227 /* convert out of vec4: */
232 emit_const(ring
, base
, size
, const_state
->immediates
[0].val
);
237 cs_ibo_emit(struct fd_ringbuffer
*ring
, struct fd_submit
*submit
,
238 struct kernel
*kernel
)
240 struct fd_ringbuffer
*state
=
241 fd_submit_new_ringbuffer(submit
,
242 kernel
->num_bufs
* 16 * 4,
243 FD_RINGBUFFER_STREAMING
);
245 for (unsigned i
= 0; i
< kernel
->num_bufs
; i
++) {
246 /* size is encoded with low 15b in WIDTH and high bits in HEIGHT,
247 * in units of elements:
249 unsigned sz
= kernel
->buf_sizes
[i
];
250 unsigned width
= sz
& MASK(15);
251 unsigned height
= sz
>> 15;
253 OUT_RING(state
, A6XX_IBO_0_FMT(FMT6_32_UINT
) |
254 A6XX_IBO_0_TILE_MODE(0));
255 OUT_RING(state
, A6XX_IBO_1_WIDTH(width
) |
256 A6XX_IBO_1_HEIGHT(height
));
257 OUT_RING(state
, A6XX_IBO_2_PITCH(0) |
258 A6XX_IBO_2_UNK4
| A6XX_IBO_2_UNK31
|
259 A6XX_IBO_2_TYPE(A6XX_TEX_1D
));
260 OUT_RING(state
, A6XX_IBO_3_ARRAY_PITCH(0));
261 OUT_RELOCW(state
, kernel
->bufs
[i
], 0, 0, 0);
262 OUT_RING(state
, 0x00000000);
263 OUT_RING(state
, 0x00000000);
264 OUT_RING(state
, 0x00000000);
265 OUT_RING(state
, 0x00000000);
266 OUT_RING(state
, 0x00000000);
267 OUT_RING(state
, 0x00000000);
268 OUT_RING(state
, 0x00000000);
269 OUT_RING(state
, 0x00000000);
270 OUT_RING(state
, 0x00000000);
271 OUT_RING(state
, 0x00000000);
274 OUT_PKT7(ring
, CP_LOAD_STATE6_FRAG
, 3);
275 OUT_RING(ring
, CP_LOAD_STATE6_0_DST_OFF(0) |
276 CP_LOAD_STATE6_0_STATE_TYPE(ST6_IBO
) |
277 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
278 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_CS_SHADER
) |
279 CP_LOAD_STATE6_0_NUM_UNIT(kernel
->num_bufs
));
282 OUT_PKT4(ring
, REG_A6XX_SP_CS_IBO_LO
, 2);
285 OUT_PKT4(ring
, REG_A6XX_SP_CS_IBO_COUNT
, 1);
286 OUT_RING(ring
, kernel
->num_bufs
);
288 fd_ringbuffer_del(state
);
291 static inline unsigned
292 event_write(struct fd_ringbuffer
*ring
, struct kernel
*kernel
,
293 enum vgt_event_type evt
, bool timestamp
)
297 OUT_PKT7(ring
, CP_EVENT_WRITE
, timestamp
? 4 : 1);
298 OUT_RING(ring
, CP_EVENT_WRITE_0_EVENT(evt
));
300 struct ir3_kernel
*ir3_kernel
= to_ir3_kernel(kernel
);
301 struct a6xx_backend
*a6xx_backend
= to_a6xx_backend(ir3_kernel
->backend
);
302 seqno
= ++a6xx_backend
->seqno
;
303 OUT_RELOCW(ring
, control_ptr(a6xx_backend
, seqno
)); /* ADDR_LO/HI */
304 OUT_RING(ring
, seqno
);
311 cache_flush(struct fd_ringbuffer
*ring
, struct kernel
*kernel
)
313 struct ir3_kernel
*ir3_kernel
= to_ir3_kernel(kernel
);
314 struct a6xx_backend
*a6xx_backend
= to_a6xx_backend(ir3_kernel
->backend
);
317 seqno
= event_write(ring
, kernel
, RB_DONE_TS
, true);
319 OUT_PKT7(ring
, CP_WAIT_REG_MEM
, 6);
320 OUT_RING(ring
, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ
) |
321 CP_WAIT_REG_MEM_0_POLL_MEMORY
);
322 OUT_RELOC(ring
, control_ptr(a6xx_backend
, seqno
));
323 OUT_RING(ring
, CP_WAIT_REG_MEM_3_REF(seqno
));
324 OUT_RING(ring
, CP_WAIT_REG_MEM_4_MASK(~0));
325 OUT_RING(ring
, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(16));
327 seqno
= event_write(ring
, kernel
, CACHE_FLUSH_TS
, true);
329 OUT_PKT7(ring
, CP_WAIT_MEM_GTE
, 4);
330 OUT_RING(ring
, CP_WAIT_MEM_GTE_0_RESERVED(0));
331 OUT_RELOC(ring
, control_ptr(a6xx_backend
, seqno
));
332 OUT_RING(ring
, CP_WAIT_MEM_GTE_3_REF(seqno
));
336 a6xx_emit_grid(struct kernel
*kernel
, uint32_t grid
[3], struct fd_submit
*submit
)
338 struct ir3_kernel
*ir3_kernel
= to_ir3_kernel(kernel
);
339 struct a6xx_backend
*a6xx_backend
= to_a6xx_backend(ir3_kernel
->backend
);
340 struct fd_ringbuffer
*ring
= fd_submit_new_ringbuffer(submit
, 0,
341 FD_RINGBUFFER_PRIMARY
| FD_RINGBUFFER_GROWABLE
);
343 cs_program_emit(ring
, kernel
);
344 cs_const_emit(ring
, kernel
, grid
);
345 cs_ibo_emit(ring
, submit
, kernel
);
347 OUT_PKT7(ring
, CP_SET_MARKER
, 1);
348 OUT_RING(ring
, A6XX_CP_SET_MARKER_0_MODE(RM6_COMPUTE
));
350 const unsigned *local_size
= kernel
->local_size
;
351 const unsigned *num_groups
= grid
;
353 unsigned work_dim
= 0;
354 for (int i
= 0; i
< 3; i
++) {
360 OUT_PKT4(ring
, REG_A6XX_HLSQ_CS_NDRANGE_0
, 7);
361 OUT_RING(ring
, A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(work_dim
) |
362 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(local_size
[0] - 1) |
363 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(local_size
[1] - 1) |
364 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(local_size
[2] - 1));
365 OUT_RING(ring
, A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(local_size
[0] * num_groups
[0]));
366 OUT_RING(ring
, 0); /* HLSQ_CS_NDRANGE_2_GLOBALOFF_X */
367 OUT_RING(ring
, A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(local_size
[1] * num_groups
[1]));
368 OUT_RING(ring
, 0); /* HLSQ_CS_NDRANGE_4_GLOBALOFF_Y */
369 OUT_RING(ring
, A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(local_size
[2] * num_groups
[2]));
370 OUT_RING(ring
, 0); /* HLSQ_CS_NDRANGE_6_GLOBALOFF_Z */
372 OUT_PKT4(ring
, REG_A6XX_HLSQ_CS_KERNEL_GROUP_X
, 3);
373 OUT_RING(ring
, 1); /* HLSQ_CS_KERNEL_GROUP_X */
374 OUT_RING(ring
, 1); /* HLSQ_CS_KERNEL_GROUP_Y */
375 OUT_RING(ring
, 1); /* HLSQ_CS_KERNEL_GROUP_Z */
377 if (a6xx_backend
->num_perfcntrs
> 0) {
378 a6xx_backend
->query_mem
= fd_bo_new(a6xx_backend
->dev
,
379 a6xx_backend
->num_perfcntrs
* sizeof(struct fd6_query_sample
),
380 DRM_FREEDRENO_GEM_TYPE_KMEM
, "query");
382 /* configure the performance counters to count the requested
385 for (unsigned i
= 0; i
< a6xx_backend
->num_perfcntrs
; i
++) {
386 const struct perfcntr
*counter
= &a6xx_backend
->perfcntrs
[i
];
388 OUT_PKT4(ring
, counter
->select_reg
, 1);
389 OUT_RING(ring
, counter
->selector
);
392 OUT_PKT7(ring
, CP_WAIT_FOR_IDLE
, 0);
394 /* and snapshot the start values: */
395 for (unsigned i
= 0; i
< a6xx_backend
->num_perfcntrs
; i
++) {
396 const struct perfcntr
*counter
= &a6xx_backend
->perfcntrs
[i
];
398 OUT_PKT7(ring
, CP_REG_TO_MEM
, 3);
399 OUT_RING(ring
, CP_REG_TO_MEM_0_64B
|
400 CP_REG_TO_MEM_0_REG(counter
->counter_reg_lo
));
401 OUT_RELOCW(ring
, query_sample_idx(a6xx_backend
, i
, start
));
405 OUT_PKT7(ring
, CP_EXEC_CS
, 4);
406 OUT_RING(ring
, 0x00000000);
407 OUT_RING(ring
, CP_EXEC_CS_1_NGROUPS_X(grid
[0]));
408 OUT_RING(ring
, CP_EXEC_CS_2_NGROUPS_Y(grid
[1]));
409 OUT_RING(ring
, CP_EXEC_CS_3_NGROUPS_Z(grid
[2]));
411 OUT_PKT7(ring
, CP_WAIT_FOR_IDLE
, 0);
413 if (a6xx_backend
->num_perfcntrs
> 0) {
414 /* snapshot the end values: */
415 for (unsigned i
= 0; i
< a6xx_backend
->num_perfcntrs
; i
++) {
416 const struct perfcntr
*counter
= &a6xx_backend
->perfcntrs
[i
];
418 OUT_PKT7(ring
, CP_REG_TO_MEM
, 3);
419 OUT_RING(ring
, CP_REG_TO_MEM_0_64B
|
420 CP_REG_TO_MEM_0_REG(counter
->counter_reg_lo
));
421 OUT_RELOCW(ring
, query_sample_idx(a6xx_backend
, i
, stop
));
424 /* and compute the result: */
425 for (unsigned i
= 0; i
< a6xx_backend
->num_perfcntrs
; i
++) {
426 /* result += stop - start: */
427 OUT_PKT7(ring
, CP_MEM_TO_MEM
, 9);
428 OUT_RING(ring
, CP_MEM_TO_MEM_0_DOUBLE
|
429 CP_MEM_TO_MEM_0_NEG_C
);
430 OUT_RELOCW(ring
, query_sample_idx(a6xx_backend
, i
, result
)); /* dst */
431 OUT_RELOC(ring
, query_sample_idx(a6xx_backend
, i
, result
)); /* srcA */
432 OUT_RELOC(ring
, query_sample_idx(a6xx_backend
, i
, stop
)); /* srcB */
433 OUT_RELOC(ring
, query_sample_idx(a6xx_backend
, i
, start
)); /* srcC */
437 cache_flush(ring
, kernel
);
441 a6xx_set_perfcntrs(struct backend
*b
, const struct perfcntr
*perfcntrs
,
442 unsigned num_perfcntrs
)
444 struct a6xx_backend
*a6xx_backend
= to_a6xx_backend(b
);
446 a6xx_backend
->perfcntrs
= perfcntrs
;
447 a6xx_backend
->num_perfcntrs
= num_perfcntrs
;
451 a6xx_read_perfcntrs(struct backend
*b
, uint64_t *results
)
453 struct a6xx_backend
*a6xx_backend
= to_a6xx_backend(b
);
455 fd_bo_cpu_prep(a6xx_backend
->query_mem
, NULL
, DRM_FREEDRENO_PREP_READ
);
456 struct fd6_query_sample
*samples
= fd_bo_map(a6xx_backend
->query_mem
);
458 for (unsigned i
= 0; i
< a6xx_backend
->num_perfcntrs
; i
++) {
459 results
[i
] = samples
[i
].result
;
464 a6xx_init(struct fd_device
*dev
, uint32_t gpu_id
)
466 struct a6xx_backend
*a6xx_backend
= calloc(1, sizeof(*a6xx_backend
));
468 a6xx_backend
->base
= (struct backend
) {
469 .assemble
= a6xx_assemble
,
470 .disassemble
= a6xx_disassemble
,
471 .emit_grid
= a6xx_emit_grid
,
472 .set_perfcntrs
= a6xx_set_perfcntrs
,
473 .read_perfcntrs
= a6xx_read_perfcntrs
,
476 a6xx_backend
->compiler
= ir3_compiler_create(dev
, gpu_id
);
477 a6xx_backend
->dev
= dev
;
479 a6xx_backend
->control_mem
= fd_bo_new(dev
, 0x1000,
480 DRM_FREEDRENO_GEM_TYPE_KMEM
, "control");
482 return &a6xx_backend
->base
;