2 * Copyright (c) 2012 Rob Clark <robdclark@gmail.com>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 #include "instr-a2xx.h"
33 static const char *levels
[] = {
54 static struct rnn
*rnn
;
60 static const char chan_names
[] = {
62 /* these only apply to FETCH dst's: */
66 static void print_srcreg(uint32_t num
, uint32_t type
,
67 uint32_t swiz
, uint32_t negate
, uint32_t abs
)
73 printf("%c%u", type
? 'R' : 'C', num
);
77 for (i
= 0; i
< 4; i
++) {
78 printf("%c", chan_names
[(swiz
+ i
) & 0x3]);
86 static void print_dstreg(uint32_t num
, uint32_t mask
, uint32_t dst_exp
)
88 printf("%s%u", dst_exp
? "export" : "R", num
);
92 for (i
= 0; i
< 4; i
++) {
93 printf("%c", (mask
& 0x1) ? chan_names
[i
] : '_');
99 static void print_export_comment(uint32_t num
, enum shader_t type
)
101 const char *name
= NULL
;
105 case 62: name
= "gl_Position"; break;
106 case 63: name
= "gl_PointSize"; break;
109 case SHADER_FRAGMENT
:
111 case 0: name
= "gl_FragColor"; break;
117 /* if we had a symbol table here, we could look
118 * up the name of the varying..
121 printf("\t; %s", name
);
128 } vector_instructions
[0x20] = {
129 #define INSTR(opc, num_srcs) [opc] = { num_srcs, #opc }
147 INSTR(DOT2ADDv
, 3), // ???
150 INSTR(PRED_SETE_PUSHv
, 2),
151 INSTR(PRED_SETNE_PUSHv
, 2),
152 INSTR(PRED_SETGT_PUSHv
, 2),
153 INSTR(PRED_SETGTE_PUSHv
, 2),
160 }, scalar_instructions
[0x40] = {
165 INSTR(MUL_PREV2s
, 1),
178 INSTR(RECIP_CLAMP
, 1),
180 INSTR(RECIP_IEEE
, 1),
181 INSTR(RECIPSQ_CLAMP
, 1),
182 INSTR(RECIPSQ_FF
, 1),
183 INSTR(RECIPSQ_IEEE
, 1),
185 INSTR(MOVA_FLOORs
, 1),
188 INSTR(PRED_SETEs
, 1),
189 INSTR(PRED_SETNEs
, 1),
190 INSTR(PRED_SETGTs
, 1),
191 INSTR(PRED_SETGTEs
, 1),
192 INSTR(PRED_SET_INVs
, 1),
193 INSTR(PRED_SET_POPs
, 1),
194 INSTR(PRED_SET_CLRs
, 1),
195 INSTR(PRED_SET_RESTOREs
, 1),
202 INSTR(MUL_CONST_0
, 1),
203 INSTR(MUL_CONST_1
, 1),
204 INSTR(ADD_CONST_0
, 1),
205 INSTR(ADD_CONST_1
, 1),
206 INSTR(SUB_CONST_0
, 1),
207 INSTR(SUB_CONST_1
, 1),
210 INSTR(RETAIN_PREV
, 1),
214 static int disasm_alu(uint32_t *dwords
, uint32_t alu_off
,
215 int level
, int sync
, enum shader_t type
)
217 instr_alu_t
*alu
= (instr_alu_t
*)dwords
;
219 printf("%s", levels
[level
]);
220 if (debug
& PRINT_RAW
) {
221 printf("%02x: %08x %08x %08x\t", alu_off
,
222 dwords
[0], dwords
[1], dwords
[2]);
225 printf(" %sALU:\t", sync
? "(S)" : " ");
227 printf("%s", vector_instructions
[alu
->vector_opc
].name
);
229 if (alu
->pred_select
& 0x2) {
230 /* seems to work similar to conditional execution in ARM instruction
231 * set, so let's use a similar syntax for now:
233 printf((alu
->pred_select
& 0x1) ? "EQ" : "NE");
238 print_dstreg(alu
->vector_dest
, alu
->vector_write_mask
, alu
->export_data
);
240 if (vector_instructions
[alu
->vector_opc
].num_srcs
== 3) {
241 print_srcreg(alu
->src3_reg
, alu
->src3_sel
, alu
->src3_swiz
,
242 alu
->src3_reg_negate
, alu
->src3_reg_abs
);
245 print_srcreg(alu
->src1_reg
, alu
->src1_sel
, alu
->src1_swiz
,
246 alu
->src1_reg_negate
, alu
->src1_reg_abs
);
247 if (vector_instructions
[alu
->vector_opc
].num_srcs
> 1) {
249 print_srcreg(alu
->src2_reg
, alu
->src2_sel
, alu
->src2_swiz
,
250 alu
->src2_reg_negate
, alu
->src2_reg_abs
);
253 if (alu
->vector_clamp
)
256 if (alu
->export_data
)
257 print_export_comment(alu
->vector_dest
, type
);
261 if (alu
->scalar_write_mask
|| !alu
->vector_write_mask
) {
262 /* 2nd optional scalar op: */
264 printf("%s", levels
[level
]);
265 if (debug
& PRINT_RAW
)
268 if (scalar_instructions
[alu
->scalar_opc
].name
) {
269 printf("\t \t%s\t", scalar_instructions
[alu
->scalar_opc
].name
);
271 printf("\t \tOP(%u)\t", alu
->scalar_opc
);
274 print_dstreg(alu
->scalar_dest
, alu
->scalar_write_mask
, alu
->export_data
);
276 print_srcreg(alu
->src3_reg
, alu
->src3_sel
, alu
->src3_swiz
,
277 alu
->src3_reg_negate
, alu
->src3_reg_abs
);
278 // TODO ADD/MUL must have another src?!?
279 if (alu
->scalar_clamp
)
281 if (alu
->export_data
)
282 print_export_comment(alu
->scalar_dest
, type
);
291 * FETCH instructions:
294 static void print_fetch_dst(uint32_t dst_reg
, uint32_t dst_swiz
)
297 printf("\tR%u.", dst_reg
);
298 for (i
= 0; i
< 4; i
++) {
299 printf("%c", chan_names
[dst_swiz
& 0x7]);
304 static void print_fetch_vtx(instr_fetch_t
*fetch
)
306 instr_fetch_vtx_t
*vtx
= &fetch
->vtx
;
308 if (vtx
->pred_select
) {
309 /* seems to work similar to conditional execution in ARM instruction
310 * set, so let's use a similar syntax for now:
312 printf(vtx
->pred_condition
? "EQ" : "NE");
315 print_fetch_dst(vtx
->dst_reg
, vtx
->dst_swiz
);
316 printf(" = R%u.", vtx
->src_reg
);
317 printf("%c", chan_names
[vtx
->src_swiz
& 0x3]);
319 const char *fmt
= rnn_enumname(rnn
, "a2xx_sq_surfaceformat", vtx
->format
);
323 printf(" TYPE(0x%x)", vtx
->format
);
325 printf(" %s", vtx
->format_comp_all
? "SIGNED" : "UNSIGNED");
326 if (!vtx
->num_format_all
)
327 printf(" NORMALIZED");
328 printf(" STRIDE(%u)", vtx
->stride
);
330 printf(" OFFSET(%u)", vtx
->offset
);
331 printf(" CONST(%u, %u)", vtx
->const_index
, vtx
->const_index_sel
);
334 printf(" src_reg_am=%u", vtx
->src_reg_am
);
335 printf(" dst_reg_am=%u", vtx
->dst_reg_am
);
336 printf(" num_format_all=%u", vtx
->num_format_all
);
337 printf(" signed_rf_mode_all=%u", vtx
->signed_rf_mode_all
);
338 printf(" exp_adjust_all=%u", vtx
->exp_adjust_all
);
342 static void print_fetch_tex(instr_fetch_t
*fetch
)
344 static const char *filter
[] = {
345 [TEX_FILTER_POINT
] = "POINT",
346 [TEX_FILTER_LINEAR
] = "LINEAR",
347 [TEX_FILTER_BASEMAP
] = "BASEMAP",
349 static const char *aniso_filter
[] = {
350 [ANISO_FILTER_DISABLED
] = "DISABLED",
351 [ANISO_FILTER_MAX_1_1
] = "MAX_1_1",
352 [ANISO_FILTER_MAX_2_1
] = "MAX_2_1",
353 [ANISO_FILTER_MAX_4_1
] = "MAX_4_1",
354 [ANISO_FILTER_MAX_8_1
] = "MAX_8_1",
355 [ANISO_FILTER_MAX_16_1
] = "MAX_16_1",
357 static const char *arbitrary_filter
[] = {
358 [ARBITRARY_FILTER_2X4_SYM
] = "2x4_SYM",
359 [ARBITRARY_FILTER_2X4_ASYM
] = "2x4_ASYM",
360 [ARBITRARY_FILTER_4X2_SYM
] = "4x2_SYM",
361 [ARBITRARY_FILTER_4X2_ASYM
] = "4x2_ASYM",
362 [ARBITRARY_FILTER_4X4_SYM
] = "4x4_SYM",
363 [ARBITRARY_FILTER_4X4_ASYM
] = "4x4_ASYM",
365 static const char *sample_loc
[] = {
366 [SAMPLE_CENTROID
] = "CENTROID",
367 [SAMPLE_CENTER
] = "CENTER",
369 instr_fetch_tex_t
*tex
= &fetch
->tex
;
370 uint32_t src_swiz
= tex
->src_swiz
;
373 if (tex
->pred_select
) {
374 /* seems to work similar to conditional execution in ARM instruction
375 * set, so let's use a similar syntax for now:
377 printf(tex
->pred_condition
? "EQ" : "NE");
380 print_fetch_dst(tex
->dst_reg
, tex
->dst_swiz
);
381 printf(" = R%u.", tex
->src_reg
);
382 for (i
= 0; i
< 3; i
++) {
383 printf("%c", chan_names
[src_swiz
& 0x3]);
386 printf(" CONST(%u)", tex
->const_idx
);
387 if (tex
->fetch_valid_only
)
388 printf(" VALID_ONLY");
389 if (tex
->tx_coord_denorm
)
391 if (tex
->mag_filter
!= TEX_FILTER_USE_FETCH_CONST
)
392 printf(" MAG(%s)", filter
[tex
->mag_filter
]);
393 if (tex
->min_filter
!= TEX_FILTER_USE_FETCH_CONST
)
394 printf(" MIN(%s)", filter
[tex
->min_filter
]);
395 if (tex
->mip_filter
!= TEX_FILTER_USE_FETCH_CONST
)
396 printf(" MIP(%s)", filter
[tex
->mip_filter
]);
397 if (tex
->aniso_filter
!= ANISO_FILTER_USE_FETCH_CONST
)
398 printf(" ANISO(%s)", aniso_filter
[tex
->aniso_filter
]);
399 if (tex
->arbitrary_filter
!= ARBITRARY_FILTER_USE_FETCH_CONST
)
400 printf(" ARBITRARY(%s)", arbitrary_filter
[tex
->arbitrary_filter
]);
401 if (tex
->vol_mag_filter
!= TEX_FILTER_USE_FETCH_CONST
)
402 printf(" VOL_MAG(%s)", filter
[tex
->vol_mag_filter
]);
403 if (tex
->vol_min_filter
!= TEX_FILTER_USE_FETCH_CONST
)
404 printf(" VOL_MIN(%s)", filter
[tex
->vol_min_filter
]);
405 if (!tex
->use_comp_lod
) {
406 printf(" LOD(%u)", tex
->use_comp_lod
);
407 printf(" LOD_BIAS(%u)", tex
->lod_bias
);
409 if (tex
->use_reg_lod
) {
410 printf(" REG_LOD(%u)", tex
->use_reg_lod
);
412 if (tex
->use_reg_gradients
)
413 printf(" USE_REG_GRADIENTS");
414 printf(" LOCATION(%s)", sample_loc
[tex
->sample_location
]);
415 if (tex
->offset_x
|| tex
->offset_y
|| tex
->offset_z
)
416 printf(" OFFSET(%u,%u,%u)", tex
->offset_x
, tex
->offset_y
, tex
->offset_z
);
421 void (*fxn
)(instr_fetch_t
*cf
);
422 } fetch_instructions
[] = {
423 #define INSTR(opc, name, fxn) [opc] = { name, fxn }
424 INSTR(VTX_FETCH
, "VERTEX", print_fetch_vtx
),
425 INSTR(TEX_FETCH
, "SAMPLE", print_fetch_tex
),
426 INSTR(TEX_GET_BORDER_COLOR_FRAC
, "?", print_fetch_tex
),
427 INSTR(TEX_GET_COMP_TEX_LOD
, "?", print_fetch_tex
),
428 INSTR(TEX_GET_GRADIENTS
, "?", print_fetch_tex
),
429 INSTR(TEX_GET_WEIGHTS
, "?", print_fetch_tex
),
430 INSTR(TEX_SET_TEX_LOD
, "SET_TEX_LOD", print_fetch_tex
),
431 INSTR(TEX_SET_GRADIENTS_H
, "?", print_fetch_tex
),
432 INSTR(TEX_SET_GRADIENTS_V
, "?", print_fetch_tex
),
433 INSTR(TEX_RESERVED_4
, "?", print_fetch_tex
),
437 static int disasm_fetch(uint32_t *dwords
, uint32_t alu_off
, int level
, int sync
)
439 instr_fetch_t
*fetch
= (instr_fetch_t
*)dwords
;
441 printf("%s", levels
[level
]);
442 if (debug
& PRINT_RAW
) {
443 printf("%02x: %08x %08x %08x\t", alu_off
,
444 dwords
[0], dwords
[1], dwords
[2]);
447 printf(" %sFETCH:\t", sync
? "(S)" : " ");
448 printf("%s", fetch_instructions
[fetch
->opc
].name
);
449 fetch_instructions
[fetch
->opc
].fxn(fetch
);
459 static int cf_exec(instr_cf_t
*cf
)
461 return (cf
->opc
== EXEC
) ||
462 (cf
->opc
== EXEC_END
) ||
463 (cf
->opc
== COND_EXEC
) ||
464 (cf
->opc
== COND_EXEC_END
) ||
465 (cf
->opc
== COND_PRED_EXEC
) ||
466 (cf
->opc
== COND_PRED_EXEC_END
) ||
467 (cf
->opc
== COND_EXEC_PRED_CLEAN
) ||
468 (cf
->opc
== COND_EXEC_PRED_CLEAN_END
);
471 static int cf_cond_exec(instr_cf_t
*cf
)
473 return (cf
->opc
== COND_EXEC
) ||
474 (cf
->opc
== COND_EXEC_END
) ||
475 (cf
->opc
== COND_PRED_EXEC
) ||
476 (cf
->opc
== COND_PRED_EXEC_END
) ||
477 (cf
->opc
== COND_EXEC_PRED_CLEAN
) ||
478 (cf
->opc
== COND_EXEC_PRED_CLEAN_END
);
481 static void print_cf_nop(instr_cf_t
*cf
)
485 static void print_cf_exec(instr_cf_t
*cf
)
487 printf(" ADDR(0x%x) CNT(0x%x)", cf
->exec
.address
, cf
->exec
.count
);
491 printf(" VC(0x%x)", cf
->exec
.vc
);
492 if (cf
->exec
.bool_addr
)
493 printf(" BOOL_ADDR(0x%x)", cf
->exec
.bool_addr
);
494 if (cf
->exec
.address_mode
== ABSOLUTE_ADDR
)
495 printf(" ABSOLUTE_ADDR");
496 if (cf_cond_exec(cf
))
497 printf(" COND(%d)", cf
->exec
.condition
);
500 static void print_cf_loop(instr_cf_t
*cf
)
502 printf(" ADDR(0x%x) LOOP_ID(%d)", cf
->loop
.address
, cf
->loop
.loop_id
);
503 if (cf
->loop
.address_mode
== ABSOLUTE_ADDR
)
504 printf(" ABSOLUTE_ADDR");
507 static void print_cf_jmp_call(instr_cf_t
*cf
)
509 printf(" ADDR(0x%x) DIR(%d)", cf
->jmp_call
.address
, cf
->jmp_call
.direction
);
510 if (cf
->jmp_call
.force_call
)
511 printf(" FORCE_CALL");
512 if (cf
->jmp_call
.predicated_jmp
)
513 printf(" COND(%d)", cf
->jmp_call
.condition
);
514 if (cf
->jmp_call
.bool_addr
)
515 printf(" BOOL_ADDR(0x%x)", cf
->jmp_call
.bool_addr
);
516 if (cf
->jmp_call
.address_mode
== ABSOLUTE_ADDR
)
517 printf(" ABSOLUTE_ADDR");
520 static void print_cf_alloc(instr_cf_t
*cf
)
522 static const char *bufname
[] = {
523 [SQ_NO_ALLOC
] = "NO ALLOC",
524 [SQ_POSITION
] = "POSITION",
525 [SQ_PARAMETER_PIXEL
] = "PARAM/PIXEL",
526 [SQ_MEMORY
] = "MEMORY",
528 printf(" %s SIZE(0x%x)", bufname
[cf
->alloc
.buffer_select
], cf
->alloc
.size
);
529 if (cf
->alloc
.no_serial
)
530 printf(" NO_SERIAL");
531 if (cf
->alloc
.alloc_mode
) // ???
532 printf(" ALLOC_MODE");
537 void (*fxn
)(instr_cf_t
*cf
);
538 } cf_instructions
[] = {
539 #define INSTR(opc, fxn) [opc] = { #opc, fxn }
540 INSTR(NOP
, print_cf_nop
),
541 INSTR(EXEC
, print_cf_exec
),
542 INSTR(EXEC_END
, print_cf_exec
),
543 INSTR(COND_EXEC
, print_cf_exec
),
544 INSTR(COND_EXEC_END
, print_cf_exec
),
545 INSTR(COND_PRED_EXEC
, print_cf_exec
),
546 INSTR(COND_PRED_EXEC_END
, print_cf_exec
),
547 INSTR(LOOP_START
, print_cf_loop
),
548 INSTR(LOOP_END
, print_cf_loop
),
549 INSTR(COND_CALL
, print_cf_jmp_call
),
550 INSTR(RETURN
, print_cf_jmp_call
),
551 INSTR(COND_JMP
, print_cf_jmp_call
),
552 INSTR(ALLOC
, print_cf_alloc
),
553 INSTR(COND_EXEC_PRED_CLEAN
, print_cf_exec
),
554 INSTR(COND_EXEC_PRED_CLEAN_END
, print_cf_exec
),
555 INSTR(MARK_VS_FETCH_DONE
, print_cf_nop
), // ??
559 static void print_cf(instr_cf_t
*cf
, int level
)
561 printf("%s", levels
[level
]);
562 if (debug
& PRINT_RAW
) {
563 uint16_t *words
= (uint16_t *)cf
;
564 printf(" %04x %04x %04x \t",
565 words
[0], words
[1], words
[2]);
567 printf("%s", cf_instructions
[cf
->opc
].name
);
568 cf_instructions
[cf
->opc
].fxn(cf
);
573 * The adreno shader microcode consists of two parts:
574 * 1) A CF (control-flow) program, at the header of the compiled shader,
575 * which refers to ALU/FETCH instructions that follow it by address.
576 * 2) ALU and FETCH instructions
579 int disasm_a2xx(uint32_t *dwords
, int sizedwords
, int level
, enum shader_t type
)
581 instr_cf_t
*cfs
= (instr_cf_t
*)dwords
;
586 rnn_load(rnn
, "a2xx");
589 for (idx
= 0; ; idx
++) {
590 instr_cf_t
*cf
= &cfs
[idx
];
592 max_idx
= 2 * cf
->exec
.address
;
597 for (idx
= 0; idx
< max_idx
; idx
++) {
598 instr_cf_t
*cf
= &cfs
[idx
];
603 uint32_t sequence
= cf
->exec
.serialize
;
605 for (i
= 0; i
< cf
->exec
.count
; i
++) {
606 uint32_t alu_off
= (cf
->exec
.address
+ i
);
607 if (sequence
& 0x1) {
608 disasm_fetch(dwords
+ alu_off
* 3, alu_off
, level
, sequence
& 0x2);
610 disasm_alu(dwords
+ alu_off
* 3, alu_off
, level
, sequence
& 0x2, type
);
620 void disasm_set_debug(enum debug_t d
)