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freedreno: drop shader_t
[mesa.git] / src / freedreno / decode / disasm-a3xx.c
1 /*
2 * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <stdio.h>
25 #include <stdlib.h>
26 #include <stdint.h>
27 #include <stdbool.h>
28 #include <string.h>
29 #include <assert.h>
30
31 #include "disasm.h"
32 #include "instr-a3xx.h"
33
34 #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
35
36 extern enum debug_t debug;
37
38 static const char *levels[] = {
39 "",
40 "\t",
41 "\t\t",
42 "\t\t\t",
43 "\t\t\t\t",
44 "\t\t\t\t\t",
45 "\t\t\t\t\t\t",
46 "\t\t\t\t\t\t\t",
47 "\t\t\t\t\t\t\t\t",
48 "\t\t\t\t\t\t\t\t\t",
49 "x",
50 "x",
51 "x",
52 "x",
53 "x",
54 "x",
55 };
56
57 static const char *component = "xyzw";
58
59 static const char *type[] = {
60 [TYPE_F16] = "f16",
61 [TYPE_F32] = "f32",
62 [TYPE_U16] = "u16",
63 [TYPE_U32] = "u32",
64 [TYPE_S16] = "s16",
65 [TYPE_S32] = "s32",
66 [TYPE_U8] = "u8",
67 [TYPE_S8] = "s8",
68 };
69
70
71 #define MAX_REG 4096
72
73 typedef struct {
74 uint8_t full[MAX_REG/8];
75 uint8_t half[MAX_REG/8];
76 } regmask_t;
77
78 struct disasm_ctx {
79 FILE *out;
80 int level;
81 unsigned gpu_id;
82
83 struct shader_stats *stats;
84
85 /* we have to process the dst register after src to avoid tripping up
86 * the read-before-write detection
87 */
88 unsigned last_dst;
89 bool last_dst_full;
90 bool last_dst_valid;
91
92 /* current instruction repeat flag: */
93 unsigned repeat;
94 /* current instruction repeat indx/offset (for --expand): */
95 unsigned repeatidx;
96
97 /* tracking for register usage */
98 struct {
99 regmask_t used;
100 regmask_t used_merged;
101 regmask_t rbw; /* read before write */
102 regmask_t war; /* write after read */
103 regmask_t cnst; /* used consts */
104 } regs;
105 };
106
107 static const char *float_imms[] = {
108 "0.0",
109 "0.5",
110 "1.0",
111 "2.0",
112 "e",
113 "pi",
114 "1/pi",
115 "1/log2(e)",
116 "log2(e)",
117 "1/log2(10)",
118 "log2(10)",
119 "4.0",
120 };
121
122 static void print_reg(struct disasm_ctx *ctx, reg_t reg, bool full,
123 bool is_float, bool r,
124 bool c, bool im, bool neg, bool abs, bool addr_rel)
125 {
126 const char type = c ? 'c' : 'r';
127
128 // XXX I prefer - and || for neg/abs, but preserving format used
129 // by libllvm-a3xx for easy diffing..
130
131 if (abs && neg)
132 fprintf(ctx->out, "(absneg)");
133 else if (neg)
134 fprintf(ctx->out, "(neg)");
135 else if (abs)
136 fprintf(ctx->out, "(abs)");
137
138 if (r)
139 fprintf(ctx->out, "(r)");
140
141 if (im) {
142 if (is_float && full && reg.iim_val < ARRAY_SIZE(float_imms)) {
143 fprintf(ctx->out, "(%s)", float_imms[reg.iim_val]);
144 } else {
145 fprintf(ctx->out, "%d", reg.iim_val);
146 }
147 } else if (addr_rel) {
148 /* I would just use %+d but trying to make it diff'able with
149 * libllvm-a3xx...
150 */
151 if (reg.iim_val < 0)
152 fprintf(ctx->out, "%s%c<a0.x - %d>", full ? "" : "h", type, -reg.iim_val);
153 else if (reg.iim_val > 0)
154 fprintf(ctx->out, "%s%c<a0.x + %d>", full ? "" : "h", type, reg.iim_val);
155 else
156 fprintf(ctx->out, "%s%c<a0.x>", full ? "" : "h", type);
157 } else if ((reg.num == REG_A0) && !c) {
158 /* This matches libllvm output, the second (scalar) address register
159 * seems to be called a1.x instead of a0.y.
160 */
161 fprintf(ctx->out, "a%d.x", reg.comp);
162 } else if ((reg.num == REG_P0) && !c) {
163 fprintf(ctx->out, "p0.%c", component[reg.comp]);
164 } else {
165 fprintf(ctx->out, "%s%c%d.%c", full ? "" : "h", type, reg.num, component[reg.comp]);
166 }
167 }
168
169 /* Tracking for registers used, read-before-write (input), and
170 * write-after-read (output.. but not 100%)..
171 */
172
173 static void regmask_set(regmask_t *regmask, unsigned num, bool full, unsigned val)
174 {
175 unsigned i = num / 8;
176 unsigned j = num % 8;
177 ir3_assert(num < MAX_REG);
178 if (full) {
179 regmask->full[i] = (regmask->full[i] & ~(1 << j)) | (val << j);
180 } else {
181 regmask->half[i] = (regmask->half[i] & ~(1 << j)) | (val << j);
182 }
183 }
184
185 static unsigned regmask_get(regmask_t *regmask, unsigned num, bool full)
186 {
187 unsigned i = num / 8;
188 unsigned j = num % 8;
189 ir3_assert(num < MAX_REG);
190 if (full) {
191 return (regmask->full[i] >> j) & 0x1;
192 } else {
193 return (regmask->half[i] >> j) & 0x1;
194 }
195 }
196
197 static unsigned regidx(reg_t reg)
198 {
199 return (4 * reg.num) + reg.comp;
200 }
201
202 static reg_t idxreg(unsigned idx)
203 {
204 return (reg_t){
205 .comp = idx & 0x3,
206 .num = idx >> 2,
207 };
208 }
209
210 static int print_regs(struct disasm_ctx *ctx, regmask_t *regmask, bool full)
211 {
212 int num, max = 0, cnt = 0;
213 int first, last;
214
215 void print_sequence(void)
216 {
217 if (first != MAX_REG) {
218 if (first == last) {
219 fprintf(ctx->out, " %d", first);
220 } else {
221 fprintf(ctx->out, " %d-%d", first, last);
222 }
223 }
224 }
225
226 first = last = MAX_REG;
227
228 for (num = 0; num < MAX_REG; num++) {
229 if (regmask_get(regmask, num, full)) {
230 if (num != (last + 1)) {
231 print_sequence();
232 first = num;
233 }
234 last = num;
235 if (num < (48*4))
236 max = num;
237 cnt++;
238 }
239 }
240
241 print_sequence();
242
243 fprintf(ctx->out, " (cnt=%d, max=%d)", cnt, max);
244
245 return max;
246 }
247
248 static void print_reg_stats(struct disasm_ctx *ctx)
249 {
250 int fullreg, halfreg;
251
252 fprintf(ctx->out, "%sRegister Stats:\n", levels[ctx->level]);
253 fprintf(ctx->out, "%s- used (half):", levels[ctx->level]);
254 halfreg = print_regs(ctx, &ctx->regs.used, false);
255 fprintf(ctx->out, "\n");
256 fprintf(ctx->out, "%s- used (full):", levels[ctx->level]);
257 fullreg = print_regs(ctx, &ctx->regs.used, true);
258 fprintf(ctx->out, "\n");
259 fprintf(ctx->out, "%s- used (merged):", levels[ctx->level]);
260 print_regs(ctx, &ctx->regs.used_merged, false);
261 fprintf(ctx->out, "\n");
262 fprintf(ctx->out, "%s- input (half):", levels[ctx->level]);
263 print_regs(ctx, &ctx->regs.rbw, false);
264 fprintf(ctx->out, "\n");
265 fprintf(ctx->out, "%s- input (full):", levels[ctx->level]);
266 print_regs(ctx, &ctx->regs.rbw, true);
267 fprintf(ctx->out, "\n");
268 fprintf(ctx->out, "%s- const (half):", levels[ctx->level]);
269 print_regs(ctx, &ctx->regs.cnst, false);
270 fprintf(ctx->out, "\n");
271 fprintf(ctx->out, "%s- const (full):", levels[ctx->level]);
272 print_regs(ctx, &ctx->regs.cnst, true);
273 fprintf(ctx->out, "\n");
274 fprintf(ctx->out, "%s- output (half):", levels[ctx->level]);
275 print_regs(ctx, &ctx->regs.war, false);
276 fprintf(ctx->out, " (estimated)\n");
277 fprintf(ctx->out, "%s- output (full):", levels[ctx->level]);
278 print_regs(ctx, &ctx->regs.war, true);
279 fprintf(ctx->out, " (estimated)\n");
280
281 /* convert to vec4, which is the granularity that registers are
282 * assigned to shader:
283 */
284 fullreg = (fullreg + 3) / 4;
285 halfreg = (halfreg + 3) / 4;
286
287 // Note this count of instructions includes rptN, which matches
288 // up to how mesa prints this:
289 fprintf(ctx->out, "%s- shaderdb: %d instructions, %d nops, %d non-nops, "
290 "(%d instlen), %d half, %d full\n",
291 levels[ctx->level], ctx->stats->instructions, ctx->stats->nops,
292 ctx->stats->instructions - ctx->stats->nops, ctx->stats->instlen,
293 halfreg, fullreg);
294 fprintf(ctx->out, "%s- shaderdb: %d (ss), %d (sy)\n", levels[ctx->level],
295 ctx->stats->ss, ctx->stats->sy);
296 }
297
298 static void process_reg_dst(struct disasm_ctx *ctx)
299 {
300 int i;
301
302 if (!ctx->last_dst_valid)
303 return;
304
305 for (i = 0; i <= ctx->repeat; i++) {
306 unsigned dst = ctx->last_dst + i;
307
308 regmask_set(&ctx->regs.war, dst, ctx->last_dst_full, 1);
309 regmask_set(&ctx->regs.used, dst, ctx->last_dst_full, 1);
310
311 if (ctx->last_dst_full) {
312 regmask_set(&ctx->regs.used_merged, (dst*2)+0, false, 1);
313 regmask_set(&ctx->regs.used_merged, (dst*2)+1, false, 1);
314 } else {
315 regmask_set(&ctx->regs.used_merged, dst, false, 1);
316 }
317 }
318
319 ctx->last_dst_valid = false;
320 }
321
322 static void print_reg_dst(struct disasm_ctx *ctx, reg_t reg, bool full, bool addr_rel)
323 {
324 /* presumably the special registers a0.c and p0.c don't count.. */
325 if (!(addr_rel || (reg.num == 61) || (reg.num == 62))) {
326 ctx->last_dst = regidx(reg);
327 ctx->last_dst_full = full;
328 ctx->last_dst_valid = true;
329 }
330 reg = idxreg(regidx(reg) + ctx->repeatidx);
331 print_reg(ctx, reg, full, false, false, false, false, false, false, addr_rel);
332 }
333
334 static void print_reg_src(struct disasm_ctx *ctx, reg_t reg, bool full, bool f, bool r,
335 bool c, bool im, bool neg, bool abs, bool addr_rel)
336 {
337 /* presumably the special registers a0.c and p0.c don't count.. */
338 if (!(addr_rel || c || im || (reg.num == 61) || (reg.num == 62))) {
339 int i, num = regidx(reg);
340 for (i = 0; i <= ctx->repeat; i++) {
341 unsigned src = num + i;
342
343 if (!regmask_get(&ctx->regs.used, src, full))
344 regmask_set(&ctx->regs.rbw, src, full, 1);
345
346 regmask_set(&ctx->regs.war, src, full, 0);
347 regmask_set(&ctx->regs.used, src, full, 1);
348
349 if (full) {
350 regmask_set(&ctx->regs.used_merged, (src*2)+0, false, 1);
351 regmask_set(&ctx->regs.used_merged, (src*2)+1, false, 1);
352 } else {
353 regmask_set(&ctx->regs.used_merged, src, false, 1);
354 }
355
356 if (!r)
357 break;
358 }
359 } else if (c) {
360 int i, num = regidx(reg);
361 for (i = 0; i <= ctx->repeat; i++) {
362 unsigned src = num + i;
363
364 regmask_set(&ctx->regs.cnst, src, full, 1);
365
366 if (!r)
367 break;
368 }
369
370 unsigned max = (num + ctx->repeat + 1 + 3) / 4;
371 if (max > ctx->stats->constlen)
372 ctx->stats->constlen = max;
373 }
374
375 if (r)
376 reg = idxreg(regidx(reg) + ctx->repeatidx);
377
378 print_reg(ctx, reg, full, f, r, c, im, neg, abs, addr_rel);
379 }
380
381 /* TODO switch to using reginfo struct everywhere, since more readable
382 * than passing a bunch of bools to print_reg_src
383 */
384
385 struct reginfo {
386 reg_t reg;
387 bool full;
388 bool r;
389 bool c;
390 bool f; /* src reg is interpreted as float, used for printing immediates */
391 bool im;
392 bool neg;
393 bool abs;
394 bool addr_rel;
395 };
396
397 static void print_src(struct disasm_ctx *ctx, struct reginfo *info)
398 {
399 reg_t reg = info->reg;
400
401 if (info->r)
402 reg = idxreg(regidx(info->reg) + ctx->repeatidx);
403
404 print_reg_src(ctx, reg, info->full, info->f, info->r, info->c, info->im,
405 info->neg, info->abs, info->addr_rel);
406 }
407
408 //static void print_dst(struct disasm_ctx *ctx, struct reginfo *info)
409 //{
410 // print_reg_dst(ctx, info->reg, info->full, info->addr_rel);
411 //}
412
413 static void print_instr_cat0(struct disasm_ctx *ctx, instr_t *instr)
414 {
415 static const struct {
416 const char *suffix;
417 int nsrc;
418 bool idx;
419 } brinfo[7] = {
420 [BRANCH_PLAIN] = { "r", 1, false },
421 [BRANCH_OR] = { "rao", 2, false },
422 [BRANCH_AND] = { "raa", 2, false },
423 [BRANCH_CONST] = { "rac", 0, true },
424 [BRANCH_ANY] = { "any", 1, false },
425 [BRANCH_ALL] = { "all", 1, false },
426 [BRANCH_X] = { "rax", 0, false },
427 };
428 instr_cat0_t *cat0 = &instr->cat0;
429
430 switch (instr_opc(instr, ctx->gpu_id)) {
431 case OPC_KILL:
432 case OPC_PREDT:
433 case OPC_PREDF:
434 fprintf(ctx->out, " %sp0.%c", cat0->inv0 ? "!" : "",
435 component[cat0->comp0]);
436 break;
437 case OPC_B:
438 fprintf(ctx->out, "%s", brinfo[cat0->brtype].suffix);
439 if (brinfo[cat0->brtype].idx) {
440 fprintf(ctx->out, ".%u", cat0->idx);
441 }
442 if (brinfo[cat0->brtype].nsrc >= 1) {
443 fprintf(ctx->out, " %sp0.%c,", cat0->inv0 ? "!" : "",
444 component[cat0->comp0]);
445 }
446 if (brinfo[cat0->brtype].nsrc >= 2) {
447 fprintf(ctx->out, " %sp0.%c,", cat0->inv1 ? "!" : "",
448 component[cat0->comp1]);
449 }
450 fprintf(ctx->out, " #%d", cat0->a3xx.immed);
451 break;
452 case OPC_JUMP:
453 case OPC_CALL:
454 case OPC_BKT:
455 case OPC_GETONE:
456 case OPC_SHPS:
457 fprintf(ctx->out, " #%d", cat0->a3xx.immed);
458 break;
459 }
460
461 if ((debug & PRINT_VERBOSE) && (cat0->dummy3|cat0->dummy4))
462 fprintf(ctx->out, "\t{0: %x,%x}", cat0->dummy3, cat0->dummy4);
463 }
464
465 static void print_instr_cat1(struct disasm_ctx *ctx, instr_t *instr)
466 {
467 instr_cat1_t *cat1 = &instr->cat1;
468
469 if (cat1->ul)
470 fprintf(ctx->out, "(ul)");
471
472 if (cat1->src_type == cat1->dst_type) {
473 if ((cat1->src_type == TYPE_S16) && (((reg_t)cat1->dst).num == REG_A0)) {
474 /* special case (nmemonic?): */
475 fprintf(ctx->out, "mova");
476 } else {
477 fprintf(ctx->out, "mov.%s%s", type[cat1->src_type], type[cat1->dst_type]);
478 }
479 } else {
480 fprintf(ctx->out, "cov.%s%s", type[cat1->src_type], type[cat1->dst_type]);
481 }
482
483 fprintf(ctx->out, " ");
484
485 if (cat1->even)
486 fprintf(ctx->out, "(even)");
487
488 if (cat1->pos_inf)
489 fprintf(ctx->out, "(pos_infinity)");
490
491 print_reg_dst(ctx, (reg_t)(cat1->dst), type_size(cat1->dst_type) == 32,
492 cat1->dst_rel);
493
494 fprintf(ctx->out, ", ");
495
496 /* ugg, have to special case this.. vs print_reg().. */
497 if (cat1->src_im) {
498 if (type_float(cat1->src_type))
499 fprintf(ctx->out, "(%f)", cat1->fim_val);
500 else if (type_uint(cat1->src_type))
501 fprintf(ctx->out, "0x%08x", cat1->uim_val);
502 else
503 fprintf(ctx->out, "%d", cat1->iim_val);
504 } else if (cat1->src_rel && !cat1->src_c) {
505 /* I would just use %+d but trying to make it diff'able with
506 * libllvm-a3xx...
507 */
508 char type = cat1->src_rel_c ? 'c' : 'r';
509 const char *full = (type_size(cat1->src_type) == 32) ? "" : "h";
510 if (cat1->off < 0)
511 fprintf(ctx->out, "%s%c<a0.x - %d>", full, type, -cat1->off);
512 else if (cat1->off > 0)
513 fprintf(ctx->out, "%s%c<a0.x + %d>", full, type, cat1->off);
514 else
515 fprintf(ctx->out, "%s%c<a0.x>", full, type);
516 } else {
517 struct reginfo src = {
518 .reg = (reg_t)cat1->src,
519 .full = type_size(cat1->src_type) == 32,
520 .r = cat1->src_r,
521 .c = cat1->src_c,
522 .im = cat1->src_im,
523 };
524 print_src(ctx, &src);
525 }
526
527 if ((debug & PRINT_VERBOSE) && (cat1->must_be_0))
528 fprintf(ctx->out, "\t{1: %x}", cat1->must_be_0);
529 }
530
531 static void print_instr_cat2(struct disasm_ctx *ctx, instr_t *instr)
532 {
533 instr_cat2_t *cat2 = &instr->cat2;
534 int opc = _OPC(2, cat2->opc);
535 static const char *cond[] = {
536 "lt",
537 "le",
538 "gt",
539 "ge",
540 "eq",
541 "ne",
542 "?6?",
543 };
544
545 switch (opc) {
546 case OPC_CMPS_F:
547 case OPC_CMPS_U:
548 case OPC_CMPS_S:
549 case OPC_CMPV_F:
550 case OPC_CMPV_U:
551 case OPC_CMPV_S:
552 fprintf(ctx->out, ".%s", cond[cat2->cond]);
553 break;
554 }
555
556 fprintf(ctx->out, " ");
557 if (cat2->ei)
558 fprintf(ctx->out, "(ei)");
559 print_reg_dst(ctx, (reg_t)(cat2->dst), cat2->full ^ cat2->dst_half, false);
560 fprintf(ctx->out, ", ");
561
562 struct reginfo src1 = {
563 .full = cat2->full,
564 .r = cat2->repeat ? cat2->src1_r : 0,
565 .f = is_cat2_float(opc),
566 .im = cat2->src1_im,
567 .abs = cat2->src1_abs,
568 .neg = cat2->src1_neg,
569 };
570
571 if (cat2->c1.src1_c) {
572 src1.reg = (reg_t)(cat2->c1.src1);
573 src1.c = true;
574 } else if (cat2->rel1.src1_rel) {
575 src1.reg = (reg_t)(cat2->rel1.src1);
576 src1.c = cat2->rel1.src1_c;
577 src1.addr_rel = true;
578 } else {
579 src1.reg = (reg_t)(cat2->src1);
580 }
581 print_src(ctx, &src1);
582
583 struct reginfo src2 = {
584 .r = cat2->repeat ? cat2->src2_r : 0,
585 .full = cat2->full,
586 .f = is_cat2_float(opc),
587 .abs = cat2->src2_abs,
588 .neg = cat2->src2_neg,
589 .im = cat2->src2_im,
590 };
591 switch (opc) {
592 case OPC_ABSNEG_F:
593 case OPC_ABSNEG_S:
594 case OPC_CLZ_B:
595 case OPC_CLZ_S:
596 case OPC_SIGN_F:
597 case OPC_FLOOR_F:
598 case OPC_CEIL_F:
599 case OPC_RNDNE_F:
600 case OPC_RNDAZ_F:
601 case OPC_TRUNC_F:
602 case OPC_NOT_B:
603 case OPC_BFREV_B:
604 case OPC_SETRM:
605 case OPC_CBITS_B:
606 /* these only have one src reg */
607 break;
608 default:
609 fprintf(ctx->out, ", ");
610 if (cat2->c2.src2_c) {
611 src2.reg = (reg_t)(cat2->c2.src2);
612 src2.c = true;
613 } else if (cat2->rel2.src2_rel) {
614 src2.reg = (reg_t)(cat2->rel2.src2);
615 src2.c = cat2->rel2.src2_c;
616 src2.addr_rel = true;
617 } else {
618 src2.reg = (reg_t)(cat2->src2);
619 }
620 print_src(ctx, &src2);
621 break;
622 }
623 }
624
625 static void print_instr_cat3(struct disasm_ctx *ctx, instr_t *instr)
626 {
627 instr_cat3_t *cat3 = &instr->cat3;
628 bool full = instr_cat3_full(cat3);
629
630 fprintf(ctx->out, " ");
631 print_reg_dst(ctx, (reg_t)(cat3->dst), full ^ cat3->dst_half, false);
632 fprintf(ctx->out, ", ");
633
634 struct reginfo src1 = {
635 .r = cat3->repeat ? cat3->src1_r : 0,
636 .full = full,
637 .neg = cat3->src1_neg,
638 };
639 if (cat3->c1.src1_c) {
640 src1.reg = (reg_t)(cat3->c1.src1);
641 src1.c = true;
642 } else if (cat3->rel1.src1_rel) {
643 src1.reg = (reg_t)(cat3->rel1.src1);
644 src1.c = cat3->rel1.src1_c;
645 src1.addr_rel = true;
646 } else {
647 src1.reg = (reg_t)(cat3->src1);
648 }
649 print_src(ctx, &src1);
650
651 fprintf(ctx->out, ", ");
652 struct reginfo src2 = {
653 .reg = (reg_t)cat3->src2,
654 .full = full,
655 .r = cat3->repeat ? cat3->src2_r : 0,
656 .c = cat3->src2_c,
657 .neg = cat3->src2_neg,
658 };
659 print_src(ctx, &src2);
660
661 fprintf(ctx->out, ", ");
662 struct reginfo src3 = {
663 .r = cat3->src3_r,
664 .full = full,
665 .neg = cat3->src3_neg,
666 };
667 if (cat3->c2.src3_c) {
668 src3.reg = (reg_t)(cat3->c2.src3);
669 src3.c = true;
670 } else if (cat3->rel2.src3_rel) {
671 src3.reg = (reg_t)(cat3->rel2.src3);
672 src3.c = cat3->rel2.src3_c;
673 src3.addr_rel = true;
674 } else {
675 src3.reg = (reg_t)(cat3->src3);
676 }
677 print_src(ctx, &src3);
678 }
679
680 static void print_instr_cat4(struct disasm_ctx *ctx, instr_t *instr)
681 {
682 instr_cat4_t *cat4 = &instr->cat4;
683
684 fprintf(ctx->out, " ");
685 print_reg_dst(ctx, (reg_t)(cat4->dst), cat4->full ^ cat4->dst_half, false);
686 fprintf(ctx->out, ", ");
687
688 struct reginfo src = {
689 .r = cat4->src_r,
690 .im = cat4->src_im,
691 .full = cat4->full,
692 .neg = cat4->src_neg,
693 .abs = cat4->src_abs,
694 };
695 if (cat4->c.src_c) {
696 src.reg = (reg_t)(cat4->c.src);
697 src.c = true;
698 } else if (cat4->rel.src_rel) {
699 src.reg = (reg_t)(cat4->rel.src);
700 src.c = cat4->rel.src_c;
701 src.addr_rel = true;
702 } else {
703 src.reg = (reg_t)(cat4->src);
704 }
705 print_src(ctx, &src);
706
707 if ((debug & PRINT_VERBOSE) && (cat4->dummy1|cat4->dummy2))
708 fprintf(ctx->out, "\t{4: %x,%x}", cat4->dummy1, cat4->dummy2);
709 }
710
711 static void print_instr_cat5(struct disasm_ctx *ctx, instr_t *instr)
712 {
713 static const struct {
714 bool src1, src2, samp, tex;
715 } info[0x1f] = {
716 [opc_op(OPC_ISAM)] = { true, false, true, true, },
717 [opc_op(OPC_ISAML)] = { true, true, true, true, },
718 [opc_op(OPC_ISAMM)] = { true, false, true, true, },
719 [opc_op(OPC_SAM)] = { true, false, true, true, },
720 [opc_op(OPC_SAMB)] = { true, true, true, true, },
721 [opc_op(OPC_SAML)] = { true, true, true, true, },
722 [opc_op(OPC_SAMGQ)] = { true, false, true, true, },
723 [opc_op(OPC_GETLOD)] = { true, false, true, true, },
724 [opc_op(OPC_CONV)] = { true, true, true, true, },
725 [opc_op(OPC_CONVM)] = { true, true, true, true, },
726 [opc_op(OPC_GETSIZE)] = { true, false, false, true, },
727 [opc_op(OPC_GETBUF)] = { false, false, false, true, },
728 [opc_op(OPC_GETPOS)] = { true, false, false, true, },
729 [opc_op(OPC_GETINFO)] = { false, false, false, true, },
730 [opc_op(OPC_DSX)] = { true, false, false, false, },
731 [opc_op(OPC_DSY)] = { true, false, false, false, },
732 [opc_op(OPC_GATHER4R)] = { true, false, true, true, },
733 [opc_op(OPC_GATHER4G)] = { true, false, true, true, },
734 [opc_op(OPC_GATHER4B)] = { true, false, true, true, },
735 [opc_op(OPC_GATHER4A)] = { true, false, true, true, },
736 [opc_op(OPC_SAMGP0)] = { true, false, true, true, },
737 [opc_op(OPC_SAMGP1)] = { true, false, true, true, },
738 [opc_op(OPC_SAMGP2)] = { true, false, true, true, },
739 [opc_op(OPC_SAMGP3)] = { true, false, true, true, },
740 [opc_op(OPC_DSXPP_1)] = { true, false, false, false, },
741 [opc_op(OPC_DSYPP_1)] = { true, false, false, false, },
742 [opc_op(OPC_RGETPOS)] = { true, false, false, false, },
743 [opc_op(OPC_RGETINFO)] = { false, false, false, false, },
744 };
745
746 static const struct {
747 bool indirect;
748 bool bindless;
749 bool use_a1;
750 bool uniform;
751 } desc_features[8] = {
752 [CAT5_NONUNIFORM] = { .indirect = true, },
753 [CAT5_UNIFORM] = { .indirect = true, .uniform = true, },
754 [CAT5_BINDLESS_IMM] = { .bindless = true, },
755 [CAT5_BINDLESS_UNIFORM] = {
756 .bindless = true,
757 .indirect = true,
758 .uniform = true,
759 },
760 [CAT5_BINDLESS_NONUNIFORM] = {
761 .bindless = true,
762 .indirect = true,
763 },
764 [CAT5_BINDLESS_A1_IMM] = {
765 .bindless = true,
766 .use_a1 = true,
767 },
768 [CAT5_BINDLESS_A1_UNIFORM] = {
769 .bindless = true,
770 .indirect = true,
771 .uniform = true,
772 .use_a1 = true,
773 },
774 [CAT5_BINDLESS_A1_NONUNIFORM] = {
775 .bindless = true,
776 .indirect = true,
777 .use_a1 = true,
778 },
779 };
780
781 instr_cat5_t *cat5 = &instr->cat5;
782 int i;
783
784 bool desc_indirect =
785 cat5->is_s2en_bindless &&
786 desc_features[cat5->s2en_bindless.desc_mode].indirect;
787 bool bindless =
788 cat5->is_s2en_bindless &&
789 desc_features[cat5->s2en_bindless.desc_mode].bindless;
790 bool use_a1 =
791 cat5->is_s2en_bindless &&
792 desc_features[cat5->s2en_bindless.desc_mode].use_a1;
793 bool uniform =
794 cat5->is_s2en_bindless &&
795 desc_features[cat5->s2en_bindless.desc_mode].uniform;
796
797 if (cat5->is_3d) fprintf(ctx->out, ".3d");
798 if (cat5->is_a) fprintf(ctx->out, ".a");
799 if (cat5->is_o) fprintf(ctx->out, ".o");
800 if (cat5->is_p) fprintf(ctx->out, ".p");
801 if (cat5->is_s) fprintf(ctx->out, ".s");
802 if (desc_indirect) fprintf(ctx->out, ".s2en");
803 if (uniform) fprintf(ctx->out, ".uniform");
804
805 if (bindless) {
806 unsigned base = (cat5->s2en_bindless.base_hi << 1) | cat5->base_lo;
807 fprintf(ctx->out, ".base%d", base);
808 }
809
810 fprintf(ctx->out, " ");
811
812 switch (_OPC(5, cat5->opc)) {
813 case OPC_DSXPP_1:
814 case OPC_DSYPP_1:
815 break;
816 default:
817 fprintf(ctx->out, "(%s)", type[cat5->type]);
818 break;
819 }
820
821 fprintf(ctx->out, "(");
822 for (i = 0; i < 4; i++)
823 if (cat5->wrmask & (1 << i))
824 fprintf(ctx->out, "%c", "xyzw"[i]);
825 fprintf(ctx->out, ")");
826
827 print_reg_dst(ctx, (reg_t)(cat5->dst), type_size(cat5->type) == 32, false);
828
829 if (info[cat5->opc].src1) {
830 fprintf(ctx->out, ", ");
831 struct reginfo src = { .reg = (reg_t)(cat5->src1), .full = cat5->full };
832 print_src(ctx, &src);
833 }
834
835 if (cat5->is_o || info[cat5->opc].src2) {
836 fprintf(ctx->out, ", ");
837 struct reginfo src = { .reg = (reg_t)(cat5->src2), .full = cat5->full };
838 print_src(ctx, &src);
839 }
840 if (cat5->is_s2en_bindless) {
841 if (!desc_indirect) {
842 if (info[cat5->opc].samp) {
843 if (use_a1)
844 fprintf(ctx->out, ", s#%d", cat5->s2en_bindless.src3);
845 else
846 fprintf(ctx->out, ", s#%d", cat5->s2en_bindless.src3 & 0xf);
847 }
848
849 if (info[cat5->opc].tex && !use_a1) {
850 fprintf(ctx->out, ", t#%d", cat5->s2en_bindless.src3 >> 4);
851 }
852 }
853 } else {
854 if (info[cat5->opc].samp)
855 fprintf(ctx->out, ", s#%d", cat5->norm.samp);
856 if (info[cat5->opc].tex)
857 fprintf(ctx->out, ", t#%d", cat5->norm.tex);
858 }
859
860 if (desc_indirect) {
861 fprintf(ctx->out, ", ");
862 struct reginfo src = { .reg = (reg_t)(cat5->s2en_bindless.src3), .full = bindless };
863 print_src(ctx, &src);
864 }
865
866 if (use_a1)
867 fprintf(ctx->out, ", a1.x");
868
869 if (debug & PRINT_VERBOSE) {
870 if (cat5->is_s2en_bindless) {
871 if ((debug & PRINT_VERBOSE) && cat5->s2en_bindless.dummy1)
872 fprintf(ctx->out, "\t{5: %x}", cat5->s2en_bindless.dummy1);
873 } else {
874 if ((debug & PRINT_VERBOSE) && cat5->norm.dummy1)
875 fprintf(ctx->out, "\t{5: %x}", cat5->norm.dummy1);
876 }
877 }
878 }
879
880 static void print_instr_cat6_a3xx(struct disasm_ctx *ctx, instr_t *instr)
881 {
882 instr_cat6_t *cat6 = &instr->cat6;
883 char sd = 0, ss = 0; /* dst/src address space */
884 bool nodst = false;
885 struct reginfo dst, src1, src2;
886 int src1off = 0, dstoff = 0;
887
888 memset(&dst, 0, sizeof(dst));
889 memset(&src1, 0, sizeof(src1));
890 memset(&src2, 0, sizeof(src2));
891
892 switch (_OPC(6, cat6->opc)) {
893 case OPC_RESINFO:
894 case OPC_RESFMT:
895 dst.full = type_size(cat6->type) == 32;
896 src1.full = type_size(cat6->type) == 32;
897 src2.full = type_size(cat6->type) == 32;
898 break;
899 case OPC_L2G:
900 case OPC_G2L:
901 dst.full = true;
902 src1.full = true;
903 src2.full = true;
904 break;
905 case OPC_STG:
906 case OPC_STL:
907 case OPC_STP:
908 case OPC_STLW:
909 case OPC_STIB:
910 dst.full = type_size(cat6->type) == 32;
911 src1.full = type_size(cat6->type) == 32;
912 src2.full = type_size(cat6->type) == 32;
913 break;
914 default:
915 dst.full = type_size(cat6->type) == 32;
916 src1.full = true;
917 src2.full = true;
918 break;
919 }
920
921 switch (_OPC(6, cat6->opc)) {
922 case OPC_PREFETCH:
923 break;
924 case OPC_RESINFO:
925 fprintf(ctx->out, ".%dd", cat6->ldgb.d + 1);
926 break;
927 case OPC_LDGB:
928 fprintf(ctx->out, ".%s", cat6->ldgb.typed ? "typed" : "untyped");
929 fprintf(ctx->out, ".%dd", cat6->ldgb.d + 1);
930 fprintf(ctx->out, ".%s", type[cat6->type]);
931 fprintf(ctx->out, ".%d", cat6->ldgb.type_size + 1);
932 break;
933 case OPC_STGB:
934 case OPC_STIB:
935 fprintf(ctx->out, ".%s", cat6->stgb.typed ? "typed" : "untyped");
936 fprintf(ctx->out, ".%dd", cat6->stgb.d + 1);
937 fprintf(ctx->out, ".%s", type[cat6->type]);
938 fprintf(ctx->out, ".%d", cat6->stgb.type_size + 1);
939 break;
940 case OPC_ATOMIC_ADD:
941 case OPC_ATOMIC_SUB:
942 case OPC_ATOMIC_XCHG:
943 case OPC_ATOMIC_INC:
944 case OPC_ATOMIC_DEC:
945 case OPC_ATOMIC_CMPXCHG:
946 case OPC_ATOMIC_MIN:
947 case OPC_ATOMIC_MAX:
948 case OPC_ATOMIC_AND:
949 case OPC_ATOMIC_OR:
950 case OPC_ATOMIC_XOR:
951 ss = cat6->g ? 'g' : 'l';
952 fprintf(ctx->out, ".%s", cat6->ldgb.typed ? "typed" : "untyped");
953 fprintf(ctx->out, ".%dd", cat6->ldgb.d + 1);
954 fprintf(ctx->out, ".%s", type[cat6->type]);
955 fprintf(ctx->out, ".%d", cat6->ldgb.type_size + 1);
956 fprintf(ctx->out, ".%c", ss);
957 break;
958 default:
959 dst.im = cat6->g && !cat6->dst_off;
960 fprintf(ctx->out, ".%s", type[cat6->type]);
961 break;
962 }
963 fprintf(ctx->out, " ");
964
965 switch (_OPC(6, cat6->opc)) {
966 case OPC_STG:
967 sd = 'g';
968 break;
969 case OPC_STP:
970 sd = 'p';
971 break;
972 case OPC_STL:
973 case OPC_STLW:
974 sd = 'l';
975 break;
976
977 case OPC_LDG:
978 case OPC_LDC:
979 ss = 'g';
980 break;
981 case OPC_LDP:
982 ss = 'p';
983 break;
984 case OPC_LDL:
985 case OPC_LDLW:
986 case OPC_LDLV:
987 ss = 'l';
988 break;
989
990 case OPC_L2G:
991 ss = 'l';
992 sd = 'g';
993 break;
994
995 case OPC_G2L:
996 ss = 'g';
997 sd = 'l';
998 break;
999
1000 case OPC_PREFETCH:
1001 ss = 'g';
1002 nodst = true;
1003 break;
1004 }
1005
1006 if ((_OPC(6, cat6->opc) == OPC_STGB) || (_OPC(6, cat6->opc) == OPC_STIB)) {
1007 struct reginfo src3;
1008
1009 memset(&src3, 0, sizeof(src3));
1010
1011 src1.reg = (reg_t)(cat6->stgb.src1);
1012 src2.reg = (reg_t)(cat6->stgb.src2);
1013 src2.im = cat6->stgb.src2_im;
1014 src3.reg = (reg_t)(cat6->stgb.src3);
1015 src3.im = cat6->stgb.src3_im;
1016 src3.full = true;
1017
1018 fprintf(ctx->out, "g[%u], ", cat6->stgb.dst_ssbo);
1019 print_src(ctx, &src1);
1020 fprintf(ctx->out, ", ");
1021 print_src(ctx, &src2);
1022 fprintf(ctx->out, ", ");
1023 print_src(ctx, &src3);
1024
1025 if (debug & PRINT_VERBOSE)
1026 fprintf(ctx->out, " (pad0=%x, pad3=%x)", cat6->stgb.pad0, cat6->stgb.pad3);
1027
1028 return;
1029 }
1030
1031 if (is_atomic(_OPC(6, cat6->opc))) {
1032
1033 src1.reg = (reg_t)(cat6->ldgb.src1);
1034 src1.im = cat6->ldgb.src1_im;
1035 src2.reg = (reg_t)(cat6->ldgb.src2);
1036 src2.im = cat6->ldgb.src2_im;
1037 dst.reg = (reg_t)(cat6->ldgb.dst);
1038
1039 print_src(ctx, &dst);
1040 fprintf(ctx->out, ", ");
1041 if (ss == 'g') {
1042 struct reginfo src3;
1043 memset(&src3, 0, sizeof(src3));
1044
1045 src3.reg = (reg_t)(cat6->ldgb.src3);
1046 src3.full = true;
1047
1048 /* For images, the ".typed" variant is used and src2 is
1049 * the ivecN coordinates, ie ivec2 for 2d.
1050 *
1051 * For SSBOs, the ".untyped" variant is used and src2 is
1052 * a simple dword offset.. src3 appears to be
1053 * uvec2(offset * 4, 0). Not sure the point of that.
1054 */
1055
1056 fprintf(ctx->out, "g[%u], ", cat6->ldgb.src_ssbo);
1057 print_src(ctx, &src1); /* value */
1058 fprintf(ctx->out, ", ");
1059 print_src(ctx, &src2); /* offset/coords */
1060 fprintf(ctx->out, ", ");
1061 print_src(ctx, &src3); /* 64b byte offset.. */
1062
1063 if (debug & PRINT_VERBOSE) {
1064 fprintf(ctx->out, " (pad0=%x, pad3=%x, mustbe0=%x)", cat6->ldgb.pad0,
1065 cat6->ldgb.pad3, cat6->ldgb.mustbe0);
1066 }
1067 } else { /* ss == 'l' */
1068 fprintf(ctx->out, "l[");
1069 print_src(ctx, &src1); /* simple byte offset */
1070 fprintf(ctx->out, "], ");
1071 print_src(ctx, &src2); /* value */
1072
1073 if (debug & PRINT_VERBOSE) {
1074 fprintf(ctx->out, " (src3=%x, pad0=%x, pad3=%x, mustbe0=%x)",
1075 cat6->ldgb.src3, cat6->ldgb.pad0,
1076 cat6->ldgb.pad3, cat6->ldgb.mustbe0);
1077 }
1078 }
1079
1080 return;
1081 } else if (_OPC(6, cat6->opc) == OPC_RESINFO) {
1082 dst.reg = (reg_t)(cat6->ldgb.dst);
1083
1084 print_src(ctx, &dst);
1085 fprintf(ctx->out, ", ");
1086 fprintf(ctx->out, "g[%u]", cat6->ldgb.src_ssbo);
1087
1088 return;
1089 } else if (_OPC(6, cat6->opc) == OPC_LDGB) {
1090
1091 src1.reg = (reg_t)(cat6->ldgb.src1);
1092 src1.im = cat6->ldgb.src1_im;
1093 src2.reg = (reg_t)(cat6->ldgb.src2);
1094 src2.im = cat6->ldgb.src2_im;
1095 dst.reg = (reg_t)(cat6->ldgb.dst);
1096
1097 print_src(ctx, &dst);
1098 fprintf(ctx->out, ", ");
1099 fprintf(ctx->out, "g[%u], ", cat6->ldgb.src_ssbo);
1100 print_src(ctx, &src1);
1101 fprintf(ctx->out, ", ");
1102 print_src(ctx, &src2);
1103
1104 if (debug & PRINT_VERBOSE)
1105 fprintf(ctx->out, " (pad0=%x, pad3=%x, mustbe0=%x)", cat6->ldgb.pad0, cat6->ldgb.pad3, cat6->ldgb.mustbe0);
1106
1107 return;
1108 } else if (_OPC(6, cat6->opc) == OPC_LDG && cat6->a.src1_im && cat6->a.src2_im) {
1109 struct reginfo src3;
1110
1111 memset(&src3, 0, sizeof(src3));
1112 src1.reg = (reg_t)(cat6->a.src1);
1113 src2.reg = (reg_t)(cat6->a.src2);
1114 src2.im = cat6->a.src2_im;
1115 src3.reg = (reg_t)(cat6->a.off);
1116 src3.full = true;
1117 dst.reg = (reg_t)(cat6->d.dst);
1118
1119 print_src(ctx, &dst);
1120 fprintf(ctx->out, ", g[");
1121 print_src(ctx, &src1);
1122 fprintf(ctx->out, "+");
1123 print_src(ctx, &src3);
1124 fprintf(ctx->out, "], ");
1125 print_src(ctx, &src2);
1126
1127 return;
1128 }
1129 if (cat6->dst_off) {
1130 dst.reg = (reg_t)(cat6->c.dst);
1131 dstoff = cat6->c.off;
1132 } else {
1133 dst.reg = (reg_t)(cat6->d.dst);
1134 }
1135
1136 if (cat6->src_off) {
1137 src1.reg = (reg_t)(cat6->a.src1);
1138 src1.im = cat6->a.src1_im;
1139 src2.reg = (reg_t)(cat6->a.src2);
1140 src2.im = cat6->a.src2_im;
1141 src1off = cat6->a.off;
1142 } else {
1143 src1.reg = (reg_t)(cat6->b.src1);
1144 src1.im = cat6->b.src1_im;
1145 src2.reg = (reg_t)(cat6->b.src2);
1146 src2.im = cat6->b.src2_im;
1147 }
1148
1149 if (!nodst) {
1150 if (sd)
1151 fprintf(ctx->out, "%c[", sd);
1152 /* note: dst might actually be a src (ie. address to store to) */
1153 print_src(ctx, &dst);
1154 if (cat6->dst_off && cat6->g) {
1155 struct reginfo dstoff_reg = {0};
1156 dstoff_reg.reg = (reg_t) cat6->c.off;
1157 dstoff_reg.full = true;
1158 fprintf(ctx->out, "+");
1159 print_src(ctx, &dstoff_reg);
1160 } else if (dstoff)
1161 fprintf(ctx->out, "%+d", dstoff);
1162 if (sd)
1163 fprintf(ctx->out, "]");
1164 fprintf(ctx->out, ", ");
1165 }
1166
1167 if (ss)
1168 fprintf(ctx->out, "%c[", ss);
1169
1170 /* can have a larger than normal immed, so hack: */
1171 if (src1.im) {
1172 fprintf(ctx->out, "%u", src1.reg.dummy13);
1173 } else {
1174 print_src(ctx, &src1);
1175 }
1176
1177 if (cat6->src_off && cat6->g)
1178 print_src(ctx, &src2);
1179 else if (src1off)
1180 fprintf(ctx->out, "%+d", src1off);
1181 if (ss)
1182 fprintf(ctx->out, "]");
1183
1184 switch (_OPC(6, cat6->opc)) {
1185 case OPC_RESINFO:
1186 case OPC_RESFMT:
1187 break;
1188 default:
1189 fprintf(ctx->out, ", ");
1190 print_src(ctx, &src2);
1191 break;
1192 }
1193 }
1194
1195 static void print_instr_cat6_a6xx(struct disasm_ctx *ctx, instr_t *instr)
1196 {
1197 instr_cat6_a6xx_t *cat6 = &instr->cat6_a6xx;
1198 struct reginfo src1, src2, ssbo;
1199 bool uses_type = _OPC(6, cat6->opc) != OPC_LDC;
1200
1201 static const struct {
1202 bool indirect;
1203 bool bindless;
1204 const char *name;
1205 } desc_features[8] = {
1206 [CAT6_IMM] = {
1207 .name = "imm"
1208 },
1209 [CAT6_UNIFORM] = {
1210 .indirect = true,
1211 .name = "uniform"
1212 },
1213 [CAT6_NONUNIFORM] = {
1214 .indirect = true,
1215 .name = "nonuniform"
1216 },
1217 [CAT6_BINDLESS_IMM] = {
1218 .bindless = true,
1219 .name = "imm"
1220 },
1221 [CAT6_BINDLESS_UNIFORM] = {
1222 .bindless = true,
1223 .indirect = true,
1224 .name = "uniform"
1225 },
1226 [CAT6_BINDLESS_NONUNIFORM] = {
1227 .bindless = true,
1228 .indirect = true,
1229 .name = "nonuniform"
1230 },
1231 };
1232
1233 bool indirect_ssbo = desc_features[cat6->desc_mode].indirect;
1234 bool bindless = desc_features[cat6->desc_mode].bindless;
1235 bool type_full = cat6->type != TYPE_U16;
1236
1237
1238 memset(&src1, 0, sizeof(src1));
1239 memset(&src2, 0, sizeof(src2));
1240 memset(&ssbo, 0, sizeof(ssbo));
1241
1242 if (uses_type) {
1243 fprintf(ctx->out, ".%s", cat6->typed ? "typed" : "untyped");
1244 fprintf(ctx->out, ".%dd", cat6->d + 1);
1245 fprintf(ctx->out, ".%s", type[cat6->type]);
1246 } else {
1247 fprintf(ctx->out, ".offset%d", cat6->d);
1248 }
1249 fprintf(ctx->out, ".%u", cat6->type_size + 1);
1250
1251 fprintf(ctx->out, ".%s", desc_features[cat6->desc_mode].name);
1252 if (bindless)
1253 fprintf(ctx->out, ".base%d", cat6->base);
1254 fprintf(ctx->out, " ");
1255
1256 src2.reg = (reg_t)(cat6->src2);
1257 src2.full = type_full;
1258 print_src(ctx, &src2);
1259 fprintf(ctx->out, ", ");
1260
1261 src1.reg = (reg_t)(cat6->src1);
1262 src1.full = true; // XXX
1263 print_src(ctx, &src1);
1264 fprintf(ctx->out, ", ");
1265 ssbo.reg = (reg_t)(cat6->ssbo);
1266 ssbo.im = !indirect_ssbo;
1267 ssbo.full = true;
1268 print_src(ctx, &ssbo);
1269
1270 if (debug & PRINT_VERBOSE) {
1271 fprintf(ctx->out, " (pad1=%x, pad2=%x, pad3=%x, pad4=%x, pad5=%x)",
1272 cat6->pad1, cat6->pad2, cat6->pad3, cat6->pad4, cat6->pad5);
1273 }
1274 }
1275
1276 static void print_instr_cat6(struct disasm_ctx *ctx, instr_t *instr)
1277 {
1278 if (!is_cat6_legacy(instr, ctx->gpu_id)) {
1279 print_instr_cat6_a6xx(ctx, instr);
1280 if (debug & PRINT_VERBOSE)
1281 fprintf(ctx->out, " NEW");
1282 } else {
1283 print_instr_cat6_a3xx(ctx, instr);
1284 if (debug & PRINT_VERBOSE)
1285 fprintf(ctx->out, " LEGACY");
1286 }
1287 }
1288 static void print_instr_cat7(struct disasm_ctx *ctx, instr_t *instr)
1289 {
1290 instr_cat7_t *cat7 = &instr->cat7;
1291
1292 if (cat7->g)
1293 fprintf(ctx->out, ".g");
1294 if (cat7->l)
1295 fprintf(ctx->out, ".l");
1296
1297 if (_OPC(7, cat7->opc) == OPC_FENCE) {
1298 if (cat7->r)
1299 fprintf(ctx->out, ".r");
1300 if (cat7->w)
1301 fprintf(ctx->out, ".w");
1302 }
1303 }
1304
1305 /* size of largest OPC field of all the instruction categories: */
1306 #define NOPC_BITS 6
1307
1308 static const struct opc_info {
1309 uint16_t cat;
1310 uint16_t opc;
1311 const char *name;
1312 void (*print)(struct disasm_ctx *ctx, instr_t *instr);
1313 } opcs[1 << (3+NOPC_BITS)] = {
1314 #define OPC(cat, opc, name) [(opc)] = { (cat), (opc), #name, print_instr_cat##cat }
1315 /* category 0: */
1316 OPC(0, OPC_NOP, nop),
1317 OPC(0, OPC_B, b),
1318 OPC(0, OPC_JUMP, jump),
1319 OPC(0, OPC_CALL, call),
1320 OPC(0, OPC_RET, ret),
1321 OPC(0, OPC_KILL, kill),
1322 OPC(0, OPC_END, end),
1323 OPC(0, OPC_EMIT, emit),
1324 OPC(0, OPC_CUT, cut),
1325 OPC(0, OPC_CHMASK, chmask),
1326 OPC(0, OPC_CHSH, chsh),
1327 OPC(0, OPC_FLOW_REV, flow_rev),
1328 OPC(0, OPC_PREDT, predt),
1329 OPC(0, OPC_PREDF, predf),
1330 OPC(0, OPC_PREDE, prede),
1331 OPC(0, OPC_BKT, bkt),
1332 OPC(0, OPC_STKS, stks),
1333 OPC(0, OPC_STKR, stkr),
1334 OPC(0, OPC_XSET, xset),
1335 OPC(0, OPC_XCLR, xclr),
1336 OPC(0, OPC_GETONE, getone),
1337 OPC(0, OPC_DBG, dbg),
1338 OPC(0, OPC_SHPS, shps),
1339 OPC(0, OPC_SHPE, shpe),
1340
1341 /* category 1: */
1342 OPC(1, OPC_MOV, ),
1343
1344 /* category 2: */
1345 OPC(2, OPC_ADD_F, add.f),
1346 OPC(2, OPC_MIN_F, min.f),
1347 OPC(2, OPC_MAX_F, max.f),
1348 OPC(2, OPC_MUL_F, mul.f),
1349 OPC(2, OPC_SIGN_F, sign.f),
1350 OPC(2, OPC_CMPS_F, cmps.f),
1351 OPC(2, OPC_ABSNEG_F, absneg.f),
1352 OPC(2, OPC_CMPV_F, cmpv.f),
1353 OPC(2, OPC_FLOOR_F, floor.f),
1354 OPC(2, OPC_CEIL_F, ceil.f),
1355 OPC(2, OPC_RNDNE_F, rndne.f),
1356 OPC(2, OPC_RNDAZ_F, rndaz.f),
1357 OPC(2, OPC_TRUNC_F, trunc.f),
1358 OPC(2, OPC_ADD_U, add.u),
1359 OPC(2, OPC_ADD_S, add.s),
1360 OPC(2, OPC_SUB_U, sub.u),
1361 OPC(2, OPC_SUB_S, sub.s),
1362 OPC(2, OPC_CMPS_U, cmps.u),
1363 OPC(2, OPC_CMPS_S, cmps.s),
1364 OPC(2, OPC_MIN_U, min.u),
1365 OPC(2, OPC_MIN_S, min.s),
1366 OPC(2, OPC_MAX_U, max.u),
1367 OPC(2, OPC_MAX_S, max.s),
1368 OPC(2, OPC_ABSNEG_S, absneg.s),
1369 OPC(2, OPC_AND_B, and.b),
1370 OPC(2, OPC_OR_B, or.b),
1371 OPC(2, OPC_NOT_B, not.b),
1372 OPC(2, OPC_XOR_B, xor.b),
1373 OPC(2, OPC_CMPV_U, cmpv.u),
1374 OPC(2, OPC_CMPV_S, cmpv.s),
1375 OPC(2, OPC_MUL_U24, mul.u24),
1376 OPC(2, OPC_MUL_S24, mul.s24),
1377 OPC(2, OPC_MULL_U, mull.u),
1378 OPC(2, OPC_BFREV_B, bfrev.b),
1379 OPC(2, OPC_CLZ_S, clz.s),
1380 OPC(2, OPC_CLZ_B, clz.b),
1381 OPC(2, OPC_SHL_B, shl.b),
1382 OPC(2, OPC_SHR_B, shr.b),
1383 OPC(2, OPC_ASHR_B, ashr.b),
1384 OPC(2, OPC_BARY_F, bary.f),
1385 OPC(2, OPC_MGEN_B, mgen.b),
1386 OPC(2, OPC_GETBIT_B, getbit.b),
1387 OPC(2, OPC_SETRM, setrm),
1388 OPC(2, OPC_CBITS_B, cbits.b),
1389 OPC(2, OPC_SHB, shb),
1390 OPC(2, OPC_MSAD, msad),
1391
1392 /* category 3: */
1393 OPC(3, OPC_MAD_U16, mad.u16),
1394 OPC(3, OPC_MADSH_U16, madsh.u16),
1395 OPC(3, OPC_MAD_S16, mad.s16),
1396 OPC(3, OPC_MADSH_M16, madsh.m16),
1397 OPC(3, OPC_MAD_U24, mad.u24),
1398 OPC(3, OPC_MAD_S24, mad.s24),
1399 OPC(3, OPC_MAD_F16, mad.f16),
1400 OPC(3, OPC_MAD_F32, mad.f32),
1401 OPC(3, OPC_SEL_B16, sel.b16),
1402 OPC(3, OPC_SEL_B32, sel.b32),
1403 OPC(3, OPC_SEL_S16, sel.s16),
1404 OPC(3, OPC_SEL_S32, sel.s32),
1405 OPC(3, OPC_SEL_F16, sel.f16),
1406 OPC(3, OPC_SEL_F32, sel.f32),
1407 OPC(3, OPC_SAD_S16, sad.s16),
1408 OPC(3, OPC_SAD_S32, sad.s32),
1409
1410 /* category 4: */
1411 OPC(4, OPC_RCP, rcp),
1412 OPC(4, OPC_RSQ, rsq),
1413 OPC(4, OPC_LOG2, log2),
1414 OPC(4, OPC_EXP2, exp2),
1415 OPC(4, OPC_SIN, sin),
1416 OPC(4, OPC_COS, cos),
1417 OPC(4, OPC_SQRT, sqrt),
1418 OPC(4, OPC_HRSQ, hrsq),
1419 OPC(4, OPC_HLOG2, hlog2),
1420 OPC(4, OPC_HEXP2, hexp2),
1421
1422 /* category 5: */
1423 OPC(5, OPC_ISAM, isam),
1424 OPC(5, OPC_ISAML, isaml),
1425 OPC(5, OPC_ISAMM, isamm),
1426 OPC(5, OPC_SAM, sam),
1427 OPC(5, OPC_SAMB, samb),
1428 OPC(5, OPC_SAML, saml),
1429 OPC(5, OPC_SAMGQ, samgq),
1430 OPC(5, OPC_GETLOD, getlod),
1431 OPC(5, OPC_CONV, conv),
1432 OPC(5, OPC_CONVM, convm),
1433 OPC(5, OPC_GETSIZE, getsize),
1434 OPC(5, OPC_GETBUF, getbuf),
1435 OPC(5, OPC_GETPOS, getpos),
1436 OPC(5, OPC_GETINFO, getinfo),
1437 OPC(5, OPC_DSX, dsx),
1438 OPC(5, OPC_DSY, dsy),
1439 OPC(5, OPC_GATHER4R, gather4r),
1440 OPC(5, OPC_GATHER4G, gather4g),
1441 OPC(5, OPC_GATHER4B, gather4b),
1442 OPC(5, OPC_GATHER4A, gather4a),
1443 OPC(5, OPC_SAMGP0, samgp0),
1444 OPC(5, OPC_SAMGP1, samgp1),
1445 OPC(5, OPC_SAMGP2, samgp2),
1446 OPC(5, OPC_SAMGP3, samgp3),
1447 OPC(5, OPC_DSXPP_1, dsxpp.1),
1448 OPC(5, OPC_DSYPP_1, dsypp.1),
1449 OPC(5, OPC_RGETPOS, rgetpos),
1450 OPC(5, OPC_RGETINFO, rgetinfo),
1451
1452
1453 /* category 6: */
1454 OPC(6, OPC_LDG, ldg),
1455 OPC(6, OPC_LDL, ldl),
1456 OPC(6, OPC_LDP, ldp),
1457 OPC(6, OPC_STG, stg),
1458 OPC(6, OPC_STL, stl),
1459 OPC(6, OPC_STP, stp),
1460 OPC(6, OPC_LDIB, ldib),
1461 OPC(6, OPC_G2L, g2l),
1462 OPC(6, OPC_L2G, l2g),
1463 OPC(6, OPC_PREFETCH, prefetch),
1464 OPC(6, OPC_LDLW, ldlw),
1465 OPC(6, OPC_STLW, stlw),
1466 OPC(6, OPC_RESFMT, resfmt),
1467 OPC(6, OPC_RESINFO, resinfo),
1468 OPC(6, OPC_ATOMIC_ADD, atomic.add),
1469 OPC(6, OPC_ATOMIC_SUB, atomic.sub),
1470 OPC(6, OPC_ATOMIC_XCHG, atomic.xchg),
1471 OPC(6, OPC_ATOMIC_INC, atomic.inc),
1472 OPC(6, OPC_ATOMIC_DEC, atomic.dec),
1473 OPC(6, OPC_ATOMIC_CMPXCHG, atomic.cmpxchg),
1474 OPC(6, OPC_ATOMIC_MIN, atomic.min),
1475 OPC(6, OPC_ATOMIC_MAX, atomic.max),
1476 OPC(6, OPC_ATOMIC_AND, atomic.and),
1477 OPC(6, OPC_ATOMIC_OR, atomic.or),
1478 OPC(6, OPC_ATOMIC_XOR, atomic.xor),
1479 OPC(6, OPC_LDGB, ldgb),
1480 OPC(6, OPC_STGB, stgb),
1481 OPC(6, OPC_STIB, stib),
1482 OPC(6, OPC_LDC, ldc),
1483 OPC(6, OPC_LDLV, ldlv),
1484
1485 OPC(7, OPC_BAR, bar),
1486 OPC(7, OPC_FENCE, fence),
1487
1488
1489 #undef OPC
1490 };
1491
1492 #define GETINFO(instr) (&(opcs[((instr)->opc_cat << NOPC_BITS) | instr_opc(instr, ctx->gpu_id)]))
1493
1494 static void print_single_instr(struct disasm_ctx *ctx, instr_t *instr)
1495 {
1496 const char *name = GETINFO(instr)->name;
1497 uint32_t opc = instr_opc(instr, ctx->gpu_id);
1498
1499 if (name) {
1500 fprintf(ctx->out, "%s", name);
1501 GETINFO(instr)->print(ctx, instr);
1502 } else {
1503 fprintf(ctx->out, "unknown(%d,%d)", instr->opc_cat, opc);
1504
1505 switch (instr->opc_cat) {
1506 case 0: print_instr_cat0(ctx, instr); break;
1507 case 1: print_instr_cat1(ctx, instr); break;
1508 case 2: print_instr_cat2(ctx, instr); break;
1509 case 3: print_instr_cat3(ctx, instr); break;
1510 case 4: print_instr_cat4(ctx, instr); break;
1511 case 5: print_instr_cat5(ctx, instr); break;
1512 case 6: print_instr_cat6(ctx, instr); break;
1513 case 7: print_instr_cat7(ctx, instr); break;
1514 }
1515 }
1516 }
1517
1518 static bool print_instr(struct disasm_ctx *ctx, uint32_t *dwords, int n)
1519 {
1520 instr_t *instr = (instr_t *)dwords;
1521 uint32_t opc = instr_opc(instr, ctx->gpu_id);
1522 unsigned nop = 0;
1523 unsigned cycles = ctx->stats->instructions;
1524
1525 fprintf(ctx->out, "%s:%d:%04d:%04d[%08xx_%08xx] ", levels[ctx->level],
1526 instr->opc_cat, n, cycles++, dwords[1], dwords[0]);
1527
1528 #if 0
1529 /* print unknown bits: */
1530 if (debug & PRINT_RAW)
1531 fprintf(ctx->out, "[%08xx_%08xx] ", dwords[1] & 0x001ff800, dwords[0] & 0x00000000);
1532
1533 if (debug & PRINT_VERBOSE)
1534 fprintf(ctx->out, "%d,%02d ", instr->opc_cat, opc);
1535 #endif
1536
1537 /* NOTE: order flags are printed is a bit fugly.. but for now I
1538 * try to match the order in llvm-a3xx disassembler for easy
1539 * diff'ing..
1540 */
1541
1542 ctx->repeat = instr_repeat(instr);
1543 ctx->stats->instructions += 1 + ctx->repeat;
1544 ctx->stats->instlen++;
1545
1546 if (instr->sync) {
1547 fprintf(ctx->out, "(sy)");
1548 ctx->stats->sy++;
1549 }
1550 if (instr->ss && ((instr->opc_cat <= 4) || (instr->opc_cat == 7))) {
1551 fprintf(ctx->out, "(ss)");
1552 ctx->stats->ss++;
1553 }
1554 if (instr->jmp_tgt)
1555 fprintf(ctx->out, "(jp)");
1556 if ((instr->opc_cat == 0) && instr->cat0.eq)
1557 fprintf(ctx->out, "(eq)");
1558 if (instr_sat(instr))
1559 fprintf(ctx->out, "(sat)");
1560 if (ctx->repeat)
1561 fprintf(ctx->out, "(rpt%d)", ctx->repeat);
1562 else if ((instr->opc_cat == 2) && (instr->cat2.src1_r || instr->cat2.src2_r))
1563 nop = (instr->cat2.src2_r * 2) + instr->cat2.src1_r;
1564 else if ((instr->opc_cat == 3) && (instr->cat3.src1_r || instr->cat3.src2_r))
1565 nop = (instr->cat3.src2_r * 2) + instr->cat3.src1_r;
1566 ctx->stats->instructions += nop;
1567 ctx->stats->nops += nop;
1568 if (opc == OPC_NOP)
1569 ctx->stats->nops += 1 + ctx->repeat;
1570 if (nop)
1571 fprintf(ctx->out, "(nop%d) ", nop);
1572
1573 if (instr->ul && ((2 <= instr->opc_cat) && (instr->opc_cat <= 4)))
1574 fprintf(ctx->out, "(ul)");
1575
1576 print_single_instr(ctx, instr);
1577 fprintf(ctx->out, "\n");
1578
1579 process_reg_dst(ctx);
1580
1581 if ((instr->opc_cat <= 4) && (debug & EXPAND_REPEAT)) {
1582 int i;
1583 for (i = 0; i < nop; i++) {
1584 fprintf(ctx->out, "%s:%d:%04d:%04d[ ] ",
1585 levels[ctx->level], instr->opc_cat, n, cycles++);
1586 fprintf(ctx->out, "nop\n");
1587 }
1588 for (i = 0; i < ctx->repeat; i++) {
1589 ctx->repeatidx = i + 1;
1590 fprintf(ctx->out, "%s:%d:%04d:%04d[ ] ",
1591 levels[ctx->level], instr->opc_cat, n, cycles++);
1592
1593 print_single_instr(ctx, instr);
1594 fprintf(ctx->out, "\n");
1595 }
1596 ctx->repeatidx = 0;
1597 }
1598
1599 return (instr->opc_cat == 0) &&
1600 ((opc == OPC_END) || (opc == OPC_CHSH));
1601 }
1602
1603 int disasm_a3xx(uint32_t *dwords, int sizedwords, int level, FILE *out, unsigned gpu_id)
1604 {
1605 struct shader_stats stats;
1606 return disasm_a3xx_stat(dwords, sizedwords, level, out, gpu_id, &stats);
1607 }
1608
1609 int disasm_a3xx_stat(uint32_t *dwords, int sizedwords, int level, FILE *out,
1610 unsigned gpu_id, struct shader_stats *stats)
1611 {
1612 struct disasm_ctx ctx;
1613 int i;
1614 int nop_count = 0;
1615 bool has_end = false;
1616
1617 // ir3_assert((sizedwords % 2) == 0);
1618
1619 memset(&ctx, 0, sizeof(ctx));
1620 ctx.out = out;
1621 ctx.level = level;
1622 ctx.gpu_id = gpu_id;
1623 ctx.stats = stats;
1624 memset(ctx.stats, 0, sizeof(*ctx.stats));
1625
1626 for (i = 0; i < sizedwords; i += 2) {
1627 has_end |= print_instr(&ctx, &dwords[i], i/2);
1628 if (!has_end)
1629 continue;
1630 if (dwords[i] == 0 && dwords[i + 1] == 0)
1631 nop_count++;
1632 else
1633 nop_count = 0;
1634 if (nop_count > 3)
1635 break;
1636 }
1637
1638 print_reg_stats(&ctx);
1639
1640 return 0;
1641 }