spirv: Rewrite CFG construction
[mesa.git] / src / freedreno / drm-shim / freedreno_noop.c
1 /*
2 * Copyright © 2019 Google LLC
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <limits.h>
25 #include <stdio.h>
26 #include <stdlib.h>
27 #include <sys/ioctl.h>
28 #include "drm-uapi/msm_drm.h"
29 #include "drm-shim/drm_shim.h"
30
31 struct msm_bo {
32 struct shim_bo base;
33 uint32_t offset;
34 };
35
36 static struct msm_bo *
37 msm_bo(struct shim_bo *bo)
38 {
39 return (struct msm_bo *)bo;
40 }
41
42 struct msm_device {
43 uint32_t next_offset;
44 };
45
46 static struct msm_device msm = {
47 .next_offset = 0x1000,
48 };
49
50 static int
51 msm_ioctl_noop(int fd, unsigned long request, void *arg)
52 {
53 return 0;
54 }
55
56 static int
57 msm_ioctl_gem_new(int fd, unsigned long request, void *arg)
58 {
59 struct shim_fd *shim_fd = drm_shim_fd_lookup(fd);
60 struct drm_msm_gem_new *create = arg;
61 struct msm_bo *bo = calloc(1, sizeof(*bo));
62
63 drm_shim_bo_init(&bo->base, create->size);
64
65 assert(UINT_MAX - msm.next_offset > create->size);
66
67 bo->offset = msm.next_offset;
68 msm.next_offset += create->size;
69
70 create->handle = drm_shim_bo_get_handle(shim_fd, &bo->base);
71
72 drm_shim_bo_put(&bo->base);
73
74 return 0;
75 }
76
77 static int
78 msm_ioctl_gem_info(int fd, unsigned long request, void *arg)
79 {
80 struct shim_fd *shim_fd = drm_shim_fd_lookup(fd);
81 struct drm_msm_gem_info *args = arg;
82 struct shim_bo *bo = drm_shim_bo_lookup(shim_fd, args->handle);
83
84 switch (args->info) {
85 case MSM_INFO_GET_OFFSET:
86 args->value = drm_shim_bo_get_mmap_offset(shim_fd, bo);
87 break;
88 case MSM_INFO_GET_IOVA:
89 args->value = msm_bo(bo)->offset;
90 break;
91 case MSM_INFO_SET_NAME:
92 break;
93 default:
94 fprintf(stderr, "Unknown DRM_IOCTL_MSM_GEM_INFO %d\n", args->info);
95 drm_shim_bo_put(bo);
96 return -1;
97 }
98
99 drm_shim_bo_put(bo);
100
101 return 0;
102 }
103
104 static int
105 msm_ioctl_get_param(int fd, unsigned long request, void *arg)
106 {
107 struct drm_msm_param *gp = arg;
108
109 switch (gp->param) {
110 case MSM_PARAM_GPU_ID:
111 gp->value = 630;
112 return 0;
113 case MSM_PARAM_GMEM_SIZE:
114 gp->value = 1024 * 1024;
115 return 0;
116 case MSM_PARAM_GMEM_BASE:
117 gp->value = 0x100000;
118 return 0;
119 case MSM_PARAM_CHIP_ID:
120 gp->value = (6 << 24) | (3 << 16) | (0 << 8) | (0xff << 0);
121 return 0;
122 case MSM_PARAM_NR_RINGS:
123 gp->value = 1;
124 return 0;
125 case MSM_PARAM_MAX_FREQ:
126 gp->value = 1000000;
127 return 0;
128 case MSM_PARAM_TIMESTAMP:
129 gp->value = 0;
130 return 0;
131 case MSM_PARAM_PP_PGTABLE:
132 gp->value = 1;
133 return 0;
134 case MSM_PARAM_FAULTS:
135 gp->value = 0;
136 return 0;
137 default:
138 fprintf(stderr, "Unknown DRM_IOCTL_MSM_GET_PARAM %d\n",
139 gp->param);
140 return -1;
141 }
142 }
143
144 static int
145 msm_ioctl_gem_madvise(int fd, unsigned long request, void *arg)
146 {
147 struct drm_msm_gem_madvise *args = arg;
148
149 args->retained = true;
150
151 return 0;
152 }
153
154 static ioctl_fn_t driver_ioctls[] = {
155 [DRM_MSM_GET_PARAM] = msm_ioctl_get_param,
156 [DRM_MSM_GEM_NEW] = msm_ioctl_gem_new,
157 [DRM_MSM_GEM_INFO] = msm_ioctl_gem_info,
158 [DRM_MSM_GEM_CPU_PREP] = msm_ioctl_noop,
159 [DRM_MSM_GEM_CPU_FINI] = msm_ioctl_noop,
160 [DRM_MSM_GEM_SUBMIT] = msm_ioctl_noop,
161 [DRM_MSM_WAIT_FENCE] = msm_ioctl_noop,
162 [DRM_MSM_GEM_MADVISE] = msm_ioctl_gem_madvise,
163 [DRM_MSM_SUBMITQUEUE_NEW] = msm_ioctl_noop,
164 [DRM_MSM_SUBMITQUEUE_CLOSE] = msm_ioctl_noop,
165 [DRM_MSM_SUBMITQUEUE_QUERY] = msm_ioctl_noop,
166 };
167
168 void
169 drm_shim_driver_init(void)
170 {
171 shim_device.driver_name = "msm";
172 shim_device.driver_ioctls = driver_ioctls;
173 shim_device.driver_ioctl_count = ARRAY_SIZE(driver_ioctls);
174
175 /* msm uses the DRM version to expose features, instead of getparam. */
176 shim_device.version_major = 1;
177 shim_device.version_minor = 5;
178 shim_device.version_patchlevel = 0;
179
180 drm_shim_override_file("OF_FULLNAME=/rdb/msm\n"
181 "OF_COMPATIBLE_N=1\n"
182 "OF_COMPATIBLE_0=qcom,adreno\n",
183 "/sys/dev/char/%d:%d/device/uevent",
184 DRM_MAJOR, render_node_minor);
185 }