src/freedreno/fdl/fd6_layout.c

   1 /*
   2  * Copyright (C) 2018 Rob Clark <robclark@freedesktop.org>
   3  * Copyright © 2018-2019 Google, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  * Authors:
  25  *    Rob Clark <robclark@freedesktop.org>
  26  */
  27
  28 #include <stdio.h>
  29
  30 #include "freedreno_layout.h"
  31
  32 /* indexed by cpp, including msaa 2x and 4x:
  33  * TODO:
  34  * cpp=1 UBWC needs testing at larger texture sizes
  35  * missing UBWC blockwidth/blockheight for npot+64 cpp
  36  * missing 96/128 CPP for 8x MSAA with 32_32_32/32_32_32_32
  37  */
  38 static const struct {
  39         unsigned pitchalign;
  40         unsigned heightalign;
  41         uint8_t ubwc_blockwidth;
  42         uint8_t ubwc_blockheight;
  43 } tile_alignment[] = {
  44         [1]  = { 128, 32, 16, 4 },
  45         [2]  = { 128, 16, 16, 4 },
  46         [3]  = {  64, 32 },
  47         [4]  = {  64, 16, 16, 4 },
  48         [6]  = {  64, 16 },
  49         [8]  = {  64, 16, 8, 4, },
  50         [12] = {  64, 16 },
  51         [16] = {  64, 16, 4, 4, },
  52         [24] = {  64, 16 },
  53         [32] = {  64, 16, 4, 2 },
  54         [48] = {  64, 16 },
  55         [64] = {  64, 16 },
  56
  57         /* special cases for r8g8: */
  58         [0]  = {  64, 32, 16, 4 },
  59 };
  60
  61 #define RGB_TILE_WIDTH_ALIGNMENT 64
  62 #define RGB_TILE_HEIGHT_ALIGNMENT 16
  63 #define UBWC_PLANE_SIZE_ALIGNMENT 4096
  64
  65 /* NOTE: good way to test this is:  (for example)
  66  *  piglit/bin/texelFetch fs sampler3D 100x100x8
  67  */
  68 void
  69 fdl6_layout(struct fdl_layout *layout,
  70                 enum pipe_format format, uint32_t nr_samples,
  71                 uint32_t width0, uint32_t height0, uint32_t depth0,
  72                 uint32_t mip_levels, uint32_t array_size, bool is_3d, bool ubwc)
  73 {
  74         assert(nr_samples > 0);
  75         layout->width0 = width0;
  76         layout->height0 = height0;
  77         layout->depth0 = depth0;
  78
  79         layout->cpp = util_format_get_blocksize(format);
  80         layout->cpp *= nr_samples;
  81         layout->format = format;
  82         layout->nr_samples = nr_samples;
  83
  84         const struct util_format_description *format_desc =
  85                 util_format_description(format);
  86         uint32_t depth = depth0;
  87         /* linear dimensions: */
  88         uint32_t lwidth = width0;
  89         uint32_t lheight = height0;
  90         /* tile_mode dimensions: */
  91         uint32_t twidth = util_next_power_of_two(lwidth);
  92         uint32_t theight = util_next_power_of_two(lheight);
  93         int ta = layout->cpp;
  94
  95         /* The z16/r16 formats seem to not play by the normal tiling rules: */
  96         if ((layout->cpp == 2) && (util_format_get_nr_components(format) == 2))
  97                 ta = 0;
  98
  99         uint32_t alignment;
 100         if (is_3d) {
 101                 layout->layer_first = false;
 102                 alignment = 4096;
 103         } else {
 104                 layout->layer_first = true;
 105                 alignment = 1;
 106         }
 107         /* in layer_first layout, the level (slice) contains just one
 108          * layer (since in fact the layer contains the slices)
 109          */
 110         uint32_t layers_in_level = layout->layer_first ? 1 : array_size;
 111
 112         debug_assert(ta < ARRAY_SIZE(tile_alignment));
 113         debug_assert(tile_alignment[ta].pitchalign);
 114
 115         for (uint32_t level = 0; level < mip_levels; level++) {
 116                 struct fdl_slice *slice = &layout->slices[level];
 117                 struct fdl_slice *ubwc_slice = &layout->ubwc_slices[level];
 118                 uint32_t tile_mode = (ubwc ?
 119                                 layout->tile_mode : fdl_tile_mode(layout, level));
 120                 uint32_t width, height;
 121
 122                 /* tiled levels of 3D textures are rounded up to PoT dimensions: */
 123                 if (is_3d && tile_mode) {
 124                         width = twidth;
 125                         height = theight;
 126                 } else {
 127                         width = lwidth;
 128                         height = lheight;
 129                 }
 130                 uint32_t aligned_height = height;
 131                 uint32_t pitchalign;
 132
 133                 if (tile_mode) {
 134                         pitchalign = tile_alignment[ta].pitchalign;
 135                         aligned_height = align(aligned_height,
 136                                         tile_alignment[ta].heightalign);
 137                 } else {
 138                         pitchalign = 64;
 139                 }
 140
 141                 /* The blits used for mem<->gmem work at a granularity of
 142                  * 32x32, which can cause faults due to over-fetch on the
 143                  * last level.  The simple solution is to over-allocate a
 144                  * bit the last level to ensure any over-fetch is harmless.
 145                  * The pitch is already sufficiently aligned, but height
 146                  * may not be:
 147                  */
 148                 if (level == mip_levels - 1)
 149                         aligned_height = align(aligned_height, 32);
 150
 151                 if (format_desc->layout == UTIL_FORMAT_LAYOUT_ASTC)
 152                         slice->pitch =
 153                                 util_align_npot(width, pitchalign * util_format_get_blockwidth(format));
 154                 else
 155                         slice->pitch = align(width, pitchalign);
 156
 157                 slice->offset = layout->size;
 158                 uint32_t blocks = util_format_get_nblocks(format,
 159                                 slice->pitch, aligned_height);
 160
 161                 /* 1d array and 2d array textures must all have the same layer size
 162                  * for each miplevel on a6xx. 3d textures can have different layer
 163                  * sizes for high levels, but the hw auto-sizer is buggy (or at least
 164                  * different than what this code does), so as soon as the layer size
 165                  * range gets into range, we stop reducing it.
 166                  */
 167                 if (is_3d) {
 168                         if (level < 1 || layout->slices[level - 1].size0 > 0xf000) {
 169                                 slice->size0 = align(blocks * layout->cpp, alignment);
 170                         } else {
 171                                 slice->size0 = layout->slices[level - 1].size0;
 172                         }
 173                 } else {
 174                         slice->size0 = align(blocks * layout->cpp, alignment);
 175                 }
 176
 177                 layout->size += slice->size0 * depth * layers_in_level;
 178
 179                 if (ubwc) {
 180                         /* with UBWC every level is aligned to 4K */
 181                         layout->size = align(layout->size, 4096);
 182
 183                         uint32_t block_width = tile_alignment[ta].ubwc_blockwidth;
 184                         uint32_t block_height = tile_alignment[ta].ubwc_blockheight;
 185                         uint32_t meta_pitch = align(DIV_ROUND_UP(width, block_width),
 186                                         RGB_TILE_WIDTH_ALIGNMENT);
 187                         uint32_t meta_height = align(DIV_ROUND_UP(height, block_height),
 188                                         RGB_TILE_HEIGHT_ALIGNMENT);
 189
 190                         /* it looks like mipmaps need alignment to power of two
 191                          * TODO: needs testing with large npot textures
 192                          * (needed for the first level?)
 193                          */
 194                         if (mip_levels > 1) {
 195                                 meta_pitch = util_next_power_of_two(meta_pitch);
 196                                 meta_height = util_next_power_of_two(meta_height);
 197                         }
 198
 199                         ubwc_slice->size0 = align(meta_pitch * meta_height, UBWC_PLANE_SIZE_ALIGNMENT);
 200                         ubwc_slice->pitch = meta_pitch;
 201                         ubwc_slice->offset = layout->ubwc_size;
 202                         layout->ubwc_size += ubwc_slice->size0;
 203                 }
 204
 205                 depth = u_minify(depth, 1);
 206                 lwidth = u_minify(lwidth, 1);
 207                 lheight = u_minify(lheight, 1);
 208                 twidth = u_minify(twidth, 1);
 209                 theight = u_minify(theight, 1);
 210         }
 211
 212         if (layout->layer_first) {
 213                 layout->layer_size = align(layout->size, 4096);
 214                 layout->size = layout->layer_size * array_size;
 215         }
 216
 217         /* Place the UBWC slices before the uncompressed slices, because the
 218          * kernel expects UBWC to be at the start of the buffer.  In the HW, we
 219          * get to program the UBWC and non-UBWC offset/strides
 220          * independently.
 221          */
 222         if (ubwc) {
 223                 for (uint32_t level = 0; level < mip_levels; level++)
 224                         layout->slices[level].offset += layout->ubwc_size * array_size;
 225                 layout->size += layout->ubwc_size * array_size;
 226         }
 227 }
 228
 229 void
 230 fdl6_get_ubwc_blockwidth(struct fdl_layout *layout,
 231                 uint32_t *blockwidth, uint32_t *blockheight)
 232 {
 233         *blockwidth = tile_alignment[layout->cpp].ubwc_blockwidth;
 234         *blockheight = tile_alignment[layout->cpp].ubwc_blockheight;
 235 }