2 * Copyright (C) 2018 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018-2019 Google, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 * Rob Clark <robclark@freedesktop.org>
30 #include "freedreno_layout.h"
32 /* indexed by cpp, including msaa 2x and 4x:
34 * cpp=1 UBWC needs testing at larger texture sizes
35 * missing UBWC blockwidth/blockheight for npot+64 cpp
36 * missing 96/128 CPP for 8x MSAA with 32_32_32/32_32_32_32
42 uint8_t ubwc_blockwidth
;
43 uint8_t ubwc_blockheight
;
44 } tile_alignment
[] = {
45 [1] = { 64, 128, 32, 16, 4 },
46 [2] = { 128, 128, 16, 16, 4 },
47 [3] = { 256, 64, 32 },
48 [4] = { 256, 64, 16, 16, 4 },
49 [6] = { 256, 64, 16 },
50 [8] = { 256, 64, 16, 8, 4, },
51 [12] = { 256, 64, 16 },
52 [16] = { 256, 64, 16, 4, 4, },
53 [24] = { 256, 64, 16 },
54 [32] = { 256, 64, 16, 4, 2 },
55 [48] = { 256, 64, 16 },
56 [64] = { 256, 64, 16 },
58 /* special cases for r8g8: */
59 [0] = { 256, 64, 32, 16, 4 },
62 #define RGB_TILE_WIDTH_ALIGNMENT 64
63 #define RGB_TILE_HEIGHT_ALIGNMENT 16
64 #define UBWC_PLANE_SIZE_ALIGNMENT 4096
66 /* NOTE: good way to test this is: (for example)
67 * piglit/bin/texelFetch fs sampler3D 100x100x8
70 fdl6_layout(struct fdl_layout
*layout
,
71 enum pipe_format format
, uint32_t nr_samples
,
72 uint32_t width0
, uint32_t height0
, uint32_t depth0
,
73 uint32_t mip_levels
, uint32_t array_size
, bool is_3d
)
75 assert(nr_samples
> 0);
76 layout
->width0
= width0
;
77 layout
->height0
= height0
;
78 layout
->depth0
= depth0
;
80 layout
->cpp
= util_format_get_blocksize(format
);
81 layout
->cpp
*= nr_samples
;
82 layout
->format
= format
;
83 layout
->nr_samples
= nr_samples
;
84 layout
->layer_first
= !is_3d
;
88 if (tile_alignment
[layout
->cpp
].ubwc_blockwidth
== 0)
91 const struct util_format_description
*format_desc
=
92 util_format_description(format
);
95 /* The z16/r16 formats seem to not play by the normal tiling rules: */
96 if ((layout
->cpp
== 2) && (util_format_get_nr_components(format
) == 2))
99 /* in layer_first layout, the level (slice) contains just one
100 * layer (since in fact the layer contains the slices)
102 uint32_t layers_in_level
= layout
->layer_first
? 1 : array_size
;
104 debug_assert(ta
< ARRAY_SIZE(tile_alignment
));
105 debug_assert(tile_alignment
[ta
].pitchalign
);
107 if (layout
->tile_mode
) {
108 layout
->base_align
= tile_alignment
[ta
].basealign
;
110 layout
->base_align
= 64;
113 for (uint32_t level
= 0; level
< mip_levels
; level
++) {
114 uint32_t depth
= u_minify(depth0
, level
);
115 struct fdl_slice
*slice
= &layout
->slices
[level
];
116 struct fdl_slice
*ubwc_slice
= &layout
->ubwc_slices
[level
];
117 uint32_t tile_mode
= fdl_tile_mode(layout
, level
);
118 uint32_t width
, height
;
120 /* tiled levels of 3D textures are rounded up to PoT dimensions: */
121 if (is_3d
&& tile_mode
) {
122 width
= u_minify(util_next_power_of_two(width0
), level
);
123 height
= u_minify(util_next_power_of_two(height0
), level
);
125 width
= u_minify(width0
, level
);
126 height
= u_minify(height0
, level
);
131 pitchalign
= tile_alignment
[ta
].pitchalign
;
132 height
= align(height
, tile_alignment
[ta
].heightalign
);
137 /* The blits used for mem<->gmem work at a granularity of
138 * 32x32, which can cause faults due to over-fetch on the
139 * last level. The simple solution is to over-allocate a
140 * bit the last level to ensure any over-fetch is harmless.
141 * The pitch is already sufficiently aligned, but height
144 if (level
== mip_levels
- 1)
145 height
= align(height
, 32);
147 if (format_desc
->layout
== UTIL_FORMAT_LAYOUT_ASTC
)
149 util_align_npot(width
, pitchalign
* util_format_get_blockwidth(format
));
151 slice
->pitch
= align(width
, pitchalign
);
153 slice
->offset
= layout
->size
;
154 uint32_t blocks
= util_format_get_nblocks(format
,
155 slice
->pitch
, height
);
157 /* 1d array and 2d array textures must all have the same layer size
158 * for each miplevel on a6xx. 3d textures can have different layer
159 * sizes for high levels, but the hw auto-sizer is buggy (or at least
160 * different than what this code does), so as soon as the layer size
161 * range gets into range, we stop reducing it.
164 if (level
< 1 || layout
->slices
[level
- 1].size0
> 0xf000) {
165 slice
->size0
= align(blocks
* layout
->cpp
, 4096);
167 slice
->size0
= layout
->slices
[level
- 1].size0
;
170 slice
->size0
= blocks
* layout
->cpp
;
173 layout
->size
+= slice
->size0
* depth
* layers_in_level
;
176 /* with UBWC every level is aligned to 4K */
177 layout
->size
= align(layout
->size
, 4096);
179 uint32_t block_width
= tile_alignment
[ta
].ubwc_blockwidth
;
180 uint32_t block_height
= tile_alignment
[ta
].ubwc_blockheight
;
181 uint32_t meta_pitch
= align(DIV_ROUND_UP(width
, block_width
),
182 RGB_TILE_WIDTH_ALIGNMENT
);
183 uint32_t meta_height
= align(DIV_ROUND_UP(height
, block_height
),
184 RGB_TILE_HEIGHT_ALIGNMENT
);
186 /* it looks like mipmaps need alignment to power of two
187 * TODO: needs testing with large npot textures
188 * (needed for the first level?)
190 if (mip_levels
> 1) {
191 meta_pitch
= util_next_power_of_two(meta_pitch
);
192 meta_height
= util_next_power_of_two(meta_height
);
195 ubwc_slice
->size0
= align(meta_pitch
* meta_height
, UBWC_PLANE_SIZE_ALIGNMENT
);
196 ubwc_slice
->pitch
= meta_pitch
;
197 ubwc_slice
->offset
= layout
->ubwc_layer_size
;
198 layout
->ubwc_layer_size
+= ubwc_slice
->size0
;
202 if (layout
->layer_first
) {
203 layout
->layer_size
= align(layout
->size
, 4096);
204 layout
->size
= layout
->layer_size
* array_size
;
207 /* Place the UBWC slices before the uncompressed slices, because the
208 * kernel expects UBWC to be at the start of the buffer. In the HW, we
209 * get to program the UBWC and non-UBWC offset/strides
213 for (uint32_t level
= 0; level
< mip_levels
; level
++)
214 layout
->slices
[level
].offset
+= layout
->ubwc_layer_size
* array_size
;
215 layout
->size
+= layout
->ubwc_layer_size
* array_size
;
220 fdl6_get_ubwc_blockwidth(struct fdl_layout
*layout
,
221 uint32_t *blockwidth
, uint32_t *blockheight
)
223 *blockwidth
= tile_alignment
[layout
->cpp
].ubwc_blockwidth
;
224 *blockheight
= tile_alignment
[layout
->cpp
].ubwc_blockheight
;