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[mesa.git] / src / freedreno / ir3 / disasm-a3xx.c
1 /*
2 * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <stdio.h>
25 #include <stdlib.h>
26 #include <stdint.h>
27 #include <stdbool.h>
28 #include <string.h>
29 #include <assert.h>
30
31 #include <util/u_debug.h>
32
33 #include "instr-a3xx.h"
34
35 /* bitmask of debug flags */
36 enum debug_t {
37 PRINT_RAW = 0x1, /* dump raw hexdump */
38 PRINT_VERBOSE = 0x2,
39 EXPAND_REPEAT = 0x4,
40 };
41
42 static enum debug_t debug;
43
44 #define printf debug_printf
45
46 static const char *levels[] = {
47 "",
48 "\t",
49 "\t\t",
50 "\t\t\t",
51 "\t\t\t\t",
52 "\t\t\t\t\t",
53 "\t\t\t\t\t\t",
54 "\t\t\t\t\t\t\t",
55 "\t\t\t\t\t\t\t\t",
56 "\t\t\t\t\t\t\t\t\t",
57 "x",
58 "x",
59 "x",
60 "x",
61 "x",
62 "x",
63 };
64
65 static const char *component = "xyzw";
66
67 static const char *type[] = {
68 [TYPE_F16] = "f16",
69 [TYPE_F32] = "f32",
70 [TYPE_U16] = "u16",
71 [TYPE_U32] = "u32",
72 [TYPE_S16] = "s16",
73 [TYPE_S32] = "s32",
74 [TYPE_U8] = "u8",
75 [TYPE_S8] = "s8",
76 };
77
78 struct disasm_ctx {
79 FILE *out;
80 int level;
81 unsigned gpu_id;
82
83 /* current instruction repeat flag: */
84 unsigned repeat;
85 /* current instruction repeat indx/offset (for --expand): */
86 unsigned repeatidx;
87
88 unsigned instructions;
89 };
90
91 static const char *float_imms[] = {
92 "0.0",
93 "0.5",
94 "1.0",
95 "2.0",
96 "e",
97 "pi",
98 "1/pi",
99 "1/log2(e)",
100 "log2(e)",
101 "1/log2(10)",
102 "log2(10)",
103 "4.0",
104 };
105
106 static void print_reg(struct disasm_ctx *ctx, reg_t reg, bool full,
107 bool is_float, bool r,
108 bool c, bool im, bool neg, bool abs, bool addr_rel)
109 {
110 const char type = c ? 'c' : 'r';
111
112 // XXX I prefer - and || for neg/abs, but preserving format used
113 // by libllvm-a3xx for easy diffing..
114
115 if (abs && neg)
116 fprintf(ctx->out, "(absneg)");
117 else if (neg)
118 fprintf(ctx->out, "(neg)");
119 else if (abs)
120 fprintf(ctx->out, "(abs)");
121
122 if (r)
123 fprintf(ctx->out, "(r)");
124
125 if (im) {
126 if (is_float && full && reg.iim_val < ARRAY_SIZE(float_imms)) {
127 fprintf(ctx->out, "(%s)", float_imms[reg.iim_val]);
128 } else {
129 fprintf(ctx->out, "%d", reg.iim_val);
130 }
131 } else if (addr_rel) {
132 /* I would just use %+d but trying to make it diff'able with
133 * libllvm-a3xx...
134 */
135 if (reg.iim_val < 0)
136 fprintf(ctx->out, "%s%c<a0.x - %d>", full ? "" : "h", type, -reg.iim_val);
137 else if (reg.iim_val > 0)
138 fprintf(ctx->out, "%s%c<a0.x + %d>", full ? "" : "h", type, reg.iim_val);
139 else
140 fprintf(ctx->out, "%s%c<a0.x>", full ? "" : "h", type);
141 } else if ((reg.num == REG_A0) && !c) {
142 /* This matches libllvm output, the second (scalar) address register
143 * seems to be called a1.x instead of a0.y.
144 */
145 fprintf(ctx->out, "a%d.x", reg.comp);
146 } else if ((reg.num == REG_P0) && !c) {
147 fprintf(ctx->out, "p0.%c", component[reg.comp]);
148 } else {
149 fprintf(ctx->out, "%s%c%d.%c", full ? "" : "h", type, reg.num, component[reg.comp]);
150 }
151 }
152
153 static unsigned regidx(reg_t reg)
154 {
155 return (4 * reg.num) + reg.comp;
156 }
157
158 static reg_t idxreg(unsigned idx)
159 {
160 return (reg_t){
161 .comp = idx & 0x3,
162 .num = idx >> 2,
163 };
164 }
165
166 static void print_reg_dst(struct disasm_ctx *ctx, reg_t reg, bool full, bool addr_rel)
167 {
168 reg = idxreg(regidx(reg) + ctx->repeatidx);
169 print_reg(ctx, reg, full, false, false, false, false, false, false, addr_rel);
170 }
171
172 /* TODO switch to using reginfo struct everywhere, since more readable
173 * than passing a bunch of bools to print_reg_src
174 */
175
176 struct reginfo {
177 reg_t reg;
178 bool full;
179 bool r;
180 bool c;
181 bool f; /* src reg is interpreted as float, used for printing immediates */
182 bool im;
183 bool neg;
184 bool abs;
185 bool addr_rel;
186 };
187
188 static void print_src(struct disasm_ctx *ctx, struct reginfo *info)
189 {
190 reg_t reg = info->reg;
191
192 if (info->r)
193 reg = idxreg(regidx(info->reg) + ctx->repeatidx);
194
195 print_reg(ctx, reg, info->full, info->f, info->r, info->c, info->im,
196 info->neg, info->abs, info->addr_rel);
197 }
198
199 //static void print_dst(struct disasm_ctx *ctx, struct reginfo *info)
200 //{
201 // print_reg_dst(ctx, info->reg, info->full, info->addr_rel);
202 //}
203
204 static void print_instr_cat0(struct disasm_ctx *ctx, instr_t *instr)
205 {
206 static const struct {
207 const char *suffix;
208 int nsrc;
209 bool idx;
210 } brinfo[7] = {
211 [BRANCH_PLAIN] = { "r", 1, false },
212 [BRANCH_OR] = { "rao", 2, false },
213 [BRANCH_AND] = { "raa", 2, false },
214 [BRANCH_CONST] = { "rac", 0, true },
215 [BRANCH_ANY] = { "any", 1, false },
216 [BRANCH_ALL] = { "all", 1, false },
217 [BRANCH_X] = { "rax", 0, false },
218 };
219 instr_cat0_t *cat0 = &instr->cat0;
220
221 switch (instr_opc(instr, ctx->gpu_id)) {
222 case OPC_KILL:
223 case OPC_PREDT:
224 case OPC_PREDF:
225 fprintf(ctx->out, " %sp0.%c", cat0->inv0 ? "!" : "",
226 component[cat0->comp0]);
227 break;
228 case OPC_B:
229 fprintf(ctx->out, "%s", brinfo[cat0->brtype].suffix);
230 if (brinfo[cat0->brtype].idx) {
231 fprintf(ctx->out, ".%u", cat0->idx);
232 }
233 if (brinfo[cat0->brtype].nsrc >= 1) {
234 fprintf(ctx->out, " %sp0.%c,", cat0->inv0 ? "!" : "",
235 component[cat0->comp0]);
236 }
237 if (brinfo[cat0->brtype].nsrc >= 2) {
238 fprintf(ctx->out, " %sp0.%c,", cat0->inv1 ? "!" : "",
239 component[cat0->comp1]);
240 }
241 fprintf(ctx->out, " #%d", cat0->a3xx.immed);
242 break;
243 case OPC_JUMP:
244 case OPC_CALL:
245 case OPC_BKT:
246 case OPC_GETONE:
247 case OPC_SHPS:
248 fprintf(ctx->out, " #%d", cat0->a3xx.immed);
249 break;
250 }
251
252 if ((debug & PRINT_VERBOSE) && (cat0->dummy3|cat0->dummy4))
253 fprintf(ctx->out, "\t{0: %x,%x}", cat0->dummy3, cat0->dummy4);
254 }
255
256 static void print_instr_cat1(struct disasm_ctx *ctx, instr_t *instr)
257 {
258 instr_cat1_t *cat1 = &instr->cat1;
259
260 if (cat1->ul)
261 fprintf(ctx->out, "(ul)");
262
263 if (cat1->src_type == cat1->dst_type) {
264 if ((cat1->src_type == TYPE_S16) && (((reg_t)cat1->dst).num == REG_A0)) {
265 /* special case (nmemonic?): */
266 fprintf(ctx->out, "mova");
267 } else {
268 fprintf(ctx->out, "mov.%s%s", type[cat1->src_type], type[cat1->dst_type]);
269 }
270 } else {
271 fprintf(ctx->out, "cov.%s%s", type[cat1->src_type], type[cat1->dst_type]);
272 }
273
274 fprintf(ctx->out, " ");
275
276 if (cat1->even)
277 fprintf(ctx->out, "(even)");
278
279 if (cat1->pos_inf)
280 fprintf(ctx->out, "(pos_infinity)");
281
282 print_reg_dst(ctx, (reg_t)(cat1->dst), type_size(cat1->dst_type) == 32,
283 cat1->dst_rel);
284
285 fprintf(ctx->out, ", ");
286
287 /* ugg, have to special case this.. vs print_reg().. */
288 if (cat1->src_im) {
289 if (type_float(cat1->src_type))
290 fprintf(ctx->out, "(%f)", cat1->fim_val);
291 else if (type_uint(cat1->src_type))
292 fprintf(ctx->out, "0x%08x", cat1->uim_val);
293 else
294 fprintf(ctx->out, "%d", cat1->iim_val);
295 } else if (cat1->src_rel && !cat1->src_c) {
296 /* I would just use %+d but trying to make it diff'able with
297 * libllvm-a3xx...
298 */
299 char type = cat1->src_rel_c ? 'c' : 'r';
300 const char *full = (type_size(cat1->src_type) == 32) ? "" : "h";
301 if (cat1->off < 0)
302 fprintf(ctx->out, "%s%c<a0.x - %d>", full, type, -cat1->off);
303 else if (cat1->off > 0)
304 fprintf(ctx->out, "%s%c<a0.x + %d>", full, type, cat1->off);
305 else
306 fprintf(ctx->out, "%s%c<a0.x>", full, type);
307 } else {
308 struct reginfo src = {
309 .reg = (reg_t)cat1->src,
310 .full = type_size(cat1->src_type) == 32,
311 .r = cat1->src_r,
312 .c = cat1->src_c,
313 .im = cat1->src_im,
314 };
315 print_src(ctx, &src);
316 }
317
318 if ((debug & PRINT_VERBOSE) && (cat1->must_be_0))
319 fprintf(ctx->out, "\t{1: %x}", cat1->must_be_0);
320 }
321
322 static void print_instr_cat2(struct disasm_ctx *ctx, instr_t *instr)
323 {
324 instr_cat2_t *cat2 = &instr->cat2;
325 int opc = _OPC(2, cat2->opc);
326 static const char *cond[] = {
327 "lt",
328 "le",
329 "gt",
330 "ge",
331 "eq",
332 "ne",
333 "?6?",
334 };
335
336 switch (opc) {
337 case OPC_CMPS_F:
338 case OPC_CMPS_U:
339 case OPC_CMPS_S:
340 case OPC_CMPV_F:
341 case OPC_CMPV_U:
342 case OPC_CMPV_S:
343 fprintf(ctx->out, ".%s", cond[cat2->cond]);
344 break;
345 }
346
347 fprintf(ctx->out, " ");
348 if (cat2->ei)
349 fprintf(ctx->out, "(ei)");
350 print_reg_dst(ctx, (reg_t)(cat2->dst), cat2->full ^ cat2->dst_half, false);
351 fprintf(ctx->out, ", ");
352
353 struct reginfo src1 = {
354 .full = cat2->full,
355 .r = cat2->repeat ? cat2->src1_r : 0,
356 .f = is_cat2_float(opc),
357 .im = cat2->src1_im,
358 .abs = cat2->src1_abs,
359 .neg = cat2->src1_neg,
360 };
361
362 if (cat2->c1.src1_c) {
363 src1.reg = (reg_t)(cat2->c1.src1);
364 src1.c = true;
365 } else if (cat2->rel1.src1_rel) {
366 src1.reg = (reg_t)(cat2->rel1.src1);
367 src1.c = cat2->rel1.src1_c;
368 src1.addr_rel = true;
369 } else {
370 src1.reg = (reg_t)(cat2->src1);
371 }
372 print_src(ctx, &src1);
373
374 struct reginfo src2 = {
375 .r = cat2->repeat ? cat2->src2_r : 0,
376 .full = cat2->full,
377 .f = is_cat2_float(opc),
378 .abs = cat2->src2_abs,
379 .neg = cat2->src2_neg,
380 .im = cat2->src2_im,
381 };
382 switch (opc) {
383 case OPC_ABSNEG_F:
384 case OPC_ABSNEG_S:
385 case OPC_CLZ_B:
386 case OPC_CLZ_S:
387 case OPC_SIGN_F:
388 case OPC_FLOOR_F:
389 case OPC_CEIL_F:
390 case OPC_RNDNE_F:
391 case OPC_RNDAZ_F:
392 case OPC_TRUNC_F:
393 case OPC_NOT_B:
394 case OPC_BFREV_B:
395 case OPC_SETRM:
396 case OPC_CBITS_B:
397 /* these only have one src reg */
398 break;
399 default:
400 fprintf(ctx->out, ", ");
401 if (cat2->c2.src2_c) {
402 src2.reg = (reg_t)(cat2->c2.src2);
403 src2.c = true;
404 } else if (cat2->rel2.src2_rel) {
405 src2.reg = (reg_t)(cat2->rel2.src2);
406 src2.c = cat2->rel2.src2_c;
407 src2.addr_rel = true;
408 } else {
409 src2.reg = (reg_t)(cat2->src2);
410 }
411 print_src(ctx, &src2);
412 break;
413 }
414 }
415
416 static void print_instr_cat3(struct disasm_ctx *ctx, instr_t *instr)
417 {
418 instr_cat3_t *cat3 = &instr->cat3;
419 bool full = instr_cat3_full(cat3);
420
421 fprintf(ctx->out, " ");
422 print_reg_dst(ctx, (reg_t)(cat3->dst), full ^ cat3->dst_half, false);
423 fprintf(ctx->out, ", ");
424
425 struct reginfo src1 = {
426 .r = cat3->repeat ? cat3->src1_r : 0,
427 .full = full,
428 .neg = cat3->src1_neg,
429 };
430 if (cat3->c1.src1_c) {
431 src1.reg = (reg_t)(cat3->c1.src1);
432 src1.c = true;
433 } else if (cat3->rel1.src1_rel) {
434 src1.reg = (reg_t)(cat3->rel1.src1);
435 src1.c = cat3->rel1.src1_c;
436 src1.addr_rel = true;
437 } else {
438 src1.reg = (reg_t)(cat3->src1);
439 }
440 print_src(ctx, &src1);
441
442 fprintf(ctx->out, ", ");
443 struct reginfo src2 = {
444 .reg = (reg_t)cat3->src2,
445 .full = full,
446 .r = cat3->repeat ? cat3->src2_r : 0,
447 .c = cat3->src2_c,
448 .neg = cat3->src2_neg,
449 };
450 print_src(ctx, &src2);
451
452 fprintf(ctx->out, ", ");
453 struct reginfo src3 = {
454 .r = cat3->src3_r,
455 .full = full,
456 .neg = cat3->src3_neg,
457 };
458 if (cat3->c2.src3_c) {
459 src3.reg = (reg_t)(cat3->c2.src3);
460 src3.c = true;
461 } else if (cat3->rel2.src3_rel) {
462 src3.reg = (reg_t)(cat3->rel2.src3);
463 src3.c = cat3->rel2.src3_c;
464 src3.addr_rel = true;
465 } else {
466 src3.reg = (reg_t)(cat3->src3);
467 }
468 print_src(ctx, &src3);
469 }
470
471 static void print_instr_cat4(struct disasm_ctx *ctx, instr_t *instr)
472 {
473 instr_cat4_t *cat4 = &instr->cat4;
474
475 fprintf(ctx->out, " ");
476 print_reg_dst(ctx, (reg_t)(cat4->dst), cat4->full ^ cat4->dst_half, false);
477 fprintf(ctx->out, ", ");
478
479 struct reginfo src = {
480 .r = cat4->src_r,
481 .im = cat4->src_im,
482 .full = cat4->full,
483 .neg = cat4->src_neg,
484 .abs = cat4->src_abs,
485 };
486 if (cat4->c.src_c) {
487 src.reg = (reg_t)(cat4->c.src);
488 src.c = true;
489 } else if (cat4->rel.src_rel) {
490 src.reg = (reg_t)(cat4->rel.src);
491 src.c = cat4->rel.src_c;
492 src.addr_rel = true;
493 } else {
494 src.reg = (reg_t)(cat4->src);
495 }
496 print_src(ctx, &src);
497
498 if ((debug & PRINT_VERBOSE) && (cat4->dummy1|cat4->dummy2))
499 fprintf(ctx->out, "\t{4: %x,%x}", cat4->dummy1, cat4->dummy2);
500 }
501
502 static void print_instr_cat5(struct disasm_ctx *ctx, instr_t *instr)
503 {
504 static const struct {
505 bool src1, src2, samp, tex;
506 } info[0x1f] = {
507 [opc_op(OPC_ISAM)] = { true, false, true, true, },
508 [opc_op(OPC_ISAML)] = { true, true, true, true, },
509 [opc_op(OPC_ISAMM)] = { true, false, true, true, },
510 [opc_op(OPC_SAM)] = { true, false, true, true, },
511 [opc_op(OPC_SAMB)] = { true, true, true, true, },
512 [opc_op(OPC_SAML)] = { true, true, true, true, },
513 [opc_op(OPC_SAMGQ)] = { true, false, true, true, },
514 [opc_op(OPC_GETLOD)] = { true, false, true, true, },
515 [opc_op(OPC_CONV)] = { true, true, true, true, },
516 [opc_op(OPC_CONVM)] = { true, true, true, true, },
517 [opc_op(OPC_GETSIZE)] = { true, false, false, true, },
518 [opc_op(OPC_GETBUF)] = { false, false, false, true, },
519 [opc_op(OPC_GETPOS)] = { true, false, false, true, },
520 [opc_op(OPC_GETINFO)] = { false, false, false, true, },
521 [opc_op(OPC_DSX)] = { true, false, false, false, },
522 [opc_op(OPC_DSY)] = { true, false, false, false, },
523 [opc_op(OPC_GATHER4R)] = { true, false, true, true, },
524 [opc_op(OPC_GATHER4G)] = { true, false, true, true, },
525 [opc_op(OPC_GATHER4B)] = { true, false, true, true, },
526 [opc_op(OPC_GATHER4A)] = { true, false, true, true, },
527 [opc_op(OPC_SAMGP0)] = { true, false, true, true, },
528 [opc_op(OPC_SAMGP1)] = { true, false, true, true, },
529 [opc_op(OPC_SAMGP2)] = { true, false, true, true, },
530 [opc_op(OPC_SAMGP3)] = { true, false, true, true, },
531 [opc_op(OPC_DSXPP_1)] = { true, false, false, false, },
532 [opc_op(OPC_DSYPP_1)] = { true, false, false, false, },
533 [opc_op(OPC_RGETPOS)] = { true, false, false, false, },
534 [opc_op(OPC_RGETINFO)] = { false, false, false, false, },
535 };
536
537 static const struct {
538 bool indirect;
539 bool bindless;
540 bool use_a1;
541 bool uniform;
542 } desc_features[8] = {
543 [CAT5_NONUNIFORM] = { .indirect = true, },
544 [CAT5_UNIFORM] = { .indirect = true, .uniform = true, },
545 [CAT5_BINDLESS_IMM] = { .bindless = true, },
546 [CAT5_BINDLESS_UNIFORM] = {
547 .bindless = true,
548 .indirect = true,
549 .uniform = true,
550 },
551 [CAT5_BINDLESS_NONUNIFORM] = {
552 .bindless = true,
553 .indirect = true,
554 },
555 [CAT5_BINDLESS_A1_IMM] = {
556 .bindless = true,
557 .use_a1 = true,
558 },
559 [CAT5_BINDLESS_A1_UNIFORM] = {
560 .bindless = true,
561 .indirect = true,
562 .uniform = true,
563 .use_a1 = true,
564 },
565 [CAT5_BINDLESS_A1_NONUNIFORM] = {
566 .bindless = true,
567 .indirect = true,
568 .use_a1 = true,
569 },
570 };
571
572 instr_cat5_t *cat5 = &instr->cat5;
573 int i;
574
575 bool desc_indirect =
576 cat5->is_s2en_bindless &&
577 desc_features[cat5->s2en_bindless.desc_mode].indirect;
578 bool bindless =
579 cat5->is_s2en_bindless &&
580 desc_features[cat5->s2en_bindless.desc_mode].bindless;
581 bool use_a1 =
582 cat5->is_s2en_bindless &&
583 desc_features[cat5->s2en_bindless.desc_mode].use_a1;
584 bool uniform =
585 cat5->is_s2en_bindless &&
586 desc_features[cat5->s2en_bindless.desc_mode].uniform;
587
588 if (cat5->is_3d) fprintf(ctx->out, ".3d");
589 if (cat5->is_a) fprintf(ctx->out, ".a");
590 if (cat5->is_o) fprintf(ctx->out, ".o");
591 if (cat5->is_p) fprintf(ctx->out, ".p");
592 if (cat5->is_s) fprintf(ctx->out, ".s");
593 if (desc_indirect) fprintf(ctx->out, ".s2en");
594 if (uniform) fprintf(ctx->out, ".uniform");
595
596 if (bindless) {
597 unsigned base = (cat5->s2en_bindless.base_hi << 1) | cat5->base_lo;
598 fprintf(ctx->out, ".base%d", base);
599 }
600
601 fprintf(ctx->out, " ");
602
603 switch (_OPC(5, cat5->opc)) {
604 case OPC_DSXPP_1:
605 case OPC_DSYPP_1:
606 break;
607 default:
608 fprintf(ctx->out, "(%s)", type[cat5->type]);
609 break;
610 }
611
612 fprintf(ctx->out, "(");
613 for (i = 0; i < 4; i++)
614 if (cat5->wrmask & (1 << i))
615 fprintf(ctx->out, "%c", "xyzw"[i]);
616 fprintf(ctx->out, ")");
617
618 print_reg_dst(ctx, (reg_t)(cat5->dst), type_size(cat5->type) == 32, false);
619
620 if (info[cat5->opc].src1) {
621 fprintf(ctx->out, ", ");
622 struct reginfo src = { .reg = (reg_t)(cat5->src1), .full = cat5->full };
623 print_src(ctx, &src);
624 }
625
626 if (cat5->is_o || info[cat5->opc].src2) {
627 fprintf(ctx->out, ", ");
628 struct reginfo src = { .reg = (reg_t)(cat5->src2), .full = cat5->full };
629 print_src(ctx, &src);
630 }
631 if (cat5->is_s2en_bindless) {
632 if (!desc_indirect) {
633 if (info[cat5->opc].samp) {
634 if (use_a1)
635 fprintf(ctx->out, ", s#%d", cat5->s2en_bindless.src3);
636 else
637 fprintf(ctx->out, ", s#%d", cat5->s2en_bindless.src3 & 0xf);
638 }
639
640 if (info[cat5->opc].tex && !use_a1) {
641 fprintf(ctx->out, ", t#%d", cat5->s2en_bindless.src3 >> 4);
642 }
643 }
644 } else {
645 if (info[cat5->opc].samp)
646 fprintf(ctx->out, ", s#%d", cat5->norm.samp);
647 if (info[cat5->opc].tex)
648 fprintf(ctx->out, ", t#%d", cat5->norm.tex);
649 }
650
651 if (desc_indirect) {
652 fprintf(ctx->out, ", ");
653 struct reginfo src = { .reg = (reg_t)(cat5->s2en_bindless.src3), .full = bindless };
654 print_src(ctx, &src);
655 }
656
657 if (use_a1)
658 fprintf(ctx->out, ", a1.x");
659
660 if (debug & PRINT_VERBOSE) {
661 if (cat5->is_s2en_bindless) {
662 if ((debug & PRINT_VERBOSE) && cat5->s2en_bindless.dummy1)
663 fprintf(ctx->out, "\t{5: %x}", cat5->s2en_bindless.dummy1);
664 } else {
665 if ((debug & PRINT_VERBOSE) && cat5->norm.dummy1)
666 fprintf(ctx->out, "\t{5: %x}", cat5->norm.dummy1);
667 }
668 }
669 }
670
671 static void print_instr_cat6_a3xx(struct disasm_ctx *ctx, instr_t *instr)
672 {
673 instr_cat6_t *cat6 = &instr->cat6;
674 char sd = 0, ss = 0; /* dst/src address space */
675 bool nodst = false;
676 struct reginfo dst, src1, src2, ssbo;
677 int src1off = 0, dstoff = 0;
678
679 memset(&dst, 0, sizeof(dst));
680 memset(&src1, 0, sizeof(src1));
681 memset(&src2, 0, sizeof(src2));
682 memset(&ssbo, 0, sizeof(ssbo));
683
684 switch (_OPC(6, cat6->opc)) {
685 case OPC_RESINFO:
686 case OPC_RESFMT:
687 dst.full = type_size(cat6->type) == 32;
688 src1.full = type_size(cat6->type) == 32;
689 src2.full = type_size(cat6->type) == 32;
690 break;
691 case OPC_L2G:
692 case OPC_G2L:
693 dst.full = true;
694 src1.full = true;
695 src2.full = true;
696 break;
697 case OPC_STG:
698 case OPC_STL:
699 case OPC_STP:
700 case OPC_STLW:
701 case OPC_STIB:
702 dst.full = type_size(cat6->type) == 32;
703 src1.full = type_size(cat6->type) == 32;
704 src2.full = type_size(cat6->type) == 32;
705 break;
706 default:
707 dst.full = type_size(cat6->type) == 32;
708 src1.full = true;
709 src2.full = true;
710 break;
711 }
712
713 switch (_OPC(6, cat6->opc)) {
714 case OPC_PREFETCH:
715 break;
716 case OPC_RESINFO:
717 fprintf(ctx->out, ".%dd", cat6->ldgb.d + 1);
718 break;
719 case OPC_LDGB:
720 fprintf(ctx->out, ".%s", cat6->ldgb.typed ? "typed" : "untyped");
721 fprintf(ctx->out, ".%dd", cat6->ldgb.d + 1);
722 fprintf(ctx->out, ".%s", type[cat6->type]);
723 fprintf(ctx->out, ".%d", cat6->ldgb.type_size + 1);
724 break;
725 case OPC_STGB:
726 case OPC_STIB:
727 fprintf(ctx->out, ".%s", cat6->stgb.typed ? "typed" : "untyped");
728 fprintf(ctx->out, ".%dd", cat6->stgb.d + 1);
729 fprintf(ctx->out, ".%s", type[cat6->type]);
730 fprintf(ctx->out, ".%d", cat6->stgb.type_size + 1);
731 break;
732 case OPC_ATOMIC_ADD:
733 case OPC_ATOMIC_SUB:
734 case OPC_ATOMIC_XCHG:
735 case OPC_ATOMIC_INC:
736 case OPC_ATOMIC_DEC:
737 case OPC_ATOMIC_CMPXCHG:
738 case OPC_ATOMIC_MIN:
739 case OPC_ATOMIC_MAX:
740 case OPC_ATOMIC_AND:
741 case OPC_ATOMIC_OR:
742 case OPC_ATOMIC_XOR:
743 ss = cat6->g ? 'g' : 'l';
744 fprintf(ctx->out, ".%s", cat6->ldgb.typed ? "typed" : "untyped");
745 fprintf(ctx->out, ".%dd", cat6->ldgb.d + 1);
746 fprintf(ctx->out, ".%s", type[cat6->type]);
747 fprintf(ctx->out, ".%d", cat6->ldgb.type_size + 1);
748 fprintf(ctx->out, ".%c", ss);
749 break;
750 default:
751 dst.im = cat6->g && !cat6->dst_off;
752 fprintf(ctx->out, ".%s", type[cat6->type]);
753 break;
754 }
755 fprintf(ctx->out, " ");
756
757 switch (_OPC(6, cat6->opc)) {
758 case OPC_STG:
759 sd = 'g';
760 break;
761 case OPC_STP:
762 sd = 'p';
763 break;
764 case OPC_STL:
765 case OPC_STLW:
766 sd = 'l';
767 break;
768
769 case OPC_LDG:
770 case OPC_LDC:
771 ss = 'g';
772 break;
773 case OPC_LDP:
774 ss = 'p';
775 break;
776 case OPC_LDL:
777 case OPC_LDLW:
778 case OPC_LDLV:
779 ss = 'l';
780 break;
781
782 case OPC_L2G:
783 ss = 'l';
784 sd = 'g';
785 break;
786
787 case OPC_G2L:
788 ss = 'g';
789 sd = 'l';
790 break;
791
792 case OPC_PREFETCH:
793 ss = 'g';
794 nodst = true;
795 break;
796 }
797
798 if ((_OPC(6, cat6->opc) == OPC_STGB) || (_OPC(6, cat6->opc) == OPC_STIB)) {
799 struct reginfo src3;
800
801 memset(&src3, 0, sizeof(src3));
802
803 src1.reg = (reg_t)(cat6->stgb.src1);
804 src2.reg = (reg_t)(cat6->stgb.src2);
805 src2.im = cat6->stgb.src2_im;
806 src3.reg = (reg_t)(cat6->stgb.src3);
807 src3.im = cat6->stgb.src3_im;
808 src3.full = true;
809
810 fprintf(ctx->out, "g[%u], ", cat6->stgb.dst_ssbo);
811 print_src(ctx, &src1);
812 fprintf(ctx->out, ", ");
813 print_src(ctx, &src2);
814 fprintf(ctx->out, ", ");
815 print_src(ctx, &src3);
816
817 if (debug & PRINT_VERBOSE)
818 fprintf(ctx->out, " (pad0=%x, pad3=%x)", cat6->stgb.pad0, cat6->stgb.pad3);
819
820 return;
821 }
822
823 if (is_atomic(_OPC(6, cat6->opc))) {
824
825 src1.reg = (reg_t)(cat6->ldgb.src1);
826 src1.im = cat6->ldgb.src1_im;
827 src2.reg = (reg_t)(cat6->ldgb.src2);
828 src2.im = cat6->ldgb.src2_im;
829 dst.reg = (reg_t)(cat6->ldgb.dst);
830
831 print_src(ctx, &dst);
832 fprintf(ctx->out, ", ");
833 if (ss == 'g') {
834 struct reginfo src3;
835 memset(&src3, 0, sizeof(src3));
836
837 src3.reg = (reg_t)(cat6->ldgb.src3);
838 src3.full = true;
839
840 /* For images, the ".typed" variant is used and src2 is
841 * the ivecN coordinates, ie ivec2 for 2d.
842 *
843 * For SSBOs, the ".untyped" variant is used and src2 is
844 * a simple dword offset.. src3 appears to be
845 * uvec2(offset * 4, 0). Not sure the point of that.
846 */
847
848 fprintf(ctx->out, "g[%u], ", cat6->ldgb.src_ssbo);
849 print_src(ctx, &src1); /* value */
850 fprintf(ctx->out, ", ");
851 print_src(ctx, &src2); /* offset/coords */
852 fprintf(ctx->out, ", ");
853 print_src(ctx, &src3); /* 64b byte offset.. */
854
855 if (debug & PRINT_VERBOSE) {
856 fprintf(ctx->out, " (pad0=%x, mustbe0=%x)", cat6->ldgb.pad0,
857 cat6->ldgb.mustbe0);
858 }
859 } else { /* ss == 'l' */
860 fprintf(ctx->out, "l[");
861 print_src(ctx, &src1); /* simple byte offset */
862 fprintf(ctx->out, "], ");
863 print_src(ctx, &src2); /* value */
864
865 if (debug & PRINT_VERBOSE) {
866 fprintf(ctx->out, " (src3=%x, pad0=%x, src_ssbo_im=%x, mustbe0=%x)",
867 cat6->ldgb.src3, cat6->ldgb.pad0,
868 cat6->ldgb.src_ssbo_im, cat6->ldgb.mustbe0);
869 }
870 }
871
872 return;
873 } else if (_OPC(6, cat6->opc) == OPC_RESINFO) {
874 dst.reg = (reg_t)(cat6->ldgb.dst);
875 ssbo.reg = (reg_t)(cat6->ldgb.src_ssbo);
876 ssbo.im = cat6->ldgb.src_ssbo_im;
877
878 print_src(ctx, &dst);
879 fprintf(ctx->out, ", ");
880
881 fprintf(ctx->out, "g[");
882 print_src(ctx, &ssbo);
883 fprintf(ctx->out, "]");
884
885 return;
886 } else if (_OPC(6, cat6->opc) == OPC_LDGB) {
887
888 src1.reg = (reg_t)(cat6->ldgb.src1);
889 src1.im = cat6->ldgb.src1_im;
890 src2.reg = (reg_t)(cat6->ldgb.src2);
891 src2.im = cat6->ldgb.src2_im;
892 ssbo.reg = (reg_t)(cat6->ldgb.src_ssbo);
893 ssbo.im = cat6->ldgb.src_ssbo_im;
894 dst.reg = (reg_t)(cat6->ldgb.dst);
895
896 print_src(ctx, &dst);
897 fprintf(ctx->out, ", ");
898
899 fprintf(ctx->out, "g[");
900 print_src(ctx, &ssbo);
901 fprintf(ctx->out, "], ");
902
903 print_src(ctx, &src1);
904 fprintf(ctx->out, ", ");
905 print_src(ctx, &src2);
906
907 if (debug & PRINT_VERBOSE)
908 fprintf(ctx->out, " (pad0=%x, ssbo_im=%x, mustbe0=%x)", cat6->ldgb.pad0, cat6->ldgb.src_ssbo_im, cat6->ldgb.mustbe0);
909
910 return;
911 } else if (_OPC(6, cat6->opc) == OPC_LDG && cat6->a.src1_im && cat6->a.src2_im) {
912 struct reginfo src3;
913
914 memset(&src3, 0, sizeof(src3));
915 src1.reg = (reg_t)(cat6->a.src1);
916 src2.reg = (reg_t)(cat6->a.src2);
917 src2.im = cat6->a.src2_im;
918 src3.reg = (reg_t)(cat6->a.off);
919 src3.full = true;
920 dst.reg = (reg_t)(cat6->d.dst);
921
922 print_src(ctx, &dst);
923 fprintf(ctx->out, ", g[");
924 print_src(ctx, &src1);
925 fprintf(ctx->out, "+");
926 print_src(ctx, &src3);
927 fprintf(ctx->out, "], ");
928 print_src(ctx, &src2);
929
930 return;
931 }
932 if (cat6->dst_off) {
933 dst.reg = (reg_t)(cat6->c.dst);
934 dstoff = cat6->c.off;
935 } else {
936 dst.reg = (reg_t)(cat6->d.dst);
937 }
938
939 if (cat6->src_off) {
940 src1.reg = (reg_t)(cat6->a.src1);
941 src1.im = cat6->a.src1_im;
942 src2.reg = (reg_t)(cat6->a.src2);
943 src2.im = cat6->a.src2_im;
944 src1off = cat6->a.off;
945 } else {
946 src1.reg = (reg_t)(cat6->b.src1);
947 src1.im = cat6->b.src1_im;
948 src2.reg = (reg_t)(cat6->b.src2);
949 src2.im = cat6->b.src2_im;
950 }
951
952 if (!nodst) {
953 if (sd)
954 fprintf(ctx->out, "%c[", sd);
955 /* note: dst might actually be a src (ie. address to store to) */
956 print_src(ctx, &dst);
957 if (cat6->dst_off && cat6->g) {
958 struct reginfo dstoff_reg = {0};
959 dstoff_reg.reg = (reg_t) cat6->c.off;
960 dstoff_reg.full = true;
961 fprintf(ctx->out, "+");
962 print_src(ctx, &dstoff_reg);
963 } else if (dstoff)
964 fprintf(ctx->out, "%+d", dstoff);
965 if (sd)
966 fprintf(ctx->out, "]");
967 fprintf(ctx->out, ", ");
968 }
969
970 if (ss)
971 fprintf(ctx->out, "%c[", ss);
972
973 /* can have a larger than normal immed, so hack: */
974 if (src1.im) {
975 fprintf(ctx->out, "%u", src1.reg.dummy13);
976 } else {
977 print_src(ctx, &src1);
978 }
979
980 if (cat6->src_off && cat6->g)
981 print_src(ctx, &src2);
982 else if (src1off)
983 fprintf(ctx->out, "%+d", src1off);
984 if (ss)
985 fprintf(ctx->out, "]");
986
987 switch (_OPC(6, cat6->opc)) {
988 case OPC_RESINFO:
989 case OPC_RESFMT:
990 break;
991 default:
992 fprintf(ctx->out, ", ");
993 print_src(ctx, &src2);
994 break;
995 }
996 }
997
998 static void print_instr_cat6_a6xx(struct disasm_ctx *ctx, instr_t *instr)
999 {
1000 instr_cat6_a6xx_t *cat6 = &instr->cat6_a6xx;
1001 struct reginfo src1, src2, ssbo;
1002 uint32_t opc = _OPC(6, cat6->opc);
1003 bool uses_type = opc != OPC_LDC;
1004
1005 static const struct {
1006 bool indirect;
1007 bool bindless;
1008 const char *name;
1009 } desc_features[8] = {
1010 [CAT6_IMM] = {
1011 .name = "imm"
1012 },
1013 [CAT6_UNIFORM] = {
1014 .indirect = true,
1015 .name = "uniform"
1016 },
1017 [CAT6_NONUNIFORM] = {
1018 .indirect = true,
1019 .name = "nonuniform"
1020 },
1021 [CAT6_BINDLESS_IMM] = {
1022 .bindless = true,
1023 .name = "imm"
1024 },
1025 [CAT6_BINDLESS_UNIFORM] = {
1026 .bindless = true,
1027 .indirect = true,
1028 .name = "uniform"
1029 },
1030 [CAT6_BINDLESS_NONUNIFORM] = {
1031 .bindless = true,
1032 .indirect = true,
1033 .name = "nonuniform"
1034 },
1035 };
1036
1037 bool indirect_ssbo = desc_features[cat6->desc_mode].indirect;
1038 bool bindless = desc_features[cat6->desc_mode].bindless;
1039 bool type_full = cat6->type != TYPE_U16;
1040
1041
1042 memset(&src1, 0, sizeof(src1));
1043 memset(&src2, 0, sizeof(src2));
1044 memset(&ssbo, 0, sizeof(ssbo));
1045
1046 if (uses_type) {
1047 fprintf(ctx->out, ".%s", cat6->typed ? "typed" : "untyped");
1048 fprintf(ctx->out, ".%dd", cat6->d + 1);
1049 fprintf(ctx->out, ".%s", type[cat6->type]);
1050 } else {
1051 fprintf(ctx->out, ".offset%d", cat6->d);
1052 }
1053 fprintf(ctx->out, ".%u", cat6->type_size + 1);
1054
1055 fprintf(ctx->out, ".%s", desc_features[cat6->desc_mode].name);
1056 if (bindless)
1057 fprintf(ctx->out, ".base%d", cat6->base);
1058 fprintf(ctx->out, " ");
1059
1060 src2.reg = (reg_t)(cat6->src2);
1061 src2.full = type_full;
1062 print_src(ctx, &src2);
1063 fprintf(ctx->out, ", ");
1064
1065 if (opc != OPC_RESINFO) {
1066 src1.reg = (reg_t)(cat6->src1);
1067 src1.full = true; // XXX
1068 print_src(ctx, &src1);
1069 fprintf(ctx->out, ", ");
1070 }
1071
1072 ssbo.reg = (reg_t)(cat6->ssbo);
1073 ssbo.im = !indirect_ssbo;
1074 ssbo.full = true;
1075 print_src(ctx, &ssbo);
1076
1077 if (debug & PRINT_VERBOSE) {
1078 fprintf(ctx->out, " (pad1=%x, pad2=%x, pad3=%x, pad4=%x, pad5=%x)",
1079 cat6->pad1, cat6->pad2, cat6->pad3, cat6->pad4, cat6->pad5);
1080 }
1081 }
1082
1083 static void print_instr_cat6(struct disasm_ctx *ctx, instr_t *instr)
1084 {
1085 if (!is_cat6_legacy(instr, ctx->gpu_id)) {
1086 print_instr_cat6_a6xx(ctx, instr);
1087 if (debug & PRINT_VERBOSE)
1088 fprintf(ctx->out, " NEW");
1089 } else {
1090 print_instr_cat6_a3xx(ctx, instr);
1091 if (debug & PRINT_VERBOSE)
1092 fprintf(ctx->out, " LEGACY");
1093 }
1094 }
1095 static void print_instr_cat7(struct disasm_ctx *ctx, instr_t *instr)
1096 {
1097 instr_cat7_t *cat7 = &instr->cat7;
1098
1099 if (cat7->g)
1100 fprintf(ctx->out, ".g");
1101 if (cat7->l)
1102 fprintf(ctx->out, ".l");
1103
1104 if (_OPC(7, cat7->opc) == OPC_FENCE) {
1105 if (cat7->r)
1106 fprintf(ctx->out, ".r");
1107 if (cat7->w)
1108 fprintf(ctx->out, ".w");
1109 }
1110 }
1111
1112 /* size of largest OPC field of all the instruction categories: */
1113 #define NOPC_BITS 6
1114
1115 static const struct opc_info {
1116 uint16_t cat;
1117 uint16_t opc;
1118 const char *name;
1119 void (*print)(struct disasm_ctx *ctx, instr_t *instr);
1120 } opcs[1 << (3+NOPC_BITS)] = {
1121 #define OPC(cat, opc, name) [(opc)] = { (cat), (opc), #name, print_instr_cat##cat }
1122 /* category 0: */
1123 OPC(0, OPC_NOP, nop),
1124 OPC(0, OPC_B, b),
1125 OPC(0, OPC_JUMP, jump),
1126 OPC(0, OPC_CALL, call),
1127 OPC(0, OPC_RET, ret),
1128 OPC(0, OPC_KILL, kill),
1129 OPC(0, OPC_END, end),
1130 OPC(0, OPC_EMIT, emit),
1131 OPC(0, OPC_CUT, cut),
1132 OPC(0, OPC_CHMASK, chmask),
1133 OPC(0, OPC_CHSH, chsh),
1134 OPC(0, OPC_FLOW_REV, flow_rev),
1135 OPC(0, OPC_PREDT, predt),
1136 OPC(0, OPC_PREDF, predf),
1137 OPC(0, OPC_PREDE, prede),
1138 OPC(0, OPC_BKT, bkt),
1139 OPC(0, OPC_STKS, stks),
1140 OPC(0, OPC_STKR, stkr),
1141 OPC(0, OPC_XSET, xset),
1142 OPC(0, OPC_XCLR, xclr),
1143 OPC(0, OPC_GETONE, getone),
1144 OPC(0, OPC_DBG, dbg),
1145 OPC(0, OPC_SHPS, shps),
1146 OPC(0, OPC_SHPE, shpe),
1147
1148 /* category 1: */
1149 OPC(1, OPC_MOV, ),
1150
1151 /* category 2: */
1152 OPC(2, OPC_ADD_F, add.f),
1153 OPC(2, OPC_MIN_F, min.f),
1154 OPC(2, OPC_MAX_F, max.f),
1155 OPC(2, OPC_MUL_F, mul.f),
1156 OPC(2, OPC_SIGN_F, sign.f),
1157 OPC(2, OPC_CMPS_F, cmps.f),
1158 OPC(2, OPC_ABSNEG_F, absneg.f),
1159 OPC(2, OPC_CMPV_F, cmpv.f),
1160 OPC(2, OPC_FLOOR_F, floor.f),
1161 OPC(2, OPC_CEIL_F, ceil.f),
1162 OPC(2, OPC_RNDNE_F, rndne.f),
1163 OPC(2, OPC_RNDAZ_F, rndaz.f),
1164 OPC(2, OPC_TRUNC_F, trunc.f),
1165 OPC(2, OPC_ADD_U, add.u),
1166 OPC(2, OPC_ADD_S, add.s),
1167 OPC(2, OPC_SUB_U, sub.u),
1168 OPC(2, OPC_SUB_S, sub.s),
1169 OPC(2, OPC_CMPS_U, cmps.u),
1170 OPC(2, OPC_CMPS_S, cmps.s),
1171 OPC(2, OPC_MIN_U, min.u),
1172 OPC(2, OPC_MIN_S, min.s),
1173 OPC(2, OPC_MAX_U, max.u),
1174 OPC(2, OPC_MAX_S, max.s),
1175 OPC(2, OPC_ABSNEG_S, absneg.s),
1176 OPC(2, OPC_AND_B, and.b),
1177 OPC(2, OPC_OR_B, or.b),
1178 OPC(2, OPC_NOT_B, not.b),
1179 OPC(2, OPC_XOR_B, xor.b),
1180 OPC(2, OPC_CMPV_U, cmpv.u),
1181 OPC(2, OPC_CMPV_S, cmpv.s),
1182 OPC(2, OPC_MUL_U24, mul.u24),
1183 OPC(2, OPC_MUL_S24, mul.s24),
1184 OPC(2, OPC_MULL_U, mull.u),
1185 OPC(2, OPC_BFREV_B, bfrev.b),
1186 OPC(2, OPC_CLZ_S, clz.s),
1187 OPC(2, OPC_CLZ_B, clz.b),
1188 OPC(2, OPC_SHL_B, shl.b),
1189 OPC(2, OPC_SHR_B, shr.b),
1190 OPC(2, OPC_ASHR_B, ashr.b),
1191 OPC(2, OPC_BARY_F, bary.f),
1192 OPC(2, OPC_MGEN_B, mgen.b),
1193 OPC(2, OPC_GETBIT_B, getbit.b),
1194 OPC(2, OPC_SETRM, setrm),
1195 OPC(2, OPC_CBITS_B, cbits.b),
1196 OPC(2, OPC_SHB, shb),
1197 OPC(2, OPC_MSAD, msad),
1198
1199 /* category 3: */
1200 OPC(3, OPC_MAD_U16, mad.u16),
1201 OPC(3, OPC_MADSH_U16, madsh.u16),
1202 OPC(3, OPC_MAD_S16, mad.s16),
1203 OPC(3, OPC_MADSH_M16, madsh.m16),
1204 OPC(3, OPC_MAD_U24, mad.u24),
1205 OPC(3, OPC_MAD_S24, mad.s24),
1206 OPC(3, OPC_MAD_F16, mad.f16),
1207 OPC(3, OPC_MAD_F32, mad.f32),
1208 OPC(3, OPC_SEL_B16, sel.b16),
1209 OPC(3, OPC_SEL_B32, sel.b32),
1210 OPC(3, OPC_SEL_S16, sel.s16),
1211 OPC(3, OPC_SEL_S32, sel.s32),
1212 OPC(3, OPC_SEL_F16, sel.f16),
1213 OPC(3, OPC_SEL_F32, sel.f32),
1214 OPC(3, OPC_SAD_S16, sad.s16),
1215 OPC(3, OPC_SAD_S32, sad.s32),
1216
1217 /* category 4: */
1218 OPC(4, OPC_RCP, rcp),
1219 OPC(4, OPC_RSQ, rsq),
1220 OPC(4, OPC_LOG2, log2),
1221 OPC(4, OPC_EXP2, exp2),
1222 OPC(4, OPC_SIN, sin),
1223 OPC(4, OPC_COS, cos),
1224 OPC(4, OPC_SQRT, sqrt),
1225 OPC(4, OPC_HRSQ, hrsq),
1226 OPC(4, OPC_HLOG2, hlog2),
1227 OPC(4, OPC_HEXP2, hexp2),
1228
1229 /* category 5: */
1230 OPC(5, OPC_ISAM, isam),
1231 OPC(5, OPC_ISAML, isaml),
1232 OPC(5, OPC_ISAMM, isamm),
1233 OPC(5, OPC_SAM, sam),
1234 OPC(5, OPC_SAMB, samb),
1235 OPC(5, OPC_SAML, saml),
1236 OPC(5, OPC_SAMGQ, samgq),
1237 OPC(5, OPC_GETLOD, getlod),
1238 OPC(5, OPC_CONV, conv),
1239 OPC(5, OPC_CONVM, convm),
1240 OPC(5, OPC_GETSIZE, getsize),
1241 OPC(5, OPC_GETBUF, getbuf),
1242 OPC(5, OPC_GETPOS, getpos),
1243 OPC(5, OPC_GETINFO, getinfo),
1244 OPC(5, OPC_DSX, dsx),
1245 OPC(5, OPC_DSY, dsy),
1246 OPC(5, OPC_GATHER4R, gather4r),
1247 OPC(5, OPC_GATHER4G, gather4g),
1248 OPC(5, OPC_GATHER4B, gather4b),
1249 OPC(5, OPC_GATHER4A, gather4a),
1250 OPC(5, OPC_SAMGP0, samgp0),
1251 OPC(5, OPC_SAMGP1, samgp1),
1252 OPC(5, OPC_SAMGP2, samgp2),
1253 OPC(5, OPC_SAMGP3, samgp3),
1254 OPC(5, OPC_DSXPP_1, dsxpp.1),
1255 OPC(5, OPC_DSYPP_1, dsypp.1),
1256 OPC(5, OPC_RGETPOS, rgetpos),
1257 OPC(5, OPC_RGETINFO, rgetinfo),
1258
1259
1260 /* category 6: */
1261 OPC(6, OPC_LDG, ldg),
1262 OPC(6, OPC_LDL, ldl),
1263 OPC(6, OPC_LDP, ldp),
1264 OPC(6, OPC_STG, stg),
1265 OPC(6, OPC_STL, stl),
1266 OPC(6, OPC_STP, stp),
1267 OPC(6, OPC_LDIB, ldib),
1268 OPC(6, OPC_G2L, g2l),
1269 OPC(6, OPC_L2G, l2g),
1270 OPC(6, OPC_PREFETCH, prefetch),
1271 OPC(6, OPC_LDLW, ldlw),
1272 OPC(6, OPC_STLW, stlw),
1273 OPC(6, OPC_RESFMT, resfmt),
1274 OPC(6, OPC_RESINFO, resinfo),
1275 OPC(6, OPC_ATOMIC_ADD, atomic.add),
1276 OPC(6, OPC_ATOMIC_SUB, atomic.sub),
1277 OPC(6, OPC_ATOMIC_XCHG, atomic.xchg),
1278 OPC(6, OPC_ATOMIC_INC, atomic.inc),
1279 OPC(6, OPC_ATOMIC_DEC, atomic.dec),
1280 OPC(6, OPC_ATOMIC_CMPXCHG, atomic.cmpxchg),
1281 OPC(6, OPC_ATOMIC_MIN, atomic.min),
1282 OPC(6, OPC_ATOMIC_MAX, atomic.max),
1283 OPC(6, OPC_ATOMIC_AND, atomic.and),
1284 OPC(6, OPC_ATOMIC_OR, atomic.or),
1285 OPC(6, OPC_ATOMIC_XOR, atomic.xor),
1286 OPC(6, OPC_LDGB, ldgb),
1287 OPC(6, OPC_STGB, stgb),
1288 OPC(6, OPC_STIB, stib),
1289 OPC(6, OPC_LDC, ldc),
1290 OPC(6, OPC_LDLV, ldlv),
1291
1292 OPC(7, OPC_BAR, bar),
1293 OPC(7, OPC_FENCE, fence),
1294
1295 #undef OPC
1296 };
1297
1298 #define GETINFO(instr) (&(opcs[((instr)->opc_cat << NOPC_BITS) | instr_opc(instr, ctx->gpu_id)]))
1299
1300 // XXX hack.. probably should move this table somewhere common:
1301 #include "ir3.h"
1302 const char *ir3_instr_name(struct ir3_instruction *instr)
1303 {
1304 if (opc_cat(instr->opc) == -1) return "??meta??";
1305 return opcs[instr->opc].name;
1306 }
1307
1308 static void print_single_instr(struct disasm_ctx *ctx, instr_t *instr)
1309 {
1310 const char *name = GETINFO(instr)->name;
1311 uint32_t opc = instr_opc(instr, ctx->gpu_id);
1312
1313 if (name) {
1314 fprintf(ctx->out, "%s", name);
1315 GETINFO(instr)->print(ctx, instr);
1316 } else {
1317 fprintf(ctx->out, "unknown(%d,%d)", instr->opc_cat, opc);
1318
1319 switch (instr->opc_cat) {
1320 case 0: print_instr_cat0(ctx, instr); break;
1321 case 1: print_instr_cat1(ctx, instr); break;
1322 case 2: print_instr_cat2(ctx, instr); break;
1323 case 3: print_instr_cat3(ctx, instr); break;
1324 case 4: print_instr_cat4(ctx, instr); break;
1325 case 5: print_instr_cat5(ctx, instr); break;
1326 case 6: print_instr_cat6(ctx, instr); break;
1327 case 7: print_instr_cat7(ctx, instr); break;
1328 }
1329 }
1330 }
1331
1332 static bool print_instr(struct disasm_ctx *ctx, uint32_t *dwords, int n)
1333 {
1334 instr_t *instr = (instr_t *)dwords;
1335 uint32_t opc = instr_opc(instr, ctx->gpu_id);
1336 unsigned nop = 0;
1337 unsigned cycles = ctx->instructions;
1338
1339 if (debug & PRINT_VERBOSE) {
1340 fprintf(ctx->out, "%s%04d:%04d[%08xx_%08xx] ", levels[ctx->level],
1341 n, cycles++, dwords[1], dwords[0]);
1342 }
1343
1344 /* NOTE: order flags are printed is a bit fugly.. but for now I
1345 * try to match the order in llvm-a3xx disassembler for easy
1346 * diff'ing..
1347 */
1348
1349 ctx->repeat = instr_repeat(instr);
1350 ctx->instructions += 1 + ctx->repeat;
1351
1352 if (instr->sync) {
1353 fprintf(ctx->out, "(sy)");
1354 }
1355 if (instr->ss && ((instr->opc_cat <= 4) || (instr->opc_cat == 7))) {
1356 fprintf(ctx->out, "(ss)");
1357 }
1358 if (instr->jmp_tgt)
1359 fprintf(ctx->out, "(jp)");
1360 if ((instr->opc_cat == 0) && instr->cat0.eq)
1361 fprintf(ctx->out, "(eq)");
1362 if (instr_sat(instr))
1363 fprintf(ctx->out, "(sat)");
1364 if (ctx->repeat)
1365 fprintf(ctx->out, "(rpt%d)", ctx->repeat);
1366 else if ((instr->opc_cat == 2) && (instr->cat2.src1_r || instr->cat2.src2_r))
1367 nop = (instr->cat2.src2_r * 2) + instr->cat2.src1_r;
1368 else if ((instr->opc_cat == 3) && (instr->cat3.src1_r || instr->cat3.src2_r))
1369 nop = (instr->cat3.src2_r * 2) + instr->cat3.src1_r;
1370 ctx->instructions += nop;
1371 if (nop)
1372 fprintf(ctx->out, "(nop%d) ", nop);
1373
1374 if (instr->ul && ((2 <= instr->opc_cat) && (instr->opc_cat <= 4)))
1375 fprintf(ctx->out, "(ul)");
1376
1377 print_single_instr(ctx, instr);
1378 fprintf(ctx->out, "\n");
1379
1380 if ((instr->opc_cat <= 4) && (debug & EXPAND_REPEAT)) {
1381 int i;
1382 for (i = 0; i < nop; i++) {
1383 if (debug & PRINT_VERBOSE) {
1384 fprintf(ctx->out, "%s%04d:%04d[ ] ",
1385 levels[ctx->level], n, cycles++);
1386 }
1387 fprintf(ctx->out, "nop\n");
1388 }
1389 for (i = 0; i < ctx->repeat; i++) {
1390 ctx->repeatidx = i + 1;
1391 if (debug & PRINT_VERBOSE) {
1392 fprintf(ctx->out, "%s%04d:%04d[ ] ",
1393 levels[ctx->level], n, cycles++);
1394 }
1395 print_single_instr(ctx, instr);
1396 fprintf(ctx->out, "\n");
1397 }
1398 ctx->repeatidx = 0;
1399 }
1400
1401 return (instr->opc_cat == 0) && (opc == OPC_END);
1402 }
1403
1404 int disasm_a3xx(uint32_t *dwords, int sizedwords, int level, FILE *out, unsigned gpu_id)
1405 {
1406 struct disasm_ctx ctx;
1407 int i;
1408 int nop_count = 0;
1409
1410 assert((sizedwords % 2) == 0);
1411
1412 memset(&ctx, 0, sizeof(ctx));
1413 ctx.out = out;
1414 ctx.level = level;
1415 ctx.gpu_id = gpu_id;
1416
1417 for (i = 0; i < sizedwords; i += 2) {
1418 print_instr(&ctx, &dwords[i], i/2);
1419 if (dwords[i] == 0 && dwords[i + 1] == 0)
1420 nop_count++;
1421 else
1422 nop_count = 0;
1423 if (nop_count > 3)
1424 break;
1425 }
1426
1427 return 0;
1428 }