2 * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 #include <util/u_debug.h>
33 #include "instr-a3xx.h"
35 /* bitmask of debug flags */
37 PRINT_RAW
= 0x1, /* dump raw hexdump */
42 static enum debug_t debug
;
44 #define printf debug_printf
46 static const char *levels
[] = {
65 static const char *component
= "xyzw";
67 static const char *type
[] = {
83 /* current instruction repeat flag: */
85 /* current instruction repeat indx/offset (for --expand): */
88 unsigned instructions
;
91 static const char *float_imms
[] = {
106 static void print_reg(struct disasm_ctx
*ctx
, reg_t reg
, bool full
,
107 bool is_float
, bool r
,
108 bool c
, bool im
, bool neg
, bool abs
, bool addr_rel
)
110 const char type
= c
? 'c' : 'r';
112 // XXX I prefer - and || for neg/abs, but preserving format used
113 // by libllvm-a3xx for easy diffing..
116 fprintf(ctx
->out
, "(absneg)");
118 fprintf(ctx
->out
, "(neg)");
120 fprintf(ctx
->out
, "(abs)");
123 fprintf(ctx
->out
, "(r)");
126 if (is_float
&& full
&& reg
.iim_val
< ARRAY_SIZE(float_imms
)) {
127 fprintf(ctx
->out
, "(%s)", float_imms
[reg
.iim_val
]);
129 fprintf(ctx
->out
, "%d", reg
.iim_val
);
131 } else if (addr_rel
) {
132 /* I would just use %+d but trying to make it diff'able with
136 fprintf(ctx
->out
, "%s%c<a0.x - %d>", full
? "" : "h", type
, -reg
.iim_val
);
137 else if (reg
.iim_val
> 0)
138 fprintf(ctx
->out
, "%s%c<a0.x + %d>", full
? "" : "h", type
, reg
.iim_val
);
140 fprintf(ctx
->out
, "%s%c<a0.x>", full
? "" : "h", type
);
141 } else if ((reg
.num
== REG_A0
) && !c
) {
142 /* This matches libllvm output, the second (scalar) address register
143 * seems to be called a1.x instead of a0.y.
145 fprintf(ctx
->out
, "a%d.x", reg
.comp
);
146 } else if ((reg
.num
== REG_P0
) && !c
) {
147 fprintf(ctx
->out
, "p0.%c", component
[reg
.comp
]);
149 fprintf(ctx
->out
, "%s%c%d.%c", full
? "" : "h", type
, reg
.num
, component
[reg
.comp
]);
153 static unsigned regidx(reg_t reg
)
155 return (4 * reg
.num
) + reg
.comp
;
158 static reg_t
idxreg(unsigned idx
)
166 static void print_reg_dst(struct disasm_ctx
*ctx
, reg_t reg
, bool full
, bool addr_rel
)
168 reg
= idxreg(regidx(reg
) + ctx
->repeatidx
);
169 print_reg(ctx
, reg
, full
, false, false, false, false, false, false, addr_rel
);
172 /* TODO switch to using reginfo struct everywhere, since more readable
173 * than passing a bunch of bools to print_reg_src
181 bool f
; /* src reg is interpreted as float, used for printing immediates */
188 static void print_src(struct disasm_ctx
*ctx
, struct reginfo
*info
)
190 reg_t reg
= info
->reg
;
193 reg
= idxreg(regidx(info
->reg
) + ctx
->repeatidx
);
195 print_reg(ctx
, reg
, info
->full
, info
->f
, info
->r
, info
->c
, info
->im
,
196 info
->neg
, info
->abs
, info
->addr_rel
);
199 //static void print_dst(struct disasm_ctx *ctx, struct reginfo *info)
201 // print_reg_dst(ctx, info->reg, info->full, info->addr_rel);
204 static void print_instr_cat0(struct disasm_ctx
*ctx
, instr_t
*instr
)
206 static const struct {
211 [BRANCH_PLAIN
] = { "r", 1, false },
212 [BRANCH_OR
] = { "rao", 2, false },
213 [BRANCH_AND
] = { "raa", 2, false },
214 [BRANCH_CONST
] = { "rac", 0, true },
215 [BRANCH_ANY
] = { "any", 1, false },
216 [BRANCH_ALL
] = { "all", 1, false },
217 [BRANCH_X
] = { "rax", 0, false },
219 instr_cat0_t
*cat0
= &instr
->cat0
;
221 switch (instr_opc(instr
, ctx
->gpu_id
)) {
225 fprintf(ctx
->out
, " %sp0.%c", cat0
->inv0
? "!" : "",
226 component
[cat0
->comp0
]);
229 fprintf(ctx
->out
, "%s", brinfo
[cat0
->brtype
].suffix
);
230 if (brinfo
[cat0
->brtype
].idx
) {
231 fprintf(ctx
->out
, ".%u", cat0
->idx
);
233 if (brinfo
[cat0
->brtype
].nsrc
>= 1) {
234 fprintf(ctx
->out
, " %sp0.%c,", cat0
->inv0
? "!" : "",
235 component
[cat0
->comp0
]);
237 if (brinfo
[cat0
->brtype
].nsrc
>= 2) {
238 fprintf(ctx
->out
, " %sp0.%c,", cat0
->inv1
? "!" : "",
239 component
[cat0
->comp1
]);
241 fprintf(ctx
->out
, " #%d", cat0
->a3xx
.immed
);
248 fprintf(ctx
->out
, " #%d", cat0
->a3xx
.immed
);
252 if ((debug
& PRINT_VERBOSE
) && (cat0
->dummy3
|cat0
->dummy4
))
253 fprintf(ctx
->out
, "\t{0: %x,%x}", cat0
->dummy3
, cat0
->dummy4
);
256 static void print_instr_cat1(struct disasm_ctx
*ctx
, instr_t
*instr
)
258 instr_cat1_t
*cat1
= &instr
->cat1
;
261 fprintf(ctx
->out
, "(ul)");
263 if (cat1
->src_type
== cat1
->dst_type
) {
264 if ((cat1
->src_type
== TYPE_S16
) && (((reg_t
)cat1
->dst
).num
== REG_A0
)) {
265 /* special case (nmemonic?): */
266 fprintf(ctx
->out
, "mova");
268 fprintf(ctx
->out
, "mov.%s%s", type
[cat1
->src_type
], type
[cat1
->dst_type
]);
271 fprintf(ctx
->out
, "cov.%s%s", type
[cat1
->src_type
], type
[cat1
->dst_type
]);
274 fprintf(ctx
->out
, " ");
277 fprintf(ctx
->out
, "(even)");
280 fprintf(ctx
->out
, "(pos_infinity)");
282 print_reg_dst(ctx
, (reg_t
)(cat1
->dst
), type_size(cat1
->dst_type
) == 32,
285 fprintf(ctx
->out
, ", ");
287 /* ugg, have to special case this.. vs print_reg().. */
289 if (type_float(cat1
->src_type
))
290 fprintf(ctx
->out
, "(%f)", cat1
->fim_val
);
291 else if (type_uint(cat1
->src_type
))
292 fprintf(ctx
->out
, "0x%08x", cat1
->uim_val
);
294 fprintf(ctx
->out
, "%d", cat1
->iim_val
);
295 } else if (cat1
->src_rel
&& !cat1
->src_c
) {
296 /* I would just use %+d but trying to make it diff'able with
299 char type
= cat1
->src_rel_c
? 'c' : 'r';
300 const char *full
= (type_size(cat1
->src_type
) == 32) ? "" : "h";
302 fprintf(ctx
->out
, "%s%c<a0.x - %d>", full
, type
, -cat1
->off
);
303 else if (cat1
->off
> 0)
304 fprintf(ctx
->out
, "%s%c<a0.x + %d>", full
, type
, cat1
->off
);
306 fprintf(ctx
->out
, "%s%c<a0.x>", full
, type
);
308 struct reginfo src
= {
309 .reg
= (reg_t
)cat1
->src
,
310 .full
= type_size(cat1
->src_type
) == 32,
315 print_src(ctx
, &src
);
318 if ((debug
& PRINT_VERBOSE
) && (cat1
->must_be_0
))
319 fprintf(ctx
->out
, "\t{1: %x}", cat1
->must_be_0
);
322 static void print_instr_cat2(struct disasm_ctx
*ctx
, instr_t
*instr
)
324 instr_cat2_t
*cat2
= &instr
->cat2
;
325 int opc
= _OPC(2, cat2
->opc
);
326 static const char *cond
[] = {
343 fprintf(ctx
->out
, ".%s", cond
[cat2
->cond
]);
347 fprintf(ctx
->out
, " ");
349 fprintf(ctx
->out
, "(ei)");
350 print_reg_dst(ctx
, (reg_t
)(cat2
->dst
), cat2
->full
^ cat2
->dst_half
, false);
351 fprintf(ctx
->out
, ", ");
353 struct reginfo src1
= {
355 .r
= cat2
->repeat
? cat2
->src1_r
: 0,
356 .f
= is_cat2_float(opc
),
358 .abs
= cat2
->src1_abs
,
359 .neg
= cat2
->src1_neg
,
362 if (cat2
->c1
.src1_c
) {
363 src1
.reg
= (reg_t
)(cat2
->c1
.src1
);
365 } else if (cat2
->rel1
.src1_rel
) {
366 src1
.reg
= (reg_t
)(cat2
->rel1
.src1
);
367 src1
.c
= cat2
->rel1
.src1_c
;
368 src1
.addr_rel
= true;
370 src1
.reg
= (reg_t
)(cat2
->src1
);
372 print_src(ctx
, &src1
);
374 struct reginfo src2
= {
375 .r
= cat2
->repeat
? cat2
->src2_r
: 0,
377 .f
= is_cat2_float(opc
),
378 .abs
= cat2
->src2_abs
,
379 .neg
= cat2
->src2_neg
,
397 /* these only have one src reg */
400 fprintf(ctx
->out
, ", ");
401 if (cat2
->c2
.src2_c
) {
402 src2
.reg
= (reg_t
)(cat2
->c2
.src2
);
404 } else if (cat2
->rel2
.src2_rel
) {
405 src2
.reg
= (reg_t
)(cat2
->rel2
.src2
);
406 src2
.c
= cat2
->rel2
.src2_c
;
407 src2
.addr_rel
= true;
409 src2
.reg
= (reg_t
)(cat2
->src2
);
411 print_src(ctx
, &src2
);
416 static void print_instr_cat3(struct disasm_ctx
*ctx
, instr_t
*instr
)
418 instr_cat3_t
*cat3
= &instr
->cat3
;
419 bool full
= instr_cat3_full(cat3
);
421 fprintf(ctx
->out
, " ");
422 print_reg_dst(ctx
, (reg_t
)(cat3
->dst
), full
^ cat3
->dst_half
, false);
423 fprintf(ctx
->out
, ", ");
425 struct reginfo src1
= {
426 .r
= cat3
->repeat
? cat3
->src1_r
: 0,
428 .neg
= cat3
->src1_neg
,
430 if (cat3
->c1
.src1_c
) {
431 src1
.reg
= (reg_t
)(cat3
->c1
.src1
);
433 } else if (cat3
->rel1
.src1_rel
) {
434 src1
.reg
= (reg_t
)(cat3
->rel1
.src1
);
435 src1
.c
= cat3
->rel1
.src1_c
;
436 src1
.addr_rel
= true;
438 src1
.reg
= (reg_t
)(cat3
->src1
);
440 print_src(ctx
, &src1
);
442 fprintf(ctx
->out
, ", ");
443 struct reginfo src2
= {
444 .reg
= (reg_t
)cat3
->src2
,
446 .r
= cat3
->repeat
? cat3
->src2_r
: 0,
448 .neg
= cat3
->src2_neg
,
450 print_src(ctx
, &src2
);
452 fprintf(ctx
->out
, ", ");
453 struct reginfo src3
= {
456 .neg
= cat3
->src3_neg
,
458 if (cat3
->c2
.src3_c
) {
459 src3
.reg
= (reg_t
)(cat3
->c2
.src3
);
461 } else if (cat3
->rel2
.src3_rel
) {
462 src3
.reg
= (reg_t
)(cat3
->rel2
.src3
);
463 src3
.c
= cat3
->rel2
.src3_c
;
464 src3
.addr_rel
= true;
466 src3
.reg
= (reg_t
)(cat3
->src3
);
468 print_src(ctx
, &src3
);
471 static void print_instr_cat4(struct disasm_ctx
*ctx
, instr_t
*instr
)
473 instr_cat4_t
*cat4
= &instr
->cat4
;
475 fprintf(ctx
->out
, " ");
476 print_reg_dst(ctx
, (reg_t
)(cat4
->dst
), cat4
->full
^ cat4
->dst_half
, false);
477 fprintf(ctx
->out
, ", ");
479 struct reginfo src
= {
483 .neg
= cat4
->src_neg
,
484 .abs
= cat4
->src_abs
,
487 src
.reg
= (reg_t
)(cat4
->c
.src
);
489 } else if (cat4
->rel
.src_rel
) {
490 src
.reg
= (reg_t
)(cat4
->rel
.src
);
491 src
.c
= cat4
->rel
.src_c
;
494 src
.reg
= (reg_t
)(cat4
->src
);
496 print_src(ctx
, &src
);
498 if ((debug
& PRINT_VERBOSE
) && (cat4
->dummy1
|cat4
->dummy2
))
499 fprintf(ctx
->out
, "\t{4: %x,%x}", cat4
->dummy1
, cat4
->dummy2
);
502 static void print_instr_cat5(struct disasm_ctx
*ctx
, instr_t
*instr
)
504 static const struct {
505 bool src1
, src2
, samp
, tex
;
507 [opc_op(OPC_ISAM
)] = { true, false, true, true, },
508 [opc_op(OPC_ISAML
)] = { true, true, true, true, },
509 [opc_op(OPC_ISAMM
)] = { true, false, true, true, },
510 [opc_op(OPC_SAM
)] = { true, false, true, true, },
511 [opc_op(OPC_SAMB
)] = { true, true, true, true, },
512 [opc_op(OPC_SAML
)] = { true, true, true, true, },
513 [opc_op(OPC_SAMGQ
)] = { true, false, true, true, },
514 [opc_op(OPC_GETLOD
)] = { true, false, true, true, },
515 [opc_op(OPC_CONV
)] = { true, true, true, true, },
516 [opc_op(OPC_CONVM
)] = { true, true, true, true, },
517 [opc_op(OPC_GETSIZE
)] = { true, false, false, true, },
518 [opc_op(OPC_GETBUF
)] = { false, false, false, true, },
519 [opc_op(OPC_GETPOS
)] = { true, false, false, true, },
520 [opc_op(OPC_GETINFO
)] = { false, false, false, true, },
521 [opc_op(OPC_DSX
)] = { true, false, false, false, },
522 [opc_op(OPC_DSY
)] = { true, false, false, false, },
523 [opc_op(OPC_GATHER4R
)] = { true, false, true, true, },
524 [opc_op(OPC_GATHER4G
)] = { true, false, true, true, },
525 [opc_op(OPC_GATHER4B
)] = { true, false, true, true, },
526 [opc_op(OPC_GATHER4A
)] = { true, false, true, true, },
527 [opc_op(OPC_SAMGP0
)] = { true, false, true, true, },
528 [opc_op(OPC_SAMGP1
)] = { true, false, true, true, },
529 [opc_op(OPC_SAMGP2
)] = { true, false, true, true, },
530 [opc_op(OPC_SAMGP3
)] = { true, false, true, true, },
531 [opc_op(OPC_DSXPP_1
)] = { true, false, false, false, },
532 [opc_op(OPC_DSYPP_1
)] = { true, false, false, false, },
533 [opc_op(OPC_RGETPOS
)] = { true, false, false, false, },
534 [opc_op(OPC_RGETINFO
)] = { false, false, false, false, },
537 static const struct {
542 } desc_features
[8] = {
543 [CAT5_NONUNIFORM
] = { .indirect
= true, },
544 [CAT5_UNIFORM
] = { .indirect
= true, .uniform
= true, },
545 [CAT5_BINDLESS_IMM
] = { .bindless
= true, },
546 [CAT5_BINDLESS_UNIFORM
] = {
551 [CAT5_BINDLESS_NONUNIFORM
] = {
555 [CAT5_BINDLESS_A1_IMM
] = {
559 [CAT5_BINDLESS_A1_UNIFORM
] = {
565 [CAT5_BINDLESS_A1_NONUNIFORM
] = {
572 instr_cat5_t
*cat5
= &instr
->cat5
;
576 cat5
->is_s2en_bindless
&&
577 desc_features
[cat5
->s2en_bindless
.desc_mode
].indirect
;
579 cat5
->is_s2en_bindless
&&
580 desc_features
[cat5
->s2en_bindless
.desc_mode
].bindless
;
582 cat5
->is_s2en_bindless
&&
583 desc_features
[cat5
->s2en_bindless
.desc_mode
].use_a1
;
585 cat5
->is_s2en_bindless
&&
586 desc_features
[cat5
->s2en_bindless
.desc_mode
].uniform
;
588 if (cat5
->is_3d
) fprintf(ctx
->out
, ".3d");
589 if (cat5
->is_a
) fprintf(ctx
->out
, ".a");
590 if (cat5
->is_o
) fprintf(ctx
->out
, ".o");
591 if (cat5
->is_p
) fprintf(ctx
->out
, ".p");
592 if (cat5
->is_s
) fprintf(ctx
->out
, ".s");
593 if (desc_indirect
) fprintf(ctx
->out
, ".s2en");
594 if (uniform
) fprintf(ctx
->out
, ".uniform");
597 unsigned base
= (cat5
->s2en_bindless
.base_hi
<< 1) | cat5
->base_lo
;
598 fprintf(ctx
->out
, ".base%d", base
);
601 fprintf(ctx
->out
, " ");
603 switch (_OPC(5, cat5
->opc
)) {
608 fprintf(ctx
->out
, "(%s)", type
[cat5
->type
]);
612 fprintf(ctx
->out
, "(");
613 for (i
= 0; i
< 4; i
++)
614 if (cat5
->wrmask
& (1 << i
))
615 fprintf(ctx
->out
, "%c", "xyzw"[i
]);
616 fprintf(ctx
->out
, ")");
618 print_reg_dst(ctx
, (reg_t
)(cat5
->dst
), type_size(cat5
->type
) == 32, false);
620 if (info
[cat5
->opc
].src1
) {
621 fprintf(ctx
->out
, ", ");
622 struct reginfo src
= { .reg
= (reg_t
)(cat5
->src1
), .full
= cat5
->full
};
623 print_src(ctx
, &src
);
626 if (cat5
->is_o
|| info
[cat5
->opc
].src2
) {
627 fprintf(ctx
->out
, ", ");
628 struct reginfo src
= { .reg
= (reg_t
)(cat5
->src2
), .full
= cat5
->full
};
629 print_src(ctx
, &src
);
631 if (cat5
->is_s2en_bindless
) {
632 if (!desc_indirect
) {
633 if (info
[cat5
->opc
].samp
) {
635 fprintf(ctx
->out
, ", s#%d", cat5
->s2en_bindless
.src3
);
637 fprintf(ctx
->out
, ", s#%d", cat5
->s2en_bindless
.src3
& 0xf);
640 if (info
[cat5
->opc
].tex
&& !use_a1
) {
641 fprintf(ctx
->out
, ", t#%d", cat5
->s2en_bindless
.src3
>> 4);
645 if (info
[cat5
->opc
].samp
)
646 fprintf(ctx
->out
, ", s#%d", cat5
->norm
.samp
);
647 if (info
[cat5
->opc
].tex
)
648 fprintf(ctx
->out
, ", t#%d", cat5
->norm
.tex
);
652 fprintf(ctx
->out
, ", ");
653 struct reginfo src
= { .reg
= (reg_t
)(cat5
->s2en_bindless
.src3
), .full
= bindless
};
654 print_src(ctx
, &src
);
658 fprintf(ctx
->out
, ", a1.x");
660 if (debug
& PRINT_VERBOSE
) {
661 if (cat5
->is_s2en_bindless
) {
662 if ((debug
& PRINT_VERBOSE
) && cat5
->s2en_bindless
.dummy1
)
663 fprintf(ctx
->out
, "\t{5: %x}", cat5
->s2en_bindless
.dummy1
);
665 if ((debug
& PRINT_VERBOSE
) && cat5
->norm
.dummy1
)
666 fprintf(ctx
->out
, "\t{5: %x}", cat5
->norm
.dummy1
);
671 static void print_instr_cat6_a3xx(struct disasm_ctx
*ctx
, instr_t
*instr
)
673 instr_cat6_t
*cat6
= &instr
->cat6
;
674 char sd
= 0, ss
= 0; /* dst/src address space */
676 struct reginfo dst
, src1
, src2
, ssbo
;
677 int src1off
= 0, dstoff
= 0;
679 memset(&dst
, 0, sizeof(dst
));
680 memset(&src1
, 0, sizeof(src1
));
681 memset(&src2
, 0, sizeof(src2
));
682 memset(&ssbo
, 0, sizeof(ssbo
));
684 switch (_OPC(6, cat6
->opc
)) {
687 dst
.full
= type_size(cat6
->type
) == 32;
688 src1
.full
= type_size(cat6
->type
) == 32;
689 src2
.full
= type_size(cat6
->type
) == 32;
702 dst
.full
= type_size(cat6
->type
) == 32;
703 src1
.full
= type_size(cat6
->type
) == 32;
704 src2
.full
= type_size(cat6
->type
) == 32;
707 dst
.full
= type_size(cat6
->type
) == 32;
713 switch (_OPC(6, cat6
->opc
)) {
717 fprintf(ctx
->out
, ".%dd", cat6
->ldgb
.d
+ 1);
720 fprintf(ctx
->out
, ".%s", cat6
->ldgb
.typed
? "typed" : "untyped");
721 fprintf(ctx
->out
, ".%dd", cat6
->ldgb
.d
+ 1);
722 fprintf(ctx
->out
, ".%s", type
[cat6
->type
]);
723 fprintf(ctx
->out
, ".%d", cat6
->ldgb
.type_size
+ 1);
727 fprintf(ctx
->out
, ".%s", cat6
->stgb
.typed
? "typed" : "untyped");
728 fprintf(ctx
->out
, ".%dd", cat6
->stgb
.d
+ 1);
729 fprintf(ctx
->out
, ".%s", type
[cat6
->type
]);
730 fprintf(ctx
->out
, ".%d", cat6
->stgb
.type_size
+ 1);
734 case OPC_ATOMIC_XCHG
:
737 case OPC_ATOMIC_CMPXCHG
:
743 ss
= cat6
->g
? 'g' : 'l';
744 fprintf(ctx
->out
, ".%s", cat6
->ldgb
.typed
? "typed" : "untyped");
745 fprintf(ctx
->out
, ".%dd", cat6
->ldgb
.d
+ 1);
746 fprintf(ctx
->out
, ".%s", type
[cat6
->type
]);
747 fprintf(ctx
->out
, ".%d", cat6
->ldgb
.type_size
+ 1);
748 fprintf(ctx
->out
, ".%c", ss
);
751 dst
.im
= cat6
->g
&& !cat6
->dst_off
;
752 fprintf(ctx
->out
, ".%s", type
[cat6
->type
]);
755 fprintf(ctx
->out
, " ");
757 switch (_OPC(6, cat6
->opc
)) {
798 if ((_OPC(6, cat6
->opc
) == OPC_STGB
) || (_OPC(6, cat6
->opc
) == OPC_STIB
)) {
801 memset(&src3
, 0, sizeof(src3
));
803 src1
.reg
= (reg_t
)(cat6
->stgb
.src1
);
804 src2
.reg
= (reg_t
)(cat6
->stgb
.src2
);
805 src2
.im
= cat6
->stgb
.src2_im
;
806 src3
.reg
= (reg_t
)(cat6
->stgb
.src3
);
807 src3
.im
= cat6
->stgb
.src3_im
;
810 fprintf(ctx
->out
, "g[%u], ", cat6
->stgb
.dst_ssbo
);
811 print_src(ctx
, &src1
);
812 fprintf(ctx
->out
, ", ");
813 print_src(ctx
, &src2
);
814 fprintf(ctx
->out
, ", ");
815 print_src(ctx
, &src3
);
817 if (debug
& PRINT_VERBOSE
)
818 fprintf(ctx
->out
, " (pad0=%x, pad3=%x)", cat6
->stgb
.pad0
, cat6
->stgb
.pad3
);
823 if (is_atomic(_OPC(6, cat6
->opc
))) {
825 src1
.reg
= (reg_t
)(cat6
->ldgb
.src1
);
826 src1
.im
= cat6
->ldgb
.src1_im
;
827 src2
.reg
= (reg_t
)(cat6
->ldgb
.src2
);
828 src2
.im
= cat6
->ldgb
.src2_im
;
829 dst
.reg
= (reg_t
)(cat6
->ldgb
.dst
);
831 print_src(ctx
, &dst
);
832 fprintf(ctx
->out
, ", ");
835 memset(&src3
, 0, sizeof(src3
));
837 src3
.reg
= (reg_t
)(cat6
->ldgb
.src3
);
840 /* For images, the ".typed" variant is used and src2 is
841 * the ivecN coordinates, ie ivec2 for 2d.
843 * For SSBOs, the ".untyped" variant is used and src2 is
844 * a simple dword offset.. src3 appears to be
845 * uvec2(offset * 4, 0). Not sure the point of that.
848 fprintf(ctx
->out
, "g[%u], ", cat6
->ldgb
.src_ssbo
);
849 print_src(ctx
, &src1
); /* value */
850 fprintf(ctx
->out
, ", ");
851 print_src(ctx
, &src2
); /* offset/coords */
852 fprintf(ctx
->out
, ", ");
853 print_src(ctx
, &src3
); /* 64b byte offset.. */
855 if (debug
& PRINT_VERBOSE
) {
856 fprintf(ctx
->out
, " (pad0=%x, mustbe0=%x)", cat6
->ldgb
.pad0
,
859 } else { /* ss == 'l' */
860 fprintf(ctx
->out
, "l[");
861 print_src(ctx
, &src1
); /* simple byte offset */
862 fprintf(ctx
->out
, "], ");
863 print_src(ctx
, &src2
); /* value */
865 if (debug
& PRINT_VERBOSE
) {
866 fprintf(ctx
->out
, " (src3=%x, pad0=%x, src_ssbo_im=%x, mustbe0=%x)",
867 cat6
->ldgb
.src3
, cat6
->ldgb
.pad0
,
868 cat6
->ldgb
.src_ssbo_im
, cat6
->ldgb
.mustbe0
);
873 } else if (_OPC(6, cat6
->opc
) == OPC_RESINFO
) {
874 dst
.reg
= (reg_t
)(cat6
->ldgb
.dst
);
875 ssbo
.reg
= (reg_t
)(cat6
->ldgb
.src_ssbo
);
876 ssbo
.im
= cat6
->ldgb
.src_ssbo_im
;
878 print_src(ctx
, &dst
);
879 fprintf(ctx
->out
, ", ");
881 fprintf(ctx
->out
, "g[");
882 print_src(ctx
, &ssbo
);
883 fprintf(ctx
->out
, "]");
886 } else if (_OPC(6, cat6
->opc
) == OPC_LDGB
) {
888 src1
.reg
= (reg_t
)(cat6
->ldgb
.src1
);
889 src1
.im
= cat6
->ldgb
.src1_im
;
890 src2
.reg
= (reg_t
)(cat6
->ldgb
.src2
);
891 src2
.im
= cat6
->ldgb
.src2_im
;
892 ssbo
.reg
= (reg_t
)(cat6
->ldgb
.src_ssbo
);
893 ssbo
.im
= cat6
->ldgb
.src_ssbo_im
;
894 dst
.reg
= (reg_t
)(cat6
->ldgb
.dst
);
896 print_src(ctx
, &dst
);
897 fprintf(ctx
->out
, ", ");
899 fprintf(ctx
->out
, "g[");
900 print_src(ctx
, &ssbo
);
901 fprintf(ctx
->out
, "], ");
903 print_src(ctx
, &src1
);
904 fprintf(ctx
->out
, ", ");
905 print_src(ctx
, &src2
);
907 if (debug
& PRINT_VERBOSE
)
908 fprintf(ctx
->out
, " (pad0=%x, ssbo_im=%x, mustbe0=%x)", cat6
->ldgb
.pad0
, cat6
->ldgb
.src_ssbo_im
, cat6
->ldgb
.mustbe0
);
911 } else if (_OPC(6, cat6
->opc
) == OPC_LDG
&& cat6
->a
.src1_im
&& cat6
->a
.src2_im
) {
914 memset(&src3
, 0, sizeof(src3
));
915 src1
.reg
= (reg_t
)(cat6
->a
.src1
);
916 src2
.reg
= (reg_t
)(cat6
->a
.src2
);
917 src2
.im
= cat6
->a
.src2_im
;
918 src3
.reg
= (reg_t
)(cat6
->a
.off
);
920 dst
.reg
= (reg_t
)(cat6
->d
.dst
);
922 print_src(ctx
, &dst
);
923 fprintf(ctx
->out
, ", g[");
924 print_src(ctx
, &src1
);
925 fprintf(ctx
->out
, "+");
926 print_src(ctx
, &src3
);
927 fprintf(ctx
->out
, "], ");
928 print_src(ctx
, &src2
);
933 dst
.reg
= (reg_t
)(cat6
->c
.dst
);
934 dstoff
= cat6
->c
.off
;
936 dst
.reg
= (reg_t
)(cat6
->d
.dst
);
940 src1
.reg
= (reg_t
)(cat6
->a
.src1
);
941 src1
.im
= cat6
->a
.src1_im
;
942 src2
.reg
= (reg_t
)(cat6
->a
.src2
);
943 src2
.im
= cat6
->a
.src2_im
;
944 src1off
= cat6
->a
.off
;
946 src1
.reg
= (reg_t
)(cat6
->b
.src1
);
947 src1
.im
= cat6
->b
.src1_im
;
948 src2
.reg
= (reg_t
)(cat6
->b
.src2
);
949 src2
.im
= cat6
->b
.src2_im
;
954 fprintf(ctx
->out
, "%c[", sd
);
955 /* note: dst might actually be a src (ie. address to store to) */
956 print_src(ctx
, &dst
);
957 if (cat6
->dst_off
&& cat6
->g
) {
958 struct reginfo dstoff_reg
= {0};
959 dstoff_reg
.reg
= (reg_t
) cat6
->c
.off
;
960 dstoff_reg
.full
= true;
961 fprintf(ctx
->out
, "+");
962 print_src(ctx
, &dstoff_reg
);
964 fprintf(ctx
->out
, "%+d", dstoff
);
966 fprintf(ctx
->out
, "]");
967 fprintf(ctx
->out
, ", ");
971 fprintf(ctx
->out
, "%c[", ss
);
973 /* can have a larger than normal immed, so hack: */
975 fprintf(ctx
->out
, "%u", src1
.reg
.dummy13
);
977 print_src(ctx
, &src1
);
980 if (cat6
->src_off
&& cat6
->g
)
981 print_src(ctx
, &src2
);
983 fprintf(ctx
->out
, "%+d", src1off
);
985 fprintf(ctx
->out
, "]");
987 switch (_OPC(6, cat6
->opc
)) {
992 fprintf(ctx
->out
, ", ");
993 print_src(ctx
, &src2
);
998 static void print_instr_cat6_a6xx(struct disasm_ctx
*ctx
, instr_t
*instr
)
1000 instr_cat6_a6xx_t
*cat6
= &instr
->cat6_a6xx
;
1001 struct reginfo src1
, src2
, ssbo
;
1002 uint32_t opc
= _OPC(6, cat6
->opc
);
1003 bool uses_type
= opc
!= OPC_LDC
;
1005 static const struct {
1009 } desc_features
[8] = {
1017 [CAT6_NONUNIFORM
] = {
1019 .name
= "nonuniform"
1021 [CAT6_BINDLESS_IMM
] = {
1025 [CAT6_BINDLESS_UNIFORM
] = {
1030 [CAT6_BINDLESS_NONUNIFORM
] = {
1033 .name
= "nonuniform"
1037 bool indirect_ssbo
= desc_features
[cat6
->desc_mode
].indirect
;
1038 bool bindless
= desc_features
[cat6
->desc_mode
].bindless
;
1039 bool type_full
= cat6
->type
!= TYPE_U16
;
1042 memset(&src1
, 0, sizeof(src1
));
1043 memset(&src2
, 0, sizeof(src2
));
1044 memset(&ssbo
, 0, sizeof(ssbo
));
1047 fprintf(ctx
->out
, ".%s", cat6
->typed
? "typed" : "untyped");
1048 fprintf(ctx
->out
, ".%dd", cat6
->d
+ 1);
1049 fprintf(ctx
->out
, ".%s", type
[cat6
->type
]);
1051 fprintf(ctx
->out
, ".offset%d", cat6
->d
);
1053 fprintf(ctx
->out
, ".%u", cat6
->type_size
+ 1);
1055 fprintf(ctx
->out
, ".%s", desc_features
[cat6
->desc_mode
].name
);
1057 fprintf(ctx
->out
, ".base%d", cat6
->base
);
1058 fprintf(ctx
->out
, " ");
1060 src2
.reg
= (reg_t
)(cat6
->src2
);
1061 src2
.full
= type_full
;
1062 print_src(ctx
, &src2
);
1063 fprintf(ctx
->out
, ", ");
1065 if (opc
!= OPC_RESINFO
) {
1066 src1
.reg
= (reg_t
)(cat6
->src1
);
1067 src1
.full
= true; // XXX
1068 print_src(ctx
, &src1
);
1069 fprintf(ctx
->out
, ", ");
1072 ssbo
.reg
= (reg_t
)(cat6
->ssbo
);
1073 ssbo
.im
= !indirect_ssbo
;
1075 print_src(ctx
, &ssbo
);
1077 if (debug
& PRINT_VERBOSE
) {
1078 fprintf(ctx
->out
, " (pad1=%x, pad2=%x, pad3=%x, pad4=%x, pad5=%x)",
1079 cat6
->pad1
, cat6
->pad2
, cat6
->pad3
, cat6
->pad4
, cat6
->pad5
);
1083 static void print_instr_cat6(struct disasm_ctx
*ctx
, instr_t
*instr
)
1085 if (!is_cat6_legacy(instr
, ctx
->gpu_id
)) {
1086 print_instr_cat6_a6xx(ctx
, instr
);
1087 if (debug
& PRINT_VERBOSE
)
1088 fprintf(ctx
->out
, " NEW");
1090 print_instr_cat6_a3xx(ctx
, instr
);
1091 if (debug
& PRINT_VERBOSE
)
1092 fprintf(ctx
->out
, " LEGACY");
1095 static void print_instr_cat7(struct disasm_ctx
*ctx
, instr_t
*instr
)
1097 instr_cat7_t
*cat7
= &instr
->cat7
;
1100 fprintf(ctx
->out
, ".g");
1102 fprintf(ctx
->out
, ".l");
1104 if (_OPC(7, cat7
->opc
) == OPC_FENCE
) {
1106 fprintf(ctx
->out
, ".r");
1108 fprintf(ctx
->out
, ".w");
1112 /* size of largest OPC field of all the instruction categories: */
1115 static const struct opc_info
{
1119 void (*print
)(struct disasm_ctx
*ctx
, instr_t
*instr
);
1120 } opcs
[1 << (3+NOPC_BITS
)] = {
1121 #define OPC(cat, opc, name) [(opc)] = { (cat), (opc), #name, print_instr_cat##cat }
1123 OPC(0, OPC_NOP
, nop
),
1125 OPC(0, OPC_JUMP
, jump
),
1126 OPC(0, OPC_CALL
, call
),
1127 OPC(0, OPC_RET
, ret
),
1128 OPC(0, OPC_KILL
, kill
),
1129 OPC(0, OPC_END
, end
),
1130 OPC(0, OPC_EMIT
, emit
),
1131 OPC(0, OPC_CUT
, cut
),
1132 OPC(0, OPC_CHMASK
, chmask
),
1133 OPC(0, OPC_CHSH
, chsh
),
1134 OPC(0, OPC_FLOW_REV
, flow_rev
),
1135 OPC(0, OPC_PREDT
, predt
),
1136 OPC(0, OPC_PREDF
, predf
),
1137 OPC(0, OPC_PREDE
, prede
),
1138 OPC(0, OPC_BKT
, bkt
),
1139 OPC(0, OPC_STKS
, stks
),
1140 OPC(0, OPC_STKR
, stkr
),
1141 OPC(0, OPC_XSET
, xset
),
1142 OPC(0, OPC_XCLR
, xclr
),
1143 OPC(0, OPC_GETONE
, getone
),
1144 OPC(0, OPC_DBG
, dbg
),
1145 OPC(0, OPC_SHPS
, shps
),
1146 OPC(0, OPC_SHPE
, shpe
),
1152 OPC(2, OPC_ADD_F
, add
.f
),
1153 OPC(2, OPC_MIN_F
, min
.f
),
1154 OPC(2, OPC_MAX_F
, max
.f
),
1155 OPC(2, OPC_MUL_F
, mul
.f
),
1156 OPC(2, OPC_SIGN_F
, sign
.f
),
1157 OPC(2, OPC_CMPS_F
, cmps
.f
),
1158 OPC(2, OPC_ABSNEG_F
, absneg
.f
),
1159 OPC(2, OPC_CMPV_F
, cmpv
.f
),
1160 OPC(2, OPC_FLOOR_F
, floor
.f
),
1161 OPC(2, OPC_CEIL_F
, ceil
.f
),
1162 OPC(2, OPC_RNDNE_F
, rndne
.f
),
1163 OPC(2, OPC_RNDAZ_F
, rndaz
.f
),
1164 OPC(2, OPC_TRUNC_F
, trunc
.f
),
1165 OPC(2, OPC_ADD_U
, add
.u
),
1166 OPC(2, OPC_ADD_S
, add
.s
),
1167 OPC(2, OPC_SUB_U
, sub
.u
),
1168 OPC(2, OPC_SUB_S
, sub
.s
),
1169 OPC(2, OPC_CMPS_U
, cmps
.u
),
1170 OPC(2, OPC_CMPS_S
, cmps
.s
),
1171 OPC(2, OPC_MIN_U
, min
.u
),
1172 OPC(2, OPC_MIN_S
, min
.s
),
1173 OPC(2, OPC_MAX_U
, max
.u
),
1174 OPC(2, OPC_MAX_S
, max
.s
),
1175 OPC(2, OPC_ABSNEG_S
, absneg
.s
),
1176 OPC(2, OPC_AND_B
, and.b
),
1177 OPC(2, OPC_OR_B
, or.b
),
1178 OPC(2, OPC_NOT_B
, not.b
),
1179 OPC(2, OPC_XOR_B
, xor.b
),
1180 OPC(2, OPC_CMPV_U
, cmpv
.u
),
1181 OPC(2, OPC_CMPV_S
, cmpv
.s
),
1182 OPC(2, OPC_MUL_U24
, mul
.u24
),
1183 OPC(2, OPC_MUL_S24
, mul
.s24
),
1184 OPC(2, OPC_MULL_U
, mull
.u
),
1185 OPC(2, OPC_BFREV_B
, bfrev
.b
),
1186 OPC(2, OPC_CLZ_S
, clz
.s
),
1187 OPC(2, OPC_CLZ_B
, clz
.b
),
1188 OPC(2, OPC_SHL_B
, shl
.b
),
1189 OPC(2, OPC_SHR_B
, shr
.b
),
1190 OPC(2, OPC_ASHR_B
, ashr
.b
),
1191 OPC(2, OPC_BARY_F
, bary
.f
),
1192 OPC(2, OPC_MGEN_B
, mgen
.b
),
1193 OPC(2, OPC_GETBIT_B
, getbit
.b
),
1194 OPC(2, OPC_SETRM
, setrm
),
1195 OPC(2, OPC_CBITS_B
, cbits
.b
),
1196 OPC(2, OPC_SHB
, shb
),
1197 OPC(2, OPC_MSAD
, msad
),
1200 OPC(3, OPC_MAD_U16
, mad
.u16
),
1201 OPC(3, OPC_MADSH_U16
, madsh
.u16
),
1202 OPC(3, OPC_MAD_S16
, mad
.s16
),
1203 OPC(3, OPC_MADSH_M16
, madsh
.m16
),
1204 OPC(3, OPC_MAD_U24
, mad
.u24
),
1205 OPC(3, OPC_MAD_S24
, mad
.s24
),
1206 OPC(3, OPC_MAD_F16
, mad
.f16
),
1207 OPC(3, OPC_MAD_F32
, mad
.f32
),
1208 OPC(3, OPC_SEL_B16
, sel
.b16
),
1209 OPC(3, OPC_SEL_B32
, sel
.b32
),
1210 OPC(3, OPC_SEL_S16
, sel
.s16
),
1211 OPC(3, OPC_SEL_S32
, sel
.s32
),
1212 OPC(3, OPC_SEL_F16
, sel
.f16
),
1213 OPC(3, OPC_SEL_F32
, sel
.f32
),
1214 OPC(3, OPC_SAD_S16
, sad
.s16
),
1215 OPC(3, OPC_SAD_S32
, sad
.s32
),
1218 OPC(4, OPC_RCP
, rcp
),
1219 OPC(4, OPC_RSQ
, rsq
),
1220 OPC(4, OPC_LOG2
, log2
),
1221 OPC(4, OPC_EXP2
, exp2
),
1222 OPC(4, OPC_SIN
, sin
),
1223 OPC(4, OPC_COS
, cos
),
1224 OPC(4, OPC_SQRT
, sqrt
),
1225 OPC(4, OPC_HRSQ
, hrsq
),
1226 OPC(4, OPC_HLOG2
, hlog2
),
1227 OPC(4, OPC_HEXP2
, hexp2
),
1230 OPC(5, OPC_ISAM
, isam
),
1231 OPC(5, OPC_ISAML
, isaml
),
1232 OPC(5, OPC_ISAMM
, isamm
),
1233 OPC(5, OPC_SAM
, sam
),
1234 OPC(5, OPC_SAMB
, samb
),
1235 OPC(5, OPC_SAML
, saml
),
1236 OPC(5, OPC_SAMGQ
, samgq
),
1237 OPC(5, OPC_GETLOD
, getlod
),
1238 OPC(5, OPC_CONV
, conv
),
1239 OPC(5, OPC_CONVM
, convm
),
1240 OPC(5, OPC_GETSIZE
, getsize
),
1241 OPC(5, OPC_GETBUF
, getbuf
),
1242 OPC(5, OPC_GETPOS
, getpos
),
1243 OPC(5, OPC_GETINFO
, getinfo
),
1244 OPC(5, OPC_DSX
, dsx
),
1245 OPC(5, OPC_DSY
, dsy
),
1246 OPC(5, OPC_GATHER4R
, gather4r
),
1247 OPC(5, OPC_GATHER4G
, gather4g
),
1248 OPC(5, OPC_GATHER4B
, gather4b
),
1249 OPC(5, OPC_GATHER4A
, gather4a
),
1250 OPC(5, OPC_SAMGP0
, samgp0
),
1251 OPC(5, OPC_SAMGP1
, samgp1
),
1252 OPC(5, OPC_SAMGP2
, samgp2
),
1253 OPC(5, OPC_SAMGP3
, samgp3
),
1254 OPC(5, OPC_DSXPP_1
, dsxpp
.1),
1255 OPC(5, OPC_DSYPP_1
, dsypp
.1),
1256 OPC(5, OPC_RGETPOS
, rgetpos
),
1257 OPC(5, OPC_RGETINFO
, rgetinfo
),
1261 OPC(6, OPC_LDG
, ldg
),
1262 OPC(6, OPC_LDL
, ldl
),
1263 OPC(6, OPC_LDP
, ldp
),
1264 OPC(6, OPC_STG
, stg
),
1265 OPC(6, OPC_STL
, stl
),
1266 OPC(6, OPC_STP
, stp
),
1267 OPC(6, OPC_LDIB
, ldib
),
1268 OPC(6, OPC_G2L
, g2l
),
1269 OPC(6, OPC_L2G
, l2g
),
1270 OPC(6, OPC_PREFETCH
, prefetch
),
1271 OPC(6, OPC_LDLW
, ldlw
),
1272 OPC(6, OPC_STLW
, stlw
),
1273 OPC(6, OPC_RESFMT
, resfmt
),
1274 OPC(6, OPC_RESINFO
, resinfo
),
1275 OPC(6, OPC_ATOMIC_ADD
, atomic
.add
),
1276 OPC(6, OPC_ATOMIC_SUB
, atomic
.sub
),
1277 OPC(6, OPC_ATOMIC_XCHG
, atomic
.xchg
),
1278 OPC(6, OPC_ATOMIC_INC
, atomic
.inc
),
1279 OPC(6, OPC_ATOMIC_DEC
, atomic
.dec
),
1280 OPC(6, OPC_ATOMIC_CMPXCHG
, atomic
.cmpxchg
),
1281 OPC(6, OPC_ATOMIC_MIN
, atomic
.min
),
1282 OPC(6, OPC_ATOMIC_MAX
, atomic
.max
),
1283 OPC(6, OPC_ATOMIC_AND
, atomic
.and),
1284 OPC(6, OPC_ATOMIC_OR
, atomic
.or),
1285 OPC(6, OPC_ATOMIC_XOR
, atomic
.xor),
1286 OPC(6, OPC_LDGB
, ldgb
),
1287 OPC(6, OPC_STGB
, stgb
),
1288 OPC(6, OPC_STIB
, stib
),
1289 OPC(6, OPC_LDC
, ldc
),
1290 OPC(6, OPC_LDLV
, ldlv
),
1292 OPC(7, OPC_BAR
, bar
),
1293 OPC(7, OPC_FENCE
, fence
),
1298 #define GETINFO(instr) (&(opcs[((instr)->opc_cat << NOPC_BITS) | instr_opc(instr, ctx->gpu_id)]))
1300 // XXX hack.. probably should move this table somewhere common:
1302 const char *ir3_instr_name(struct ir3_instruction
*instr
)
1304 if (opc_cat(instr
->opc
) == -1) return "??meta??";
1305 return opcs
[instr
->opc
].name
;
1308 static void print_single_instr(struct disasm_ctx
*ctx
, instr_t
*instr
)
1310 const char *name
= GETINFO(instr
)->name
;
1311 uint32_t opc
= instr_opc(instr
, ctx
->gpu_id
);
1314 fprintf(ctx
->out
, "%s", name
);
1315 GETINFO(instr
)->print(ctx
, instr
);
1317 fprintf(ctx
->out
, "unknown(%d,%d)", instr
->opc_cat
, opc
);
1319 switch (instr
->opc_cat
) {
1320 case 0: print_instr_cat0(ctx
, instr
); break;
1321 case 1: print_instr_cat1(ctx
, instr
); break;
1322 case 2: print_instr_cat2(ctx
, instr
); break;
1323 case 3: print_instr_cat3(ctx
, instr
); break;
1324 case 4: print_instr_cat4(ctx
, instr
); break;
1325 case 5: print_instr_cat5(ctx
, instr
); break;
1326 case 6: print_instr_cat6(ctx
, instr
); break;
1327 case 7: print_instr_cat7(ctx
, instr
); break;
1332 static bool print_instr(struct disasm_ctx
*ctx
, uint32_t *dwords
, int n
)
1334 instr_t
*instr
= (instr_t
*)dwords
;
1335 uint32_t opc
= instr_opc(instr
, ctx
->gpu_id
);
1337 unsigned cycles
= ctx
->instructions
;
1339 if (debug
& PRINT_VERBOSE
) {
1340 fprintf(ctx
->out
, "%s%04d:%04d[%08xx_%08xx] ", levels
[ctx
->level
],
1341 n
, cycles
++, dwords
[1], dwords
[0]);
1344 /* NOTE: order flags are printed is a bit fugly.. but for now I
1345 * try to match the order in llvm-a3xx disassembler for easy
1349 ctx
->repeat
= instr_repeat(instr
);
1350 ctx
->instructions
+= 1 + ctx
->repeat
;
1353 fprintf(ctx
->out
, "(sy)");
1355 if (instr
->ss
&& ((instr
->opc_cat
<= 4) || (instr
->opc_cat
== 7))) {
1356 fprintf(ctx
->out
, "(ss)");
1359 fprintf(ctx
->out
, "(jp)");
1360 if ((instr
->opc_cat
== 0) && instr
->cat0
.eq
)
1361 fprintf(ctx
->out
, "(eq)");
1362 if (instr_sat(instr
))
1363 fprintf(ctx
->out
, "(sat)");
1365 fprintf(ctx
->out
, "(rpt%d)", ctx
->repeat
);
1366 else if ((instr
->opc_cat
== 2) && (instr
->cat2
.src1_r
|| instr
->cat2
.src2_r
))
1367 nop
= (instr
->cat2
.src2_r
* 2) + instr
->cat2
.src1_r
;
1368 else if ((instr
->opc_cat
== 3) && (instr
->cat3
.src1_r
|| instr
->cat3
.src2_r
))
1369 nop
= (instr
->cat3
.src2_r
* 2) + instr
->cat3
.src1_r
;
1370 ctx
->instructions
+= nop
;
1372 fprintf(ctx
->out
, "(nop%d) ", nop
);
1374 if (instr
->ul
&& ((2 <= instr
->opc_cat
) && (instr
->opc_cat
<= 4)))
1375 fprintf(ctx
->out
, "(ul)");
1377 print_single_instr(ctx
, instr
);
1378 fprintf(ctx
->out
, "\n");
1380 if ((instr
->opc_cat
<= 4) && (debug
& EXPAND_REPEAT
)) {
1382 for (i
= 0; i
< nop
; i
++) {
1383 if (debug
& PRINT_VERBOSE
) {
1384 fprintf(ctx
->out
, "%s%04d:%04d[ ] ",
1385 levels
[ctx
->level
], n
, cycles
++);
1387 fprintf(ctx
->out
, "nop\n");
1389 for (i
= 0; i
< ctx
->repeat
; i
++) {
1390 ctx
->repeatidx
= i
+ 1;
1391 if (debug
& PRINT_VERBOSE
) {
1392 fprintf(ctx
->out
, "%s%04d:%04d[ ] ",
1393 levels
[ctx
->level
], n
, cycles
++);
1395 print_single_instr(ctx
, instr
);
1396 fprintf(ctx
->out
, "\n");
1401 return (instr
->opc_cat
== 0) && (opc
== OPC_END
);
1404 int disasm_a3xx(uint32_t *dwords
, int sizedwords
, int level
, FILE *out
, unsigned gpu_id
)
1406 struct disasm_ctx ctx
;
1410 assert((sizedwords
% 2) == 0);
1412 memset(&ctx
, 0, sizeof(ctx
));
1415 ctx
.gpu_id
= gpu_id
;
1417 for (i
= 0; i
< sizedwords
; i
+= 2) {
1418 print_instr(&ctx
, &dwords
[i
], i
/2);
1419 if (dwords
[i
] == 0 && dwords
[i
+ 1] == 0)