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freedreno/ir3: Fix disasm of register offsets in ldp/stp.
[mesa.git] / src / freedreno / ir3 / disasm-a3xx.c
1 /*
2 * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <stdio.h>
25 #include <stdlib.h>
26 #include <stdint.h>
27 #include <stdbool.h>
28 #include <string.h>
29 #include <assert.h>
30
31 #include <util/u_debug.h>
32
33 #include "instr-a3xx.h"
34
35 /* bitmask of debug flags */
36 enum debug_t {
37 PRINT_RAW = 0x1, /* dump raw hexdump */
38 PRINT_VERBOSE = 0x2,
39 EXPAND_REPEAT = 0x4,
40 };
41
42 static enum debug_t debug;
43
44 #define printf debug_printf
45
46 static const char *levels[] = {
47 "",
48 "\t",
49 "\t\t",
50 "\t\t\t",
51 "\t\t\t\t",
52 "\t\t\t\t\t",
53 "\t\t\t\t\t\t",
54 "\t\t\t\t\t\t\t",
55 "\t\t\t\t\t\t\t\t",
56 "\t\t\t\t\t\t\t\t\t",
57 "x",
58 "x",
59 "x",
60 "x",
61 "x",
62 "x",
63 };
64
65 static const char *component = "xyzw";
66
67 static const char *type[] = {
68 [TYPE_F16] = "f16",
69 [TYPE_F32] = "f32",
70 [TYPE_U16] = "u16",
71 [TYPE_U32] = "u32",
72 [TYPE_S16] = "s16",
73 [TYPE_S32] = "s32",
74 [TYPE_U8] = "u8",
75 [TYPE_S8] = "s8",
76 };
77
78 struct disasm_ctx {
79 FILE *out;
80 int level;
81 unsigned gpu_id;
82
83 /* current instruction repeat flag: */
84 unsigned repeat;
85 /* current instruction repeat indx/offset (for --expand): */
86 unsigned repeatidx;
87
88 unsigned instructions;
89 };
90
91 static const char *float_imms[] = {
92 "0.0",
93 "0.5",
94 "1.0",
95 "2.0",
96 "e",
97 "pi",
98 "1/pi",
99 "1/log2(e)",
100 "log2(e)",
101 "1/log2(10)",
102 "log2(10)",
103 "4.0",
104 };
105
106 static void print_reg(struct disasm_ctx *ctx, reg_t reg, bool full,
107 bool is_float, bool r,
108 bool c, bool im, bool neg, bool abs, bool addr_rel)
109 {
110 const char type = c ? 'c' : 'r';
111
112 // XXX I prefer - and || for neg/abs, but preserving format used
113 // by libllvm-a3xx for easy diffing..
114
115 if (abs && neg)
116 fprintf(ctx->out, "(absneg)");
117 else if (neg)
118 fprintf(ctx->out, "(neg)");
119 else if (abs)
120 fprintf(ctx->out, "(abs)");
121
122 if (r)
123 fprintf(ctx->out, "(r)");
124
125 if (im) {
126 if (is_float && full && reg.iim_val < ARRAY_SIZE(float_imms)) {
127 fprintf(ctx->out, "(%s)", float_imms[reg.iim_val]);
128 } else {
129 fprintf(ctx->out, "%d", reg.iim_val);
130 }
131 } else if (addr_rel) {
132 /* I would just use %+d but trying to make it diff'able with
133 * libllvm-a3xx...
134 */
135 if (reg.iim_val < 0)
136 fprintf(ctx->out, "%s%c<a0.x - %d>", full ? "" : "h", type, -reg.iim_val);
137 else if (reg.iim_val > 0)
138 fprintf(ctx->out, "%s%c<a0.x + %d>", full ? "" : "h", type, reg.iim_val);
139 else
140 fprintf(ctx->out, "%s%c<a0.x>", full ? "" : "h", type);
141 } else if ((reg.num == REG_A0) && !c) {
142 /* This matches libllvm output, the second (scalar) address register
143 * seems to be called a1.x instead of a0.y.
144 */
145 fprintf(ctx->out, "a%d.x", reg.comp);
146 } else if ((reg.num == REG_P0) && !c) {
147 fprintf(ctx->out, "p0.%c", component[reg.comp]);
148 } else {
149 fprintf(ctx->out, "%s%c%d.%c", full ? "" : "h", type, reg.num, component[reg.comp]);
150 if (0 && full && !c) {
151 reg_t hr0 = reg;
152 hr0.iim_val *= 2;
153 reg_t hr1 = hr0;
154 hr1.iim_val += 1;
155 fprintf(ctx->out, " (hr%d.%c,hr%d.%c)", hr0.num, component[hr0.comp], hr1.num, component[hr1.comp]);
156 }
157 }
158 }
159
160 static unsigned regidx(reg_t reg)
161 {
162 return (4 * reg.num) + reg.comp;
163 }
164
165 static reg_t idxreg(unsigned idx)
166 {
167 return (reg_t){
168 .comp = idx & 0x3,
169 .num = idx >> 2,
170 };
171 }
172
173 static void print_reg_dst(struct disasm_ctx *ctx, reg_t reg, bool full, bool addr_rel)
174 {
175 reg = idxreg(regidx(reg) + ctx->repeatidx);
176 print_reg(ctx, reg, full, false, false, false, false, false, false, addr_rel);
177 }
178
179 /* TODO switch to using reginfo struct everywhere, since more readable
180 * than passing a bunch of bools to print_reg_src
181 */
182
183 struct reginfo {
184 reg_t reg;
185 bool full;
186 bool r;
187 bool c;
188 bool f; /* src reg is interpreted as float, used for printing immediates */
189 bool im;
190 bool neg;
191 bool abs;
192 bool addr_rel;
193 };
194
195 static void print_src(struct disasm_ctx *ctx, struct reginfo *info)
196 {
197 reg_t reg = info->reg;
198
199 if (info->r)
200 reg = idxreg(regidx(info->reg) + ctx->repeatidx);
201
202 print_reg(ctx, reg, info->full, info->f, info->r, info->c, info->im,
203 info->neg, info->abs, info->addr_rel);
204 }
205
206 //static void print_dst(struct disasm_ctx *ctx, struct reginfo *info)
207 //{
208 // print_reg_dst(ctx, info->reg, info->full, info->addr_rel);
209 //}
210
211 static void print_instr_cat0(struct disasm_ctx *ctx, instr_t *instr)
212 {
213 static const struct {
214 const char *suffix;
215 int nsrc;
216 bool idx;
217 } brinfo[7] = {
218 [BRANCH_PLAIN] = { "r", 1, false },
219 [BRANCH_OR] = { "rao", 2, false },
220 [BRANCH_AND] = { "raa", 2, false },
221 [BRANCH_CONST] = { "rac", 0, true },
222 [BRANCH_ANY] = { "any", 1, false },
223 [BRANCH_ALL] = { "all", 1, false },
224 [BRANCH_X] = { "rax", 0, false },
225 };
226 instr_cat0_t *cat0 = &instr->cat0;
227
228 switch (instr_opc(instr, ctx->gpu_id)) {
229 case OPC_KILL:
230 case OPC_PREDT:
231 case OPC_PREDF:
232 fprintf(ctx->out, " %sp0.%c", cat0->inv0 ? "!" : "",
233 component[cat0->comp0]);
234 break;
235 case OPC_B:
236 fprintf(ctx->out, "%s", brinfo[cat0->brtype].suffix);
237 if (brinfo[cat0->brtype].idx) {
238 fprintf(ctx->out, ".%u", cat0->idx);
239 }
240 if (brinfo[cat0->brtype].nsrc >= 1) {
241 fprintf(ctx->out, " %sp0.%c,", cat0->inv0 ? "!" : "",
242 component[cat0->comp0]);
243 }
244 if (brinfo[cat0->brtype].nsrc >= 2) {
245 fprintf(ctx->out, " %sp0.%c,", cat0->inv1 ? "!" : "",
246 component[cat0->comp1]);
247 }
248 fprintf(ctx->out, " #%d", cat0->a3xx.immed);
249 break;
250 case OPC_JUMP:
251 case OPC_CALL:
252 case OPC_BKT:
253 case OPC_GETONE:
254 case OPC_SHPS:
255 fprintf(ctx->out, " #%d", cat0->a3xx.immed);
256 break;
257 }
258
259 if ((debug & PRINT_VERBOSE) && (cat0->dummy3|cat0->dummy4))
260 fprintf(ctx->out, "\t{0: %x,%x}", cat0->dummy3, cat0->dummy4);
261 }
262
263 static void print_instr_cat1(struct disasm_ctx *ctx, instr_t *instr)
264 {
265 instr_cat1_t *cat1 = &instr->cat1;
266
267 if (cat1->ul)
268 fprintf(ctx->out, "(ul)");
269
270 if (cat1->src_type == cat1->dst_type) {
271 if ((cat1->src_type == TYPE_S16) && (((reg_t)cat1->dst).num == REG_A0)) {
272 /* special case (nmemonic?): */
273 fprintf(ctx->out, "mova");
274 } else {
275 fprintf(ctx->out, "mov.%s%s", type[cat1->src_type], type[cat1->dst_type]);
276 }
277 } else {
278 fprintf(ctx->out, "cov.%s%s", type[cat1->src_type], type[cat1->dst_type]);
279 }
280
281 fprintf(ctx->out, " ");
282
283 if (cat1->even)
284 fprintf(ctx->out, "(even)");
285
286 if (cat1->pos_inf)
287 fprintf(ctx->out, "(pos_infinity)");
288
289 print_reg_dst(ctx, (reg_t)(cat1->dst), type_size(cat1->dst_type) == 32,
290 cat1->dst_rel);
291
292 fprintf(ctx->out, ", ");
293
294 /* ugg, have to special case this.. vs print_reg().. */
295 if (cat1->src_im) {
296 if (type_float(cat1->src_type))
297 fprintf(ctx->out, "(%f)", cat1->fim_val);
298 else if (type_uint(cat1->src_type))
299 fprintf(ctx->out, "0x%08x", cat1->uim_val);
300 else
301 fprintf(ctx->out, "%d", cat1->iim_val);
302 } else if (cat1->src_rel && !cat1->src_c) {
303 /* I would just use %+d but trying to make it diff'able with
304 * libllvm-a3xx...
305 */
306 char type = cat1->src_rel_c ? 'c' : 'r';
307 const char *full = (type_size(cat1->src_type) == 32) ? "" : "h";
308 if (cat1->off < 0)
309 fprintf(ctx->out, "%s%c<a0.x - %d>", full, type, -cat1->off);
310 else if (cat1->off > 0)
311 fprintf(ctx->out, "%s%c<a0.x + %d>", full, type, cat1->off);
312 else
313 fprintf(ctx->out, "%s%c<a0.x>", full, type);
314 } else {
315 struct reginfo src = {
316 .reg = (reg_t)cat1->src,
317 .full = type_size(cat1->src_type) == 32,
318 .r = cat1->src_r,
319 .c = cat1->src_c,
320 .im = cat1->src_im,
321 };
322 print_src(ctx, &src);
323 }
324
325 if ((debug & PRINT_VERBOSE) && (cat1->must_be_0))
326 fprintf(ctx->out, "\t{1: %x}", cat1->must_be_0);
327 }
328
329 static void print_instr_cat2(struct disasm_ctx *ctx, instr_t *instr)
330 {
331 instr_cat2_t *cat2 = &instr->cat2;
332 int opc = _OPC(2, cat2->opc);
333 static const char *cond[] = {
334 "lt",
335 "le",
336 "gt",
337 "ge",
338 "eq",
339 "ne",
340 "?6?",
341 };
342
343 switch (opc) {
344 case OPC_CMPS_F:
345 case OPC_CMPS_U:
346 case OPC_CMPS_S:
347 case OPC_CMPV_F:
348 case OPC_CMPV_U:
349 case OPC_CMPV_S:
350 fprintf(ctx->out, ".%s", cond[cat2->cond]);
351 break;
352 }
353
354 fprintf(ctx->out, " ");
355 if (cat2->ei)
356 fprintf(ctx->out, "(ei)");
357 print_reg_dst(ctx, (reg_t)(cat2->dst), cat2->full ^ cat2->dst_half, false);
358 fprintf(ctx->out, ", ");
359
360 struct reginfo src1 = {
361 .full = cat2->full,
362 .r = cat2->repeat ? cat2->src1_r : 0,
363 .f = is_cat2_float(opc),
364 .im = cat2->src1_im,
365 .abs = cat2->src1_abs,
366 .neg = cat2->src1_neg,
367 };
368
369 if (cat2->c1.src1_c) {
370 src1.reg = (reg_t)(cat2->c1.src1);
371 src1.c = true;
372 } else if (cat2->rel1.src1_rel) {
373 src1.reg = (reg_t)(cat2->rel1.src1);
374 src1.c = cat2->rel1.src1_c;
375 src1.addr_rel = true;
376 } else {
377 src1.reg = (reg_t)(cat2->src1);
378 }
379 print_src(ctx, &src1);
380
381 struct reginfo src2 = {
382 .r = cat2->repeat ? cat2->src2_r : 0,
383 .full = cat2->full,
384 .f = is_cat2_float(opc),
385 .abs = cat2->src2_abs,
386 .neg = cat2->src2_neg,
387 .im = cat2->src2_im,
388 };
389 switch (opc) {
390 case OPC_ABSNEG_F:
391 case OPC_ABSNEG_S:
392 case OPC_CLZ_B:
393 case OPC_CLZ_S:
394 case OPC_SIGN_F:
395 case OPC_FLOOR_F:
396 case OPC_CEIL_F:
397 case OPC_RNDNE_F:
398 case OPC_RNDAZ_F:
399 case OPC_TRUNC_F:
400 case OPC_NOT_B:
401 case OPC_BFREV_B:
402 case OPC_SETRM:
403 case OPC_CBITS_B:
404 /* these only have one src reg */
405 break;
406 default:
407 fprintf(ctx->out, ", ");
408 if (cat2->c2.src2_c) {
409 src2.reg = (reg_t)(cat2->c2.src2);
410 src2.c = true;
411 } else if (cat2->rel2.src2_rel) {
412 src2.reg = (reg_t)(cat2->rel2.src2);
413 src2.c = cat2->rel2.src2_c;
414 src2.addr_rel = true;
415 } else {
416 src2.reg = (reg_t)(cat2->src2);
417 }
418 print_src(ctx, &src2);
419 break;
420 }
421 }
422
423 static void print_instr_cat3(struct disasm_ctx *ctx, instr_t *instr)
424 {
425 instr_cat3_t *cat3 = &instr->cat3;
426 bool full = instr_cat3_full(cat3);
427
428 fprintf(ctx->out, " ");
429 print_reg_dst(ctx, (reg_t)(cat3->dst), full ^ cat3->dst_half, false);
430 fprintf(ctx->out, ", ");
431
432 struct reginfo src1 = {
433 .r = cat3->repeat ? cat3->src1_r : 0,
434 .full = full,
435 .neg = cat3->src1_neg,
436 };
437 if (cat3->c1.src1_c) {
438 src1.reg = (reg_t)(cat3->c1.src1);
439 src1.c = true;
440 } else if (cat3->rel1.src1_rel) {
441 src1.reg = (reg_t)(cat3->rel1.src1);
442 src1.c = cat3->rel1.src1_c;
443 src1.addr_rel = true;
444 } else {
445 src1.reg = (reg_t)(cat3->src1);
446 }
447 print_src(ctx, &src1);
448
449 fprintf(ctx->out, ", ");
450 struct reginfo src2 = {
451 .reg = (reg_t)cat3->src2,
452 .full = full,
453 .r = cat3->repeat ? cat3->src2_r : 0,
454 .c = cat3->src2_c,
455 .neg = cat3->src2_neg,
456 };
457 print_src(ctx, &src2);
458
459 fprintf(ctx->out, ", ");
460 struct reginfo src3 = {
461 .r = cat3->src3_r,
462 .full = full,
463 .neg = cat3->src3_neg,
464 };
465 if (cat3->c2.src3_c) {
466 src3.reg = (reg_t)(cat3->c2.src3);
467 src3.c = true;
468 } else if (cat3->rel2.src3_rel) {
469 src3.reg = (reg_t)(cat3->rel2.src3);
470 src3.c = cat3->rel2.src3_c;
471 src3.addr_rel = true;
472 } else {
473 src3.reg = (reg_t)(cat3->src3);
474 }
475 print_src(ctx, &src3);
476 }
477
478 static void print_instr_cat4(struct disasm_ctx *ctx, instr_t *instr)
479 {
480 instr_cat4_t *cat4 = &instr->cat4;
481
482 fprintf(ctx->out, " ");
483 print_reg_dst(ctx, (reg_t)(cat4->dst), cat4->full ^ cat4->dst_half, false);
484 fprintf(ctx->out, ", ");
485
486 struct reginfo src = {
487 .r = cat4->src_r,
488 .im = cat4->src_im,
489 .full = cat4->full,
490 .neg = cat4->src_neg,
491 .abs = cat4->src_abs,
492 };
493 if (cat4->c.src_c) {
494 src.reg = (reg_t)(cat4->c.src);
495 src.c = true;
496 } else if (cat4->rel.src_rel) {
497 src.reg = (reg_t)(cat4->rel.src);
498 src.c = cat4->rel.src_c;
499 src.addr_rel = true;
500 } else {
501 src.reg = (reg_t)(cat4->src);
502 }
503 print_src(ctx, &src);
504
505 if ((debug & PRINT_VERBOSE) && (cat4->dummy1|cat4->dummy2))
506 fprintf(ctx->out, "\t{4: %x,%x}", cat4->dummy1, cat4->dummy2);
507 }
508
509 static void print_instr_cat5(struct disasm_ctx *ctx, instr_t *instr)
510 {
511 static const struct {
512 bool src1, src2, samp, tex;
513 } info[0x1f] = {
514 [opc_op(OPC_ISAM)] = { true, false, true, true, },
515 [opc_op(OPC_ISAML)] = { true, true, true, true, },
516 [opc_op(OPC_ISAMM)] = { true, false, true, true, },
517 [opc_op(OPC_SAM)] = { true, false, true, true, },
518 [opc_op(OPC_SAMB)] = { true, true, true, true, },
519 [opc_op(OPC_SAML)] = { true, true, true, true, },
520 [opc_op(OPC_SAMGQ)] = { true, false, true, true, },
521 [opc_op(OPC_GETLOD)] = { true, false, true, true, },
522 [opc_op(OPC_CONV)] = { true, true, true, true, },
523 [opc_op(OPC_CONVM)] = { true, true, true, true, },
524 [opc_op(OPC_GETSIZE)] = { true, false, false, true, },
525 [opc_op(OPC_GETBUF)] = { false, false, false, true, },
526 [opc_op(OPC_GETPOS)] = { true, false, false, true, },
527 [opc_op(OPC_GETINFO)] = { false, false, false, true, },
528 [opc_op(OPC_DSX)] = { true, false, false, false, },
529 [opc_op(OPC_DSY)] = { true, false, false, false, },
530 [opc_op(OPC_GATHER4R)] = { true, false, true, true, },
531 [opc_op(OPC_GATHER4G)] = { true, false, true, true, },
532 [opc_op(OPC_GATHER4B)] = { true, false, true, true, },
533 [opc_op(OPC_GATHER4A)] = { true, false, true, true, },
534 [opc_op(OPC_SAMGP0)] = { true, false, true, true, },
535 [opc_op(OPC_SAMGP1)] = { true, false, true, true, },
536 [opc_op(OPC_SAMGP2)] = { true, false, true, true, },
537 [opc_op(OPC_SAMGP3)] = { true, false, true, true, },
538 [opc_op(OPC_DSXPP_1)] = { true, false, false, false, },
539 [opc_op(OPC_DSYPP_1)] = { true, false, false, false, },
540 [opc_op(OPC_RGETPOS)] = { true, false, false, false, },
541 [opc_op(OPC_RGETINFO)] = { false, false, false, false, },
542 };
543
544 static const struct {
545 bool indirect;
546 bool bindless;
547 bool use_a1;
548 bool uniform;
549 } desc_features[8] = {
550 [CAT5_NONUNIFORM] = { .indirect = true, },
551 [CAT5_UNIFORM] = { .indirect = true, .uniform = true, },
552 [CAT5_BINDLESS_IMM] = { .bindless = true, },
553 [CAT5_BINDLESS_UNIFORM] = {
554 .bindless = true,
555 .indirect = true,
556 .uniform = true,
557 },
558 [CAT5_BINDLESS_NONUNIFORM] = {
559 .bindless = true,
560 .indirect = true,
561 },
562 [CAT5_BINDLESS_A1_IMM] = {
563 .bindless = true,
564 .use_a1 = true,
565 },
566 [CAT5_BINDLESS_A1_UNIFORM] = {
567 .bindless = true,
568 .indirect = true,
569 .uniform = true,
570 .use_a1 = true,
571 },
572 [CAT5_BINDLESS_A1_NONUNIFORM] = {
573 .bindless = true,
574 .indirect = true,
575 .use_a1 = true,
576 },
577 };
578
579 instr_cat5_t *cat5 = &instr->cat5;
580 int i;
581
582 bool desc_indirect =
583 cat5->is_s2en_bindless &&
584 desc_features[cat5->s2en_bindless.desc_mode].indirect;
585 bool bindless =
586 cat5->is_s2en_bindless &&
587 desc_features[cat5->s2en_bindless.desc_mode].bindless;
588 bool use_a1 =
589 cat5->is_s2en_bindless &&
590 desc_features[cat5->s2en_bindless.desc_mode].use_a1;
591 bool uniform =
592 cat5->is_s2en_bindless &&
593 desc_features[cat5->s2en_bindless.desc_mode].uniform;
594
595 if (cat5->is_3d) fprintf(ctx->out, ".3d");
596 if (cat5->is_a) fprintf(ctx->out, ".a");
597 if (cat5->is_o) fprintf(ctx->out, ".o");
598 if (cat5->is_p) fprintf(ctx->out, ".p");
599 if (cat5->is_s) fprintf(ctx->out, ".s");
600 if (desc_indirect) fprintf(ctx->out, ".s2en");
601 if (uniform) fprintf(ctx->out, ".uniform");
602
603 if (bindless) {
604 unsigned base = (cat5->s2en_bindless.base_hi << 1) | cat5->base_lo;
605 fprintf(ctx->out, ".base%d", base);
606 }
607
608 fprintf(ctx->out, " ");
609
610 switch (_OPC(5, cat5->opc)) {
611 case OPC_DSXPP_1:
612 case OPC_DSYPP_1:
613 break;
614 default:
615 fprintf(ctx->out, "(%s)", type[cat5->type]);
616 break;
617 }
618
619 fprintf(ctx->out, "(");
620 for (i = 0; i < 4; i++)
621 if (cat5->wrmask & (1 << i))
622 fprintf(ctx->out, "%c", "xyzw"[i]);
623 fprintf(ctx->out, ")");
624
625 print_reg_dst(ctx, (reg_t)(cat5->dst), type_size(cat5->type) == 32, false);
626
627 if (info[cat5->opc].src1) {
628 fprintf(ctx->out, ", ");
629 struct reginfo src = { .reg = (reg_t)(cat5->src1), .full = cat5->full };
630 print_src(ctx, &src);
631 }
632
633 if (cat5->is_o || info[cat5->opc].src2) {
634 fprintf(ctx->out, ", ");
635 struct reginfo src = { .reg = (reg_t)(cat5->src2), .full = cat5->full };
636 print_src(ctx, &src);
637 }
638 if (cat5->is_s2en_bindless) {
639 if (!desc_indirect) {
640 if (info[cat5->opc].samp) {
641 if (use_a1)
642 fprintf(ctx->out, ", s#%d", cat5->s2en_bindless.src3);
643 else
644 fprintf(ctx->out, ", s#%d", cat5->s2en_bindless.src3 & 0xf);
645 }
646
647 if (info[cat5->opc].tex && !use_a1) {
648 fprintf(ctx->out, ", t#%d", cat5->s2en_bindless.src3 >> 4);
649 }
650 }
651 } else {
652 if (info[cat5->opc].samp)
653 fprintf(ctx->out, ", s#%d", cat5->norm.samp);
654 if (info[cat5->opc].tex)
655 fprintf(ctx->out, ", t#%d", cat5->norm.tex);
656 }
657
658 if (desc_indirect) {
659 fprintf(ctx->out, ", ");
660 struct reginfo src = { .reg = (reg_t)(cat5->s2en_bindless.src3), .full = bindless };
661 print_src(ctx, &src);
662 }
663
664 if (use_a1)
665 fprintf(ctx->out, ", a1.x");
666
667 if (debug & PRINT_VERBOSE) {
668 if (cat5->is_s2en_bindless) {
669 if ((debug & PRINT_VERBOSE) && cat5->s2en_bindless.dummy1)
670 fprintf(ctx->out, "\t{5: %x}", cat5->s2en_bindless.dummy1);
671 } else {
672 if ((debug & PRINT_VERBOSE) && cat5->norm.dummy1)
673 fprintf(ctx->out, "\t{5: %x}", cat5->norm.dummy1);
674 }
675 }
676 }
677
678 static void print_instr_cat6_a3xx(struct disasm_ctx *ctx, instr_t *instr)
679 {
680 instr_cat6_t *cat6 = &instr->cat6;
681 char sd = 0, ss = 0; /* dst/src address space */
682 bool nodst = false;
683 struct reginfo dst, src1, src2, ssbo;
684 int src1off = 0;
685
686 memset(&dst, 0, sizeof(dst));
687 memset(&src1, 0, sizeof(src1));
688 memset(&src2, 0, sizeof(src2));
689 memset(&ssbo, 0, sizeof(ssbo));
690
691 switch (_OPC(6, cat6->opc)) {
692 case OPC_RESINFO:
693 case OPC_RESFMT:
694 dst.full = type_size(cat6->type) == 32;
695 src1.full = type_size(cat6->type) == 32;
696 src2.full = type_size(cat6->type) == 32;
697 break;
698 case OPC_L2G:
699 case OPC_G2L:
700 dst.full = true;
701 src1.full = true;
702 src2.full = true;
703 break;
704 case OPC_STG:
705 case OPC_STL:
706 case OPC_STP:
707 case OPC_STLW:
708 case OPC_STIB:
709 dst.full = type_size(cat6->type) == 32;
710 src1.full = type_size(cat6->type) == 32;
711 src2.full = type_size(cat6->type) == 32;
712 break;
713 default:
714 dst.full = type_size(cat6->type) == 32;
715 src1.full = true;
716 src2.full = true;
717 break;
718 }
719
720 switch (_OPC(6, cat6->opc)) {
721 case OPC_PREFETCH:
722 break;
723 case OPC_RESINFO:
724 fprintf(ctx->out, ".%dd", cat6->ldgb.d + 1);
725 break;
726 case OPC_LDGB:
727 fprintf(ctx->out, ".%s", cat6->ldgb.typed ? "typed" : "untyped");
728 fprintf(ctx->out, ".%dd", cat6->ldgb.d + 1);
729 fprintf(ctx->out, ".%s", type[cat6->type]);
730 fprintf(ctx->out, ".%d", cat6->ldgb.type_size + 1);
731 break;
732 case OPC_STGB:
733 case OPC_STIB:
734 fprintf(ctx->out, ".%s", cat6->stgb.typed ? "typed" : "untyped");
735 fprintf(ctx->out, ".%dd", cat6->stgb.d + 1);
736 fprintf(ctx->out, ".%s", type[cat6->type]);
737 fprintf(ctx->out, ".%d", cat6->stgb.type_size + 1);
738 break;
739 case OPC_ATOMIC_ADD:
740 case OPC_ATOMIC_SUB:
741 case OPC_ATOMIC_XCHG:
742 case OPC_ATOMIC_INC:
743 case OPC_ATOMIC_DEC:
744 case OPC_ATOMIC_CMPXCHG:
745 case OPC_ATOMIC_MIN:
746 case OPC_ATOMIC_MAX:
747 case OPC_ATOMIC_AND:
748 case OPC_ATOMIC_OR:
749 case OPC_ATOMIC_XOR:
750 ss = cat6->g ? 'g' : 'l';
751 fprintf(ctx->out, ".%s", cat6->ldgb.typed ? "typed" : "untyped");
752 fprintf(ctx->out, ".%dd", cat6->ldgb.d + 1);
753 fprintf(ctx->out, ".%s", type[cat6->type]);
754 fprintf(ctx->out, ".%d", cat6->ldgb.type_size + 1);
755 fprintf(ctx->out, ".%c", ss);
756 break;
757 default:
758 dst.im = cat6->g && !cat6->dst_off;
759 fprintf(ctx->out, ".%s", type[cat6->type]);
760 break;
761 }
762 fprintf(ctx->out, " ");
763
764 switch (_OPC(6, cat6->opc)) {
765 case OPC_STG:
766 sd = 'g';
767 break;
768 case OPC_STP:
769 sd = 'p';
770 break;
771 case OPC_STL:
772 case OPC_STLW:
773 sd = 'l';
774 break;
775
776 case OPC_LDG:
777 case OPC_LDC:
778 ss = 'g';
779 break;
780 case OPC_LDP:
781 ss = 'p';
782 break;
783 case OPC_LDL:
784 case OPC_LDLW:
785 case OPC_LDLV:
786 ss = 'l';
787 break;
788
789 case OPC_L2G:
790 ss = 'l';
791 sd = 'g';
792 break;
793
794 case OPC_G2L:
795 ss = 'g';
796 sd = 'l';
797 break;
798
799 case OPC_PREFETCH:
800 ss = 'g';
801 nodst = true;
802 break;
803 }
804
805 if ((_OPC(6, cat6->opc) == OPC_STGB) || (_OPC(6, cat6->opc) == OPC_STIB)) {
806 struct reginfo src3;
807
808 memset(&src3, 0, sizeof(src3));
809
810 src1.reg = (reg_t)(cat6->stgb.src1);
811 src2.reg = (reg_t)(cat6->stgb.src2);
812 src2.im = cat6->stgb.src2_im;
813 src3.reg = (reg_t)(cat6->stgb.src3);
814 src3.im = cat6->stgb.src3_im;
815 src3.full = true;
816
817 fprintf(ctx->out, "g[%u], ", cat6->stgb.dst_ssbo);
818 print_src(ctx, &src1);
819 fprintf(ctx->out, ", ");
820 print_src(ctx, &src2);
821 fprintf(ctx->out, ", ");
822 print_src(ctx, &src3);
823
824 if (debug & PRINT_VERBOSE)
825 fprintf(ctx->out, " (pad0=%x, pad3=%x)", cat6->stgb.pad0, cat6->stgb.pad3);
826
827 return;
828 }
829
830 if (is_atomic(_OPC(6, cat6->opc))) {
831
832 src1.reg = (reg_t)(cat6->ldgb.src1);
833 src1.im = cat6->ldgb.src1_im;
834 src2.reg = (reg_t)(cat6->ldgb.src2);
835 src2.im = cat6->ldgb.src2_im;
836 dst.reg = (reg_t)(cat6->ldgb.dst);
837
838 print_src(ctx, &dst);
839 fprintf(ctx->out, ", ");
840 if (ss == 'g') {
841 struct reginfo src3;
842 memset(&src3, 0, sizeof(src3));
843
844 src3.reg = (reg_t)(cat6->ldgb.src3);
845 src3.full = true;
846
847 /* For images, the ".typed" variant is used and src2 is
848 * the ivecN coordinates, ie ivec2 for 2d.
849 *
850 * For SSBOs, the ".untyped" variant is used and src2 is
851 * a simple dword offset.. src3 appears to be
852 * uvec2(offset * 4, 0). Not sure the point of that.
853 */
854
855 fprintf(ctx->out, "g[%u], ", cat6->ldgb.src_ssbo);
856 print_src(ctx, &src1); /* value */
857 fprintf(ctx->out, ", ");
858 print_src(ctx, &src2); /* offset/coords */
859 fprintf(ctx->out, ", ");
860 print_src(ctx, &src3); /* 64b byte offset.. */
861
862 if (debug & PRINT_VERBOSE) {
863 fprintf(ctx->out, " (pad0=%x, mustbe0=%x)", cat6->ldgb.pad0,
864 cat6->ldgb.mustbe0);
865 }
866 } else { /* ss == 'l' */
867 fprintf(ctx->out, "l[");
868 print_src(ctx, &src1); /* simple byte offset */
869 fprintf(ctx->out, "], ");
870 print_src(ctx, &src2); /* value */
871
872 if (debug & PRINT_VERBOSE) {
873 fprintf(ctx->out, " (src3=%x, pad0=%x, src_ssbo_im=%x, mustbe0=%x)",
874 cat6->ldgb.src3, cat6->ldgb.pad0,
875 cat6->ldgb.src_ssbo_im, cat6->ldgb.mustbe0);
876 }
877 }
878
879 return;
880 } else if (_OPC(6, cat6->opc) == OPC_RESINFO) {
881 dst.reg = (reg_t)(cat6->ldgb.dst);
882 ssbo.reg = (reg_t)(cat6->ldgb.src_ssbo);
883 ssbo.im = cat6->ldgb.src_ssbo_im;
884
885 print_src(ctx, &dst);
886 fprintf(ctx->out, ", ");
887
888 fprintf(ctx->out, "g[");
889 print_src(ctx, &ssbo);
890 fprintf(ctx->out, "]");
891
892 return;
893 } else if (_OPC(6, cat6->opc) == OPC_LDGB) {
894
895 src1.reg = (reg_t)(cat6->ldgb.src1);
896 src1.im = cat6->ldgb.src1_im;
897 src2.reg = (reg_t)(cat6->ldgb.src2);
898 src2.im = cat6->ldgb.src2_im;
899 ssbo.reg = (reg_t)(cat6->ldgb.src_ssbo);
900 ssbo.im = cat6->ldgb.src_ssbo_im;
901 dst.reg = (reg_t)(cat6->ldgb.dst);
902
903 print_src(ctx, &dst);
904 fprintf(ctx->out, ", ");
905
906 fprintf(ctx->out, "g[");
907 print_src(ctx, &ssbo);
908 fprintf(ctx->out, "], ");
909
910 print_src(ctx, &src1);
911 fprintf(ctx->out, ", ");
912 print_src(ctx, &src2);
913
914 if (debug & PRINT_VERBOSE)
915 fprintf(ctx->out, " (pad0=%x, ssbo_im=%x, mustbe0=%x)", cat6->ldgb.pad0, cat6->ldgb.src_ssbo_im, cat6->ldgb.mustbe0);
916
917 return;
918 } else if (_OPC(6, cat6->opc) == OPC_LDG && cat6->a.src1_im && cat6->a.src2_im) {
919 struct reginfo src3;
920
921 memset(&src3, 0, sizeof(src3));
922 src1.reg = (reg_t)(cat6->a.src1);
923 src2.reg = (reg_t)(cat6->a.src2);
924 src2.im = cat6->a.src2_im;
925 src3.reg = (reg_t)(cat6->a.off);
926 src3.full = true;
927 dst.reg = (reg_t)(cat6->d.dst);
928
929 print_src(ctx, &dst);
930 fprintf(ctx->out, ", g[");
931 print_src(ctx, &src1);
932 fprintf(ctx->out, "+");
933 print_src(ctx, &src3);
934 fprintf(ctx->out, "], ");
935 print_src(ctx, &src2);
936
937 return;
938 }
939
940 if (cat6->src_off) {
941 src1.reg = (reg_t)(cat6->a.src1);
942 src1.im = cat6->a.src1_im;
943 src2.reg = (reg_t)(cat6->a.src2);
944 src2.im = cat6->a.src2_im;
945 src1off = cat6->a.off;
946 } else {
947 src1.reg = (reg_t)(cat6->b.src1);
948 src1.im = cat6->b.src1_im;
949 src2.reg = (reg_t)(cat6->b.src2);
950 src2.im = cat6->b.src2_im;
951 }
952
953 if (!nodst) {
954 if (sd)
955 fprintf(ctx->out, "%c[", sd);
956 /* note: dst might actually be a src (ie. address to store to) */
957 if (cat6->dst_off) {
958 dst.reg = (reg_t)(cat6->c.dst);
959 print_src(ctx, &dst);
960 if (cat6->g) {
961 struct reginfo dstoff_reg = {
962 .reg = (reg_t) cat6->c.off,
963 .full = true
964 };
965 fprintf(ctx->out, "+");
966 print_src(ctx, &dstoff_reg);
967 } else if (cat6->c.off || cat6->c.off_high) {
968 fprintf(ctx->out, "%+d", ((uint32_t)cat6->c.off_high << 8) | cat6->c.off);
969 }
970 } else {
971 dst.reg = (reg_t)(cat6->d.dst);
972 print_src(ctx, &dst);
973 }
974 if (sd)
975 fprintf(ctx->out, "]");
976 fprintf(ctx->out, ", ");
977 }
978
979 if (ss)
980 fprintf(ctx->out, "%c[", ss);
981
982 /* can have a larger than normal immed, so hack: */
983 if (src1.im) {
984 fprintf(ctx->out, "%u", src1.reg.dummy13);
985 } else {
986 print_src(ctx, &src1);
987 }
988
989 if (cat6->src_off && cat6->g)
990 print_src(ctx, &src2);
991 else if (src1off)
992 fprintf(ctx->out, "%+d", src1off);
993 if (ss)
994 fprintf(ctx->out, "]");
995
996 switch (_OPC(6, cat6->opc)) {
997 case OPC_RESINFO:
998 case OPC_RESFMT:
999 break;
1000 default:
1001 fprintf(ctx->out, ", ");
1002 print_src(ctx, &src2);
1003 break;
1004 }
1005 }
1006
1007 static void print_instr_cat6_a6xx(struct disasm_ctx *ctx, instr_t *instr)
1008 {
1009 instr_cat6_a6xx_t *cat6 = &instr->cat6_a6xx;
1010 struct reginfo src1, src2, ssbo;
1011 uint32_t opc = _OPC(6, cat6->opc);
1012 bool uses_type = opc != OPC_LDC;
1013
1014 static const struct {
1015 bool indirect;
1016 bool bindless;
1017 const char *name;
1018 } desc_features[8] = {
1019 [CAT6_IMM] = {
1020 .name = "imm"
1021 },
1022 [CAT6_UNIFORM] = {
1023 .indirect = true,
1024 .name = "uniform"
1025 },
1026 [CAT6_NONUNIFORM] = {
1027 .indirect = true,
1028 .name = "nonuniform"
1029 },
1030 [CAT6_BINDLESS_IMM] = {
1031 .bindless = true,
1032 .name = "imm"
1033 },
1034 [CAT6_BINDLESS_UNIFORM] = {
1035 .bindless = true,
1036 .indirect = true,
1037 .name = "uniform"
1038 },
1039 [CAT6_BINDLESS_NONUNIFORM] = {
1040 .bindless = true,
1041 .indirect = true,
1042 .name = "nonuniform"
1043 },
1044 };
1045
1046 bool indirect_ssbo = desc_features[cat6->desc_mode].indirect;
1047 bool bindless = desc_features[cat6->desc_mode].bindless;
1048 bool type_full = cat6->type != TYPE_U16;
1049
1050
1051 memset(&src1, 0, sizeof(src1));
1052 memset(&src2, 0, sizeof(src2));
1053 memset(&ssbo, 0, sizeof(ssbo));
1054
1055 if (uses_type) {
1056 fprintf(ctx->out, ".%s", cat6->typed ? "typed" : "untyped");
1057 fprintf(ctx->out, ".%dd", cat6->d + 1);
1058 fprintf(ctx->out, ".%s", type[cat6->type]);
1059 } else {
1060 fprintf(ctx->out, ".offset%d", cat6->d);
1061 }
1062 fprintf(ctx->out, ".%u", cat6->type_size + 1);
1063
1064 fprintf(ctx->out, ".%s", desc_features[cat6->desc_mode].name);
1065 if (bindless)
1066 fprintf(ctx->out, ".base%d", cat6->base);
1067 fprintf(ctx->out, " ");
1068
1069 src2.reg = (reg_t)(cat6->src2);
1070 src2.full = type_full;
1071 print_src(ctx, &src2);
1072 fprintf(ctx->out, ", ");
1073
1074 if (opc != OPC_RESINFO) {
1075 src1.reg = (reg_t)(cat6->src1);
1076 src1.full = true; // XXX
1077 print_src(ctx, &src1);
1078 fprintf(ctx->out, ", ");
1079 }
1080
1081 ssbo.reg = (reg_t)(cat6->ssbo);
1082 ssbo.im = !indirect_ssbo;
1083 ssbo.full = true;
1084 print_src(ctx, &ssbo);
1085
1086 if (debug & PRINT_VERBOSE) {
1087 fprintf(ctx->out, " (pad1=%x, pad2=%x, pad3=%x, pad4=%x, pad5=%x)",
1088 cat6->pad1, cat6->pad2, cat6->pad3, cat6->pad4, cat6->pad5);
1089 }
1090 }
1091
1092 static void print_instr_cat6(struct disasm_ctx *ctx, instr_t *instr)
1093 {
1094 if (!is_cat6_legacy(instr, ctx->gpu_id)) {
1095 print_instr_cat6_a6xx(ctx, instr);
1096 if (debug & PRINT_VERBOSE)
1097 fprintf(ctx->out, " NEW");
1098 } else {
1099 print_instr_cat6_a3xx(ctx, instr);
1100 if (debug & PRINT_VERBOSE)
1101 fprintf(ctx->out, " LEGACY");
1102 }
1103 }
1104 static void print_instr_cat7(struct disasm_ctx *ctx, instr_t *instr)
1105 {
1106 instr_cat7_t *cat7 = &instr->cat7;
1107
1108 if (cat7->g)
1109 fprintf(ctx->out, ".g");
1110 if (cat7->l)
1111 fprintf(ctx->out, ".l");
1112
1113 if (_OPC(7, cat7->opc) == OPC_FENCE) {
1114 if (cat7->r)
1115 fprintf(ctx->out, ".r");
1116 if (cat7->w)
1117 fprintf(ctx->out, ".w");
1118 }
1119 }
1120
1121 /* size of largest OPC field of all the instruction categories: */
1122 #define NOPC_BITS 6
1123
1124 static const struct opc_info {
1125 uint16_t cat;
1126 uint16_t opc;
1127 const char *name;
1128 void (*print)(struct disasm_ctx *ctx, instr_t *instr);
1129 } opcs[1 << (3+NOPC_BITS)] = {
1130 #define OPC(cat, opc, name) [(opc)] = { (cat), (opc), #name, print_instr_cat##cat }
1131 /* category 0: */
1132 OPC(0, OPC_NOP, nop),
1133 OPC(0, OPC_B, b),
1134 OPC(0, OPC_JUMP, jump),
1135 OPC(0, OPC_CALL, call),
1136 OPC(0, OPC_RET, ret),
1137 OPC(0, OPC_KILL, kill),
1138 OPC(0, OPC_END, end),
1139 OPC(0, OPC_EMIT, emit),
1140 OPC(0, OPC_CUT, cut),
1141 OPC(0, OPC_CHMASK, chmask),
1142 OPC(0, OPC_CHSH, chsh),
1143 OPC(0, OPC_FLOW_REV, flow_rev),
1144 OPC(0, OPC_PREDT, predt),
1145 OPC(0, OPC_PREDF, predf),
1146 OPC(0, OPC_PREDE, prede),
1147 OPC(0, OPC_BKT, bkt),
1148 OPC(0, OPC_STKS, stks),
1149 OPC(0, OPC_STKR, stkr),
1150 OPC(0, OPC_XSET, xset),
1151 OPC(0, OPC_XCLR, xclr),
1152 OPC(0, OPC_GETONE, getone),
1153 OPC(0, OPC_DBG, dbg),
1154 OPC(0, OPC_SHPS, shps),
1155 OPC(0, OPC_SHPE, shpe),
1156
1157 /* category 1: */
1158 OPC(1, OPC_MOV, ),
1159
1160 /* category 2: */
1161 OPC(2, OPC_ADD_F, add.f),
1162 OPC(2, OPC_MIN_F, min.f),
1163 OPC(2, OPC_MAX_F, max.f),
1164 OPC(2, OPC_MUL_F, mul.f),
1165 OPC(2, OPC_SIGN_F, sign.f),
1166 OPC(2, OPC_CMPS_F, cmps.f),
1167 OPC(2, OPC_ABSNEG_F, absneg.f),
1168 OPC(2, OPC_CMPV_F, cmpv.f),
1169 OPC(2, OPC_FLOOR_F, floor.f),
1170 OPC(2, OPC_CEIL_F, ceil.f),
1171 OPC(2, OPC_RNDNE_F, rndne.f),
1172 OPC(2, OPC_RNDAZ_F, rndaz.f),
1173 OPC(2, OPC_TRUNC_F, trunc.f),
1174 OPC(2, OPC_ADD_U, add.u),
1175 OPC(2, OPC_ADD_S, add.s),
1176 OPC(2, OPC_SUB_U, sub.u),
1177 OPC(2, OPC_SUB_S, sub.s),
1178 OPC(2, OPC_CMPS_U, cmps.u),
1179 OPC(2, OPC_CMPS_S, cmps.s),
1180 OPC(2, OPC_MIN_U, min.u),
1181 OPC(2, OPC_MIN_S, min.s),
1182 OPC(2, OPC_MAX_U, max.u),
1183 OPC(2, OPC_MAX_S, max.s),
1184 OPC(2, OPC_ABSNEG_S, absneg.s),
1185 OPC(2, OPC_AND_B, and.b),
1186 OPC(2, OPC_OR_B, or.b),
1187 OPC(2, OPC_NOT_B, not.b),
1188 OPC(2, OPC_XOR_B, xor.b),
1189 OPC(2, OPC_CMPV_U, cmpv.u),
1190 OPC(2, OPC_CMPV_S, cmpv.s),
1191 OPC(2, OPC_MUL_U24, mul.u24),
1192 OPC(2, OPC_MUL_S24, mul.s24),
1193 OPC(2, OPC_MULL_U, mull.u),
1194 OPC(2, OPC_BFREV_B, bfrev.b),
1195 OPC(2, OPC_CLZ_S, clz.s),
1196 OPC(2, OPC_CLZ_B, clz.b),
1197 OPC(2, OPC_SHL_B, shl.b),
1198 OPC(2, OPC_SHR_B, shr.b),
1199 OPC(2, OPC_ASHR_B, ashr.b),
1200 OPC(2, OPC_BARY_F, bary.f),
1201 OPC(2, OPC_MGEN_B, mgen.b),
1202 OPC(2, OPC_GETBIT_B, getbit.b),
1203 OPC(2, OPC_SETRM, setrm),
1204 OPC(2, OPC_CBITS_B, cbits.b),
1205 OPC(2, OPC_SHB, shb),
1206 OPC(2, OPC_MSAD, msad),
1207
1208 /* category 3: */
1209 OPC(3, OPC_MAD_U16, mad.u16),
1210 OPC(3, OPC_MADSH_U16, madsh.u16),
1211 OPC(3, OPC_MAD_S16, mad.s16),
1212 OPC(3, OPC_MADSH_M16, madsh.m16),
1213 OPC(3, OPC_MAD_U24, mad.u24),
1214 OPC(3, OPC_MAD_S24, mad.s24),
1215 OPC(3, OPC_MAD_F16, mad.f16),
1216 OPC(3, OPC_MAD_F32, mad.f32),
1217 OPC(3, OPC_SEL_B16, sel.b16),
1218 OPC(3, OPC_SEL_B32, sel.b32),
1219 OPC(3, OPC_SEL_S16, sel.s16),
1220 OPC(3, OPC_SEL_S32, sel.s32),
1221 OPC(3, OPC_SEL_F16, sel.f16),
1222 OPC(3, OPC_SEL_F32, sel.f32),
1223 OPC(3, OPC_SAD_S16, sad.s16),
1224 OPC(3, OPC_SAD_S32, sad.s32),
1225
1226 /* category 4: */
1227 OPC(4, OPC_RCP, rcp),
1228 OPC(4, OPC_RSQ, rsq),
1229 OPC(4, OPC_LOG2, log2),
1230 OPC(4, OPC_EXP2, exp2),
1231 OPC(4, OPC_SIN, sin),
1232 OPC(4, OPC_COS, cos),
1233 OPC(4, OPC_SQRT, sqrt),
1234 OPC(4, OPC_HRSQ, hrsq),
1235 OPC(4, OPC_HLOG2, hlog2),
1236 OPC(4, OPC_HEXP2, hexp2),
1237
1238 /* category 5: */
1239 OPC(5, OPC_ISAM, isam),
1240 OPC(5, OPC_ISAML, isaml),
1241 OPC(5, OPC_ISAMM, isamm),
1242 OPC(5, OPC_SAM, sam),
1243 OPC(5, OPC_SAMB, samb),
1244 OPC(5, OPC_SAML, saml),
1245 OPC(5, OPC_SAMGQ, samgq),
1246 OPC(5, OPC_GETLOD, getlod),
1247 OPC(5, OPC_CONV, conv),
1248 OPC(5, OPC_CONVM, convm),
1249 OPC(5, OPC_GETSIZE, getsize),
1250 OPC(5, OPC_GETBUF, getbuf),
1251 OPC(5, OPC_GETPOS, getpos),
1252 OPC(5, OPC_GETINFO, getinfo),
1253 OPC(5, OPC_DSX, dsx),
1254 OPC(5, OPC_DSY, dsy),
1255 OPC(5, OPC_GATHER4R, gather4r),
1256 OPC(5, OPC_GATHER4G, gather4g),
1257 OPC(5, OPC_GATHER4B, gather4b),
1258 OPC(5, OPC_GATHER4A, gather4a),
1259 OPC(5, OPC_SAMGP0, samgp0),
1260 OPC(5, OPC_SAMGP1, samgp1),
1261 OPC(5, OPC_SAMGP2, samgp2),
1262 OPC(5, OPC_SAMGP3, samgp3),
1263 OPC(5, OPC_DSXPP_1, dsxpp.1),
1264 OPC(5, OPC_DSYPP_1, dsypp.1),
1265 OPC(5, OPC_RGETPOS, rgetpos),
1266 OPC(5, OPC_RGETINFO, rgetinfo),
1267 /* macros are needed here for ir3_print */
1268 OPC(5, OPC_DSXPP_MACRO, dsxpp.macro),
1269 OPC(5, OPC_DSYPP_MACRO, dsypp.macro),
1270
1271
1272 /* category 6: */
1273 OPC(6, OPC_LDG, ldg),
1274 OPC(6, OPC_LDL, ldl),
1275 OPC(6, OPC_LDP, ldp),
1276 OPC(6, OPC_STG, stg),
1277 OPC(6, OPC_STL, stl),
1278 OPC(6, OPC_STP, stp),
1279 OPC(6, OPC_LDIB, ldib),
1280 OPC(6, OPC_G2L, g2l),
1281 OPC(6, OPC_L2G, l2g),
1282 OPC(6, OPC_PREFETCH, prefetch),
1283 OPC(6, OPC_LDLW, ldlw),
1284 OPC(6, OPC_STLW, stlw),
1285 OPC(6, OPC_RESFMT, resfmt),
1286 OPC(6, OPC_RESINFO, resinfo),
1287 OPC(6, OPC_ATOMIC_ADD, atomic.add),
1288 OPC(6, OPC_ATOMIC_SUB, atomic.sub),
1289 OPC(6, OPC_ATOMIC_XCHG, atomic.xchg),
1290 OPC(6, OPC_ATOMIC_INC, atomic.inc),
1291 OPC(6, OPC_ATOMIC_DEC, atomic.dec),
1292 OPC(6, OPC_ATOMIC_CMPXCHG, atomic.cmpxchg),
1293 OPC(6, OPC_ATOMIC_MIN, atomic.min),
1294 OPC(6, OPC_ATOMIC_MAX, atomic.max),
1295 OPC(6, OPC_ATOMIC_AND, atomic.and),
1296 OPC(6, OPC_ATOMIC_OR, atomic.or),
1297 OPC(6, OPC_ATOMIC_XOR, atomic.xor),
1298 OPC(6, OPC_LDGB, ldgb),
1299 OPC(6, OPC_STGB, stgb),
1300 OPC(6, OPC_STIB, stib),
1301 OPC(6, OPC_LDC, ldc),
1302 OPC(6, OPC_LDLV, ldlv),
1303
1304 OPC(7, OPC_BAR, bar),
1305 OPC(7, OPC_FENCE, fence),
1306
1307 #undef OPC
1308 };
1309
1310 #define GETINFO(instr) (&(opcs[((instr)->opc_cat << NOPC_BITS) | instr_opc(instr, ctx->gpu_id)]))
1311
1312 // XXX hack.. probably should move this table somewhere common:
1313 #include "ir3.h"
1314 const char *ir3_instr_name(struct ir3_instruction *instr)
1315 {
1316 if (opc_cat(instr->opc) == -1) return "??meta??";
1317 return opcs[instr->opc].name;
1318 }
1319
1320 static void print_single_instr(struct disasm_ctx *ctx, instr_t *instr)
1321 {
1322 const char *name = GETINFO(instr)->name;
1323 uint32_t opc = instr_opc(instr, ctx->gpu_id);
1324
1325 if (name) {
1326 fprintf(ctx->out, "%s", name);
1327 GETINFO(instr)->print(ctx, instr);
1328 } else {
1329 fprintf(ctx->out, "unknown(%d,%d)", instr->opc_cat, opc);
1330
1331 switch (instr->opc_cat) {
1332 case 0: print_instr_cat0(ctx, instr); break;
1333 case 1: print_instr_cat1(ctx, instr); break;
1334 case 2: print_instr_cat2(ctx, instr); break;
1335 case 3: print_instr_cat3(ctx, instr); break;
1336 case 4: print_instr_cat4(ctx, instr); break;
1337 case 5: print_instr_cat5(ctx, instr); break;
1338 case 6: print_instr_cat6(ctx, instr); break;
1339 case 7: print_instr_cat7(ctx, instr); break;
1340 }
1341 }
1342 }
1343
1344 static bool print_instr(struct disasm_ctx *ctx, uint32_t *dwords, int n)
1345 {
1346 instr_t *instr = (instr_t *)dwords;
1347 uint32_t opc = instr_opc(instr, ctx->gpu_id);
1348 unsigned nop = 0;
1349 unsigned cycles = ctx->instructions;
1350
1351 if (debug & PRINT_VERBOSE) {
1352 fprintf(ctx->out, "%s%04d:%04d[%08xx_%08xx] ", levels[ctx->level],
1353 n, cycles++, dwords[1], dwords[0]);
1354 }
1355
1356 /* NOTE: order flags are printed is a bit fugly.. but for now I
1357 * try to match the order in llvm-a3xx disassembler for easy
1358 * diff'ing..
1359 */
1360
1361 ctx->repeat = instr_repeat(instr);
1362 ctx->instructions += 1 + ctx->repeat;
1363
1364 if (instr->sync) {
1365 fprintf(ctx->out, "(sy)");
1366 }
1367 if (instr->ss && ((instr->opc_cat <= 4) || (instr->opc_cat == 7))) {
1368 fprintf(ctx->out, "(ss)");
1369 }
1370 if (instr->jmp_tgt)
1371 fprintf(ctx->out, "(jp)");
1372 if ((instr->opc_cat == 0) && instr->cat0.eq)
1373 fprintf(ctx->out, "(eq)");
1374 if (instr_sat(instr))
1375 fprintf(ctx->out, "(sat)");
1376 if (ctx->repeat)
1377 fprintf(ctx->out, "(rpt%d)", ctx->repeat);
1378 else if ((instr->opc_cat == 2) && (instr->cat2.src1_r || instr->cat2.src2_r))
1379 nop = (instr->cat2.src2_r * 2) + instr->cat2.src1_r;
1380 else if ((instr->opc_cat == 3) && (instr->cat3.src1_r || instr->cat3.src2_r))
1381 nop = (instr->cat3.src2_r * 2) + instr->cat3.src1_r;
1382 ctx->instructions += nop;
1383 if (nop)
1384 fprintf(ctx->out, "(nop%d) ", nop);
1385
1386 if (instr->ul && ((2 <= instr->opc_cat) && (instr->opc_cat <= 4)))
1387 fprintf(ctx->out, "(ul)");
1388
1389 print_single_instr(ctx, instr);
1390 fprintf(ctx->out, "\n");
1391
1392 if ((instr->opc_cat <= 4) && (debug & EXPAND_REPEAT)) {
1393 int i;
1394 for (i = 0; i < nop; i++) {
1395 if (debug & PRINT_VERBOSE) {
1396 fprintf(ctx->out, "%s%04d:%04d[ ] ",
1397 levels[ctx->level], n, cycles++);
1398 }
1399 fprintf(ctx->out, "nop\n");
1400 }
1401 for (i = 0; i < ctx->repeat; i++) {
1402 ctx->repeatidx = i + 1;
1403 if (debug & PRINT_VERBOSE) {
1404 fprintf(ctx->out, "%s%04d:%04d[ ] ",
1405 levels[ctx->level], n, cycles++);
1406 }
1407 print_single_instr(ctx, instr);
1408 fprintf(ctx->out, "\n");
1409 }
1410 ctx->repeatidx = 0;
1411 }
1412
1413 return (instr->opc_cat == 0) && (opc == OPC_END);
1414 }
1415
1416 int disasm_a3xx(uint32_t *dwords, int sizedwords, int level, FILE *out, unsigned gpu_id)
1417 {
1418 struct disasm_ctx ctx;
1419 int i;
1420 int nop_count = 0;
1421
1422 assert((sizedwords % 2) == 0);
1423
1424 memset(&ctx, 0, sizeof(ctx));
1425 ctx.out = out;
1426 ctx.level = level;
1427 ctx.gpu_id = gpu_id;
1428
1429 for (i = 0; i < sizedwords; i += 2) {
1430 print_instr(&ctx, &dwords[i], i/2);
1431 if (dwords[i] == 0 && dwords[i + 1] == 0)
1432 nop_count++;
1433 else
1434 nop_count = 0;
1435 if (nop_count > 3)
1436 break;
1437 }
1438
1439 return 0;
1440 }