2 * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
27 #define PACKED __attribute__((__packed__))
34 /* size of largest OPC field of all the instruction categories: */
37 #define _OPC(cat, opc) (((cat) << NOPC_BITS) | opc)
43 OPC_JUMP
= _OPC(0, 2),
44 OPC_CALL
= _OPC(0, 3),
46 OPC_KILL
= _OPC(0, 5),
48 OPC_EMIT
= _OPC(0, 7),
50 OPC_CHMASK
= _OPC(0, 9),
51 OPC_CHSH
= _OPC(0, 10),
52 OPC_FLOW_REV
= _OPC(0, 11),
54 OPC_BKT
= _OPC(0, 16),
55 OPC_STKS
= _OPC(0, 17),
56 OPC_STKR
= _OPC(0, 18),
57 OPC_XSET
= _OPC(0, 19),
58 OPC_XCLR
= _OPC(0, 20),
59 OPC_GETONE
= _OPC(0, 21),
60 OPC_DBG
= _OPC(0, 22),
61 OPC_SHPS
= _OPC(0, 23), /* shader prologue start */
62 OPC_SHPE
= _OPC(0, 24), /* shader prologue end */
64 OPC_PREDT
= _OPC(0, 29), /* predicated true */
65 OPC_PREDF
= _OPC(0, 30), /* predicated false */
66 OPC_PREDE
= _OPC(0, 31), /* predicated end */
72 OPC_ADD_F
= _OPC(2, 0),
73 OPC_MIN_F
= _OPC(2, 1),
74 OPC_MAX_F
= _OPC(2, 2),
75 OPC_MUL_F
= _OPC(2, 3),
76 OPC_SIGN_F
= _OPC(2, 4),
77 OPC_CMPS_F
= _OPC(2, 5),
78 OPC_ABSNEG_F
= _OPC(2, 6),
79 OPC_CMPV_F
= _OPC(2, 7),
81 OPC_FLOOR_F
= _OPC(2, 9),
82 OPC_CEIL_F
= _OPC(2, 10),
83 OPC_RNDNE_F
= _OPC(2, 11),
84 OPC_RNDAZ_F
= _OPC(2, 12),
85 OPC_TRUNC_F
= _OPC(2, 13),
87 OPC_ADD_U
= _OPC(2, 16),
88 OPC_ADD_S
= _OPC(2, 17),
89 OPC_SUB_U
= _OPC(2, 18),
90 OPC_SUB_S
= _OPC(2, 19),
91 OPC_CMPS_U
= _OPC(2, 20),
92 OPC_CMPS_S
= _OPC(2, 21),
93 OPC_MIN_U
= _OPC(2, 22),
94 OPC_MIN_S
= _OPC(2, 23),
95 OPC_MAX_U
= _OPC(2, 24),
96 OPC_MAX_S
= _OPC(2, 25),
97 OPC_ABSNEG_S
= _OPC(2, 26),
99 OPC_AND_B
= _OPC(2, 28),
100 OPC_OR_B
= _OPC(2, 29),
101 OPC_NOT_B
= _OPC(2, 30),
102 OPC_XOR_B
= _OPC(2, 31),
104 OPC_CMPV_U
= _OPC(2, 33),
105 OPC_CMPV_S
= _OPC(2, 34),
106 /* 35-47 - invalid */
107 OPC_MUL_U24
= _OPC(2, 48), /* 24b mul into 32b result */
108 OPC_MUL_S24
= _OPC(2, 49), /* 24b mul into 32b result with sign extension */
109 OPC_MULL_U
= _OPC(2, 50),
110 OPC_BFREV_B
= _OPC(2, 51),
111 OPC_CLZ_S
= _OPC(2, 52),
112 OPC_CLZ_B
= _OPC(2, 53),
113 OPC_SHL_B
= _OPC(2, 54),
114 OPC_SHR_B
= _OPC(2, 55),
115 OPC_ASHR_B
= _OPC(2, 56),
116 OPC_BARY_F
= _OPC(2, 57),
117 OPC_MGEN_B
= _OPC(2, 58),
118 OPC_GETBIT_B
= _OPC(2, 59),
119 OPC_SETRM
= _OPC(2, 60),
120 OPC_CBITS_B
= _OPC(2, 61),
121 OPC_SHB
= _OPC(2, 62),
122 OPC_MSAD
= _OPC(2, 63),
125 OPC_MAD_U16
= _OPC(3, 0),
126 OPC_MADSH_U16
= _OPC(3, 1),
127 OPC_MAD_S16
= _OPC(3, 2),
128 OPC_MADSH_M16
= _OPC(3, 3), /* should this be .s16? */
129 OPC_MAD_U24
= _OPC(3, 4),
130 OPC_MAD_S24
= _OPC(3, 5),
131 OPC_MAD_F16
= _OPC(3, 6),
132 OPC_MAD_F32
= _OPC(3, 7),
133 OPC_SEL_B16
= _OPC(3, 8),
134 OPC_SEL_B32
= _OPC(3, 9),
135 OPC_SEL_S16
= _OPC(3, 10),
136 OPC_SEL_S32
= _OPC(3, 11),
137 OPC_SEL_F16
= _OPC(3, 12),
138 OPC_SEL_F32
= _OPC(3, 13),
139 OPC_SAD_S16
= _OPC(3, 14),
140 OPC_SAD_S32
= _OPC(3, 15),
143 OPC_RCP
= _OPC(4, 0),
144 OPC_RSQ
= _OPC(4, 1),
145 OPC_LOG2
= _OPC(4, 2),
146 OPC_EXP2
= _OPC(4, 3),
147 OPC_SIN
= _OPC(4, 4),
148 OPC_COS
= _OPC(4, 5),
149 OPC_SQRT
= _OPC(4, 6),
150 /* NOTE that these are 8+opc from their highp equivs, so it's possible
151 * that the high order bit in the opc field has been repurposed for
152 * half-precision use? But note that other ops (rcp/lsin/cos/sqrt)
153 * still use the same opc as highp
155 OPC_HRSQ
= _OPC(4, 9),
156 OPC_HLOG2
= _OPC(4, 10),
157 OPC_HEXP2
= _OPC(4, 11),
160 OPC_ISAM
= _OPC(5, 0),
161 OPC_ISAML
= _OPC(5, 1),
162 OPC_ISAMM
= _OPC(5, 2),
163 OPC_SAM
= _OPC(5, 3),
164 OPC_SAMB
= _OPC(5, 4),
165 OPC_SAML
= _OPC(5, 5),
166 OPC_SAMGQ
= _OPC(5, 6),
167 OPC_GETLOD
= _OPC(5, 7),
168 OPC_CONV
= _OPC(5, 8),
169 OPC_CONVM
= _OPC(5, 9),
170 OPC_GETSIZE
= _OPC(5, 10),
171 OPC_GETBUF
= _OPC(5, 11),
172 OPC_GETPOS
= _OPC(5, 12),
173 OPC_GETINFO
= _OPC(5, 13),
174 OPC_DSX
= _OPC(5, 14),
175 OPC_DSY
= _OPC(5, 15),
176 OPC_GATHER4R
= _OPC(5, 16),
177 OPC_GATHER4G
= _OPC(5, 17),
178 OPC_GATHER4B
= _OPC(5, 18),
179 OPC_GATHER4A
= _OPC(5, 19),
180 OPC_SAMGP0
= _OPC(5, 20),
181 OPC_SAMGP1
= _OPC(5, 21),
182 OPC_SAMGP2
= _OPC(5, 22),
183 OPC_SAMGP3
= _OPC(5, 23),
184 OPC_DSXPP_1
= _OPC(5, 24),
185 OPC_DSYPP_1
= _OPC(5, 25),
186 OPC_RGETPOS
= _OPC(5, 26),
187 OPC_RGETINFO
= _OPC(5, 27),
188 /* cat5 meta instructions, placed above the cat5 opc field's size */
189 OPC_DSXPP_MACRO
= _OPC(5, 32),
190 OPC_DSYPP_MACRO
= _OPC(5, 33),
193 OPC_LDG
= _OPC(6, 0), /* load-global */
194 OPC_LDL
= _OPC(6, 1),
195 OPC_LDP
= _OPC(6, 2),
196 OPC_STG
= _OPC(6, 3), /* store-global */
197 OPC_STL
= _OPC(6, 4),
198 OPC_STP
= _OPC(6, 5),
199 OPC_LDIB
= _OPC(6, 6),
200 OPC_G2L
= _OPC(6, 7),
201 OPC_L2G
= _OPC(6, 8),
202 OPC_PREFETCH
= _OPC(6, 9),
203 OPC_LDLW
= _OPC(6, 10),
204 OPC_STLW
= _OPC(6, 11),
205 OPC_RESFMT
= _OPC(6, 14),
206 OPC_RESINFO
= _OPC(6, 15),
207 OPC_ATOMIC_ADD
= _OPC(6, 16),
208 OPC_ATOMIC_SUB
= _OPC(6, 17),
209 OPC_ATOMIC_XCHG
= _OPC(6, 18),
210 OPC_ATOMIC_INC
= _OPC(6, 19),
211 OPC_ATOMIC_DEC
= _OPC(6, 20),
212 OPC_ATOMIC_CMPXCHG
= _OPC(6, 21),
213 OPC_ATOMIC_MIN
= _OPC(6, 22),
214 OPC_ATOMIC_MAX
= _OPC(6, 23),
215 OPC_ATOMIC_AND
= _OPC(6, 24),
216 OPC_ATOMIC_OR
= _OPC(6, 25),
217 OPC_ATOMIC_XOR
= _OPC(6, 26),
218 OPC_LDGB
= _OPC(6, 27),
219 OPC_STGB
= _OPC(6, 28),
220 OPC_STIB
= _OPC(6, 29),
221 OPC_LDC
= _OPC(6, 30),
222 OPC_LDLV
= _OPC(6, 31),
225 OPC_BAR
= _OPC(7, 0),
226 OPC_FENCE
= _OPC(7, 1),
228 /* meta instructions (category -1): */
229 /* placeholder instr to mark shader inputs: */
230 OPC_META_INPUT
= _OPC(-1, 0),
231 /* The "collect" and "split" instructions are used for keeping
232 * track of instructions that write to multiple dst registers
233 * (split) like texture sample instructions, or read multiple
234 * consecutive scalar registers (collect) (bary.f, texture samp)
236 * A "split" extracts a scalar component from a vecN, and a
237 * "collect" gathers multiple scalar components into a vecN
239 OPC_META_SPLIT
= _OPC(-1, 2),
240 OPC_META_COLLECT
= _OPC(-1, 3),
242 /* placeholder for texture fetches that run before FS invocation
245 OPC_META_TEX_PREFETCH
= _OPC(-1, 4),
249 #define opc_cat(opc) ((int)((opc) >> NOPC_BITS))
250 #define opc_op(opc) ((unsigned)((opc) & ((1 << NOPC_BITS) - 1)))
260 TYPE_S8
= 7, // XXX I assume?
263 static inline uint32_t type_size(type_t type
)
278 assert(0); /* invalid type */
283 static inline int type_float(type_t type
)
285 return (type
== TYPE_F32
) || (type
== TYPE_F16
);
288 static inline int type_uint(type_t type
)
290 return (type
== TYPE_U32
) || (type
== TYPE_U16
) || (type
== TYPE_U8
);
293 static inline int type_sint(type_t type
)
295 return (type
== TYPE_S32
) || (type
== TYPE_S16
) || (type
== TYPE_S8
);
298 typedef union PACKED
{
299 /* normal gpr or const src register: */
304 /* for immediate val: */
305 int32_t iim_val
: 11;
306 /* to make compiler happy: */
308 uint32_t dummy10
: 10;
309 int32_t idummy10
: 10;
310 uint32_t dummy11
: 11;
311 uint32_t dummy12
: 12;
312 uint32_t dummy13
: 13;
314 int32_t idummy13
: 13;
318 /* special registers: */
319 #define REG_A0 61 /* address register */
320 #define REG_P0 62 /* predicate register */
322 static inline int reg_special(reg_t reg
)
324 return (reg
.num
== REG_A0
) || (reg
.num
== REG_P0
);
328 BRANCH_PLAIN
= 0, /* br */
329 BRANCH_OR
= 1, /* brao */
330 BRANCH_AND
= 2, /* braa */
331 BRANCH_CONST
= 3, /* brac */
332 BRANCH_ANY
= 4, /* bany */
333 BRANCH_ALL
= 5, /* ball */
334 BRANCH_X
= 6, /* brax ??? */
337 typedef struct PACKED
{
342 uint32_t dummy1
: 16;
346 uint32_t dummy1
: 12;
354 uint32_t idx
: 5; /* brac.N index */
355 uint32_t brtype
: 3; /* branch type, see brtype_t */
362 uint32_t opc_hi
: 1; /* at least one bit */
365 uint32_t comp0
: 2; /* component for first src */
367 uint32_t jmp_tgt
: 1;
369 uint32_t opc_cat
: 3;
372 typedef struct PACKED
{
375 /* for normal src register: */
378 /* at least low bit of pad must be zero or it will
379 * look like a address relative src
383 /* for address relative: */
386 uint32_t src_rel_c
: 1;
387 uint32_t src_rel
: 1;
388 uint32_t unknown
: 20;
402 uint32_t dst_type
: 3;
403 uint32_t dst_rel
: 1;
404 uint32_t src_type
: 3;
408 uint32_t pos_inf
: 1;
409 uint32_t must_be_0
: 2;
410 uint32_t jmp_tgt
: 1;
412 uint32_t opc_cat
: 3;
415 typedef struct PACKED
{
420 uint32_t must_be_zero1
: 2;
421 uint32_t src1_im
: 1; /* immediate */
422 uint32_t src1_neg
: 1; /* negate */
423 uint32_t src1_abs
: 1; /* absolute value */
427 uint32_t src1_c
: 1; /* relative-const */
428 uint32_t src1_rel
: 1; /* relative address */
429 uint32_t must_be_zero
: 1;
434 uint32_t src1_c
: 1; /* const */
442 uint32_t must_be_zero2
: 2;
443 uint32_t src2_im
: 1; /* immediate */
444 uint32_t src2_neg
: 1; /* negate */
445 uint32_t src2_abs
: 1; /* absolute value */
449 uint32_t src2_c
: 1; /* relative-const */
450 uint32_t src2_rel
: 1; /* relative address */
451 uint32_t must_be_zero
: 1;
456 uint32_t src2_c
: 1; /* const */
465 uint32_t src1_r
: 1; /* doubles as nop0 if repeat==0 */
467 uint32_t ul
: 1; /* dunno */
468 uint32_t dst_half
: 1; /* or widen/narrow.. ie. dst hrN <-> rN */
471 uint32_t src2_r
: 1; /* doubles as nop1 if repeat==0 */
472 uint32_t full
: 1; /* not half */
474 uint32_t jmp_tgt
: 1;
476 uint32_t opc_cat
: 3;
479 typedef struct PACKED
{
484 uint32_t must_be_zero1
: 2;
486 uint32_t src1_neg
: 1;
487 uint32_t src2_r
: 1; /* doubles as nop1 if repeat==0 */
492 uint32_t src1_rel
: 1;
493 uint32_t must_be_zero
: 1;
506 uint32_t must_be_zero2
: 2;
508 uint32_t src2_neg
: 1;
509 uint32_t src3_neg
: 1;
514 uint32_t src3_rel
: 1;
515 uint32_t must_be_zero
: 1;
529 uint32_t src1_r
: 1; /* doubles as nop0 if repeat==0 */
532 uint32_t dst_half
: 1; /* or widen/narrow.. ie. dst hrN <-> rN */
535 uint32_t jmp_tgt
: 1;
537 uint32_t opc_cat
: 3;
540 static inline bool instr_cat3_full(instr_cat3_t
*cat3
)
542 switch (_OPC(3, cat3
->opc
)) {
550 case OPC_SAD_S32
: // really??
557 typedef struct PACKED
{
562 uint32_t must_be_zero1
: 2;
563 uint32_t src_im
: 1; /* immediate */
564 uint32_t src_neg
: 1; /* negate */
565 uint32_t src_abs
: 1; /* absolute value */
569 uint32_t src_c
: 1; /* relative-const */
570 uint32_t src_rel
: 1; /* relative address */
571 uint32_t must_be_zero
: 1;
576 uint32_t src_c
: 1; /* const */
580 uint32_t dummy1
: 16; /* seem to be ignored */
589 uint32_t dst_half
: 1; /* or widen/narrow.. ie. dst hrN <-> rN */
590 uint32_t dummy2
: 5; /* seem to be ignored */
591 uint32_t full
: 1; /* not half */
593 uint32_t jmp_tgt
: 1;
595 uint32_t opc_cat
: 3;
598 /* With is_bindless_s2en = 1, this determines whether bindless is enabled and
599 * if so, how to get the (base, index) pair for both sampler and texture.
600 * There is a single base embedded in the instruction, which is always used
604 /* Use traditional GL binding model, get texture and sampler index
605 * from src3 which is not presumed to be uniform. This is
606 * backwards-compatible with earlier generations, where this field was
607 * always 0 and nonuniform-indexed sampling always worked.
611 /* The sampler base comes from the low 3 bits of a1.x, and the sampler
612 * and texture index come from src3 which is presumed to be uniform.
614 CAT5_BINDLESS_A1_UNIFORM
= 1,
616 /* The texture and sampler share the same base, and the sampler and
617 * texture index come from src3 which is *not* presumed to be uniform.
619 CAT5_BINDLESS_NONUNIFORM
= 2,
621 /* The sampler base comes from the low 3 bits of a1.x, and the sampler
622 * and texture index come from src3 which is *not* presumed to be
625 CAT5_BINDLESS_A1_NONUNIFORM
= 3,
627 /* Use traditional GL binding model, get texture and sampler index
628 * from src3 which is presumed to be uniform.
632 /* The texture and sampler share the same base, and the sampler and
633 * texture index come from src3 which is presumed to be uniform.
635 CAT5_BINDLESS_UNIFORM
= 5,
637 /* The texture and sampler share the same base, get sampler index from low
638 * 4 bits of src3 and texture index from high 4 bits.
640 CAT5_BINDLESS_IMM
= 6,
642 /* The sampler base comes from the low 3 bits of a1.x, and the texture
643 * index comes from the next 8 bits of a1.x. The sampler index is an
646 CAT5_BINDLESS_A1_IMM
= 7,
649 typedef struct PACKED
{
654 uint32_t full
: 1; /* not half */
657 uint32_t dummy1
: 4; /* seem to be ignored */
663 uint32_t full
: 1; /* not half */
667 uint32_t base_hi
: 2;
669 uint32_t desc_mode
: 3;
671 /* same in either case: */
672 // XXX I think, confirm this
674 uint32_t full
: 1; /* not half */
683 uint32_t wrmask
: 4; /* write-mask */
685 uint32_t base_lo
: 1; /* used with bindless */
690 uint32_t is_s2en_bindless
: 1;
695 uint32_t jmp_tgt
: 1;
697 uint32_t opc_cat
: 3;
700 /* dword0 encoding for src_off: [src1 + off], src2: */
701 typedef struct PACKED
{
703 uint32_t mustbe1
: 1;
706 uint32_t src1_im
: 1;
707 uint32_t src2_im
: 1;
714 /* dword0 encoding for !src_off: [src1], src2 */
715 typedef struct PACKED
{
717 uint32_t mustbe0
: 1;
720 uint32_t ignore0
: 8;
721 uint32_t src1_im
: 1;
722 uint32_t src2_im
: 1;
729 /* dword1 encoding for dst_off: */
730 typedef struct PACKED
{
732 uint32_t dw0_pad1
: 9;
733 int32_t off_high
: 5;
734 uint32_t dw0_pad2
: 18;
737 uint32_t mustbe1
: 1;
742 /* dword1 encoding for !dst_off: */
743 typedef struct PACKED
{
748 uint32_t mustbe0
: 1;
753 /* ldgb and atomics..
755 * ldgb: pad0=0, pad3=1
756 * atomic .g: pad0=1, pad3=1
759 typedef struct PACKED
{
765 uint32_t type_size
: 2;
767 uint32_t src1_im
: 1;
768 uint32_t src2_im
: 1;
773 uint32_t mustbe0
: 1;
774 uint32_t src_ssbo
: 8;
775 uint32_t pad2
: 3; // type
777 uint32_t src_ssbo_im
: 1;
778 uint32_t pad4
: 10; // opc/jmp_tgt/sync/opc_cat
781 /* stgb, pad0=0, pad3=2
783 typedef struct PACKED
{
785 uint32_t mustbe1
: 1; // ???
789 uint32_t type_size
: 2;
791 uint32_t src2_im
: 1;
796 uint32_t src3_im
: 1;
797 uint32_t dst_ssbo
: 8;
798 uint32_t pad2
: 3; // type
800 uint32_t pad4
: 10; // opc/jmp_tgt/sync/opc_cat
803 typedef union PACKED
{
808 instr_cat6ldgb_t ldgb
;
809 instr_cat6stgb_t stgb
;
812 uint32_t src_off
: 1;
817 uint32_t dst_off
: 1;
820 uint32_t g
: 1; /* or in some cases it means dst immed */
823 uint32_t jmp_tgt
: 1;
825 uint32_t opc_cat
: 3;
829 /* Similar to cat5_desc_mode_t, describes how the descriptor is loaded.
832 /* Use old GL binding model with an immediate index. */
839 /* Use the bindless model, with an immediate index.
841 CAT6_BINDLESS_IMM
= 4,
843 /* Use the bindless model, with a uniform register index.
845 CAT6_BINDLESS_UNIFORM
= 5,
847 /* Use the bindless model, with a register index that isn't guaranteed
848 * to be uniform. This presumably checks if the indices are equal and
849 * splits up the load/store, because it works the way you would
852 CAT6_BINDLESS_NONUNIFORM
= 6,
856 * For atomic ops (which return a value):
858 * pad1=1, pad3=c, pad5=3
859 * src1 - vecN offset/coords
860 * src2.x - is actually dest register
861 * src2.y - is 'data' except for cmpxchg where src2.y is 'compare'
862 * and src2.z is 'data'
864 * For stib (which does not return a value):
865 * pad1=0, pad3=c, pad5=2
866 * src1 - vecN offset/coords
867 * src2 - value to store
870 * pad1=1, pad3=c, pad5=2
871 * src1 - vecN offset/coords
873 * for ldc (load from UBO using descriptor):
874 * pad1=0, pad3=8, pad5=2
876 * pad2 and pad5 are only observed to be 0.
878 typedef struct PACKED
{
883 uint32_t desc_mode
: 3;
886 uint32_t type_size
: 2;
889 uint32_t src1
: 8; /* coordinate/offset */
892 uint32_t src2
: 8; /* or the dst for load instructions */
893 uint32_t pad4
: 1; //mustbe0 ??
894 uint32_t ssbo
: 8; /* ssbo/image binding point */
897 uint32_t jmp_tgt
: 1;
899 uint32_t opc_cat
: 3;
902 typedef struct PACKED
{
908 uint32_t ss
: 1; /* maybe in the encoding, but blob only uses (sy) */
910 uint32_t w
: 1; /* write */
911 uint32_t r
: 1; /* read */
912 uint32_t l
: 1; /* local */
913 uint32_t g
: 1; /* global */
914 uint32_t opc
: 4; /* presumed, but only a couple known OPCs */
915 uint32_t jmp_tgt
: 1; /* (jp) */
916 uint32_t sync
: 1; /* (sy) */
917 uint32_t opc_cat
: 3;
920 typedef union PACKED
{
928 instr_cat6_a6xx_t cat6_a6xx
;
936 uint32_t ss
: 1; /* cat1-cat4 (cat0??) and cat7 (?) */
937 uint32_t ul
: 1; /* cat2-cat4 (and cat1 in blob.. which may be bug??) */
939 uint32_t jmp_tgt
: 1;
941 uint32_t opc_cat
: 3;
946 static inline uint32_t instr_repeat(instr_t
*instr
)
948 switch (instr
->opc_cat
) {
949 case 0: return instr
->cat0
.repeat
;
950 case 1: return instr
->cat1
.repeat
;
951 case 2: return instr
->cat2
.repeat
;
952 case 3: return instr
->cat3
.repeat
;
953 case 4: return instr
->cat4
.repeat
;
958 static inline bool instr_sat(instr_t
*instr
)
960 switch (instr
->opc_cat
) {
961 case 2: return instr
->cat2
.sat
;
962 case 3: return instr
->cat3
.sat
;
963 case 4: return instr
->cat4
.sat
;
964 default: return false;
968 /* We can probably drop the gpu_id arg, but keeping it for now so we can
969 * assert if we see something we think should be new encoding on an older
972 static inline bool is_cat6_legacy(instr_t
*instr
, unsigned gpu_id
)
974 instr_cat6_a6xx_t
*cat6
= &instr
->cat6_a6xx
;
976 /* At least one of these two bits is pad in all the possible
977 * "legacy" cat6 encodings, and a analysis of all the pre-a6xx
978 * cmdstream traces I have indicates that the pad bit is zero
979 * in all cases. So we can use this to detect new encoding:
981 if ((cat6
->pad3
& 0x8) && (cat6
->pad5
& 0x2)) {
982 assert(gpu_id
>= 600);
983 assert(instr
->cat6
.opc
== 0);
990 static inline uint32_t instr_opc(instr_t
*instr
, unsigned gpu_id
)
992 switch (instr
->opc_cat
) {
993 case 0: return instr
->cat0
.opc
| instr
->cat0
.opc_hi
<< 4;
995 case 2: return instr
->cat2
.opc
;
996 case 3: return instr
->cat3
.opc
;
997 case 4: return instr
->cat4
.opc
;
998 case 5: return instr
->cat5
.opc
;
1000 if (!is_cat6_legacy(instr
, gpu_id
))
1001 return instr
->cat6_a6xx
.opc
;
1002 return instr
->cat6
.opc
;
1003 case 7: return instr
->cat7
.opc
;
1008 static inline bool is_mad(opc_t opc
)
1023 static inline bool is_madsh(opc_t opc
)
1034 static inline bool is_atomic(opc_t opc
)
1037 case OPC_ATOMIC_ADD
:
1038 case OPC_ATOMIC_SUB
:
1039 case OPC_ATOMIC_XCHG
:
1040 case OPC_ATOMIC_INC
:
1041 case OPC_ATOMIC_DEC
:
1042 case OPC_ATOMIC_CMPXCHG
:
1043 case OPC_ATOMIC_MIN
:
1044 case OPC_ATOMIC_MAX
:
1045 case OPC_ATOMIC_AND
:
1047 case OPC_ATOMIC_XOR
:
1054 static inline bool is_ssbo(opc_t opc
)
1068 static inline bool is_isam(opc_t opc
)
1081 static inline bool is_cat2_float(opc_t opc
)
1104 static inline bool is_cat3_float(opc_t opc
)
1117 int disasm_a3xx(uint32_t *dwords
, int sizedwords
, int level
, FILE *out
, unsigned gpu_id
);
1119 #endif /* INSTR_A3XX_H_ */