0a7ab7316435e71cd1a11aad1261c0095f9d3baa
2 * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 #include "compiler/shader_enums.h"
32 #include "util/bitscan.h"
33 #include "util/list.h"
35 #include "util/u_debug.h"
37 #include "instr-a3xx.h"
39 /* low level intermediate representation of an adreno shader program */
43 struct ir3_instruction
;
47 void *data
; /* used internally in ir3 assembler */
49 uint16_t instrs_count
; /* expanded to account for rpt's */
50 uint16_t nops_count
; /* # of nop instructions, including nopN */
53 /* NOTE: max_reg, etc, does not include registers not touched
54 * by the shader (ie. vertex fetched via VFD_DECODE but not
57 int8_t max_reg
; /* highest GPR # used by shader */
61 /* number of sync bits: */
64 /* estimate of number of cycles stalled on (ss) */
67 uint16_t last_baryf
; /* instruction # of last varying fetch */
72 IR3_REG_CONST
= 0x001,
73 IR3_REG_IMMED
= 0x002,
75 /* high registers are used for some things in compute shaders,
76 * for example. Seems to be for things that are global to all
77 * threads in a wave, so possibly these are global/shared by
78 * all the threads in the wave?
81 IR3_REG_RELATIV
= 0x010,
83 /* Most instructions, it seems, can do float abs/neg but not
84 * integer. The CP pass needs to know what is intended (int or
85 * float) in order to do the right thing. For this reason the
86 * abs/neg flags are split out into float and int variants. In
87 * addition, .b (bitwise) operations, the negate is actually a
88 * bitwise not, so split that out into a new flag to make it
97 IR3_REG_POS_INF
= 0x1000,
98 /* (ei) flag, end-input? Set on last bary, presumably to signal
99 * that the shader needs no more input:
102 /* meta-flags, for intermediate stages of IR, ie.
103 * before register assignment is done:
105 IR3_REG_SSA
= 0x4000, /* 'instr' is ptr to assigning instr */
106 IR3_REG_ARRAY
= 0x8000,
110 /* used for cat5 instructions, but also for internal/IR level
111 * tracking of what registers are read/written by an instruction.
112 * wrmask may be a bad name since it is used to represent both
113 * src and dst that touch multiple adjacent registers.
115 unsigned wrmask
: 16; /* up to vec16 */
117 /* for relative addressing, 32bits for array size is too small,
118 * but otoh we don't need to deal with disjoint sets, so instead
119 * use a simple size field (number of scalar components).
121 * Note the size field isn't important for relative const (since
122 * we don't have to do register allocation for constants).
127 * the component is in the low two bits of the reg #, so
128 * rN.x becomes: (N << 2) | x
143 /* For IR3_REG_SSA, src registers contain ptr back to assigning
146 * For IR3_REG_ARRAY, the pointer is back to the last dependent
147 * array access (although the net effect is the same, it points
148 * back to a previous instruction that we depend on).
150 struct ir3_instruction
*instr
;
154 * Stupid/simple growable array implementation:
156 #define DECLARE_ARRAY(type, name) \
157 unsigned name ## _count, name ## _sz; \
160 #define array_insert(ctx, arr, val) do { \
161 if (arr ## _count == arr ## _sz) { \
162 arr ## _sz = MAX2(2 * arr ## _sz, 16); \
163 arr = reralloc_size(ctx, arr, arr ## _sz * sizeof(arr[0])); \
165 arr[arr ##_count++] = val; \
168 struct ir3_instruction
{
169 struct ir3_block
*block
;
172 /* (sy) flag is set on first instruction, and after sample
173 * instructions (probably just on RAW hazard).
175 IR3_INSTR_SY
= 0x001,
176 /* (ss) flag is set on first instruction, and first instruction
177 * to depend on the result of "long" instructions (RAW hazard):
179 * rcp, rsq, log2, exp2, sin, cos, sqrt
181 * It seems to synchronize until all in-flight instructions are
182 * completed, for example:
185 * add.f hr2.z, (neg)hr2.z, hc0.y
186 * mul.f hr2.w, (neg)hr2.y, (neg)hr2.y
189 * mad.f16 hr2.w, hr2.z, hr2.z, hr2.w
191 * mad.f16 hr2.w, (neg)hr0.w, (neg)hr0.w, hr2.w
192 * (ss)(rpt2)mul.f hr1.x, (r)hr1.x, hr1.w
193 * (rpt2)mul.f hr0.x, (neg)(r)hr0.x, hr2.x
195 * The last mul.f does not have (ss) set, presumably because the
196 * (ss) on the previous instruction does the job.
198 * The blob driver also seems to set it on WAR hazards, although
199 * not really clear if this is needed or just blob compiler being
200 * sloppy. So far I haven't found a case where removing the (ss)
201 * causes problems for WAR hazard, but I could just be getting
205 * (ss)(rpt2)mad.f32 r3.y, (r)c9.x, r1.x, (r)r3.z
208 IR3_INSTR_SS
= 0x002,
209 /* (jp) flag is set on jump targets:
211 IR3_INSTR_JP
= 0x004,
212 IR3_INSTR_UL
= 0x008,
213 IR3_INSTR_3D
= 0x010,
218 IR3_INSTR_S2EN
= 0x200,
220 IR3_INSTR_SAT
= 0x800,
221 /* (cat5/cat6) Bindless */
222 IR3_INSTR_B
= 0x1000,
223 /* (cat5-only) Get some parts of the encoding from a1.x */
224 IR3_INSTR_A1EN
= 0x2000,
225 /* meta-flags, for intermediate stages of IR, ie.
226 * before register assignment is done:
228 IR3_INSTR_MARK
= 0x4000,
229 IR3_INSTR_UNUSED
= 0x8000,
237 struct ir3_register
**regs
;
243 struct ir3_block
*target
;
246 type_t src_type
, dst_type
;
260 unsigned tex_base
: 3;
267 int iim_val
: 3; /* for ldgb/stgb, # of components */
268 unsigned d
: 3; /* for ldc, component offset */
273 unsigned w
: 1; /* write */
274 unsigned r
: 1; /* read */
275 unsigned l
: 1; /* local */
276 unsigned g
: 1; /* global */
278 /* for meta-instructions, just used to hold extra data
279 * before instruction scheduling, etc
282 int off
; /* component/offset */
285 /* for output collects, this maps back to the entry in the
286 * ir3_shader_variant::outputs table.
292 unsigned input_offset
;
293 unsigned samp_base
: 3;
294 unsigned tex_base
: 3;
297 /* maps back to entry in ir3_shader_variant::inputs table: */
299 /* for sysvals, identifies the sysval type. Mostly so we can
300 * identify the special cases where a sysval should not be DCE'd
301 * (currently, just pre-fs texture fetch)
303 gl_system_value sysval
;
307 /* When we get to the RA stage, we need instruction's position/name: */
311 /* used for per-pass extra instruction data.
313 * TODO we should remove the per-pass data like this and 'use_count'
314 * and do something similar to what RA does w/ ir3_ra_instr_data..
315 * ie. use the ir3_count_instructions pass, and then use instr->ip
316 * to index into a table of pass-private data.
321 * Valid if pass calls ir3_find_ssa_uses().. see foreach_ssa_use()
325 int use_count
; /* currently just updated/used by cp */
327 /* Used during CP and RA stages. For collect and shader inputs/
328 * outputs where we need a sequence of consecutive registers,
329 * keep track of each src instructions left (ie 'n-1') and right
330 * (ie 'n+1') neighbor. The front-end must insert enough mov's
331 * to ensure that each instruction has at most one left and at
332 * most one right neighbor. During the copy-propagation pass,
333 * we only remove mov's when we can preserve this constraint.
334 * And during the RA stage, we use the neighbor information to
335 * allocate a block of registers in one shot.
337 * TODO: maybe just add something like:
338 * struct ir3_instruction_ref {
339 * struct ir3_instruction *instr;
343 * Or can we get away without the refcnt stuff? It seems like
344 * it should be overkill.. the problem is if, potentially after
345 * already eliminating some mov's, if you have a single mov that
346 * needs to be grouped with it's neighbors in two different
347 * places (ex. shader output and a collect).
350 struct ir3_instruction
*left
, *right
;
351 uint16_t left_cnt
, right_cnt
;
354 /* an instruction can reference at most one address register amongst
355 * it's src/dst registers. Beyond that, you need to insert mov's.
357 * NOTE: do not write this directly, use ir3_instr_set_address()
359 struct ir3_instruction
*address
;
361 /* Tracking for additional dependent instructions. Used to handle
362 * barriers, WAR hazards for arrays/SSBOs/etc.
364 DECLARE_ARRAY(struct ir3_instruction
*, deps
);
367 * From PoV of instruction scheduling, not execution (ie. ignores global/
368 * local distinction):
369 * shared image atomic SSBO everything
370 * barrier()/ - R/W R/W R/W R/W X
371 * groupMemoryBarrier()
372 * memoryBarrier() - R/W R/W
373 * (but only images declared coherent?)
374 * memoryBarrierAtomic() - R/W
375 * memoryBarrierBuffer() - R/W
376 * memoryBarrierImage() - R/W
377 * memoryBarrierShared() - R/W
379 * TODO I think for SSBO/image/shared, in cases where we can determine
380 * which variable is accessed, we don't need to care about accesses to
381 * different variables (unless declared coherent??)
384 IR3_BARRIER_EVERYTHING
= 1 << 0,
385 IR3_BARRIER_SHARED_R
= 1 << 1,
386 IR3_BARRIER_SHARED_W
= 1 << 2,
387 IR3_BARRIER_IMAGE_R
= 1 << 3,
388 IR3_BARRIER_IMAGE_W
= 1 << 4,
389 IR3_BARRIER_BUFFER_R
= 1 << 5,
390 IR3_BARRIER_BUFFER_W
= 1 << 6,
391 IR3_BARRIER_ARRAY_R
= 1 << 7,
392 IR3_BARRIER_ARRAY_W
= 1 << 8,
393 } barrier_class
, barrier_conflict
;
395 /* Entry in ir3_block's instruction list: */
396 struct list_head node
;
402 // TODO only computerator/assembler:
406 static inline struct ir3_instruction
*
407 ir3_neighbor_first(struct ir3_instruction
*instr
)
410 while (instr
->cp
.left
) {
411 instr
= instr
->cp
.left
;
412 if (++cnt
> 0xffff) {
420 static inline int ir3_neighbor_count(struct ir3_instruction
*instr
)
424 debug_assert(!instr
->cp
.left
);
426 while (instr
->cp
.right
) {
428 instr
= instr
->cp
.right
;
439 struct ir3_compiler
*compiler
;
440 gl_shader_stage type
;
442 DECLARE_ARRAY(struct ir3_instruction
*, inputs
);
443 DECLARE_ARRAY(struct ir3_instruction
*, outputs
);
445 /* Track bary.f (and ldlv) instructions.. this is needed in
446 * scheduling to ensure that all varying fetches happen before
447 * any potential kill instructions. The hw gets grumpy if all
448 * threads in a group are killed before the last bary.f gets
449 * a chance to signal end of input (ei).
451 DECLARE_ARRAY(struct ir3_instruction
*, baryfs
);
453 /* Track all indirect instructions (read and write). To avoid
454 * deadlock scenario where an address register gets scheduled,
455 * but other dependent src instructions cannot be scheduled due
456 * to dependency on a *different* address register value, the
457 * scheduler needs to ensure that all dependencies other than
458 * the instruction other than the address register are scheduled
459 * before the one that writes the address register. Having a
460 * convenient list of instructions that reference some address
461 * register simplifies this.
463 DECLARE_ARRAY(struct ir3_instruction
*, a0_users
);
466 DECLARE_ARRAY(struct ir3_instruction
*, a1_users
);
468 /* and same for instructions that consume predicate register: */
469 DECLARE_ARRAY(struct ir3_instruction
*, predicates
);
471 /* Track texture sample instructions which need texture state
472 * patched in (for astc-srgb workaround):
474 DECLARE_ARRAY(struct ir3_instruction
*, astc_srgb
);
476 /* List of blocks: */
477 struct list_head block_list
;
479 /* List of ir3_array's: */
480 struct list_head array_list
;
483 unsigned block_count
, instr_count
;
488 struct list_head node
;
492 struct nir_register
*r
;
494 /* To avoid array write's from getting DCE'd, keep track of the
495 * most recent write. Any array access depends on the most
496 * recent write. This way, nothing depends on writes after the
497 * last read. But all the writes that happen before that have
498 * something depending on them
500 struct ir3_instruction
*last_write
;
502 /* extra stuff used in RA pass: */
503 unsigned base
; /* base vreg name */
504 unsigned reg
; /* base physical reg */
505 uint16_t start_ip
, end_ip
;
507 /* Indicates if half-precision */
513 struct ir3_array
* ir3_lookup_array(struct ir3
*ir
, unsigned id
);
516 struct list_head node
;
519 const struct nir_block
*nblock
;
521 struct list_head instr_list
; /* list of ir3_instruction */
523 /* each block has either one or two successors.. in case of
524 * two successors, 'condition' decides which one to follow.
525 * A block preceding an if/else has two successors.
527 struct ir3_instruction
*condition
;
528 struct ir3_block
*successors
[2];
530 struct set
*predecessors
; /* set of ir3_block */
532 uint16_t start_ip
, end_ip
;
534 /* Track instructions which do not write a register but other-
535 * wise must not be discarded (such as kill, stg, etc)
537 DECLARE_ARRAY(struct ir3_instruction
*, keeps
);
539 /* used for per-pass extra block data. Mainly used right
540 * now in RA step to track livein/liveout.
549 static inline uint32_t
550 block_id(struct ir3_block
*block
)
553 return block
->serialno
;
555 return (uint32_t)(unsigned long)block
;
559 struct ir3_shader_variant
;
561 struct ir3
* ir3_create(struct ir3_compiler
*compiler
, struct ir3_shader_variant
*v
);
562 void ir3_destroy(struct ir3
*shader
);
564 void * ir3_assemble(struct ir3_shader_variant
*v
);
565 void * ir3_alloc(struct ir3
*shader
, int sz
);
567 struct ir3_block
* ir3_block_create(struct ir3
*shader
);
569 struct ir3_instruction
* ir3_instr_create(struct ir3_block
*block
, opc_t opc
);
570 struct ir3_instruction
* ir3_instr_create2(struct ir3_block
*block
,
571 opc_t opc
, int nreg
);
572 struct ir3_instruction
* ir3_instr_clone(struct ir3_instruction
*instr
);
573 void ir3_instr_add_dep(struct ir3_instruction
*instr
, struct ir3_instruction
*dep
);
574 const char *ir3_instr_name(struct ir3_instruction
*instr
);
576 struct ir3_register
* ir3_reg_create(struct ir3_instruction
*instr
,
578 struct ir3_register
* ir3_reg_clone(struct ir3
*shader
,
579 struct ir3_register
*reg
);
581 void ir3_instr_set_address(struct ir3_instruction
*instr
,
582 struct ir3_instruction
*addr
);
584 static inline bool ir3_instr_check_mark(struct ir3_instruction
*instr
)
586 if (instr
->flags
& IR3_INSTR_MARK
)
587 return true; /* already visited */
588 instr
->flags
|= IR3_INSTR_MARK
;
592 void ir3_block_clear_mark(struct ir3_block
*block
);
593 void ir3_clear_mark(struct ir3
*shader
);
595 unsigned ir3_count_instructions(struct ir3
*ir
);
596 unsigned ir3_count_instructions_ra(struct ir3
*ir
);
599 * Move 'instr' to just before 'after'
602 ir3_instr_move_before(struct ir3_instruction
*instr
,
603 struct ir3_instruction
*after
)
605 list_delinit(&instr
->node
);
606 list_addtail(&instr
->node
, &after
->node
);
610 * Move 'instr' to just after 'before':
613 ir3_instr_move_after(struct ir3_instruction
*instr
,
614 struct ir3_instruction
*before
)
616 list_delinit(&instr
->node
);
617 list_add(&instr
->node
, &before
->node
);
620 void ir3_find_ssa_uses(struct ir3
*ir
, void *mem_ctx
, bool falsedeps
);
622 void ir3_set_dst_type(struct ir3_instruction
*instr
, bool half
);
623 void ir3_fixup_src_type(struct ir3_instruction
*instr
);
625 bool ir3_valid_flags(struct ir3_instruction
*instr
, unsigned n
, unsigned flags
);
627 #include "util/set.h"
628 #define foreach_ssa_use(__use, __instr) \
629 for (struct ir3_instruction *__use = (void *)~0; \
630 __use && (__instr)->uses; __use = NULL) \
631 set_foreach ((__instr)->uses, __entry) \
632 if ((__use = (void *)__entry->key))
634 static inline uint32_t reg_num(struct ir3_register
*reg
)
636 return reg
->num
>> 2;
639 static inline uint32_t reg_comp(struct ir3_register
*reg
)
641 return reg
->num
& 0x3;
644 static inline bool is_flow(struct ir3_instruction
*instr
)
646 return (opc_cat(instr
->opc
) == 0);
649 static inline bool is_kill(struct ir3_instruction
*instr
)
651 return instr
->opc
== OPC_KILL
;
654 static inline bool is_nop(struct ir3_instruction
*instr
)
656 return instr
->opc
== OPC_NOP
;
659 static inline bool is_same_type_reg(struct ir3_register
*reg1
,
660 struct ir3_register
*reg2
)
662 unsigned type_reg1
= (reg1
->flags
& (IR3_REG_HIGH
| IR3_REG_HALF
));
663 unsigned type_reg2
= (reg2
->flags
& (IR3_REG_HIGH
| IR3_REG_HALF
));
665 if (type_reg1
^ type_reg2
)
671 /* Is it a non-transformative (ie. not type changing) mov? This can
672 * also include absneg.s/absneg.f, which for the most part can be
673 * treated as a mov (single src argument).
675 static inline bool is_same_type_mov(struct ir3_instruction
*instr
)
677 struct ir3_register
*dst
;
679 switch (instr
->opc
) {
681 if (instr
->cat1
.src_type
!= instr
->cat1
.dst_type
)
683 /* If the type of dest reg and src reg are different,
684 * it shouldn't be considered as same type mov
686 if (!is_same_type_reg(instr
->regs
[0], instr
->regs
[1]))
691 if (instr
->flags
& IR3_INSTR_SAT
)
693 /* If the type of dest reg and src reg are different,
694 * it shouldn't be considered as same type mov
696 if (!is_same_type_reg(instr
->regs
[0], instr
->regs
[1]))
703 dst
= instr
->regs
[0];
705 /* mov's that write to a0 or p0.x are special: */
706 if (dst
->num
== regid(REG_P0
, 0))
708 if (reg_num(dst
) == REG_A0
)
711 if (dst
->flags
& (IR3_REG_RELATIV
| IR3_REG_ARRAY
))
717 /* A move from const, which changes size but not type, can also be
718 * folded into dest instruction in some cases.
720 static inline bool is_const_mov(struct ir3_instruction
*instr
)
722 if (instr
->opc
!= OPC_MOV
)
725 if (!(instr
->regs
[1]->flags
& IR3_REG_CONST
))
728 type_t src_type
= instr
->cat1
.src_type
;
729 type_t dst_type
= instr
->cat1
.dst_type
;
731 return (type_float(src_type
) && type_float(dst_type
)) ||
732 (type_uint(src_type
) && type_uint(dst_type
)) ||
733 (type_sint(src_type
) && type_sint(dst_type
));
736 static inline bool is_alu(struct ir3_instruction
*instr
)
738 return (1 <= opc_cat(instr
->opc
)) && (opc_cat(instr
->opc
) <= 3);
741 static inline bool is_sfu(struct ir3_instruction
*instr
)
743 return (opc_cat(instr
->opc
) == 4);
746 static inline bool is_tex(struct ir3_instruction
*instr
)
748 return (opc_cat(instr
->opc
) == 5);
751 static inline bool is_tex_or_prefetch(struct ir3_instruction
*instr
)
753 return is_tex(instr
) || (instr
->opc
== OPC_META_TEX_PREFETCH
);
756 static inline bool is_mem(struct ir3_instruction
*instr
)
758 return (opc_cat(instr
->opc
) == 6);
761 static inline bool is_barrier(struct ir3_instruction
*instr
)
763 return (opc_cat(instr
->opc
) == 7);
767 is_half(struct ir3_instruction
*instr
)
769 return !!(instr
->regs
[0]->flags
& IR3_REG_HALF
);
773 is_high(struct ir3_instruction
*instr
)
775 return !!(instr
->regs
[0]->flags
& IR3_REG_HIGH
);
779 is_store(struct ir3_instruction
*instr
)
781 /* these instructions, the "destination" register is
782 * actually a source, the address to store to.
784 switch (instr
->opc
) {
799 static inline bool is_load(struct ir3_instruction
*instr
)
801 switch (instr
->opc
) {
811 /* probably some others too.. */
818 static inline bool is_input(struct ir3_instruction
*instr
)
820 /* in some cases, ldlv is used to fetch varying without
821 * interpolation.. fortunately inloc is the first src
822 * register in either case
824 switch (instr
->opc
) {
833 static inline bool is_bool(struct ir3_instruction
*instr
)
835 switch (instr
->opc
) {
846 cat3_half_opc(opc_t opc
)
849 case OPC_MAD_F32
: return OPC_MAD_F16
;
850 case OPC_SEL_B32
: return OPC_SEL_B16
;
851 case OPC_SEL_S32
: return OPC_SEL_S16
;
852 case OPC_SEL_F32
: return OPC_SEL_F16
;
853 case OPC_SAD_S32
: return OPC_SAD_S16
;
859 cat3_full_opc(opc_t opc
)
862 case OPC_MAD_F16
: return OPC_MAD_F32
;
863 case OPC_SEL_B16
: return OPC_SEL_B32
;
864 case OPC_SEL_S16
: return OPC_SEL_S32
;
865 case OPC_SEL_F16
: return OPC_SEL_F32
;
866 case OPC_SAD_S16
: return OPC_SAD_S32
;
872 cat4_half_opc(opc_t opc
)
875 case OPC_RSQ
: return OPC_HRSQ
;
876 case OPC_LOG2
: return OPC_HLOG2
;
877 case OPC_EXP2
: return OPC_HEXP2
;
883 cat4_full_opc(opc_t opc
)
886 case OPC_HRSQ
: return OPC_RSQ
;
887 case OPC_HLOG2
: return OPC_LOG2
;
888 case OPC_HEXP2
: return OPC_EXP2
;
893 static inline bool is_meta(struct ir3_instruction
*instr
)
895 return (opc_cat(instr
->opc
) == -1);
898 static inline unsigned dest_regs(struct ir3_instruction
*instr
)
900 if ((instr
->regs_count
== 0) || is_store(instr
) || is_flow(instr
))
903 return util_last_bit(instr
->regs
[0]->wrmask
);
907 writes_gpr(struct ir3_instruction
*instr
)
909 if (dest_regs(instr
) == 0)
911 /* is dest a normal temp register: */
912 struct ir3_register
*reg
= instr
->regs
[0];
913 debug_assert(!(reg
->flags
& (IR3_REG_CONST
| IR3_REG_IMMED
)));
914 if ((reg_num(reg
) == REG_A0
) ||
915 (reg
->num
== regid(REG_P0
, 0)))
920 static inline bool writes_addr0(struct ir3_instruction
*instr
)
922 if (instr
->regs_count
> 0) {
923 struct ir3_register
*dst
= instr
->regs
[0];
924 return dst
->num
== regid(REG_A0
, 0);
929 static inline bool writes_addr1(struct ir3_instruction
*instr
)
931 if (instr
->regs_count
> 0) {
932 struct ir3_register
*dst
= instr
->regs
[0];
933 return dst
->num
== regid(REG_A0
, 1);
938 static inline bool writes_pred(struct ir3_instruction
*instr
)
940 if (instr
->regs_count
> 0) {
941 struct ir3_register
*dst
= instr
->regs
[0];
942 return reg_num(dst
) == REG_P0
;
947 /* returns defining instruction for reg */
948 /* TODO better name */
949 static inline struct ir3_instruction
*ssa(struct ir3_register
*reg
)
951 if (reg
->flags
& (IR3_REG_SSA
| IR3_REG_ARRAY
)) {
957 static inline bool conflicts(struct ir3_instruction
*a
,
958 struct ir3_instruction
*b
)
960 return (a
&& b
) && (a
!= b
);
963 static inline bool reg_gpr(struct ir3_register
*r
)
965 if (r
->flags
& (IR3_REG_CONST
| IR3_REG_IMMED
))
967 if ((reg_num(r
) == REG_A0
) || (reg_num(r
) == REG_P0
))
972 static inline type_t
half_type(type_t type
)
975 case TYPE_F32
: return TYPE_F16
;
976 case TYPE_U32
: return TYPE_U16
;
977 case TYPE_S32
: return TYPE_S16
;
988 static inline type_t
full_type(type_t type
)
991 case TYPE_F16
: return TYPE_F32
;
992 case TYPE_U16
: return TYPE_U32
;
993 case TYPE_S16
: return TYPE_S32
;
1004 /* some cat2 instructions (ie. those which are not float) can embed an
1007 static inline bool ir3_cat2_int(opc_t opc
)
1047 /* map cat2 instruction to valid abs/neg flags: */
1048 static inline unsigned ir3_cat2_absneg(opc_t opc
)
1065 return IR3_REG_FABS
| IR3_REG_FNEG
;
1086 return IR3_REG_SABS
| IR3_REG_SNEG
;
1100 return IR3_REG_BNOT
;
1107 /* map cat3 instructions to valid abs/neg flags: */
1108 static inline unsigned ir3_cat3_absneg(opc_t opc
)
1115 return IR3_REG_FNEG
;
1127 /* neg *may* work on 3rd src.. */
1137 #define MASK(n) ((1 << (n)) - 1)
1139 /* iterator for an instructions's sources (reg), also returns src #: */
1140 #define foreach_src_n(__srcreg, __n, __instr) \
1141 if ((__instr)->regs_count) \
1142 for (struct ir3_register *__srcreg = (void *)~0; __srcreg; __srcreg = NULL) \
1143 for (unsigned __cnt = (__instr)->regs_count - 1, __n = 0; __n < __cnt; __n++) \
1144 if ((__srcreg = (__instr)->regs[__n + 1]))
1146 /* iterator for an instructions's sources (reg): */
1147 #define foreach_src(__srcreg, __instr) \
1148 foreach_src_n(__srcreg, __i, __instr)
1150 static inline unsigned __ssa_src_cnt(struct ir3_instruction
*instr
)
1152 unsigned cnt
= instr
->regs_count
+ instr
->deps_count
;
1158 static inline struct ir3_instruction
**
1159 __ssa_srcp_n(struct ir3_instruction
*instr
, unsigned n
)
1161 if (n
== (instr
->regs_count
+ instr
->deps_count
))
1162 return &instr
->address
;
1163 if (n
>= instr
->regs_count
)
1164 return &instr
->deps
[n
- instr
->regs_count
];
1165 if (ssa(instr
->regs
[n
]))
1166 return &instr
->regs
[n
]->instr
;
1170 static inline bool __is_false_dep(struct ir3_instruction
*instr
, unsigned n
)
1172 if (n
== (instr
->regs_count
+ instr
->deps_count
))
1174 if (n
>= instr
->regs_count
)
1179 #define foreach_ssa_srcp_n(__srcp, __n, __instr) \
1180 for (struct ir3_instruction **__srcp = (void *)~0; __srcp; __srcp = NULL) \
1181 for (unsigned __cnt = __ssa_src_cnt(__instr), __n = 0; __n < __cnt; __n++) \
1182 if ((__srcp = __ssa_srcp_n(__instr, __n)))
1184 #define foreach_ssa_srcp(__srcp, __instr) \
1185 foreach_ssa_srcp_n(__srcp, __i, __instr)
1187 /* iterator for an instruction's SSA sources (instr), also returns src #: */
1188 #define foreach_ssa_src_n(__srcinst, __n, __instr) \
1189 for (struct ir3_instruction *__srcinst = (void *)~0; __srcinst; __srcinst = NULL) \
1190 foreach_ssa_srcp_n(__srcp, __n, __instr) \
1191 if ((__srcinst = *__srcp))
1193 /* iterator for an instruction's SSA sources (instr): */
1194 #define foreach_ssa_src(__srcinst, __instr) \
1195 foreach_ssa_src_n(__srcinst, __i, __instr)
1197 /* iterators for shader inputs: */
1198 #define foreach_input_n(__ininstr, __cnt, __ir) \
1199 for (struct ir3_instruction *__ininstr = (void *)~0; __ininstr; __ininstr = NULL) \
1200 for (unsigned __cnt = 0; __cnt < (__ir)->inputs_count; __cnt++) \
1201 if ((__ininstr = (__ir)->inputs[__cnt]))
1202 #define foreach_input(__ininstr, __ir) \
1203 foreach_input_n(__ininstr, __i, __ir)
1205 /* iterators for shader outputs: */
1206 #define foreach_output_n(__outinstr, __cnt, __ir) \
1207 for (struct ir3_instruction *__outinstr = (void *)~0; __outinstr; __outinstr = NULL) \
1208 for (unsigned __cnt = 0; __cnt < (__ir)->outputs_count; __cnt++) \
1209 if ((__outinstr = (__ir)->outputs[__cnt]))
1210 #define foreach_output(__outinstr, __ir) \
1211 foreach_output_n(__outinstr, __i, __ir)
1213 /* iterators for instructions: */
1214 #define foreach_instr(__instr, __list) \
1215 list_for_each_entry(struct ir3_instruction, __instr, __list, node)
1216 #define foreach_instr_rev(__instr, __list) \
1217 list_for_each_entry_rev(struct ir3_instruction, __instr, __list, node)
1218 #define foreach_instr_safe(__instr, __list) \
1219 list_for_each_entry_safe(struct ir3_instruction, __instr, __list, node)
1221 /* iterators for blocks: */
1222 #define foreach_block(__block, __list) \
1223 list_for_each_entry(struct ir3_block, __block, __list, node)
1224 #define foreach_block_safe(__block, __list) \
1225 list_for_each_entry_safe(struct ir3_block, __block, __list, node)
1226 #define foreach_block_rev(__block, __list) \
1227 list_for_each_entry_rev(struct ir3_block, __block, __list, node)
1229 /* iterators for arrays: */
1230 #define foreach_array(__array, __list) \
1231 list_for_each_entry(struct ir3_array, __array, __list, node)
1232 #define foreach_array_safe(__array, __list) \
1233 list_for_each_entry_safe(struct ir3_array, __array, __list, node)
1235 /* Check if condition is true for any src instruction.
1238 check_src_cond(struct ir3_instruction
*instr
, bool (*cond
)(struct ir3_instruction
*))
1240 /* Note that this is also used post-RA so skip the ssa iterator: */
1241 foreach_src (reg
, instr
) {
1242 struct ir3_instruction
*src
= reg
->instr
;
1247 /* meta:split/collect aren't real instructions, the thing that
1248 * we actually care about is *their* srcs
1250 if ((src
->opc
== OPC_META_SPLIT
) || (src
->opc
== OPC_META_COLLECT
)) {
1251 if (check_src_cond(src
, cond
))
1262 #define IR3_PASS(ir, pass, ...) ({ \
1263 bool progress = pass(ir, ##__VA_ARGS__); \
1265 ir3_debug_print(ir, "AFTER: " #pass); \
1272 void ir3_validate(struct ir3
*ir
);
1275 void ir3_print(struct ir3
*ir
);
1276 void ir3_print_instr(struct ir3_instruction
*instr
);
1278 /* delay calculation: */
1279 int ir3_delayslots(struct ir3_instruction
*assigner
,
1280 struct ir3_instruction
*consumer
, unsigned n
, bool soft
);
1281 unsigned ir3_delay_calc(struct ir3_block
*block
, struct ir3_instruction
*instr
,
1282 bool soft
, bool pred
);
1283 void ir3_remove_nops(struct ir3
*ir
);
1285 /* dead code elimination: */
1286 struct ir3_shader_variant
;
1287 bool ir3_dce(struct ir3
*ir
, struct ir3_shader_variant
*so
);
1289 /* fp16 conversion folding */
1290 bool ir3_cf(struct ir3
*ir
);
1292 /* copy-propagate: */
1293 bool ir3_cp(struct ir3
*ir
, struct ir3_shader_variant
*so
);
1294 bool ir3_cp_postsched(struct ir3
*ir
);
1296 /* group neighbors and insert mov's to resolve conflicts: */
1297 bool ir3_group(struct ir3
*ir
);
1300 bool ir3_sched_add_deps(struct ir3
*ir
);
1301 int ir3_sched(struct ir3
*ir
);
1304 bool ir3_postsched(struct ir3
*ir
, struct ir3_shader_variant
*v
);
1306 bool ir3_a6xx_fixup_atomic_dests(struct ir3
*ir
, struct ir3_shader_variant
*so
);
1308 /* register assignment: */
1309 struct ir3_ra_reg_set
* ir3_ra_alloc_reg_set(struct ir3_compiler
*compiler
, bool mergedregs
);
1310 int ir3_ra(struct ir3_shader_variant
*v
, struct ir3_instruction
**precolor
, unsigned nprecolor
);
1313 bool ir3_legalize(struct ir3
*ir
, struct ir3_shader_variant
*so
, int *max_bary
);
1316 ir3_has_latency_to_hide(struct ir3
*ir
)
1318 /* VS/GS/TCS/TESS co-exist with frag shader invocations, but we don't
1319 * know the nature of the fragment shader. Just assume it will have
1322 if (ir
->type
!= MESA_SHADER_FRAGMENT
)
1325 foreach_block (block
, &ir
->block_list
) {
1326 foreach_instr (instr
, &block
->instr_list
) {
1327 if (is_tex_or_prefetch(instr
))
1330 if (is_load(instr
)) {
1331 switch (instr
->opc
) {
1346 /* ************************************************************************* */
1347 /* instruction helpers */
1349 /* creates SSA src of correct type (ie. half vs full precision) */
1350 static inline struct ir3_register
* __ssa_src(struct ir3_instruction
*instr
,
1351 struct ir3_instruction
*src
, unsigned flags
)
1353 struct ir3_register
*reg
;
1354 if (src
->regs
[0]->flags
& IR3_REG_HALF
)
1355 flags
|= IR3_REG_HALF
;
1356 reg
= ir3_reg_create(instr
, 0, IR3_REG_SSA
| flags
);
1358 reg
->wrmask
= src
->regs
[0]->wrmask
;
1362 static inline struct ir3_register
* __ssa_dst(struct ir3_instruction
*instr
)
1364 struct ir3_register
*reg
= ir3_reg_create(instr
, 0, 0);
1365 reg
->flags
|= IR3_REG_SSA
;
1369 static inline struct ir3_instruction
*
1370 create_immed_typed(struct ir3_block
*block
, uint32_t val
, type_t type
)
1372 struct ir3_instruction
*mov
;
1373 unsigned flags
= (type_size(type
) < 32) ? IR3_REG_HALF
: 0;
1375 mov
= ir3_instr_create(block
, OPC_MOV
);
1376 mov
->cat1
.src_type
= type
;
1377 mov
->cat1
.dst_type
= type
;
1378 __ssa_dst(mov
)->flags
|= flags
;
1379 ir3_reg_create(mov
, 0, IR3_REG_IMMED
| flags
)->uim_val
= val
;
1384 static inline struct ir3_instruction
*
1385 create_immed(struct ir3_block
*block
, uint32_t val
)
1387 return create_immed_typed(block
, val
, TYPE_U32
);
1390 static inline struct ir3_instruction
*
1391 create_uniform_typed(struct ir3_block
*block
, unsigned n
, type_t type
)
1393 struct ir3_instruction
*mov
;
1394 unsigned flags
= (type_size(type
) < 32) ? IR3_REG_HALF
: 0;
1396 mov
= ir3_instr_create(block
, OPC_MOV
);
1397 mov
->cat1
.src_type
= type
;
1398 mov
->cat1
.dst_type
= type
;
1399 __ssa_dst(mov
)->flags
|= flags
;
1400 ir3_reg_create(mov
, n
, IR3_REG_CONST
| flags
);
1405 static inline struct ir3_instruction
*
1406 create_uniform(struct ir3_block
*block
, unsigned n
)
1408 return create_uniform_typed(block
, n
, TYPE_F32
);
1411 static inline struct ir3_instruction
*
1412 create_uniform_indirect(struct ir3_block
*block
, int n
,
1413 struct ir3_instruction
*address
)
1415 struct ir3_instruction
*mov
;
1417 mov
= ir3_instr_create(block
, OPC_MOV
);
1418 mov
->cat1
.src_type
= TYPE_U32
;
1419 mov
->cat1
.dst_type
= TYPE_U32
;
1421 ir3_reg_create(mov
, 0, IR3_REG_CONST
| IR3_REG_RELATIV
)->array
.offset
= n
;
1423 ir3_instr_set_address(mov
, address
);
1428 static inline struct ir3_instruction
*
1429 ir3_MOV(struct ir3_block
*block
, struct ir3_instruction
*src
, type_t type
)
1431 struct ir3_instruction
*instr
= ir3_instr_create(block
, OPC_MOV
);
1432 unsigned flags
= (type_size(type
) < 32) ? IR3_REG_HALF
: 0;
1434 __ssa_dst(instr
)->flags
|= flags
;
1435 if (src
->regs
[0]->flags
& IR3_REG_ARRAY
) {
1436 struct ir3_register
*src_reg
= __ssa_src(instr
, src
, IR3_REG_ARRAY
);
1437 src_reg
->array
= src
->regs
[0]->array
;
1439 __ssa_src(instr
, src
, src
->regs
[0]->flags
& IR3_REG_HIGH
);
1441 debug_assert(!(src
->regs
[0]->flags
& IR3_REG_RELATIV
));
1442 instr
->cat1
.src_type
= type
;
1443 instr
->cat1
.dst_type
= type
;
1447 static inline struct ir3_instruction
*
1448 ir3_COV(struct ir3_block
*block
, struct ir3_instruction
*src
,
1449 type_t src_type
, type_t dst_type
)
1451 struct ir3_instruction
*instr
= ir3_instr_create(block
, OPC_MOV
);
1452 unsigned dst_flags
= (type_size(dst_type
) < 32) ? IR3_REG_HALF
: 0;
1453 unsigned src_flags
= (type_size(src_type
) < 32) ? IR3_REG_HALF
: 0;
1455 debug_assert((src
->regs
[0]->flags
& IR3_REG_HALF
) == src_flags
);
1457 __ssa_dst(instr
)->flags
|= dst_flags
;
1458 __ssa_src(instr
, src
, 0);
1459 instr
->cat1
.src_type
= src_type
;
1460 instr
->cat1
.dst_type
= dst_type
;
1461 debug_assert(!(src
->regs
[0]->flags
& IR3_REG_ARRAY
));
1465 static inline struct ir3_instruction
*
1466 ir3_NOP(struct ir3_block
*block
)
1468 return ir3_instr_create(block
, OPC_NOP
);
1471 #define IR3_INSTR_0 0
1473 #define __INSTR0(flag, name, opc) \
1474 static inline struct ir3_instruction * \
1475 ir3_##name(struct ir3_block *block) \
1477 struct ir3_instruction *instr = \
1478 ir3_instr_create(block, opc); \
1479 instr->flags |= flag; \
1482 #define INSTR0F(f, name) __INSTR0(IR3_INSTR_##f, name##_##f, OPC_##name)
1483 #define INSTR0(name) __INSTR0(0, name, OPC_##name)
1485 #define __INSTR1(flag, name, opc) \
1486 static inline struct ir3_instruction * \
1487 ir3_##name(struct ir3_block *block, \
1488 struct ir3_instruction *a, unsigned aflags) \
1490 struct ir3_instruction *instr = \
1491 ir3_instr_create(block, opc); \
1493 __ssa_src(instr, a, aflags); \
1494 instr->flags |= flag; \
1497 #define INSTR1F(f, name) __INSTR1(IR3_INSTR_##f, name##_##f, OPC_##name)
1498 #define INSTR1(name) __INSTR1(0, name, OPC_##name)
1500 #define __INSTR2(flag, name, opc) \
1501 static inline struct ir3_instruction * \
1502 ir3_##name(struct ir3_block *block, \
1503 struct ir3_instruction *a, unsigned aflags, \
1504 struct ir3_instruction *b, unsigned bflags) \
1506 struct ir3_instruction *instr = \
1507 ir3_instr_create(block, opc); \
1509 __ssa_src(instr, a, aflags); \
1510 __ssa_src(instr, b, bflags); \
1511 instr->flags |= flag; \
1514 #define INSTR2F(f, name) __INSTR2(IR3_INSTR_##f, name##_##f, OPC_##name)
1515 #define INSTR2(name) __INSTR2(0, name, OPC_##name)
1517 #define __INSTR3(flag, name, opc) \
1518 static inline struct ir3_instruction * \
1519 ir3_##name(struct ir3_block *block, \
1520 struct ir3_instruction *a, unsigned aflags, \
1521 struct ir3_instruction *b, unsigned bflags, \
1522 struct ir3_instruction *c, unsigned cflags) \
1524 struct ir3_instruction *instr = \
1525 ir3_instr_create2(block, opc, 4); \
1527 __ssa_src(instr, a, aflags); \
1528 __ssa_src(instr, b, bflags); \
1529 __ssa_src(instr, c, cflags); \
1530 instr->flags |= flag; \
1533 #define INSTR3F(f, name) __INSTR3(IR3_INSTR_##f, name##_##f, OPC_##name)
1534 #define INSTR3(name) __INSTR3(0, name, OPC_##name)
1536 #define __INSTR4(flag, name, opc) \
1537 static inline struct ir3_instruction * \
1538 ir3_##name(struct ir3_block *block, \
1539 struct ir3_instruction *a, unsigned aflags, \
1540 struct ir3_instruction *b, unsigned bflags, \
1541 struct ir3_instruction *c, unsigned cflags, \
1542 struct ir3_instruction *d, unsigned dflags) \
1544 struct ir3_instruction *instr = \
1545 ir3_instr_create2(block, opc, 5); \
1547 __ssa_src(instr, a, aflags); \
1548 __ssa_src(instr, b, bflags); \
1549 __ssa_src(instr, c, cflags); \
1550 __ssa_src(instr, d, dflags); \
1551 instr->flags |= flag; \
1554 #define INSTR4F(f, name) __INSTR4(IR3_INSTR_##f, name##_##f, OPC_##name)
1555 #define INSTR4(name) __INSTR4(0, name, OPC_##name)
1557 /* cat0 instructions: */
1568 /* cat2 instructions, most 2 src but some 1 src: */
1616 /* cat3 instructions: */
1625 /* NOTE: SEL_B32 checks for zero vs nonzero */
1635 /* cat4 instructions: */
1647 /* cat5 instructions: */
1656 static inline struct ir3_instruction
*
1657 ir3_SAM(struct ir3_block
*block
, opc_t opc
, type_t type
,
1658 unsigned wrmask
, unsigned flags
, struct ir3_instruction
*samp_tex
,
1659 struct ir3_instruction
*src0
, struct ir3_instruction
*src1
)
1661 struct ir3_instruction
*sam
;
1663 sam
= ir3_instr_create(block
, opc
);
1664 sam
->flags
|= flags
;
1665 __ssa_dst(sam
)->wrmask
= wrmask
;
1666 if (flags
& IR3_INSTR_S2EN
) {
1667 __ssa_src(sam
, samp_tex
, (flags
& IR3_INSTR_B
) ? 0 : IR3_REG_HALF
);
1670 __ssa_src(sam
, src0
, 0);
1673 __ssa_src(sam
, src1
, 0);
1675 sam
->cat5
.type
= type
;
1680 /* cat6 instructions: */
1695 INSTR2(ATOMIC_CMPXCHG
)
1705 INSTR3F(G
, ATOMIC_ADD
)
1706 INSTR3F(G
, ATOMIC_SUB
)
1707 INSTR3F(G
, ATOMIC_XCHG
)
1708 INSTR3F(G
, ATOMIC_INC
)
1709 INSTR3F(G
, ATOMIC_DEC
)
1710 INSTR3F(G
, ATOMIC_CMPXCHG
)
1711 INSTR3F(G
, ATOMIC_MIN
)
1712 INSTR3F(G
, ATOMIC_MAX
)
1713 INSTR3F(G
, ATOMIC_AND
)
1714 INSTR3F(G
, ATOMIC_OR
)
1715 INSTR3F(G
, ATOMIC_XOR
)
1720 INSTR4F(G
, ATOMIC_ADD
)
1721 INSTR4F(G
, ATOMIC_SUB
)
1722 INSTR4F(G
, ATOMIC_XCHG
)
1723 INSTR4F(G
, ATOMIC_INC
)
1724 INSTR4F(G
, ATOMIC_DEC
)
1725 INSTR4F(G
, ATOMIC_CMPXCHG
)
1726 INSTR4F(G
, ATOMIC_MIN
)
1727 INSTR4F(G
, ATOMIC_MAX
)
1728 INSTR4F(G
, ATOMIC_AND
)
1729 INSTR4F(G
, ATOMIC_OR
)
1730 INSTR4F(G
, ATOMIC_XOR
)
1735 /* cat7 instructions: */
1739 /* meta instructions: */
1740 INSTR0(META_TEX_PREFETCH
);
1742 /* ************************************************************************* */
1743 #include "regmask.h"
1745 static inline void regmask_set(regmask_t
*regmask
, struct ir3_register
*reg
)
1747 bool half
= reg
->flags
& IR3_REG_HALF
;
1748 if (reg
->flags
& IR3_REG_RELATIV
) {
1749 for (unsigned i
= 0; i
< reg
->size
; i
++)
1750 __regmask_set(regmask
, half
, reg
->array
.offset
+ i
);
1752 for (unsigned mask
= reg
->wrmask
, n
= reg
->num
; mask
; mask
>>= 1, n
++)
1754 __regmask_set(regmask
, half
, n
);
1758 static inline bool regmask_get(regmask_t
*regmask
,
1759 struct ir3_register
*reg
)
1761 bool half
= reg
->flags
& IR3_REG_HALF
;
1762 if (reg
->flags
& IR3_REG_RELATIV
) {
1763 for (unsigned i
= 0; i
< reg
->size
; i
++)
1764 if (__regmask_get(regmask
, half
, reg
->array
.offset
+ i
))
1767 for (unsigned mask
= reg
->wrmask
, n
= reg
->num
; mask
; mask
>>= 1, n
++)
1769 if (__regmask_get(regmask
, half
, n
))
1774 /* ************************************************************************* */