0a7ab7316435e71cd1a11aad1261c0095f9d3baa
[mesa.git] / src / freedreno / ir3 / ir3.h
1 /*
2 * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #ifndef IR3_H_
25 #define IR3_H_
26
27 #include <stdint.h>
28 #include <stdbool.h>
29
30 #include "compiler/shader_enums.h"
31
32 #include "util/bitscan.h"
33 #include "util/list.h"
34 #include "util/set.h"
35 #include "util/u_debug.h"
36
37 #include "instr-a3xx.h"
38
39 /* low level intermediate representation of an adreno shader program */
40
41 struct ir3_compiler;
42 struct ir3;
43 struct ir3_instruction;
44 struct ir3_block;
45
46 struct ir3_info {
47 void *data; /* used internally in ir3 assembler */
48 uint16_t sizedwords;
49 uint16_t instrs_count; /* expanded to account for rpt's */
50 uint16_t nops_count; /* # of nop instructions, including nopN */
51 uint16_t mov_count;
52 uint16_t cov_count;
53 /* NOTE: max_reg, etc, does not include registers not touched
54 * by the shader (ie. vertex fetched via VFD_DECODE but not
55 * touched by shader)
56 */
57 int8_t max_reg; /* highest GPR # used by shader */
58 int8_t max_half_reg;
59 int16_t max_const;
60
61 /* number of sync bits: */
62 uint16_t ss, sy;
63
64 /* estimate of number of cycles stalled on (ss) */
65 uint16_t sstall;
66
67 uint16_t last_baryf; /* instruction # of last varying fetch */
68 };
69
70 struct ir3_register {
71 enum {
72 IR3_REG_CONST = 0x001,
73 IR3_REG_IMMED = 0x002,
74 IR3_REG_HALF = 0x004,
75 /* high registers are used for some things in compute shaders,
76 * for example. Seems to be for things that are global to all
77 * threads in a wave, so possibly these are global/shared by
78 * all the threads in the wave?
79 */
80 IR3_REG_HIGH = 0x008,
81 IR3_REG_RELATIV= 0x010,
82 IR3_REG_R = 0x020,
83 /* Most instructions, it seems, can do float abs/neg but not
84 * integer. The CP pass needs to know what is intended (int or
85 * float) in order to do the right thing. For this reason the
86 * abs/neg flags are split out into float and int variants. In
87 * addition, .b (bitwise) operations, the negate is actually a
88 * bitwise not, so split that out into a new flag to make it
89 * more clear.
90 */
91 IR3_REG_FNEG = 0x040,
92 IR3_REG_FABS = 0x080,
93 IR3_REG_SNEG = 0x100,
94 IR3_REG_SABS = 0x200,
95 IR3_REG_BNOT = 0x400,
96 IR3_REG_EVEN = 0x800,
97 IR3_REG_POS_INF= 0x1000,
98 /* (ei) flag, end-input? Set on last bary, presumably to signal
99 * that the shader needs no more input:
100 */
101 IR3_REG_EI = 0x2000,
102 /* meta-flags, for intermediate stages of IR, ie.
103 * before register assignment is done:
104 */
105 IR3_REG_SSA = 0x4000, /* 'instr' is ptr to assigning instr */
106 IR3_REG_ARRAY = 0x8000,
107
108 } flags;
109
110 /* used for cat5 instructions, but also for internal/IR level
111 * tracking of what registers are read/written by an instruction.
112 * wrmask may be a bad name since it is used to represent both
113 * src and dst that touch multiple adjacent registers.
114 */
115 unsigned wrmask : 16; /* up to vec16 */
116
117 /* for relative addressing, 32bits for array size is too small,
118 * but otoh we don't need to deal with disjoint sets, so instead
119 * use a simple size field (number of scalar components).
120 *
121 * Note the size field isn't important for relative const (since
122 * we don't have to do register allocation for constants).
123 */
124 unsigned size : 16;
125
126 /* normal registers:
127 * the component is in the low two bits of the reg #, so
128 * rN.x becomes: (N << 2) | x
129 */
130 uint16_t num;
131 union {
132 /* immediate: */
133 int32_t iim_val;
134 uint32_t uim_val;
135 float fim_val;
136 /* relative: */
137 struct {
138 uint16_t id;
139 int16_t offset;
140 } array;
141 };
142
143 /* For IR3_REG_SSA, src registers contain ptr back to assigning
144 * instruction.
145 *
146 * For IR3_REG_ARRAY, the pointer is back to the last dependent
147 * array access (although the net effect is the same, it points
148 * back to a previous instruction that we depend on).
149 */
150 struct ir3_instruction *instr;
151 };
152
153 /*
154 * Stupid/simple growable array implementation:
155 */
156 #define DECLARE_ARRAY(type, name) \
157 unsigned name ## _count, name ## _sz; \
158 type * name;
159
160 #define array_insert(ctx, arr, val) do { \
161 if (arr ## _count == arr ## _sz) { \
162 arr ## _sz = MAX2(2 * arr ## _sz, 16); \
163 arr = reralloc_size(ctx, arr, arr ## _sz * sizeof(arr[0])); \
164 } \
165 arr[arr ##_count++] = val; \
166 } while (0)
167
168 struct ir3_instruction {
169 struct ir3_block *block;
170 opc_t opc;
171 enum {
172 /* (sy) flag is set on first instruction, and after sample
173 * instructions (probably just on RAW hazard).
174 */
175 IR3_INSTR_SY = 0x001,
176 /* (ss) flag is set on first instruction, and first instruction
177 * to depend on the result of "long" instructions (RAW hazard):
178 *
179 * rcp, rsq, log2, exp2, sin, cos, sqrt
180 *
181 * It seems to synchronize until all in-flight instructions are
182 * completed, for example:
183 *
184 * rsq hr1.w, hr1.w
185 * add.f hr2.z, (neg)hr2.z, hc0.y
186 * mul.f hr2.w, (neg)hr2.y, (neg)hr2.y
187 * rsq hr2.x, hr2.x
188 * (rpt1)nop
189 * mad.f16 hr2.w, hr2.z, hr2.z, hr2.w
190 * nop
191 * mad.f16 hr2.w, (neg)hr0.w, (neg)hr0.w, hr2.w
192 * (ss)(rpt2)mul.f hr1.x, (r)hr1.x, hr1.w
193 * (rpt2)mul.f hr0.x, (neg)(r)hr0.x, hr2.x
194 *
195 * The last mul.f does not have (ss) set, presumably because the
196 * (ss) on the previous instruction does the job.
197 *
198 * The blob driver also seems to set it on WAR hazards, although
199 * not really clear if this is needed or just blob compiler being
200 * sloppy. So far I haven't found a case where removing the (ss)
201 * causes problems for WAR hazard, but I could just be getting
202 * lucky:
203 *
204 * rcp r1.y, r3.y
205 * (ss)(rpt2)mad.f32 r3.y, (r)c9.x, r1.x, (r)r3.z
206 *
207 */
208 IR3_INSTR_SS = 0x002,
209 /* (jp) flag is set on jump targets:
210 */
211 IR3_INSTR_JP = 0x004,
212 IR3_INSTR_UL = 0x008,
213 IR3_INSTR_3D = 0x010,
214 IR3_INSTR_A = 0x020,
215 IR3_INSTR_O = 0x040,
216 IR3_INSTR_P = 0x080,
217 IR3_INSTR_S = 0x100,
218 IR3_INSTR_S2EN = 0x200,
219 IR3_INSTR_G = 0x400,
220 IR3_INSTR_SAT = 0x800,
221 /* (cat5/cat6) Bindless */
222 IR3_INSTR_B = 0x1000,
223 /* (cat5-only) Get some parts of the encoding from a1.x */
224 IR3_INSTR_A1EN = 0x2000,
225 /* meta-flags, for intermediate stages of IR, ie.
226 * before register assignment is done:
227 */
228 IR3_INSTR_MARK = 0x4000,
229 IR3_INSTR_UNUSED= 0x8000,
230 } flags;
231 uint8_t repeat;
232 uint8_t nop;
233 #ifdef DEBUG
234 unsigned regs_max;
235 #endif
236 unsigned regs_count;
237 struct ir3_register **regs;
238 union {
239 struct {
240 char inv;
241 char comp;
242 int immed;
243 struct ir3_block *target;
244 } cat0;
245 struct {
246 type_t src_type, dst_type;
247 } cat1;
248 struct {
249 enum {
250 IR3_COND_LT = 0,
251 IR3_COND_LE = 1,
252 IR3_COND_GT = 2,
253 IR3_COND_GE = 3,
254 IR3_COND_EQ = 4,
255 IR3_COND_NE = 5,
256 } condition;
257 } cat2;
258 struct {
259 unsigned samp, tex;
260 unsigned tex_base : 3;
261 type_t type;
262 } cat5;
263 struct {
264 type_t type;
265 int src_offset;
266 int dst_offset;
267 int iim_val : 3; /* for ldgb/stgb, # of components */
268 unsigned d : 3; /* for ldc, component offset */
269 bool typed : 1;
270 unsigned base : 3;
271 } cat6;
272 struct {
273 unsigned w : 1; /* write */
274 unsigned r : 1; /* read */
275 unsigned l : 1; /* local */
276 unsigned g : 1; /* global */
277 } cat7;
278 /* for meta-instructions, just used to hold extra data
279 * before instruction scheduling, etc
280 */
281 struct {
282 int off; /* component/offset */
283 } split;
284 struct {
285 /* for output collects, this maps back to the entry in the
286 * ir3_shader_variant::outputs table.
287 */
288 int outidx;
289 } collect;
290 struct {
291 unsigned samp, tex;
292 unsigned input_offset;
293 unsigned samp_base : 3;
294 unsigned tex_base : 3;
295 } prefetch;
296 struct {
297 /* maps back to entry in ir3_shader_variant::inputs table: */
298 int inidx;
299 /* for sysvals, identifies the sysval type. Mostly so we can
300 * identify the special cases where a sysval should not be DCE'd
301 * (currently, just pre-fs texture fetch)
302 */
303 gl_system_value sysval;
304 } input;
305 };
306
307 /* When we get to the RA stage, we need instruction's position/name: */
308 uint16_t ip;
309 uint16_t name;
310
311 /* used for per-pass extra instruction data.
312 *
313 * TODO we should remove the per-pass data like this and 'use_count'
314 * and do something similar to what RA does w/ ir3_ra_instr_data..
315 * ie. use the ir3_count_instructions pass, and then use instr->ip
316 * to index into a table of pass-private data.
317 */
318 void *data;
319
320 /**
321 * Valid if pass calls ir3_find_ssa_uses().. see foreach_ssa_use()
322 */
323 struct set *uses;
324
325 int use_count; /* currently just updated/used by cp */
326
327 /* Used during CP and RA stages. For collect and shader inputs/
328 * outputs where we need a sequence of consecutive registers,
329 * keep track of each src instructions left (ie 'n-1') and right
330 * (ie 'n+1') neighbor. The front-end must insert enough mov's
331 * to ensure that each instruction has at most one left and at
332 * most one right neighbor. During the copy-propagation pass,
333 * we only remove mov's when we can preserve this constraint.
334 * And during the RA stage, we use the neighbor information to
335 * allocate a block of registers in one shot.
336 *
337 * TODO: maybe just add something like:
338 * struct ir3_instruction_ref {
339 * struct ir3_instruction *instr;
340 * unsigned cnt;
341 * }
342 *
343 * Or can we get away without the refcnt stuff? It seems like
344 * it should be overkill.. the problem is if, potentially after
345 * already eliminating some mov's, if you have a single mov that
346 * needs to be grouped with it's neighbors in two different
347 * places (ex. shader output and a collect).
348 */
349 struct {
350 struct ir3_instruction *left, *right;
351 uint16_t left_cnt, right_cnt;
352 } cp;
353
354 /* an instruction can reference at most one address register amongst
355 * it's src/dst registers. Beyond that, you need to insert mov's.
356 *
357 * NOTE: do not write this directly, use ir3_instr_set_address()
358 */
359 struct ir3_instruction *address;
360
361 /* Tracking for additional dependent instructions. Used to handle
362 * barriers, WAR hazards for arrays/SSBOs/etc.
363 */
364 DECLARE_ARRAY(struct ir3_instruction *, deps);
365
366 /*
367 * From PoV of instruction scheduling, not execution (ie. ignores global/
368 * local distinction):
369 * shared image atomic SSBO everything
370 * barrier()/ - R/W R/W R/W R/W X
371 * groupMemoryBarrier()
372 * memoryBarrier() - R/W R/W
373 * (but only images declared coherent?)
374 * memoryBarrierAtomic() - R/W
375 * memoryBarrierBuffer() - R/W
376 * memoryBarrierImage() - R/W
377 * memoryBarrierShared() - R/W
378 *
379 * TODO I think for SSBO/image/shared, in cases where we can determine
380 * which variable is accessed, we don't need to care about accesses to
381 * different variables (unless declared coherent??)
382 */
383 enum {
384 IR3_BARRIER_EVERYTHING = 1 << 0,
385 IR3_BARRIER_SHARED_R = 1 << 1,
386 IR3_BARRIER_SHARED_W = 1 << 2,
387 IR3_BARRIER_IMAGE_R = 1 << 3,
388 IR3_BARRIER_IMAGE_W = 1 << 4,
389 IR3_BARRIER_BUFFER_R = 1 << 5,
390 IR3_BARRIER_BUFFER_W = 1 << 6,
391 IR3_BARRIER_ARRAY_R = 1 << 7,
392 IR3_BARRIER_ARRAY_W = 1 << 8,
393 } barrier_class, barrier_conflict;
394
395 /* Entry in ir3_block's instruction list: */
396 struct list_head node;
397
398 #ifdef DEBUG
399 uint32_t serialno;
400 #endif
401
402 // TODO only computerator/assembler:
403 int line;
404 };
405
406 static inline struct ir3_instruction *
407 ir3_neighbor_first(struct ir3_instruction *instr)
408 {
409 int cnt = 0;
410 while (instr->cp.left) {
411 instr = instr->cp.left;
412 if (++cnt > 0xffff) {
413 debug_assert(0);
414 break;
415 }
416 }
417 return instr;
418 }
419
420 static inline int ir3_neighbor_count(struct ir3_instruction *instr)
421 {
422 int num = 1;
423
424 debug_assert(!instr->cp.left);
425
426 while (instr->cp.right) {
427 num++;
428 instr = instr->cp.right;
429 if (num > 0xffff) {
430 debug_assert(0);
431 break;
432 }
433 }
434
435 return num;
436 }
437
438 struct ir3 {
439 struct ir3_compiler *compiler;
440 gl_shader_stage type;
441
442 DECLARE_ARRAY(struct ir3_instruction *, inputs);
443 DECLARE_ARRAY(struct ir3_instruction *, outputs);
444
445 /* Track bary.f (and ldlv) instructions.. this is needed in
446 * scheduling to ensure that all varying fetches happen before
447 * any potential kill instructions. The hw gets grumpy if all
448 * threads in a group are killed before the last bary.f gets
449 * a chance to signal end of input (ei).
450 */
451 DECLARE_ARRAY(struct ir3_instruction *, baryfs);
452
453 /* Track all indirect instructions (read and write). To avoid
454 * deadlock scenario where an address register gets scheduled,
455 * but other dependent src instructions cannot be scheduled due
456 * to dependency on a *different* address register value, the
457 * scheduler needs to ensure that all dependencies other than
458 * the instruction other than the address register are scheduled
459 * before the one that writes the address register. Having a
460 * convenient list of instructions that reference some address
461 * register simplifies this.
462 */
463 DECLARE_ARRAY(struct ir3_instruction *, a0_users);
464
465 /* same for a1.x: */
466 DECLARE_ARRAY(struct ir3_instruction *, a1_users);
467
468 /* and same for instructions that consume predicate register: */
469 DECLARE_ARRAY(struct ir3_instruction *, predicates);
470
471 /* Track texture sample instructions which need texture state
472 * patched in (for astc-srgb workaround):
473 */
474 DECLARE_ARRAY(struct ir3_instruction *, astc_srgb);
475
476 /* List of blocks: */
477 struct list_head block_list;
478
479 /* List of ir3_array's: */
480 struct list_head array_list;
481
482 #ifdef DEBUG
483 unsigned block_count, instr_count;
484 #endif
485 };
486
487 struct ir3_array {
488 struct list_head node;
489 unsigned length;
490 unsigned id;
491
492 struct nir_register *r;
493
494 /* To avoid array write's from getting DCE'd, keep track of the
495 * most recent write. Any array access depends on the most
496 * recent write. This way, nothing depends on writes after the
497 * last read. But all the writes that happen before that have
498 * something depending on them
499 */
500 struct ir3_instruction *last_write;
501
502 /* extra stuff used in RA pass: */
503 unsigned base; /* base vreg name */
504 unsigned reg; /* base physical reg */
505 uint16_t start_ip, end_ip;
506
507 /* Indicates if half-precision */
508 bool half;
509
510 bool unused;
511 };
512
513 struct ir3_array * ir3_lookup_array(struct ir3 *ir, unsigned id);
514
515 struct ir3_block {
516 struct list_head node;
517 struct ir3 *shader;
518
519 const struct nir_block *nblock;
520
521 struct list_head instr_list; /* list of ir3_instruction */
522
523 /* each block has either one or two successors.. in case of
524 * two successors, 'condition' decides which one to follow.
525 * A block preceding an if/else has two successors.
526 */
527 struct ir3_instruction *condition;
528 struct ir3_block *successors[2];
529
530 struct set *predecessors; /* set of ir3_block */
531
532 uint16_t start_ip, end_ip;
533
534 /* Track instructions which do not write a register but other-
535 * wise must not be discarded (such as kill, stg, etc)
536 */
537 DECLARE_ARRAY(struct ir3_instruction *, keeps);
538
539 /* used for per-pass extra block data. Mainly used right
540 * now in RA step to track livein/liveout.
541 */
542 void *data;
543
544 #ifdef DEBUG
545 uint32_t serialno;
546 #endif
547 };
548
549 static inline uint32_t
550 block_id(struct ir3_block *block)
551 {
552 #ifdef DEBUG
553 return block->serialno;
554 #else
555 return (uint32_t)(unsigned long)block;
556 #endif
557 }
558
559 struct ir3_shader_variant;
560
561 struct ir3 * ir3_create(struct ir3_compiler *compiler, struct ir3_shader_variant *v);
562 void ir3_destroy(struct ir3 *shader);
563
564 void * ir3_assemble(struct ir3_shader_variant *v);
565 void * ir3_alloc(struct ir3 *shader, int sz);
566
567 struct ir3_block * ir3_block_create(struct ir3 *shader);
568
569 struct ir3_instruction * ir3_instr_create(struct ir3_block *block, opc_t opc);
570 struct ir3_instruction * ir3_instr_create2(struct ir3_block *block,
571 opc_t opc, int nreg);
572 struct ir3_instruction * ir3_instr_clone(struct ir3_instruction *instr);
573 void ir3_instr_add_dep(struct ir3_instruction *instr, struct ir3_instruction *dep);
574 const char *ir3_instr_name(struct ir3_instruction *instr);
575
576 struct ir3_register * ir3_reg_create(struct ir3_instruction *instr,
577 int num, int flags);
578 struct ir3_register * ir3_reg_clone(struct ir3 *shader,
579 struct ir3_register *reg);
580
581 void ir3_instr_set_address(struct ir3_instruction *instr,
582 struct ir3_instruction *addr);
583
584 static inline bool ir3_instr_check_mark(struct ir3_instruction *instr)
585 {
586 if (instr->flags & IR3_INSTR_MARK)
587 return true; /* already visited */
588 instr->flags |= IR3_INSTR_MARK;
589 return false;
590 }
591
592 void ir3_block_clear_mark(struct ir3_block *block);
593 void ir3_clear_mark(struct ir3 *shader);
594
595 unsigned ir3_count_instructions(struct ir3 *ir);
596 unsigned ir3_count_instructions_ra(struct ir3 *ir);
597
598 /**
599 * Move 'instr' to just before 'after'
600 */
601 static inline void
602 ir3_instr_move_before(struct ir3_instruction *instr,
603 struct ir3_instruction *after)
604 {
605 list_delinit(&instr->node);
606 list_addtail(&instr->node, &after->node);
607 }
608
609 /**
610 * Move 'instr' to just after 'before':
611 */
612 static inline void
613 ir3_instr_move_after(struct ir3_instruction *instr,
614 struct ir3_instruction *before)
615 {
616 list_delinit(&instr->node);
617 list_add(&instr->node, &before->node);
618 }
619
620 void ir3_find_ssa_uses(struct ir3 *ir, void *mem_ctx, bool falsedeps);
621
622 void ir3_set_dst_type(struct ir3_instruction *instr, bool half);
623 void ir3_fixup_src_type(struct ir3_instruction *instr);
624
625 bool ir3_valid_flags(struct ir3_instruction *instr, unsigned n, unsigned flags);
626
627 #include "util/set.h"
628 #define foreach_ssa_use(__use, __instr) \
629 for (struct ir3_instruction *__use = (void *)~0; \
630 __use && (__instr)->uses; __use = NULL) \
631 set_foreach ((__instr)->uses, __entry) \
632 if ((__use = (void *)__entry->key))
633
634 static inline uint32_t reg_num(struct ir3_register *reg)
635 {
636 return reg->num >> 2;
637 }
638
639 static inline uint32_t reg_comp(struct ir3_register *reg)
640 {
641 return reg->num & 0x3;
642 }
643
644 static inline bool is_flow(struct ir3_instruction *instr)
645 {
646 return (opc_cat(instr->opc) == 0);
647 }
648
649 static inline bool is_kill(struct ir3_instruction *instr)
650 {
651 return instr->opc == OPC_KILL;
652 }
653
654 static inline bool is_nop(struct ir3_instruction *instr)
655 {
656 return instr->opc == OPC_NOP;
657 }
658
659 static inline bool is_same_type_reg(struct ir3_register *reg1,
660 struct ir3_register *reg2)
661 {
662 unsigned type_reg1 = (reg1->flags & (IR3_REG_HIGH | IR3_REG_HALF));
663 unsigned type_reg2 = (reg2->flags & (IR3_REG_HIGH | IR3_REG_HALF));
664
665 if (type_reg1 ^ type_reg2)
666 return false;
667 else
668 return true;
669 }
670
671 /* Is it a non-transformative (ie. not type changing) mov? This can
672 * also include absneg.s/absneg.f, which for the most part can be
673 * treated as a mov (single src argument).
674 */
675 static inline bool is_same_type_mov(struct ir3_instruction *instr)
676 {
677 struct ir3_register *dst;
678
679 switch (instr->opc) {
680 case OPC_MOV:
681 if (instr->cat1.src_type != instr->cat1.dst_type)
682 return false;
683 /* If the type of dest reg and src reg are different,
684 * it shouldn't be considered as same type mov
685 */
686 if (!is_same_type_reg(instr->regs[0], instr->regs[1]))
687 return false;
688 break;
689 case OPC_ABSNEG_F:
690 case OPC_ABSNEG_S:
691 if (instr->flags & IR3_INSTR_SAT)
692 return false;
693 /* If the type of dest reg and src reg are different,
694 * it shouldn't be considered as same type mov
695 */
696 if (!is_same_type_reg(instr->regs[0], instr->regs[1]))
697 return false;
698 break;
699 default:
700 return false;
701 }
702
703 dst = instr->regs[0];
704
705 /* mov's that write to a0 or p0.x are special: */
706 if (dst->num == regid(REG_P0, 0))
707 return false;
708 if (reg_num(dst) == REG_A0)
709 return false;
710
711 if (dst->flags & (IR3_REG_RELATIV | IR3_REG_ARRAY))
712 return false;
713
714 return true;
715 }
716
717 /* A move from const, which changes size but not type, can also be
718 * folded into dest instruction in some cases.
719 */
720 static inline bool is_const_mov(struct ir3_instruction *instr)
721 {
722 if (instr->opc != OPC_MOV)
723 return false;
724
725 if (!(instr->regs[1]->flags & IR3_REG_CONST))
726 return false;
727
728 type_t src_type = instr->cat1.src_type;
729 type_t dst_type = instr->cat1.dst_type;
730
731 return (type_float(src_type) && type_float(dst_type)) ||
732 (type_uint(src_type) && type_uint(dst_type)) ||
733 (type_sint(src_type) && type_sint(dst_type));
734 }
735
736 static inline bool is_alu(struct ir3_instruction *instr)
737 {
738 return (1 <= opc_cat(instr->opc)) && (opc_cat(instr->opc) <= 3);
739 }
740
741 static inline bool is_sfu(struct ir3_instruction *instr)
742 {
743 return (opc_cat(instr->opc) == 4);
744 }
745
746 static inline bool is_tex(struct ir3_instruction *instr)
747 {
748 return (opc_cat(instr->opc) == 5);
749 }
750
751 static inline bool is_tex_or_prefetch(struct ir3_instruction *instr)
752 {
753 return is_tex(instr) || (instr->opc == OPC_META_TEX_PREFETCH);
754 }
755
756 static inline bool is_mem(struct ir3_instruction *instr)
757 {
758 return (opc_cat(instr->opc) == 6);
759 }
760
761 static inline bool is_barrier(struct ir3_instruction *instr)
762 {
763 return (opc_cat(instr->opc) == 7);
764 }
765
766 static inline bool
767 is_half(struct ir3_instruction *instr)
768 {
769 return !!(instr->regs[0]->flags & IR3_REG_HALF);
770 }
771
772 static inline bool
773 is_high(struct ir3_instruction *instr)
774 {
775 return !!(instr->regs[0]->flags & IR3_REG_HIGH);
776 }
777
778 static inline bool
779 is_store(struct ir3_instruction *instr)
780 {
781 /* these instructions, the "destination" register is
782 * actually a source, the address to store to.
783 */
784 switch (instr->opc) {
785 case OPC_STG:
786 case OPC_STGB:
787 case OPC_STIB:
788 case OPC_STP:
789 case OPC_STL:
790 case OPC_STLW:
791 case OPC_L2G:
792 case OPC_G2L:
793 return true;
794 default:
795 return false;
796 }
797 }
798
799 static inline bool is_load(struct ir3_instruction *instr)
800 {
801 switch (instr->opc) {
802 case OPC_LDG:
803 case OPC_LDGB:
804 case OPC_LDIB:
805 case OPC_LDL:
806 case OPC_LDP:
807 case OPC_L2G:
808 case OPC_LDLW:
809 case OPC_LDC:
810 case OPC_LDLV:
811 /* probably some others too.. */
812 return true;
813 default:
814 return false;
815 }
816 }
817
818 static inline bool is_input(struct ir3_instruction *instr)
819 {
820 /* in some cases, ldlv is used to fetch varying without
821 * interpolation.. fortunately inloc is the first src
822 * register in either case
823 */
824 switch (instr->opc) {
825 case OPC_LDLV:
826 case OPC_BARY_F:
827 return true;
828 default:
829 return false;
830 }
831 }
832
833 static inline bool is_bool(struct ir3_instruction *instr)
834 {
835 switch (instr->opc) {
836 case OPC_CMPS_F:
837 case OPC_CMPS_S:
838 case OPC_CMPS_U:
839 return true;
840 default:
841 return false;
842 }
843 }
844
845 static inline opc_t
846 cat3_half_opc(opc_t opc)
847 {
848 switch (opc) {
849 case OPC_MAD_F32: return OPC_MAD_F16;
850 case OPC_SEL_B32: return OPC_SEL_B16;
851 case OPC_SEL_S32: return OPC_SEL_S16;
852 case OPC_SEL_F32: return OPC_SEL_F16;
853 case OPC_SAD_S32: return OPC_SAD_S16;
854 default: return opc;
855 }
856 }
857
858 static inline opc_t
859 cat3_full_opc(opc_t opc)
860 {
861 switch (opc) {
862 case OPC_MAD_F16: return OPC_MAD_F32;
863 case OPC_SEL_B16: return OPC_SEL_B32;
864 case OPC_SEL_S16: return OPC_SEL_S32;
865 case OPC_SEL_F16: return OPC_SEL_F32;
866 case OPC_SAD_S16: return OPC_SAD_S32;
867 default: return opc;
868 }
869 }
870
871 static inline opc_t
872 cat4_half_opc(opc_t opc)
873 {
874 switch (opc) {
875 case OPC_RSQ: return OPC_HRSQ;
876 case OPC_LOG2: return OPC_HLOG2;
877 case OPC_EXP2: return OPC_HEXP2;
878 default: return opc;
879 }
880 }
881
882 static inline opc_t
883 cat4_full_opc(opc_t opc)
884 {
885 switch (opc) {
886 case OPC_HRSQ: return OPC_RSQ;
887 case OPC_HLOG2: return OPC_LOG2;
888 case OPC_HEXP2: return OPC_EXP2;
889 default: return opc;
890 }
891 }
892
893 static inline bool is_meta(struct ir3_instruction *instr)
894 {
895 return (opc_cat(instr->opc) == -1);
896 }
897
898 static inline unsigned dest_regs(struct ir3_instruction *instr)
899 {
900 if ((instr->regs_count == 0) || is_store(instr) || is_flow(instr))
901 return 0;
902
903 return util_last_bit(instr->regs[0]->wrmask);
904 }
905
906 static inline bool
907 writes_gpr(struct ir3_instruction *instr)
908 {
909 if (dest_regs(instr) == 0)
910 return false;
911 /* is dest a normal temp register: */
912 struct ir3_register *reg = instr->regs[0];
913 debug_assert(!(reg->flags & (IR3_REG_CONST | IR3_REG_IMMED)));
914 if ((reg_num(reg) == REG_A0) ||
915 (reg->num == regid(REG_P0, 0)))
916 return false;
917 return true;
918 }
919
920 static inline bool writes_addr0(struct ir3_instruction *instr)
921 {
922 if (instr->regs_count > 0) {
923 struct ir3_register *dst = instr->regs[0];
924 return dst->num == regid(REG_A0, 0);
925 }
926 return false;
927 }
928
929 static inline bool writes_addr1(struct ir3_instruction *instr)
930 {
931 if (instr->regs_count > 0) {
932 struct ir3_register *dst = instr->regs[0];
933 return dst->num == regid(REG_A0, 1);
934 }
935 return false;
936 }
937
938 static inline bool writes_pred(struct ir3_instruction *instr)
939 {
940 if (instr->regs_count > 0) {
941 struct ir3_register *dst = instr->regs[0];
942 return reg_num(dst) == REG_P0;
943 }
944 return false;
945 }
946
947 /* returns defining instruction for reg */
948 /* TODO better name */
949 static inline struct ir3_instruction *ssa(struct ir3_register *reg)
950 {
951 if (reg->flags & (IR3_REG_SSA | IR3_REG_ARRAY)) {
952 return reg->instr;
953 }
954 return NULL;
955 }
956
957 static inline bool conflicts(struct ir3_instruction *a,
958 struct ir3_instruction *b)
959 {
960 return (a && b) && (a != b);
961 }
962
963 static inline bool reg_gpr(struct ir3_register *r)
964 {
965 if (r->flags & (IR3_REG_CONST | IR3_REG_IMMED))
966 return false;
967 if ((reg_num(r) == REG_A0) || (reg_num(r) == REG_P0))
968 return false;
969 return true;
970 }
971
972 static inline type_t half_type(type_t type)
973 {
974 switch (type) {
975 case TYPE_F32: return TYPE_F16;
976 case TYPE_U32: return TYPE_U16;
977 case TYPE_S32: return TYPE_S16;
978 case TYPE_F16:
979 case TYPE_U16:
980 case TYPE_S16:
981 return type;
982 default:
983 assert(0);
984 return ~0;
985 }
986 }
987
988 static inline type_t full_type(type_t type)
989 {
990 switch (type) {
991 case TYPE_F16: return TYPE_F32;
992 case TYPE_U16: return TYPE_U32;
993 case TYPE_S16: return TYPE_S32;
994 case TYPE_F32:
995 case TYPE_U32:
996 case TYPE_S32:
997 return type;
998 default:
999 assert(0);
1000 return ~0;
1001 }
1002 }
1003
1004 /* some cat2 instructions (ie. those which are not float) can embed an
1005 * immediate:
1006 */
1007 static inline bool ir3_cat2_int(opc_t opc)
1008 {
1009 switch (opc) {
1010 case OPC_ADD_U:
1011 case OPC_ADD_S:
1012 case OPC_SUB_U:
1013 case OPC_SUB_S:
1014 case OPC_CMPS_U:
1015 case OPC_CMPS_S:
1016 case OPC_MIN_U:
1017 case OPC_MIN_S:
1018 case OPC_MAX_U:
1019 case OPC_MAX_S:
1020 case OPC_CMPV_U:
1021 case OPC_CMPV_S:
1022 case OPC_MUL_U24:
1023 case OPC_MUL_S24:
1024 case OPC_MULL_U:
1025 case OPC_CLZ_S:
1026 case OPC_ABSNEG_S:
1027 case OPC_AND_B:
1028 case OPC_OR_B:
1029 case OPC_NOT_B:
1030 case OPC_XOR_B:
1031 case OPC_BFREV_B:
1032 case OPC_CLZ_B:
1033 case OPC_SHL_B:
1034 case OPC_SHR_B:
1035 case OPC_ASHR_B:
1036 case OPC_MGEN_B:
1037 case OPC_GETBIT_B:
1038 case OPC_CBITS_B:
1039 case OPC_BARY_F:
1040 return true;
1041
1042 default:
1043 return false;
1044 }
1045 }
1046
1047 /* map cat2 instruction to valid abs/neg flags: */
1048 static inline unsigned ir3_cat2_absneg(opc_t opc)
1049 {
1050 switch (opc) {
1051 case OPC_ADD_F:
1052 case OPC_MIN_F:
1053 case OPC_MAX_F:
1054 case OPC_MUL_F:
1055 case OPC_SIGN_F:
1056 case OPC_CMPS_F:
1057 case OPC_ABSNEG_F:
1058 case OPC_CMPV_F:
1059 case OPC_FLOOR_F:
1060 case OPC_CEIL_F:
1061 case OPC_RNDNE_F:
1062 case OPC_RNDAZ_F:
1063 case OPC_TRUNC_F:
1064 case OPC_BARY_F:
1065 return IR3_REG_FABS | IR3_REG_FNEG;
1066
1067 case OPC_ADD_U:
1068 case OPC_ADD_S:
1069 case OPC_SUB_U:
1070 case OPC_SUB_S:
1071 case OPC_CMPS_U:
1072 case OPC_CMPS_S:
1073 case OPC_MIN_U:
1074 case OPC_MIN_S:
1075 case OPC_MAX_U:
1076 case OPC_MAX_S:
1077 case OPC_CMPV_U:
1078 case OPC_CMPV_S:
1079 case OPC_MUL_U24:
1080 case OPC_MUL_S24:
1081 case OPC_MULL_U:
1082 case OPC_CLZ_S:
1083 return 0;
1084
1085 case OPC_ABSNEG_S:
1086 return IR3_REG_SABS | IR3_REG_SNEG;
1087
1088 case OPC_AND_B:
1089 case OPC_OR_B:
1090 case OPC_NOT_B:
1091 case OPC_XOR_B:
1092 case OPC_BFREV_B:
1093 case OPC_CLZ_B:
1094 case OPC_SHL_B:
1095 case OPC_SHR_B:
1096 case OPC_ASHR_B:
1097 case OPC_MGEN_B:
1098 case OPC_GETBIT_B:
1099 case OPC_CBITS_B:
1100 return IR3_REG_BNOT;
1101
1102 default:
1103 return 0;
1104 }
1105 }
1106
1107 /* map cat3 instructions to valid abs/neg flags: */
1108 static inline unsigned ir3_cat3_absneg(opc_t opc)
1109 {
1110 switch (opc) {
1111 case OPC_MAD_F16:
1112 case OPC_MAD_F32:
1113 case OPC_SEL_F16:
1114 case OPC_SEL_F32:
1115 return IR3_REG_FNEG;
1116
1117 case OPC_MAD_U16:
1118 case OPC_MADSH_U16:
1119 case OPC_MAD_S16:
1120 case OPC_MADSH_M16:
1121 case OPC_MAD_U24:
1122 case OPC_MAD_S24:
1123 case OPC_SEL_S16:
1124 case OPC_SEL_S32:
1125 case OPC_SAD_S16:
1126 case OPC_SAD_S32:
1127 /* neg *may* work on 3rd src.. */
1128
1129 case OPC_SEL_B16:
1130 case OPC_SEL_B32:
1131
1132 default:
1133 return 0;
1134 }
1135 }
1136
1137 #define MASK(n) ((1 << (n)) - 1)
1138
1139 /* iterator for an instructions's sources (reg), also returns src #: */
1140 #define foreach_src_n(__srcreg, __n, __instr) \
1141 if ((__instr)->regs_count) \
1142 for (struct ir3_register *__srcreg = (void *)~0; __srcreg; __srcreg = NULL) \
1143 for (unsigned __cnt = (__instr)->regs_count - 1, __n = 0; __n < __cnt; __n++) \
1144 if ((__srcreg = (__instr)->regs[__n + 1]))
1145
1146 /* iterator for an instructions's sources (reg): */
1147 #define foreach_src(__srcreg, __instr) \
1148 foreach_src_n(__srcreg, __i, __instr)
1149
1150 static inline unsigned __ssa_src_cnt(struct ir3_instruction *instr)
1151 {
1152 unsigned cnt = instr->regs_count + instr->deps_count;
1153 if (instr->address)
1154 cnt++;
1155 return cnt;
1156 }
1157
1158 static inline struct ir3_instruction **
1159 __ssa_srcp_n(struct ir3_instruction *instr, unsigned n)
1160 {
1161 if (n == (instr->regs_count + instr->deps_count))
1162 return &instr->address;
1163 if (n >= instr->regs_count)
1164 return &instr->deps[n - instr->regs_count];
1165 if (ssa(instr->regs[n]))
1166 return &instr->regs[n]->instr;
1167 return NULL;
1168 }
1169
1170 static inline bool __is_false_dep(struct ir3_instruction *instr, unsigned n)
1171 {
1172 if (n == (instr->regs_count + instr->deps_count))
1173 return false;
1174 if (n >= instr->regs_count)
1175 return true;
1176 return false;
1177 }
1178
1179 #define foreach_ssa_srcp_n(__srcp, __n, __instr) \
1180 for (struct ir3_instruction **__srcp = (void *)~0; __srcp; __srcp = NULL) \
1181 for (unsigned __cnt = __ssa_src_cnt(__instr), __n = 0; __n < __cnt; __n++) \
1182 if ((__srcp = __ssa_srcp_n(__instr, __n)))
1183
1184 #define foreach_ssa_srcp(__srcp, __instr) \
1185 foreach_ssa_srcp_n(__srcp, __i, __instr)
1186
1187 /* iterator for an instruction's SSA sources (instr), also returns src #: */
1188 #define foreach_ssa_src_n(__srcinst, __n, __instr) \
1189 for (struct ir3_instruction *__srcinst = (void *)~0; __srcinst; __srcinst = NULL) \
1190 foreach_ssa_srcp_n(__srcp, __n, __instr) \
1191 if ((__srcinst = *__srcp))
1192
1193 /* iterator for an instruction's SSA sources (instr): */
1194 #define foreach_ssa_src(__srcinst, __instr) \
1195 foreach_ssa_src_n(__srcinst, __i, __instr)
1196
1197 /* iterators for shader inputs: */
1198 #define foreach_input_n(__ininstr, __cnt, __ir) \
1199 for (struct ir3_instruction *__ininstr = (void *)~0; __ininstr; __ininstr = NULL) \
1200 for (unsigned __cnt = 0; __cnt < (__ir)->inputs_count; __cnt++) \
1201 if ((__ininstr = (__ir)->inputs[__cnt]))
1202 #define foreach_input(__ininstr, __ir) \
1203 foreach_input_n(__ininstr, __i, __ir)
1204
1205 /* iterators for shader outputs: */
1206 #define foreach_output_n(__outinstr, __cnt, __ir) \
1207 for (struct ir3_instruction *__outinstr = (void *)~0; __outinstr; __outinstr = NULL) \
1208 for (unsigned __cnt = 0; __cnt < (__ir)->outputs_count; __cnt++) \
1209 if ((__outinstr = (__ir)->outputs[__cnt]))
1210 #define foreach_output(__outinstr, __ir) \
1211 foreach_output_n(__outinstr, __i, __ir)
1212
1213 /* iterators for instructions: */
1214 #define foreach_instr(__instr, __list) \
1215 list_for_each_entry(struct ir3_instruction, __instr, __list, node)
1216 #define foreach_instr_rev(__instr, __list) \
1217 list_for_each_entry_rev(struct ir3_instruction, __instr, __list, node)
1218 #define foreach_instr_safe(__instr, __list) \
1219 list_for_each_entry_safe(struct ir3_instruction, __instr, __list, node)
1220
1221 /* iterators for blocks: */
1222 #define foreach_block(__block, __list) \
1223 list_for_each_entry(struct ir3_block, __block, __list, node)
1224 #define foreach_block_safe(__block, __list) \
1225 list_for_each_entry_safe(struct ir3_block, __block, __list, node)
1226 #define foreach_block_rev(__block, __list) \
1227 list_for_each_entry_rev(struct ir3_block, __block, __list, node)
1228
1229 /* iterators for arrays: */
1230 #define foreach_array(__array, __list) \
1231 list_for_each_entry(struct ir3_array, __array, __list, node)
1232 #define foreach_array_safe(__array, __list) \
1233 list_for_each_entry_safe(struct ir3_array, __array, __list, node)
1234
1235 /* Check if condition is true for any src instruction.
1236 */
1237 static inline bool
1238 check_src_cond(struct ir3_instruction *instr, bool (*cond)(struct ir3_instruction *))
1239 {
1240 /* Note that this is also used post-RA so skip the ssa iterator: */
1241 foreach_src (reg, instr) {
1242 struct ir3_instruction *src = reg->instr;
1243
1244 if (!src)
1245 continue;
1246
1247 /* meta:split/collect aren't real instructions, the thing that
1248 * we actually care about is *their* srcs
1249 */
1250 if ((src->opc == OPC_META_SPLIT) || (src->opc == OPC_META_COLLECT)) {
1251 if (check_src_cond(src, cond))
1252 return true;
1253 } else {
1254 if (cond(src))
1255 return true;
1256 }
1257 }
1258
1259 return false;
1260 }
1261
1262 #define IR3_PASS(ir, pass, ...) ({ \
1263 bool progress = pass(ir, ##__VA_ARGS__); \
1264 if (progress) { \
1265 ir3_debug_print(ir, "AFTER: " #pass); \
1266 ir3_validate(ir); \
1267 } \
1268 progress; \
1269 })
1270
1271 /* validate: */
1272 void ir3_validate(struct ir3 *ir);
1273
1274 /* dump: */
1275 void ir3_print(struct ir3 *ir);
1276 void ir3_print_instr(struct ir3_instruction *instr);
1277
1278 /* delay calculation: */
1279 int ir3_delayslots(struct ir3_instruction *assigner,
1280 struct ir3_instruction *consumer, unsigned n, bool soft);
1281 unsigned ir3_delay_calc(struct ir3_block *block, struct ir3_instruction *instr,
1282 bool soft, bool pred);
1283 void ir3_remove_nops(struct ir3 *ir);
1284
1285 /* dead code elimination: */
1286 struct ir3_shader_variant;
1287 bool ir3_dce(struct ir3 *ir, struct ir3_shader_variant *so);
1288
1289 /* fp16 conversion folding */
1290 bool ir3_cf(struct ir3 *ir);
1291
1292 /* copy-propagate: */
1293 bool ir3_cp(struct ir3 *ir, struct ir3_shader_variant *so);
1294 bool ir3_cp_postsched(struct ir3 *ir);
1295
1296 /* group neighbors and insert mov's to resolve conflicts: */
1297 bool ir3_group(struct ir3 *ir);
1298
1299 /* scheduling: */
1300 bool ir3_sched_add_deps(struct ir3 *ir);
1301 int ir3_sched(struct ir3 *ir);
1302
1303 struct ir3_context;
1304 bool ir3_postsched(struct ir3 *ir, struct ir3_shader_variant *v);
1305
1306 bool ir3_a6xx_fixup_atomic_dests(struct ir3 *ir, struct ir3_shader_variant *so);
1307
1308 /* register assignment: */
1309 struct ir3_ra_reg_set * ir3_ra_alloc_reg_set(struct ir3_compiler *compiler, bool mergedregs);
1310 int ir3_ra(struct ir3_shader_variant *v, struct ir3_instruction **precolor, unsigned nprecolor);
1311
1312 /* legalize: */
1313 bool ir3_legalize(struct ir3 *ir, struct ir3_shader_variant *so, int *max_bary);
1314
1315 static inline bool
1316 ir3_has_latency_to_hide(struct ir3 *ir)
1317 {
1318 /* VS/GS/TCS/TESS co-exist with frag shader invocations, but we don't
1319 * know the nature of the fragment shader. Just assume it will have
1320 * latency to hide:
1321 */
1322 if (ir->type != MESA_SHADER_FRAGMENT)
1323 return true;
1324
1325 foreach_block (block, &ir->block_list) {
1326 foreach_instr (instr, &block->instr_list) {
1327 if (is_tex_or_prefetch(instr))
1328 return true;
1329
1330 if (is_load(instr)) {
1331 switch (instr->opc) {
1332 case OPC_LDLV:
1333 case OPC_LDL:
1334 case OPC_LDLW:
1335 break;
1336 default:
1337 return true;
1338 }
1339 }
1340 }
1341 }
1342
1343 return false;
1344 }
1345
1346 /* ************************************************************************* */
1347 /* instruction helpers */
1348
1349 /* creates SSA src of correct type (ie. half vs full precision) */
1350 static inline struct ir3_register * __ssa_src(struct ir3_instruction *instr,
1351 struct ir3_instruction *src, unsigned flags)
1352 {
1353 struct ir3_register *reg;
1354 if (src->regs[0]->flags & IR3_REG_HALF)
1355 flags |= IR3_REG_HALF;
1356 reg = ir3_reg_create(instr, 0, IR3_REG_SSA | flags);
1357 reg->instr = src;
1358 reg->wrmask = src->regs[0]->wrmask;
1359 return reg;
1360 }
1361
1362 static inline struct ir3_register * __ssa_dst(struct ir3_instruction *instr)
1363 {
1364 struct ir3_register *reg = ir3_reg_create(instr, 0, 0);
1365 reg->flags |= IR3_REG_SSA;
1366 return reg;
1367 }
1368
1369 static inline struct ir3_instruction *
1370 create_immed_typed(struct ir3_block *block, uint32_t val, type_t type)
1371 {
1372 struct ir3_instruction *mov;
1373 unsigned flags = (type_size(type) < 32) ? IR3_REG_HALF : 0;
1374
1375 mov = ir3_instr_create(block, OPC_MOV);
1376 mov->cat1.src_type = type;
1377 mov->cat1.dst_type = type;
1378 __ssa_dst(mov)->flags |= flags;
1379 ir3_reg_create(mov, 0, IR3_REG_IMMED | flags)->uim_val = val;
1380
1381 return mov;
1382 }
1383
1384 static inline struct ir3_instruction *
1385 create_immed(struct ir3_block *block, uint32_t val)
1386 {
1387 return create_immed_typed(block, val, TYPE_U32);
1388 }
1389
1390 static inline struct ir3_instruction *
1391 create_uniform_typed(struct ir3_block *block, unsigned n, type_t type)
1392 {
1393 struct ir3_instruction *mov;
1394 unsigned flags = (type_size(type) < 32) ? IR3_REG_HALF : 0;
1395
1396 mov = ir3_instr_create(block, OPC_MOV);
1397 mov->cat1.src_type = type;
1398 mov->cat1.dst_type = type;
1399 __ssa_dst(mov)->flags |= flags;
1400 ir3_reg_create(mov, n, IR3_REG_CONST | flags);
1401
1402 return mov;
1403 }
1404
1405 static inline struct ir3_instruction *
1406 create_uniform(struct ir3_block *block, unsigned n)
1407 {
1408 return create_uniform_typed(block, n, TYPE_F32);
1409 }
1410
1411 static inline struct ir3_instruction *
1412 create_uniform_indirect(struct ir3_block *block, int n,
1413 struct ir3_instruction *address)
1414 {
1415 struct ir3_instruction *mov;
1416
1417 mov = ir3_instr_create(block, OPC_MOV);
1418 mov->cat1.src_type = TYPE_U32;
1419 mov->cat1.dst_type = TYPE_U32;
1420 __ssa_dst(mov);
1421 ir3_reg_create(mov, 0, IR3_REG_CONST | IR3_REG_RELATIV)->array.offset = n;
1422
1423 ir3_instr_set_address(mov, address);
1424
1425 return mov;
1426 }
1427
1428 static inline struct ir3_instruction *
1429 ir3_MOV(struct ir3_block *block, struct ir3_instruction *src, type_t type)
1430 {
1431 struct ir3_instruction *instr = ir3_instr_create(block, OPC_MOV);
1432 unsigned flags = (type_size(type) < 32) ? IR3_REG_HALF : 0;
1433
1434 __ssa_dst(instr)->flags |= flags;
1435 if (src->regs[0]->flags & IR3_REG_ARRAY) {
1436 struct ir3_register *src_reg = __ssa_src(instr, src, IR3_REG_ARRAY);
1437 src_reg->array = src->regs[0]->array;
1438 } else {
1439 __ssa_src(instr, src, src->regs[0]->flags & IR3_REG_HIGH);
1440 }
1441 debug_assert(!(src->regs[0]->flags & IR3_REG_RELATIV));
1442 instr->cat1.src_type = type;
1443 instr->cat1.dst_type = type;
1444 return instr;
1445 }
1446
1447 static inline struct ir3_instruction *
1448 ir3_COV(struct ir3_block *block, struct ir3_instruction *src,
1449 type_t src_type, type_t dst_type)
1450 {
1451 struct ir3_instruction *instr = ir3_instr_create(block, OPC_MOV);
1452 unsigned dst_flags = (type_size(dst_type) < 32) ? IR3_REG_HALF : 0;
1453 unsigned src_flags = (type_size(src_type) < 32) ? IR3_REG_HALF : 0;
1454
1455 debug_assert((src->regs[0]->flags & IR3_REG_HALF) == src_flags);
1456
1457 __ssa_dst(instr)->flags |= dst_flags;
1458 __ssa_src(instr, src, 0);
1459 instr->cat1.src_type = src_type;
1460 instr->cat1.dst_type = dst_type;
1461 debug_assert(!(src->regs[0]->flags & IR3_REG_ARRAY));
1462 return instr;
1463 }
1464
1465 static inline struct ir3_instruction *
1466 ir3_NOP(struct ir3_block *block)
1467 {
1468 return ir3_instr_create(block, OPC_NOP);
1469 }
1470
1471 #define IR3_INSTR_0 0
1472
1473 #define __INSTR0(flag, name, opc) \
1474 static inline struct ir3_instruction * \
1475 ir3_##name(struct ir3_block *block) \
1476 { \
1477 struct ir3_instruction *instr = \
1478 ir3_instr_create(block, opc); \
1479 instr->flags |= flag; \
1480 return instr; \
1481 }
1482 #define INSTR0F(f, name) __INSTR0(IR3_INSTR_##f, name##_##f, OPC_##name)
1483 #define INSTR0(name) __INSTR0(0, name, OPC_##name)
1484
1485 #define __INSTR1(flag, name, opc) \
1486 static inline struct ir3_instruction * \
1487 ir3_##name(struct ir3_block *block, \
1488 struct ir3_instruction *a, unsigned aflags) \
1489 { \
1490 struct ir3_instruction *instr = \
1491 ir3_instr_create(block, opc); \
1492 __ssa_dst(instr); \
1493 __ssa_src(instr, a, aflags); \
1494 instr->flags |= flag; \
1495 return instr; \
1496 }
1497 #define INSTR1F(f, name) __INSTR1(IR3_INSTR_##f, name##_##f, OPC_##name)
1498 #define INSTR1(name) __INSTR1(0, name, OPC_##name)
1499
1500 #define __INSTR2(flag, name, opc) \
1501 static inline struct ir3_instruction * \
1502 ir3_##name(struct ir3_block *block, \
1503 struct ir3_instruction *a, unsigned aflags, \
1504 struct ir3_instruction *b, unsigned bflags) \
1505 { \
1506 struct ir3_instruction *instr = \
1507 ir3_instr_create(block, opc); \
1508 __ssa_dst(instr); \
1509 __ssa_src(instr, a, aflags); \
1510 __ssa_src(instr, b, bflags); \
1511 instr->flags |= flag; \
1512 return instr; \
1513 }
1514 #define INSTR2F(f, name) __INSTR2(IR3_INSTR_##f, name##_##f, OPC_##name)
1515 #define INSTR2(name) __INSTR2(0, name, OPC_##name)
1516
1517 #define __INSTR3(flag, name, opc) \
1518 static inline struct ir3_instruction * \
1519 ir3_##name(struct ir3_block *block, \
1520 struct ir3_instruction *a, unsigned aflags, \
1521 struct ir3_instruction *b, unsigned bflags, \
1522 struct ir3_instruction *c, unsigned cflags) \
1523 { \
1524 struct ir3_instruction *instr = \
1525 ir3_instr_create2(block, opc, 4); \
1526 __ssa_dst(instr); \
1527 __ssa_src(instr, a, aflags); \
1528 __ssa_src(instr, b, bflags); \
1529 __ssa_src(instr, c, cflags); \
1530 instr->flags |= flag; \
1531 return instr; \
1532 }
1533 #define INSTR3F(f, name) __INSTR3(IR3_INSTR_##f, name##_##f, OPC_##name)
1534 #define INSTR3(name) __INSTR3(0, name, OPC_##name)
1535
1536 #define __INSTR4(flag, name, opc) \
1537 static inline struct ir3_instruction * \
1538 ir3_##name(struct ir3_block *block, \
1539 struct ir3_instruction *a, unsigned aflags, \
1540 struct ir3_instruction *b, unsigned bflags, \
1541 struct ir3_instruction *c, unsigned cflags, \
1542 struct ir3_instruction *d, unsigned dflags) \
1543 { \
1544 struct ir3_instruction *instr = \
1545 ir3_instr_create2(block, opc, 5); \
1546 __ssa_dst(instr); \
1547 __ssa_src(instr, a, aflags); \
1548 __ssa_src(instr, b, bflags); \
1549 __ssa_src(instr, c, cflags); \
1550 __ssa_src(instr, d, dflags); \
1551 instr->flags |= flag; \
1552 return instr; \
1553 }
1554 #define INSTR4F(f, name) __INSTR4(IR3_INSTR_##f, name##_##f, OPC_##name)
1555 #define INSTR4(name) __INSTR4(0, name, OPC_##name)
1556
1557 /* cat0 instructions: */
1558 INSTR1(B)
1559 INSTR0(JUMP)
1560 INSTR1(KILL)
1561 INSTR0(END)
1562 INSTR0(CHSH)
1563 INSTR0(CHMASK)
1564 INSTR1(PREDT)
1565 INSTR0(PREDF)
1566 INSTR0(PREDE)
1567
1568 /* cat2 instructions, most 2 src but some 1 src: */
1569 INSTR2(ADD_F)
1570 INSTR2(MIN_F)
1571 INSTR2(MAX_F)
1572 INSTR2(MUL_F)
1573 INSTR1(SIGN_F)
1574 INSTR2(CMPS_F)
1575 INSTR1(ABSNEG_F)
1576 INSTR2(CMPV_F)
1577 INSTR1(FLOOR_F)
1578 INSTR1(CEIL_F)
1579 INSTR1(RNDNE_F)
1580 INSTR1(RNDAZ_F)
1581 INSTR1(TRUNC_F)
1582 INSTR2(ADD_U)
1583 INSTR2(ADD_S)
1584 INSTR2(SUB_U)
1585 INSTR2(SUB_S)
1586 INSTR2(CMPS_U)
1587 INSTR2(CMPS_S)
1588 INSTR2(MIN_U)
1589 INSTR2(MIN_S)
1590 INSTR2(MAX_U)
1591 INSTR2(MAX_S)
1592 INSTR1(ABSNEG_S)
1593 INSTR2(AND_B)
1594 INSTR2(OR_B)
1595 INSTR1(NOT_B)
1596 INSTR2(XOR_B)
1597 INSTR2(CMPV_U)
1598 INSTR2(CMPV_S)
1599 INSTR2(MUL_U24)
1600 INSTR2(MUL_S24)
1601 INSTR2(MULL_U)
1602 INSTR1(BFREV_B)
1603 INSTR1(CLZ_S)
1604 INSTR1(CLZ_B)
1605 INSTR2(SHL_B)
1606 INSTR2(SHR_B)
1607 INSTR2(ASHR_B)
1608 INSTR2(BARY_F)
1609 INSTR2(MGEN_B)
1610 INSTR2(GETBIT_B)
1611 INSTR1(SETRM)
1612 INSTR1(CBITS_B)
1613 INSTR2(SHB)
1614 INSTR2(MSAD)
1615
1616 /* cat3 instructions: */
1617 INSTR3(MAD_U16)
1618 INSTR3(MADSH_U16)
1619 INSTR3(MAD_S16)
1620 INSTR3(MADSH_M16)
1621 INSTR3(MAD_U24)
1622 INSTR3(MAD_S24)
1623 INSTR3(MAD_F16)
1624 INSTR3(MAD_F32)
1625 /* NOTE: SEL_B32 checks for zero vs nonzero */
1626 INSTR3(SEL_B16)
1627 INSTR3(SEL_B32)
1628 INSTR3(SEL_S16)
1629 INSTR3(SEL_S32)
1630 INSTR3(SEL_F16)
1631 INSTR3(SEL_F32)
1632 INSTR3(SAD_S16)
1633 INSTR3(SAD_S32)
1634
1635 /* cat4 instructions: */
1636 INSTR1(RCP)
1637 INSTR1(RSQ)
1638 INSTR1(HRSQ)
1639 INSTR1(LOG2)
1640 INSTR1(HLOG2)
1641 INSTR1(EXP2)
1642 INSTR1(HEXP2)
1643 INSTR1(SIN)
1644 INSTR1(COS)
1645 INSTR1(SQRT)
1646
1647 /* cat5 instructions: */
1648 INSTR1(DSX)
1649 INSTR1(DSXPP_MACRO)
1650 INSTR1(DSY)
1651 INSTR1(DSYPP_MACRO)
1652 INSTR1F(3D, DSX)
1653 INSTR1F(3D, DSY)
1654 INSTR1(RGETPOS)
1655
1656 static inline struct ir3_instruction *
1657 ir3_SAM(struct ir3_block *block, opc_t opc, type_t type,
1658 unsigned wrmask, unsigned flags, struct ir3_instruction *samp_tex,
1659 struct ir3_instruction *src0, struct ir3_instruction *src1)
1660 {
1661 struct ir3_instruction *sam;
1662
1663 sam = ir3_instr_create(block, opc);
1664 sam->flags |= flags;
1665 __ssa_dst(sam)->wrmask = wrmask;
1666 if (flags & IR3_INSTR_S2EN) {
1667 __ssa_src(sam, samp_tex, (flags & IR3_INSTR_B) ? 0 : IR3_REG_HALF);
1668 }
1669 if (src0) {
1670 __ssa_src(sam, src0, 0);
1671 }
1672 if (src1) {
1673 __ssa_src(sam, src1, 0);
1674 }
1675 sam->cat5.type = type;
1676
1677 return sam;
1678 }
1679
1680 /* cat6 instructions: */
1681 INSTR2(LDLV)
1682 INSTR3(LDG)
1683 INSTR3(LDL)
1684 INSTR3(LDLW)
1685 INSTR3(STG)
1686 INSTR3(STL)
1687 INSTR3(STLW)
1688 INSTR1(RESINFO)
1689 INSTR1(RESFMT)
1690 INSTR2(ATOMIC_ADD)
1691 INSTR2(ATOMIC_SUB)
1692 INSTR2(ATOMIC_XCHG)
1693 INSTR2(ATOMIC_INC)
1694 INSTR2(ATOMIC_DEC)
1695 INSTR2(ATOMIC_CMPXCHG)
1696 INSTR2(ATOMIC_MIN)
1697 INSTR2(ATOMIC_MAX)
1698 INSTR2(ATOMIC_AND)
1699 INSTR2(ATOMIC_OR)
1700 INSTR2(ATOMIC_XOR)
1701 INSTR2(LDC)
1702 #if GPU >= 600
1703 INSTR3(STIB);
1704 INSTR2(LDIB);
1705 INSTR3F(G, ATOMIC_ADD)
1706 INSTR3F(G, ATOMIC_SUB)
1707 INSTR3F(G, ATOMIC_XCHG)
1708 INSTR3F(G, ATOMIC_INC)
1709 INSTR3F(G, ATOMIC_DEC)
1710 INSTR3F(G, ATOMIC_CMPXCHG)
1711 INSTR3F(G, ATOMIC_MIN)
1712 INSTR3F(G, ATOMIC_MAX)
1713 INSTR3F(G, ATOMIC_AND)
1714 INSTR3F(G, ATOMIC_OR)
1715 INSTR3F(G, ATOMIC_XOR)
1716 #elif GPU >= 400
1717 INSTR3(LDGB)
1718 INSTR4(STGB)
1719 INSTR4(STIB)
1720 INSTR4F(G, ATOMIC_ADD)
1721 INSTR4F(G, ATOMIC_SUB)
1722 INSTR4F(G, ATOMIC_XCHG)
1723 INSTR4F(G, ATOMIC_INC)
1724 INSTR4F(G, ATOMIC_DEC)
1725 INSTR4F(G, ATOMIC_CMPXCHG)
1726 INSTR4F(G, ATOMIC_MIN)
1727 INSTR4F(G, ATOMIC_MAX)
1728 INSTR4F(G, ATOMIC_AND)
1729 INSTR4F(G, ATOMIC_OR)
1730 INSTR4F(G, ATOMIC_XOR)
1731 #endif
1732
1733 INSTR4F(G, STG)
1734
1735 /* cat7 instructions: */
1736 INSTR0(BAR)
1737 INSTR0(FENCE)
1738
1739 /* meta instructions: */
1740 INSTR0(META_TEX_PREFETCH);
1741
1742 /* ************************************************************************* */
1743 #include "regmask.h"
1744
1745 static inline void regmask_set(regmask_t *regmask, struct ir3_register *reg)
1746 {
1747 bool half = reg->flags & IR3_REG_HALF;
1748 if (reg->flags & IR3_REG_RELATIV) {
1749 for (unsigned i = 0; i < reg->size; i++)
1750 __regmask_set(regmask, half, reg->array.offset + i);
1751 } else {
1752 for (unsigned mask = reg->wrmask, n = reg->num; mask; mask >>= 1, n++)
1753 if (mask & 1)
1754 __regmask_set(regmask, half, n);
1755 }
1756 }
1757
1758 static inline bool regmask_get(regmask_t *regmask,
1759 struct ir3_register *reg)
1760 {
1761 bool half = reg->flags & IR3_REG_HALF;
1762 if (reg->flags & IR3_REG_RELATIV) {
1763 for (unsigned i = 0; i < reg->size; i++)
1764 if (__regmask_get(regmask, half, reg->array.offset + i))
1765 return true;
1766 } else {
1767 for (unsigned mask = reg->wrmask, n = reg->num; mask; mask >>= 1, n++)
1768 if (mask & 1)
1769 if (__regmask_get(regmask, half, n))
1770 return true;
1771 }
1772 return false;
1773 }
1774 /* ************************************************************************* */
1775
1776 #endif /* IR3_H_ */