2 * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 #include "compiler/shader_enums.h"
32 #include "util/bitscan.h"
33 #include "util/list.h"
35 #include "util/u_debug.h"
37 #include "instr-a3xx.h"
39 /* low level intermediate representation of an adreno shader program */
43 struct ir3_instruction
;
47 void *data
; /* used internally in ir3 assembler */
49 uint16_t instrs_count
; /* expanded to account for rpt's */
50 uint16_t nops_count
; /* # of nop instructions, including nopN */
53 /* NOTE: max_reg, etc, does not include registers not touched
54 * by the shader (ie. vertex fetched via VFD_DECODE but not
57 int8_t max_reg
; /* highest GPR # used by shader */
61 /* number of sync bits: */
64 /* estimate of number of cycles stalled on (ss) */
67 uint16_t last_baryf
; /* instruction # of last varying fetch */
69 /* Number of instructions of a given category: */
70 uint16_t instrs_per_cat
[8];
75 IR3_REG_CONST
= 0x001,
76 IR3_REG_IMMED
= 0x002,
78 /* high registers are used for some things in compute shaders,
79 * for example. Seems to be for things that are global to all
80 * threads in a wave, so possibly these are global/shared by
81 * all the threads in the wave?
84 IR3_REG_RELATIV
= 0x010,
86 /* Most instructions, it seems, can do float abs/neg but not
87 * integer. The CP pass needs to know what is intended (int or
88 * float) in order to do the right thing. For this reason the
89 * abs/neg flags are split out into float and int variants. In
90 * addition, .b (bitwise) operations, the negate is actually a
91 * bitwise not, so split that out into a new flag to make it
100 IR3_REG_POS_INF
= 0x1000,
101 /* (ei) flag, end-input? Set on last bary, presumably to signal
102 * that the shader needs no more input:
105 /* meta-flags, for intermediate stages of IR, ie.
106 * before register assignment is done:
108 IR3_REG_SSA
= 0x4000, /* 'instr' is ptr to assigning instr */
109 IR3_REG_ARRAY
= 0x8000,
113 /* used for cat5 instructions, but also for internal/IR level
114 * tracking of what registers are read/written by an instruction.
115 * wrmask may be a bad name since it is used to represent both
116 * src and dst that touch multiple adjacent registers.
118 unsigned wrmask
: 16; /* up to vec16 */
120 /* for relative addressing, 32bits for array size is too small,
121 * but otoh we don't need to deal with disjoint sets, so instead
122 * use a simple size field (number of scalar components).
124 * Note the size field isn't important for relative const (since
125 * we don't have to do register allocation for constants).
130 * the component is in the low two bits of the reg #, so
131 * rN.x becomes: (N << 2) | x
146 /* For IR3_REG_SSA, src registers contain ptr back to assigning
149 * For IR3_REG_ARRAY, the pointer is back to the last dependent
150 * array access (although the net effect is the same, it points
151 * back to a previous instruction that we depend on).
153 struct ir3_instruction
*instr
;
157 * Stupid/simple growable array implementation:
159 #define DECLARE_ARRAY(type, name) \
160 unsigned name ## _count, name ## _sz; \
163 #define array_insert(ctx, arr, val) do { \
164 if (arr ## _count == arr ## _sz) { \
165 arr ## _sz = MAX2(2 * arr ## _sz, 16); \
166 arr = reralloc_size(ctx, arr, arr ## _sz * sizeof(arr[0])); \
168 arr[arr ##_count++] = val; \
171 struct ir3_instruction
{
172 struct ir3_block
*block
;
175 /* (sy) flag is set on first instruction, and after sample
176 * instructions (probably just on RAW hazard).
178 IR3_INSTR_SY
= 0x001,
179 /* (ss) flag is set on first instruction, and first instruction
180 * to depend on the result of "long" instructions (RAW hazard):
182 * rcp, rsq, log2, exp2, sin, cos, sqrt
184 * It seems to synchronize until all in-flight instructions are
185 * completed, for example:
188 * add.f hr2.z, (neg)hr2.z, hc0.y
189 * mul.f hr2.w, (neg)hr2.y, (neg)hr2.y
192 * mad.f16 hr2.w, hr2.z, hr2.z, hr2.w
194 * mad.f16 hr2.w, (neg)hr0.w, (neg)hr0.w, hr2.w
195 * (ss)(rpt2)mul.f hr1.x, (r)hr1.x, hr1.w
196 * (rpt2)mul.f hr0.x, (neg)(r)hr0.x, hr2.x
198 * The last mul.f does not have (ss) set, presumably because the
199 * (ss) on the previous instruction does the job.
201 * The blob driver also seems to set it on WAR hazards, although
202 * not really clear if this is needed or just blob compiler being
203 * sloppy. So far I haven't found a case where removing the (ss)
204 * causes problems for WAR hazard, but I could just be getting
208 * (ss)(rpt2)mad.f32 r3.y, (r)c9.x, r1.x, (r)r3.z
211 IR3_INSTR_SS
= 0x002,
212 /* (jp) flag is set on jump targets:
214 IR3_INSTR_JP
= 0x004,
215 IR3_INSTR_UL
= 0x008,
216 IR3_INSTR_3D
= 0x010,
221 IR3_INSTR_S2EN
= 0x200,
223 IR3_INSTR_SAT
= 0x800,
224 /* (cat5/cat6) Bindless */
225 IR3_INSTR_B
= 0x1000,
226 /* (cat5-only) Get some parts of the encoding from a1.x */
227 IR3_INSTR_A1EN
= 0x2000,
228 /* meta-flags, for intermediate stages of IR, ie.
229 * before register assignment is done:
231 IR3_INSTR_MARK
= 0x4000,
232 IR3_INSTR_UNUSED
= 0x8000,
240 struct ir3_register
**regs
;
246 struct ir3_block
*target
;
249 type_t src_type
, dst_type
;
263 unsigned tex_base
: 3;
270 int iim_val
: 3; /* for ldgb/stgb, # of components */
271 unsigned d
: 3; /* for ldc, component offset */
276 unsigned w
: 1; /* write */
277 unsigned r
: 1; /* read */
278 unsigned l
: 1; /* local */
279 unsigned g
: 1; /* global */
281 /* for meta-instructions, just used to hold extra data
282 * before instruction scheduling, etc
285 int off
; /* component/offset */
288 /* for output collects, this maps back to the entry in the
289 * ir3_shader_variant::outputs table.
295 unsigned input_offset
;
296 unsigned samp_base
: 3;
297 unsigned tex_base
: 3;
300 /* maps back to entry in ir3_shader_variant::inputs table: */
302 /* for sysvals, identifies the sysval type. Mostly so we can
303 * identify the special cases where a sysval should not be DCE'd
304 * (currently, just pre-fs texture fetch)
306 gl_system_value sysval
;
310 /* When we get to the RA stage, we need instruction's position/name: */
314 /* used for per-pass extra instruction data.
316 * TODO we should remove the per-pass data like this and 'use_count'
317 * and do something similar to what RA does w/ ir3_ra_instr_data..
318 * ie. use the ir3_count_instructions pass, and then use instr->ip
319 * to index into a table of pass-private data.
324 * Valid if pass calls ir3_find_ssa_uses().. see foreach_ssa_use()
328 int use_count
; /* currently just updated/used by cp */
330 /* Used during CP and RA stages. For collect and shader inputs/
331 * outputs where we need a sequence of consecutive registers,
332 * keep track of each src instructions left (ie 'n-1') and right
333 * (ie 'n+1') neighbor. The front-end must insert enough mov's
334 * to ensure that each instruction has at most one left and at
335 * most one right neighbor. During the copy-propagation pass,
336 * we only remove mov's when we can preserve this constraint.
337 * And during the RA stage, we use the neighbor information to
338 * allocate a block of registers in one shot.
340 * TODO: maybe just add something like:
341 * struct ir3_instruction_ref {
342 * struct ir3_instruction *instr;
346 * Or can we get away without the refcnt stuff? It seems like
347 * it should be overkill.. the problem is if, potentially after
348 * already eliminating some mov's, if you have a single mov that
349 * needs to be grouped with it's neighbors in two different
350 * places (ex. shader output and a collect).
353 struct ir3_instruction
*left
, *right
;
354 uint16_t left_cnt
, right_cnt
;
357 /* an instruction can reference at most one address register amongst
358 * it's src/dst registers. Beyond that, you need to insert mov's.
360 * NOTE: do not write this directly, use ir3_instr_set_address()
362 struct ir3_instruction
*address
;
364 /* Tracking for additional dependent instructions. Used to handle
365 * barriers, WAR hazards for arrays/SSBOs/etc.
367 DECLARE_ARRAY(struct ir3_instruction
*, deps
);
370 * From PoV of instruction scheduling, not execution (ie. ignores global/
371 * local distinction):
372 * shared image atomic SSBO everything
373 * barrier()/ - R/W R/W R/W R/W X
374 * groupMemoryBarrier()
375 * memoryBarrier() - R/W R/W
376 * (but only images declared coherent?)
377 * memoryBarrierAtomic() - R/W
378 * memoryBarrierBuffer() - R/W
379 * memoryBarrierImage() - R/W
380 * memoryBarrierShared() - R/W
382 * TODO I think for SSBO/image/shared, in cases where we can determine
383 * which variable is accessed, we don't need to care about accesses to
384 * different variables (unless declared coherent??)
387 IR3_BARRIER_EVERYTHING
= 1 << 0,
388 IR3_BARRIER_SHARED_R
= 1 << 1,
389 IR3_BARRIER_SHARED_W
= 1 << 2,
390 IR3_BARRIER_IMAGE_R
= 1 << 3,
391 IR3_BARRIER_IMAGE_W
= 1 << 4,
392 IR3_BARRIER_BUFFER_R
= 1 << 5,
393 IR3_BARRIER_BUFFER_W
= 1 << 6,
394 IR3_BARRIER_ARRAY_R
= 1 << 7,
395 IR3_BARRIER_ARRAY_W
= 1 << 8,
396 } barrier_class
, barrier_conflict
;
398 /* Entry in ir3_block's instruction list: */
399 struct list_head node
;
405 // TODO only computerator/assembler:
409 static inline struct ir3_instruction
*
410 ir3_neighbor_first(struct ir3_instruction
*instr
)
413 while (instr
->cp
.left
) {
414 instr
= instr
->cp
.left
;
415 if (++cnt
> 0xffff) {
423 static inline int ir3_neighbor_count(struct ir3_instruction
*instr
)
427 debug_assert(!instr
->cp
.left
);
429 while (instr
->cp
.right
) {
431 instr
= instr
->cp
.right
;
442 struct ir3_compiler
*compiler
;
443 gl_shader_stage type
;
445 DECLARE_ARRAY(struct ir3_instruction
*, inputs
);
446 DECLARE_ARRAY(struct ir3_instruction
*, outputs
);
448 /* Track bary.f (and ldlv) instructions.. this is needed in
449 * scheduling to ensure that all varying fetches happen before
450 * any potential kill instructions. The hw gets grumpy if all
451 * threads in a group are killed before the last bary.f gets
452 * a chance to signal end of input (ei).
454 DECLARE_ARRAY(struct ir3_instruction
*, baryfs
);
456 /* Track all indirect instructions (read and write). To avoid
457 * deadlock scenario where an address register gets scheduled,
458 * but other dependent src instructions cannot be scheduled due
459 * to dependency on a *different* address register value, the
460 * scheduler needs to ensure that all dependencies other than
461 * the instruction other than the address register are scheduled
462 * before the one that writes the address register. Having a
463 * convenient list of instructions that reference some address
464 * register simplifies this.
466 DECLARE_ARRAY(struct ir3_instruction
*, a0_users
);
469 DECLARE_ARRAY(struct ir3_instruction
*, a1_users
);
471 /* and same for instructions that consume predicate register: */
472 DECLARE_ARRAY(struct ir3_instruction
*, predicates
);
474 /* Track texture sample instructions which need texture state
475 * patched in (for astc-srgb workaround):
477 DECLARE_ARRAY(struct ir3_instruction
*, astc_srgb
);
479 /* List of blocks: */
480 struct list_head block_list
;
482 /* List of ir3_array's: */
483 struct list_head array_list
;
486 unsigned block_count
, instr_count
;
491 struct list_head node
;
495 struct nir_register
*r
;
497 /* To avoid array write's from getting DCE'd, keep track of the
498 * most recent write. Any array access depends on the most
499 * recent write. This way, nothing depends on writes after the
500 * last read. But all the writes that happen before that have
501 * something depending on them
503 struct ir3_instruction
*last_write
;
505 /* extra stuff used in RA pass: */
506 unsigned base
; /* base vreg name */
507 unsigned reg
; /* base physical reg */
508 uint16_t start_ip
, end_ip
;
510 /* Indicates if half-precision */
516 struct ir3_array
* ir3_lookup_array(struct ir3
*ir
, unsigned id
);
519 struct list_head node
;
522 const struct nir_block
*nblock
;
524 struct list_head instr_list
; /* list of ir3_instruction */
526 /* each block has either one or two successors.. in case of
527 * two successors, 'condition' decides which one to follow.
528 * A block preceding an if/else has two successors.
530 struct ir3_instruction
*condition
;
531 struct ir3_block
*successors
[2];
533 struct set
*predecessors
; /* set of ir3_block */
535 uint16_t start_ip
, end_ip
;
537 /* Track instructions which do not write a register but other-
538 * wise must not be discarded (such as kill, stg, etc)
540 DECLARE_ARRAY(struct ir3_instruction
*, keeps
);
542 /* used for per-pass extra block data. Mainly used right
543 * now in RA step to track livein/liveout.
552 static inline uint32_t
553 block_id(struct ir3_block
*block
)
556 return block
->serialno
;
558 return (uint32_t)(unsigned long)block
;
562 struct ir3_shader_variant
;
564 struct ir3
* ir3_create(struct ir3_compiler
*compiler
, struct ir3_shader_variant
*v
);
565 void ir3_destroy(struct ir3
*shader
);
567 void * ir3_assemble(struct ir3_shader_variant
*v
);
568 void * ir3_alloc(struct ir3
*shader
, int sz
);
570 struct ir3_block
* ir3_block_create(struct ir3
*shader
);
572 struct ir3_instruction
* ir3_instr_create(struct ir3_block
*block
, opc_t opc
);
573 struct ir3_instruction
* ir3_instr_create2(struct ir3_block
*block
,
574 opc_t opc
, int nreg
);
575 struct ir3_instruction
* ir3_instr_clone(struct ir3_instruction
*instr
);
576 void ir3_instr_add_dep(struct ir3_instruction
*instr
, struct ir3_instruction
*dep
);
577 const char *ir3_instr_name(struct ir3_instruction
*instr
);
579 struct ir3_register
* ir3_reg_create(struct ir3_instruction
*instr
,
581 struct ir3_register
* ir3_reg_clone(struct ir3
*shader
,
582 struct ir3_register
*reg
);
584 void ir3_instr_set_address(struct ir3_instruction
*instr
,
585 struct ir3_instruction
*addr
);
587 static inline bool ir3_instr_check_mark(struct ir3_instruction
*instr
)
589 if (instr
->flags
& IR3_INSTR_MARK
)
590 return true; /* already visited */
591 instr
->flags
|= IR3_INSTR_MARK
;
595 void ir3_block_clear_mark(struct ir3_block
*block
);
596 void ir3_clear_mark(struct ir3
*shader
);
598 unsigned ir3_count_instructions(struct ir3
*ir
);
599 unsigned ir3_count_instructions_ra(struct ir3
*ir
);
602 * Move 'instr' to just before 'after'
605 ir3_instr_move_before(struct ir3_instruction
*instr
,
606 struct ir3_instruction
*after
)
608 list_delinit(&instr
->node
);
609 list_addtail(&instr
->node
, &after
->node
);
613 * Move 'instr' to just after 'before':
616 ir3_instr_move_after(struct ir3_instruction
*instr
,
617 struct ir3_instruction
*before
)
619 list_delinit(&instr
->node
);
620 list_add(&instr
->node
, &before
->node
);
623 void ir3_find_ssa_uses(struct ir3
*ir
, void *mem_ctx
, bool falsedeps
);
625 void ir3_set_dst_type(struct ir3_instruction
*instr
, bool half
);
626 void ir3_fixup_src_type(struct ir3_instruction
*instr
);
628 bool ir3_valid_flags(struct ir3_instruction
*instr
, unsigned n
, unsigned flags
);
630 #include "util/set.h"
631 #define foreach_ssa_use(__use, __instr) \
632 for (struct ir3_instruction *__use = (void *)~0; \
633 __use && (__instr)->uses; __use = NULL) \
634 set_foreach ((__instr)->uses, __entry) \
635 if ((__use = (void *)__entry->key))
637 static inline uint32_t reg_num(struct ir3_register
*reg
)
639 return reg
->num
>> 2;
642 static inline uint32_t reg_comp(struct ir3_register
*reg
)
644 return reg
->num
& 0x3;
647 static inline bool is_flow(struct ir3_instruction
*instr
)
649 return (opc_cat(instr
->opc
) == 0);
652 static inline bool is_kill(struct ir3_instruction
*instr
)
654 return instr
->opc
== OPC_KILL
;
657 static inline bool is_nop(struct ir3_instruction
*instr
)
659 return instr
->opc
== OPC_NOP
;
662 static inline bool is_same_type_reg(struct ir3_register
*reg1
,
663 struct ir3_register
*reg2
)
665 unsigned type_reg1
= (reg1
->flags
& (IR3_REG_HIGH
| IR3_REG_HALF
));
666 unsigned type_reg2
= (reg2
->flags
& (IR3_REG_HIGH
| IR3_REG_HALF
));
668 if (type_reg1
^ type_reg2
)
674 /* Is it a non-transformative (ie. not type changing) mov? This can
675 * also include absneg.s/absneg.f, which for the most part can be
676 * treated as a mov (single src argument).
678 static inline bool is_same_type_mov(struct ir3_instruction
*instr
)
680 struct ir3_register
*dst
;
682 switch (instr
->opc
) {
684 if (instr
->cat1
.src_type
!= instr
->cat1
.dst_type
)
686 /* If the type of dest reg and src reg are different,
687 * it shouldn't be considered as same type mov
689 if (!is_same_type_reg(instr
->regs
[0], instr
->regs
[1]))
694 if (instr
->flags
& IR3_INSTR_SAT
)
696 /* If the type of dest reg and src reg are different,
697 * it shouldn't be considered as same type mov
699 if (!is_same_type_reg(instr
->regs
[0], instr
->regs
[1]))
706 dst
= instr
->regs
[0];
708 /* mov's that write to a0 or p0.x are special: */
709 if (dst
->num
== regid(REG_P0
, 0))
711 if (reg_num(dst
) == REG_A0
)
714 if (dst
->flags
& (IR3_REG_RELATIV
| IR3_REG_ARRAY
))
720 /* A move from const, which changes size but not type, can also be
721 * folded into dest instruction in some cases.
723 static inline bool is_const_mov(struct ir3_instruction
*instr
)
725 if (instr
->opc
!= OPC_MOV
)
728 if (!(instr
->regs
[1]->flags
& IR3_REG_CONST
))
731 type_t src_type
= instr
->cat1
.src_type
;
732 type_t dst_type
= instr
->cat1
.dst_type
;
734 return (type_float(src_type
) && type_float(dst_type
)) ||
735 (type_uint(src_type
) && type_uint(dst_type
)) ||
736 (type_sint(src_type
) && type_sint(dst_type
));
739 static inline bool is_alu(struct ir3_instruction
*instr
)
741 return (1 <= opc_cat(instr
->opc
)) && (opc_cat(instr
->opc
) <= 3);
744 static inline bool is_sfu(struct ir3_instruction
*instr
)
746 return (opc_cat(instr
->opc
) == 4);
749 static inline bool is_tex(struct ir3_instruction
*instr
)
751 return (opc_cat(instr
->opc
) == 5);
754 static inline bool is_tex_or_prefetch(struct ir3_instruction
*instr
)
756 return is_tex(instr
) || (instr
->opc
== OPC_META_TEX_PREFETCH
);
759 static inline bool is_mem(struct ir3_instruction
*instr
)
761 return (opc_cat(instr
->opc
) == 6);
764 static inline bool is_barrier(struct ir3_instruction
*instr
)
766 return (opc_cat(instr
->opc
) == 7);
770 is_half(struct ir3_instruction
*instr
)
772 return !!(instr
->regs
[0]->flags
& IR3_REG_HALF
);
776 is_high(struct ir3_instruction
*instr
)
778 return !!(instr
->regs
[0]->flags
& IR3_REG_HIGH
);
782 is_store(struct ir3_instruction
*instr
)
784 /* these instructions, the "destination" register is
785 * actually a source, the address to store to.
787 switch (instr
->opc
) {
802 static inline bool is_load(struct ir3_instruction
*instr
)
804 switch (instr
->opc
) {
814 /* probably some others too.. */
821 static inline bool is_input(struct ir3_instruction
*instr
)
823 /* in some cases, ldlv is used to fetch varying without
824 * interpolation.. fortunately inloc is the first src
825 * register in either case
827 switch (instr
->opc
) {
836 static inline bool is_bool(struct ir3_instruction
*instr
)
838 switch (instr
->opc
) {
849 cat3_half_opc(opc_t opc
)
852 case OPC_MAD_F32
: return OPC_MAD_F16
;
853 case OPC_SEL_B32
: return OPC_SEL_B16
;
854 case OPC_SEL_S32
: return OPC_SEL_S16
;
855 case OPC_SEL_F32
: return OPC_SEL_F16
;
856 case OPC_SAD_S32
: return OPC_SAD_S16
;
862 cat3_full_opc(opc_t opc
)
865 case OPC_MAD_F16
: return OPC_MAD_F32
;
866 case OPC_SEL_B16
: return OPC_SEL_B32
;
867 case OPC_SEL_S16
: return OPC_SEL_S32
;
868 case OPC_SEL_F16
: return OPC_SEL_F32
;
869 case OPC_SAD_S16
: return OPC_SAD_S32
;
875 cat4_half_opc(opc_t opc
)
878 case OPC_RSQ
: return OPC_HRSQ
;
879 case OPC_LOG2
: return OPC_HLOG2
;
880 case OPC_EXP2
: return OPC_HEXP2
;
886 cat4_full_opc(opc_t opc
)
889 case OPC_HRSQ
: return OPC_RSQ
;
890 case OPC_HLOG2
: return OPC_LOG2
;
891 case OPC_HEXP2
: return OPC_EXP2
;
896 static inline bool is_meta(struct ir3_instruction
*instr
)
898 return (opc_cat(instr
->opc
) == -1);
901 static inline unsigned dest_regs(struct ir3_instruction
*instr
)
903 if ((instr
->regs_count
== 0) || is_store(instr
) || is_flow(instr
))
906 return util_last_bit(instr
->regs
[0]->wrmask
);
910 writes_gpr(struct ir3_instruction
*instr
)
912 if (dest_regs(instr
) == 0)
914 /* is dest a normal temp register: */
915 struct ir3_register
*reg
= instr
->regs
[0];
916 debug_assert(!(reg
->flags
& (IR3_REG_CONST
| IR3_REG_IMMED
)));
917 if ((reg_num(reg
) == REG_A0
) ||
918 (reg
->num
== regid(REG_P0
, 0)))
923 static inline bool writes_addr0(struct ir3_instruction
*instr
)
925 if (instr
->regs_count
> 0) {
926 struct ir3_register
*dst
= instr
->regs
[0];
927 return dst
->num
== regid(REG_A0
, 0);
932 static inline bool writes_addr1(struct ir3_instruction
*instr
)
934 if (instr
->regs_count
> 0) {
935 struct ir3_register
*dst
= instr
->regs
[0];
936 return dst
->num
== regid(REG_A0
, 1);
941 static inline bool writes_pred(struct ir3_instruction
*instr
)
943 if (instr
->regs_count
> 0) {
944 struct ir3_register
*dst
= instr
->regs
[0];
945 return reg_num(dst
) == REG_P0
;
950 /* returns defining instruction for reg */
951 /* TODO better name */
952 static inline struct ir3_instruction
*ssa(struct ir3_register
*reg
)
954 if (reg
->flags
& (IR3_REG_SSA
| IR3_REG_ARRAY
)) {
960 static inline bool conflicts(struct ir3_instruction
*a
,
961 struct ir3_instruction
*b
)
963 return (a
&& b
) && (a
!= b
);
966 static inline bool reg_gpr(struct ir3_register
*r
)
968 if (r
->flags
& (IR3_REG_CONST
| IR3_REG_IMMED
))
970 if ((reg_num(r
) == REG_A0
) || (reg_num(r
) == REG_P0
))
975 static inline type_t
half_type(type_t type
)
978 case TYPE_F32
: return TYPE_F16
;
979 case TYPE_U32
: return TYPE_U16
;
980 case TYPE_S32
: return TYPE_S16
;
991 static inline type_t
full_type(type_t type
)
994 case TYPE_F16
: return TYPE_F32
;
995 case TYPE_U16
: return TYPE_U32
;
996 case TYPE_S16
: return TYPE_S32
;
1007 /* some cat2 instructions (ie. those which are not float) can embed an
1010 static inline bool ir3_cat2_int(opc_t opc
)
1050 /* map cat2 instruction to valid abs/neg flags: */
1051 static inline unsigned ir3_cat2_absneg(opc_t opc
)
1068 return IR3_REG_FABS
| IR3_REG_FNEG
;
1089 return IR3_REG_SABS
| IR3_REG_SNEG
;
1103 return IR3_REG_BNOT
;
1110 /* map cat3 instructions to valid abs/neg flags: */
1111 static inline unsigned ir3_cat3_absneg(opc_t opc
)
1118 return IR3_REG_FNEG
;
1130 /* neg *may* work on 3rd src.. */
1140 #define MASK(n) ((1 << (n)) - 1)
1142 /* iterator for an instructions's sources (reg), also returns src #: */
1143 #define foreach_src_n(__srcreg, __n, __instr) \
1144 if ((__instr)->regs_count) \
1145 for (struct ir3_register *__srcreg = (void *)~0; __srcreg; __srcreg = NULL) \
1146 for (unsigned __cnt = (__instr)->regs_count - 1, __n = 0; __n < __cnt; __n++) \
1147 if ((__srcreg = (__instr)->regs[__n + 1]))
1149 /* iterator for an instructions's sources (reg): */
1150 #define foreach_src(__srcreg, __instr) \
1151 foreach_src_n(__srcreg, __i, __instr)
1153 static inline unsigned __ssa_src_cnt(struct ir3_instruction
*instr
)
1155 unsigned cnt
= instr
->regs_count
+ instr
->deps_count
;
1161 static inline struct ir3_instruction
**
1162 __ssa_srcp_n(struct ir3_instruction
*instr
, unsigned n
)
1164 if (n
== (instr
->regs_count
+ instr
->deps_count
))
1165 return &instr
->address
;
1166 if (n
>= instr
->regs_count
)
1167 return &instr
->deps
[n
- instr
->regs_count
];
1168 if (ssa(instr
->regs
[n
]))
1169 return &instr
->regs
[n
]->instr
;
1173 static inline bool __is_false_dep(struct ir3_instruction
*instr
, unsigned n
)
1175 if (n
== (instr
->regs_count
+ instr
->deps_count
))
1177 if (n
>= instr
->regs_count
)
1182 #define foreach_ssa_srcp_n(__srcp, __n, __instr) \
1183 for (struct ir3_instruction **__srcp = (void *)~0; __srcp; __srcp = NULL) \
1184 for (unsigned __cnt = __ssa_src_cnt(__instr), __n = 0; __n < __cnt; __n++) \
1185 if ((__srcp = __ssa_srcp_n(__instr, __n)))
1187 #define foreach_ssa_srcp(__srcp, __instr) \
1188 foreach_ssa_srcp_n(__srcp, __i, __instr)
1190 /* iterator for an instruction's SSA sources (instr), also returns src #: */
1191 #define foreach_ssa_src_n(__srcinst, __n, __instr) \
1192 for (struct ir3_instruction *__srcinst = (void *)~0; __srcinst; __srcinst = NULL) \
1193 foreach_ssa_srcp_n(__srcp, __n, __instr) \
1194 if ((__srcinst = *__srcp))
1196 /* iterator for an instruction's SSA sources (instr): */
1197 #define foreach_ssa_src(__srcinst, __instr) \
1198 foreach_ssa_src_n(__srcinst, __i, __instr)
1200 /* iterators for shader inputs: */
1201 #define foreach_input_n(__ininstr, __cnt, __ir) \
1202 for (struct ir3_instruction *__ininstr = (void *)~0; __ininstr; __ininstr = NULL) \
1203 for (unsigned __cnt = 0; __cnt < (__ir)->inputs_count; __cnt++) \
1204 if ((__ininstr = (__ir)->inputs[__cnt]))
1205 #define foreach_input(__ininstr, __ir) \
1206 foreach_input_n(__ininstr, __i, __ir)
1208 /* iterators for shader outputs: */
1209 #define foreach_output_n(__outinstr, __cnt, __ir) \
1210 for (struct ir3_instruction *__outinstr = (void *)~0; __outinstr; __outinstr = NULL) \
1211 for (unsigned __cnt = 0; __cnt < (__ir)->outputs_count; __cnt++) \
1212 if ((__outinstr = (__ir)->outputs[__cnt]))
1213 #define foreach_output(__outinstr, __ir) \
1214 foreach_output_n(__outinstr, __i, __ir)
1216 /* iterators for instructions: */
1217 #define foreach_instr(__instr, __list) \
1218 list_for_each_entry(struct ir3_instruction, __instr, __list, node)
1219 #define foreach_instr_rev(__instr, __list) \
1220 list_for_each_entry_rev(struct ir3_instruction, __instr, __list, node)
1221 #define foreach_instr_safe(__instr, __list) \
1222 list_for_each_entry_safe(struct ir3_instruction, __instr, __list, node)
1224 /* iterators for blocks: */
1225 #define foreach_block(__block, __list) \
1226 list_for_each_entry(struct ir3_block, __block, __list, node)
1227 #define foreach_block_safe(__block, __list) \
1228 list_for_each_entry_safe(struct ir3_block, __block, __list, node)
1229 #define foreach_block_rev(__block, __list) \
1230 list_for_each_entry_rev(struct ir3_block, __block, __list, node)
1232 /* iterators for arrays: */
1233 #define foreach_array(__array, __list) \
1234 list_for_each_entry(struct ir3_array, __array, __list, node)
1235 #define foreach_array_safe(__array, __list) \
1236 list_for_each_entry_safe(struct ir3_array, __array, __list, node)
1238 /* Check if condition is true for any src instruction.
1241 check_src_cond(struct ir3_instruction
*instr
, bool (*cond
)(struct ir3_instruction
*))
1243 /* Note that this is also used post-RA so skip the ssa iterator: */
1244 foreach_src (reg
, instr
) {
1245 struct ir3_instruction
*src
= reg
->instr
;
1250 /* meta:split/collect aren't real instructions, the thing that
1251 * we actually care about is *their* srcs
1253 if ((src
->opc
== OPC_META_SPLIT
) || (src
->opc
== OPC_META_COLLECT
)) {
1254 if (check_src_cond(src
, cond
))
1265 #define IR3_PASS(ir, pass, ...) ({ \
1266 bool progress = pass(ir, ##__VA_ARGS__); \
1268 ir3_debug_print(ir, "AFTER: " #pass); \
1275 void ir3_validate(struct ir3
*ir
);
1278 void ir3_print(struct ir3
*ir
);
1279 void ir3_print_instr(struct ir3_instruction
*instr
);
1281 /* delay calculation: */
1282 int ir3_delayslots(struct ir3_instruction
*assigner
,
1283 struct ir3_instruction
*consumer
, unsigned n
, bool soft
);
1284 unsigned ir3_delay_calc(struct ir3_block
*block
, struct ir3_instruction
*instr
,
1285 bool soft
, bool pred
);
1286 void ir3_remove_nops(struct ir3
*ir
);
1288 /* dead code elimination: */
1289 struct ir3_shader_variant
;
1290 bool ir3_dce(struct ir3
*ir
, struct ir3_shader_variant
*so
);
1292 /* fp16 conversion folding */
1293 bool ir3_cf(struct ir3
*ir
);
1295 /* copy-propagate: */
1296 bool ir3_cp(struct ir3
*ir
, struct ir3_shader_variant
*so
);
1297 bool ir3_cp_postsched(struct ir3
*ir
);
1299 /* group neighbors and insert mov's to resolve conflicts: */
1300 bool ir3_group(struct ir3
*ir
);
1303 bool ir3_sched_add_deps(struct ir3
*ir
);
1304 int ir3_sched(struct ir3
*ir
);
1307 bool ir3_postsched(struct ir3
*ir
, struct ir3_shader_variant
*v
);
1309 bool ir3_a6xx_fixup_atomic_dests(struct ir3
*ir
, struct ir3_shader_variant
*so
);
1311 /* register assignment: */
1312 struct ir3_ra_reg_set
* ir3_ra_alloc_reg_set(struct ir3_compiler
*compiler
, bool mergedregs
);
1313 int ir3_ra(struct ir3_shader_variant
*v
, struct ir3_instruction
**precolor
, unsigned nprecolor
);
1316 bool ir3_legalize(struct ir3
*ir
, struct ir3_shader_variant
*so
, int *max_bary
);
1319 ir3_has_latency_to_hide(struct ir3
*ir
)
1321 /* VS/GS/TCS/TESS co-exist with frag shader invocations, but we don't
1322 * know the nature of the fragment shader. Just assume it will have
1325 if (ir
->type
!= MESA_SHADER_FRAGMENT
)
1328 foreach_block (block
, &ir
->block_list
) {
1329 foreach_instr (instr
, &block
->instr_list
) {
1330 if (is_tex_or_prefetch(instr
))
1333 if (is_load(instr
)) {
1334 switch (instr
->opc
) {
1349 /* ************************************************************************* */
1350 /* instruction helpers */
1352 /* creates SSA src of correct type (ie. half vs full precision) */
1353 static inline struct ir3_register
* __ssa_src(struct ir3_instruction
*instr
,
1354 struct ir3_instruction
*src
, unsigned flags
)
1356 struct ir3_register
*reg
;
1357 if (src
->regs
[0]->flags
& IR3_REG_HALF
)
1358 flags
|= IR3_REG_HALF
;
1359 reg
= ir3_reg_create(instr
, 0, IR3_REG_SSA
| flags
);
1361 reg
->wrmask
= src
->regs
[0]->wrmask
;
1365 static inline struct ir3_register
* __ssa_dst(struct ir3_instruction
*instr
)
1367 struct ir3_register
*reg
= ir3_reg_create(instr
, 0, 0);
1368 reg
->flags
|= IR3_REG_SSA
;
1372 static inline struct ir3_instruction
*
1373 create_immed_typed(struct ir3_block
*block
, uint32_t val
, type_t type
)
1375 struct ir3_instruction
*mov
;
1376 unsigned flags
= (type_size(type
) < 32) ? IR3_REG_HALF
: 0;
1378 mov
= ir3_instr_create(block
, OPC_MOV
);
1379 mov
->cat1
.src_type
= type
;
1380 mov
->cat1
.dst_type
= type
;
1381 __ssa_dst(mov
)->flags
|= flags
;
1382 ir3_reg_create(mov
, 0, IR3_REG_IMMED
| flags
)->uim_val
= val
;
1387 static inline struct ir3_instruction
*
1388 create_immed(struct ir3_block
*block
, uint32_t val
)
1390 return create_immed_typed(block
, val
, TYPE_U32
);
1393 static inline struct ir3_instruction
*
1394 create_uniform_typed(struct ir3_block
*block
, unsigned n
, type_t type
)
1396 struct ir3_instruction
*mov
;
1397 unsigned flags
= (type_size(type
) < 32) ? IR3_REG_HALF
: 0;
1399 mov
= ir3_instr_create(block
, OPC_MOV
);
1400 mov
->cat1
.src_type
= type
;
1401 mov
->cat1
.dst_type
= type
;
1402 __ssa_dst(mov
)->flags
|= flags
;
1403 ir3_reg_create(mov
, n
, IR3_REG_CONST
| flags
);
1408 static inline struct ir3_instruction
*
1409 create_uniform(struct ir3_block
*block
, unsigned n
)
1411 return create_uniform_typed(block
, n
, TYPE_F32
);
1414 static inline struct ir3_instruction
*
1415 create_uniform_indirect(struct ir3_block
*block
, int n
, type_t type
,
1416 struct ir3_instruction
*address
)
1418 struct ir3_instruction
*mov
;
1420 mov
= ir3_instr_create(block
, OPC_MOV
);
1421 mov
->cat1
.src_type
= type
;
1422 mov
->cat1
.dst_type
= type
;
1424 ir3_reg_create(mov
, 0, IR3_REG_CONST
| IR3_REG_RELATIV
)->array
.offset
= n
;
1426 ir3_instr_set_address(mov
, address
);
1431 static inline struct ir3_instruction
*
1432 ir3_MOV(struct ir3_block
*block
, struct ir3_instruction
*src
, type_t type
)
1434 struct ir3_instruction
*instr
= ir3_instr_create(block
, OPC_MOV
);
1435 unsigned flags
= (type_size(type
) < 32) ? IR3_REG_HALF
: 0;
1437 __ssa_dst(instr
)->flags
|= flags
;
1438 if (src
->regs
[0]->flags
& IR3_REG_ARRAY
) {
1439 struct ir3_register
*src_reg
= __ssa_src(instr
, src
, IR3_REG_ARRAY
);
1440 src_reg
->array
= src
->regs
[0]->array
;
1442 __ssa_src(instr
, src
, src
->regs
[0]->flags
& IR3_REG_HIGH
);
1444 debug_assert(!(src
->regs
[0]->flags
& IR3_REG_RELATIV
));
1445 instr
->cat1
.src_type
= type
;
1446 instr
->cat1
.dst_type
= type
;
1450 static inline struct ir3_instruction
*
1451 ir3_COV(struct ir3_block
*block
, struct ir3_instruction
*src
,
1452 type_t src_type
, type_t dst_type
)
1454 struct ir3_instruction
*instr
= ir3_instr_create(block
, OPC_MOV
);
1455 unsigned dst_flags
= (type_size(dst_type
) < 32) ? IR3_REG_HALF
: 0;
1456 unsigned src_flags
= (type_size(src_type
) < 32) ? IR3_REG_HALF
: 0;
1458 debug_assert((src
->regs
[0]->flags
& IR3_REG_HALF
) == src_flags
);
1460 __ssa_dst(instr
)->flags
|= dst_flags
;
1461 __ssa_src(instr
, src
, 0);
1462 instr
->cat1
.src_type
= src_type
;
1463 instr
->cat1
.dst_type
= dst_type
;
1464 debug_assert(!(src
->regs
[0]->flags
& IR3_REG_ARRAY
));
1468 static inline struct ir3_instruction
*
1469 ir3_NOP(struct ir3_block
*block
)
1471 return ir3_instr_create(block
, OPC_NOP
);
1474 #define IR3_INSTR_0 0
1476 #define __INSTR0(flag, name, opc) \
1477 static inline struct ir3_instruction * \
1478 ir3_##name(struct ir3_block *block) \
1480 struct ir3_instruction *instr = \
1481 ir3_instr_create(block, opc); \
1482 instr->flags |= flag; \
1485 #define INSTR0F(f, name) __INSTR0(IR3_INSTR_##f, name##_##f, OPC_##name)
1486 #define INSTR0(name) __INSTR0(0, name, OPC_##name)
1488 #define __INSTR1(flag, name, opc) \
1489 static inline struct ir3_instruction * \
1490 ir3_##name(struct ir3_block *block, \
1491 struct ir3_instruction *a, unsigned aflags) \
1493 struct ir3_instruction *instr = \
1494 ir3_instr_create(block, opc); \
1496 __ssa_src(instr, a, aflags); \
1497 instr->flags |= flag; \
1500 #define INSTR1F(f, name) __INSTR1(IR3_INSTR_##f, name##_##f, OPC_##name)
1501 #define INSTR1(name) __INSTR1(0, name, OPC_##name)
1503 #define __INSTR2(flag, name, opc) \
1504 static inline struct ir3_instruction * \
1505 ir3_##name(struct ir3_block *block, \
1506 struct ir3_instruction *a, unsigned aflags, \
1507 struct ir3_instruction *b, unsigned bflags) \
1509 struct ir3_instruction *instr = \
1510 ir3_instr_create(block, opc); \
1512 __ssa_src(instr, a, aflags); \
1513 __ssa_src(instr, b, bflags); \
1514 instr->flags |= flag; \
1517 #define INSTR2F(f, name) __INSTR2(IR3_INSTR_##f, name##_##f, OPC_##name)
1518 #define INSTR2(name) __INSTR2(0, name, OPC_##name)
1520 #define __INSTR3(flag, name, opc) \
1521 static inline struct ir3_instruction * \
1522 ir3_##name(struct ir3_block *block, \
1523 struct ir3_instruction *a, unsigned aflags, \
1524 struct ir3_instruction *b, unsigned bflags, \
1525 struct ir3_instruction *c, unsigned cflags) \
1527 struct ir3_instruction *instr = \
1528 ir3_instr_create2(block, opc, 4); \
1530 __ssa_src(instr, a, aflags); \
1531 __ssa_src(instr, b, bflags); \
1532 __ssa_src(instr, c, cflags); \
1533 instr->flags |= flag; \
1536 #define INSTR3F(f, name) __INSTR3(IR3_INSTR_##f, name##_##f, OPC_##name)
1537 #define INSTR3(name) __INSTR3(0, name, OPC_##name)
1539 #define __INSTR4(flag, name, opc) \
1540 static inline struct ir3_instruction * \
1541 ir3_##name(struct ir3_block *block, \
1542 struct ir3_instruction *a, unsigned aflags, \
1543 struct ir3_instruction *b, unsigned bflags, \
1544 struct ir3_instruction *c, unsigned cflags, \
1545 struct ir3_instruction *d, unsigned dflags) \
1547 struct ir3_instruction *instr = \
1548 ir3_instr_create2(block, opc, 5); \
1550 __ssa_src(instr, a, aflags); \
1551 __ssa_src(instr, b, bflags); \
1552 __ssa_src(instr, c, cflags); \
1553 __ssa_src(instr, d, dflags); \
1554 instr->flags |= flag; \
1557 #define INSTR4F(f, name) __INSTR4(IR3_INSTR_##f, name##_##f, OPC_##name)
1558 #define INSTR4(name) __INSTR4(0, name, OPC_##name)
1560 /* cat0 instructions: */
1571 /* cat2 instructions, most 2 src but some 1 src: */
1619 /* cat3 instructions: */
1628 /* NOTE: SEL_B32 checks for zero vs nonzero */
1638 /* cat4 instructions: */
1650 /* cat5 instructions: */
1659 static inline struct ir3_instruction
*
1660 ir3_SAM(struct ir3_block
*block
, opc_t opc
, type_t type
,
1661 unsigned wrmask
, unsigned flags
, struct ir3_instruction
*samp_tex
,
1662 struct ir3_instruction
*src0
, struct ir3_instruction
*src1
)
1664 struct ir3_instruction
*sam
;
1666 sam
= ir3_instr_create(block
, opc
);
1667 sam
->flags
|= flags
;
1668 __ssa_dst(sam
)->wrmask
= wrmask
;
1669 if (flags
& IR3_INSTR_S2EN
) {
1670 __ssa_src(sam
, samp_tex
, (flags
& IR3_INSTR_B
) ? 0 : IR3_REG_HALF
);
1673 __ssa_src(sam
, src0
, 0);
1676 __ssa_src(sam
, src1
, 0);
1678 sam
->cat5
.type
= type
;
1683 /* cat6 instructions: */
1698 INSTR2(ATOMIC_CMPXCHG
)
1708 INSTR3F(G
, ATOMIC_ADD
)
1709 INSTR3F(G
, ATOMIC_SUB
)
1710 INSTR3F(G
, ATOMIC_XCHG
)
1711 INSTR3F(G
, ATOMIC_INC
)
1712 INSTR3F(G
, ATOMIC_DEC
)
1713 INSTR3F(G
, ATOMIC_CMPXCHG
)
1714 INSTR3F(G
, ATOMIC_MIN
)
1715 INSTR3F(G
, ATOMIC_MAX
)
1716 INSTR3F(G
, ATOMIC_AND
)
1717 INSTR3F(G
, ATOMIC_OR
)
1718 INSTR3F(G
, ATOMIC_XOR
)
1723 INSTR4F(G
, ATOMIC_ADD
)
1724 INSTR4F(G
, ATOMIC_SUB
)
1725 INSTR4F(G
, ATOMIC_XCHG
)
1726 INSTR4F(G
, ATOMIC_INC
)
1727 INSTR4F(G
, ATOMIC_DEC
)
1728 INSTR4F(G
, ATOMIC_CMPXCHG
)
1729 INSTR4F(G
, ATOMIC_MIN
)
1730 INSTR4F(G
, ATOMIC_MAX
)
1731 INSTR4F(G
, ATOMIC_AND
)
1732 INSTR4F(G
, ATOMIC_OR
)
1733 INSTR4F(G
, ATOMIC_XOR
)
1738 /* cat7 instructions: */
1742 /* meta instructions: */
1743 INSTR0(META_TEX_PREFETCH
);
1745 /* ************************************************************************* */
1746 #include "regmask.h"
1748 static inline void regmask_set(regmask_t
*regmask
, struct ir3_register
*reg
)
1750 bool half
= reg
->flags
& IR3_REG_HALF
;
1751 if (reg
->flags
& IR3_REG_RELATIV
) {
1752 for (unsigned i
= 0; i
< reg
->size
; i
++)
1753 __regmask_set(regmask
, half
, reg
->array
.offset
+ i
);
1755 for (unsigned mask
= reg
->wrmask
, n
= reg
->num
; mask
; mask
>>= 1, n
++)
1757 __regmask_set(regmask
, half
, n
);
1761 static inline bool regmask_get(regmask_t
*regmask
,
1762 struct ir3_register
*reg
)
1764 bool half
= reg
->flags
& IR3_REG_HALF
;
1765 if (reg
->flags
& IR3_REG_RELATIV
) {
1766 for (unsigned i
= 0; i
< reg
->size
; i
++)
1767 if (__regmask_get(regmask
, half
, reg
->array
.offset
+ i
))
1770 for (unsigned mask
= reg
->wrmask
, n
= reg
->num
; mask
; mask
>>= 1, n
++)
1772 if (__regmask_get(regmask
, half
, n
))
1777 /* ************************************************************************* */