2 * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 #include "compiler/shader_enums.h"
32 #include "util/bitscan.h"
33 #include "util/list.h"
35 #include "util/u_debug.h"
37 #include "instr-a3xx.h"
39 /* low level intermediate representation of an adreno shader program */
43 struct ir3_instruction
;
49 uint16_t instrs_count
; /* expanded to account for rpt's */
50 uint16_t nops_count
; /* # of nop instructions, including nopN */
51 /* NOTE: max_reg, etc, does not include registers not touched
52 * by the shader (ie. vertex fetched via VFD_DECODE but not
55 int8_t max_reg
; /* highest GPR # used by shader */
59 /* number of sync bits: */
62 /* estimate of number of cycles stalled on (ss) */
65 uint16_t last_baryf
; /* instruction # of last varying fetch */
70 IR3_REG_CONST
= 0x001,
71 IR3_REG_IMMED
= 0x002,
73 /* high registers are used for some things in compute shaders,
74 * for example. Seems to be for things that are global to all
75 * threads in a wave, so possibly these are global/shared by
76 * all the threads in the wave?
79 IR3_REG_RELATIV
= 0x010,
81 /* Most instructions, it seems, can do float abs/neg but not
82 * integer. The CP pass needs to know what is intended (int or
83 * float) in order to do the right thing. For this reason the
84 * abs/neg flags are split out into float and int variants. In
85 * addition, .b (bitwise) operations, the negate is actually a
86 * bitwise not, so split that out into a new flag to make it
95 IR3_REG_POS_INF
= 0x1000,
96 /* (ei) flag, end-input? Set on last bary, presumably to signal
97 * that the shader needs no more input:
100 /* meta-flags, for intermediate stages of IR, ie.
101 * before register assignment is done:
103 IR3_REG_SSA
= 0x4000, /* 'instr' is ptr to assigning instr */
104 IR3_REG_ARRAY
= 0x8000,
108 /* used for cat5 instructions, but also for internal/IR level
109 * tracking of what registers are read/written by an instruction.
110 * wrmask may be a bad name since it is used to represent both
111 * src and dst that touch multiple adjacent registers.
113 unsigned wrmask
: 16; /* up to vec16 */
115 /* for relative addressing, 32bits for array size is too small,
116 * but otoh we don't need to deal with disjoint sets, so instead
117 * use a simple size field (number of scalar components).
119 * Note the size field isn't important for relative const (since
120 * we don't have to do register allocation for constants).
124 bool merged
: 1; /* half-regs conflict with full regs (ie >= a6xx) */
127 * the component is in the low two bits of the reg #, so
128 * rN.x becomes: (N << 2) | x
143 /* For IR3_REG_SSA, src registers contain ptr back to assigning
146 * For IR3_REG_ARRAY, the pointer is back to the last dependent
147 * array access (although the net effect is the same, it points
148 * back to a previous instruction that we depend on).
150 struct ir3_instruction
*instr
;
154 * Stupid/simple growable array implementation:
156 #define DECLARE_ARRAY(type, name) \
157 unsigned name ## _count, name ## _sz; \
160 #define array_insert(ctx, arr, val) do { \
161 if (arr ## _count == arr ## _sz) { \
162 arr ## _sz = MAX2(2 * arr ## _sz, 16); \
163 arr = reralloc_size(ctx, arr, arr ## _sz * sizeof(arr[0])); \
165 arr[arr ##_count++] = val; \
168 struct ir3_instruction
{
169 struct ir3_block
*block
;
172 /* (sy) flag is set on first instruction, and after sample
173 * instructions (probably just on RAW hazard).
175 IR3_INSTR_SY
= 0x001,
176 /* (ss) flag is set on first instruction, and first instruction
177 * to depend on the result of "long" instructions (RAW hazard):
179 * rcp, rsq, log2, exp2, sin, cos, sqrt
181 * It seems to synchronize until all in-flight instructions are
182 * completed, for example:
185 * add.f hr2.z, (neg)hr2.z, hc0.y
186 * mul.f hr2.w, (neg)hr2.y, (neg)hr2.y
189 * mad.f16 hr2.w, hr2.z, hr2.z, hr2.w
191 * mad.f16 hr2.w, (neg)hr0.w, (neg)hr0.w, hr2.w
192 * (ss)(rpt2)mul.f hr1.x, (r)hr1.x, hr1.w
193 * (rpt2)mul.f hr0.x, (neg)(r)hr0.x, hr2.x
195 * The last mul.f does not have (ss) set, presumably because the
196 * (ss) on the previous instruction does the job.
198 * The blob driver also seems to set it on WAR hazards, although
199 * not really clear if this is needed or just blob compiler being
200 * sloppy. So far I haven't found a case where removing the (ss)
201 * causes problems for WAR hazard, but I could just be getting
205 * (ss)(rpt2)mad.f32 r3.y, (r)c9.x, r1.x, (r)r3.z
208 IR3_INSTR_SS
= 0x002,
209 /* (jp) flag is set on jump targets:
211 IR3_INSTR_JP
= 0x004,
212 IR3_INSTR_UL
= 0x008,
213 IR3_INSTR_3D
= 0x010,
218 IR3_INSTR_S2EN
= 0x200,
220 IR3_INSTR_SAT
= 0x800,
221 /* (cat5/cat6) Bindless */
222 IR3_INSTR_B
= 0x1000,
223 /* (cat5-only) Get some parts of the encoding from a1.x */
224 IR3_INSTR_A1EN
= 0x2000,
225 /* meta-flags, for intermediate stages of IR, ie.
226 * before register assignment is done:
228 IR3_INSTR_MARK
= 0x4000,
229 IR3_INSTR_UNUSED
= 0x8000,
237 struct ir3_register
**regs
;
243 struct ir3_block
*target
;
246 type_t src_type
, dst_type
;
260 unsigned tex_base
: 3;
267 int iim_val
: 3; /* for ldgb/stgb, # of components */
273 unsigned w
: 1; /* write */
274 unsigned r
: 1; /* read */
275 unsigned l
: 1; /* local */
276 unsigned g
: 1; /* global */
278 /* for meta-instructions, just used to hold extra data
279 * before instruction scheduling, etc
282 int off
; /* component/offset */
285 /* for output collects, this maps back to the entry in the
286 * ir3_shader_variant::outputs table.
292 unsigned input_offset
;
293 unsigned samp_base
: 3;
294 unsigned tex_base
: 3;
297 /* maps back to entry in ir3_shader_variant::inputs table: */
299 /* for sysvals, identifies the sysval type. Mostly so we can
300 * identify the special cases where a sysval should not be DCE'd
301 * (currently, just pre-fs texture fetch)
303 gl_system_value sysval
;
307 /* transient values used during various algorithms: */
309 /* The instruction depth is the max dependency distance to output.
311 * You can also think of it as the "cost", if we did any sort of
312 * optimization for register footprint. Ie. a value that is just
313 * result of moving a const to a reg would have a low cost, so to
314 * it could make sense to duplicate the instruction at various
315 * points where the result is needed to reduce register footprint.
318 /* When we get to the RA stage, we no longer need depth, but
319 * we do need instruction's position/name:
327 /* used for per-pass extra instruction data.
329 * TODO we should remove the per-pass data like this and 'use_count'
330 * and do something similar to what RA does w/ ir3_ra_instr_data..
331 * ie. use the ir3_count_instructions pass, and then use instr->ip
332 * to index into a table of pass-private data.
337 * Valid if pass calls ir3_find_ssa_uses().. see foreach_ssa_use()
341 int sun
; /* Sethi–Ullman number, used by sched */
342 int use_count
; /* currently just updated/used by cp */
344 /* Used during CP and RA stages. For collect and shader inputs/
345 * outputs where we need a sequence of consecutive registers,
346 * keep track of each src instructions left (ie 'n-1') and right
347 * (ie 'n+1') neighbor. The front-end must insert enough mov's
348 * to ensure that each instruction has at most one left and at
349 * most one right neighbor. During the copy-propagation pass,
350 * we only remove mov's when we can preserve this constraint.
351 * And during the RA stage, we use the neighbor information to
352 * allocate a block of registers in one shot.
354 * TODO: maybe just add something like:
355 * struct ir3_instruction_ref {
356 * struct ir3_instruction *instr;
360 * Or can we get away without the refcnt stuff? It seems like
361 * it should be overkill.. the problem is if, potentially after
362 * already eliminating some mov's, if you have a single mov that
363 * needs to be grouped with it's neighbors in two different
364 * places (ex. shader output and a collect).
367 struct ir3_instruction
*left
, *right
;
368 uint16_t left_cnt
, right_cnt
;
371 /* an instruction can reference at most one address register amongst
372 * it's src/dst registers. Beyond that, you need to insert mov's.
374 * NOTE: do not write this directly, use ir3_instr_set_address()
376 struct ir3_instruction
*address
;
378 /* Tracking for additional dependent instructions. Used to handle
379 * barriers, WAR hazards for arrays/SSBOs/etc.
381 DECLARE_ARRAY(struct ir3_instruction
*, deps
);
384 * From PoV of instruction scheduling, not execution (ie. ignores global/
385 * local distinction):
386 * shared image atomic SSBO everything
387 * barrier()/ - R/W R/W R/W R/W X
388 * groupMemoryBarrier()
389 * memoryBarrier() - R/W R/W
390 * (but only images declared coherent?)
391 * memoryBarrierAtomic() - R/W
392 * memoryBarrierBuffer() - R/W
393 * memoryBarrierImage() - R/W
394 * memoryBarrierShared() - R/W
396 * TODO I think for SSBO/image/shared, in cases where we can determine
397 * which variable is accessed, we don't need to care about accesses to
398 * different variables (unless declared coherent??)
401 IR3_BARRIER_EVERYTHING
= 1 << 0,
402 IR3_BARRIER_SHARED_R
= 1 << 1,
403 IR3_BARRIER_SHARED_W
= 1 << 2,
404 IR3_BARRIER_IMAGE_R
= 1 << 3,
405 IR3_BARRIER_IMAGE_W
= 1 << 4,
406 IR3_BARRIER_BUFFER_R
= 1 << 5,
407 IR3_BARRIER_BUFFER_W
= 1 << 6,
408 IR3_BARRIER_ARRAY_R
= 1 << 7,
409 IR3_BARRIER_ARRAY_W
= 1 << 8,
410 } barrier_class
, barrier_conflict
;
412 /* Entry in ir3_block's instruction list: */
413 struct list_head node
;
419 // TODO only computerator/assembler:
423 static inline struct ir3_instruction
*
424 ir3_neighbor_first(struct ir3_instruction
*instr
)
427 while (instr
->cp
.left
) {
428 instr
= instr
->cp
.left
;
429 if (++cnt
> 0xffff) {
437 static inline int ir3_neighbor_count(struct ir3_instruction
*instr
)
441 debug_assert(!instr
->cp
.left
);
443 while (instr
->cp
.right
) {
445 instr
= instr
->cp
.right
;
456 struct ir3_compiler
*compiler
;
457 gl_shader_stage type
;
459 DECLARE_ARRAY(struct ir3_instruction
*, inputs
);
460 DECLARE_ARRAY(struct ir3_instruction
*, outputs
);
462 /* Track bary.f (and ldlv) instructions.. this is needed in
463 * scheduling to ensure that all varying fetches happen before
464 * any potential kill instructions. The hw gets grumpy if all
465 * threads in a group are killed before the last bary.f gets
466 * a chance to signal end of input (ei).
468 DECLARE_ARRAY(struct ir3_instruction
*, baryfs
);
470 /* Track all indirect instructions (read and write). To avoid
471 * deadlock scenario where an address register gets scheduled,
472 * but other dependent src instructions cannot be scheduled due
473 * to dependency on a *different* address register value, the
474 * scheduler needs to ensure that all dependencies other than
475 * the instruction other than the address register are scheduled
476 * before the one that writes the address register. Having a
477 * convenient list of instructions that reference some address
478 * register simplifies this.
480 DECLARE_ARRAY(struct ir3_instruction
*, a0_users
);
483 DECLARE_ARRAY(struct ir3_instruction
*, a1_users
);
485 /* and same for instructions that consume predicate register: */
486 DECLARE_ARRAY(struct ir3_instruction
*, predicates
);
488 /* Track texture sample instructions which need texture state
489 * patched in (for astc-srgb workaround):
491 DECLARE_ARRAY(struct ir3_instruction
*, astc_srgb
);
493 /* List of blocks: */
494 struct list_head block_list
;
496 /* List of ir3_array's: */
497 struct list_head array_list
;
499 unsigned max_sun
; /* max Sethi–Ullman number */
502 unsigned block_count
, instr_count
;
507 struct list_head node
;
511 struct nir_register
*r
;
513 /* To avoid array write's from getting DCE'd, keep track of the
514 * most recent write. Any array access depends on the most
515 * recent write. This way, nothing depends on writes after the
516 * last read. But all the writes that happen before that have
517 * something depending on them
519 struct ir3_instruction
*last_write
;
521 /* extra stuff used in RA pass: */
522 unsigned base
; /* base vreg name */
523 unsigned reg
; /* base physical reg */
524 uint16_t start_ip
, end_ip
;
526 /* Indicates if half-precision */
530 struct ir3_array
* ir3_lookup_array(struct ir3
*ir
, unsigned id
);
533 struct list_head node
;
536 const struct nir_block
*nblock
;
538 struct list_head instr_list
; /* list of ir3_instruction */
540 /* each block has either one or two successors.. in case of
541 * two successors, 'condition' decides which one to follow.
542 * A block preceding an if/else has two successors.
544 struct ir3_instruction
*condition
;
545 struct ir3_block
*successors
[2];
547 struct set
*predecessors
; /* set of ir3_block */
549 uint16_t start_ip
, end_ip
;
551 /* Track instructions which do not write a register but other-
552 * wise must not be discarded (such as kill, stg, etc)
554 DECLARE_ARRAY(struct ir3_instruction
*, keeps
);
556 /* used for per-pass extra block data. Mainly used right
557 * now in RA step to track livein/liveout.
566 static inline uint32_t
567 block_id(struct ir3_block
*block
)
570 return block
->serialno
;
572 return (uint32_t)(unsigned long)block
;
576 struct ir3
* ir3_create(struct ir3_compiler
*compiler
, gl_shader_stage type
);
577 void ir3_destroy(struct ir3
*shader
);
578 void * ir3_assemble(struct ir3
*shader
,
579 struct ir3_info
*info
, uint32_t gpu_id
);
580 void * ir3_alloc(struct ir3
*shader
, int sz
);
582 struct ir3_block
* ir3_block_create(struct ir3
*shader
);
584 struct ir3_instruction
* ir3_instr_create(struct ir3_block
*block
, opc_t opc
);
585 struct ir3_instruction
* ir3_instr_create2(struct ir3_block
*block
,
586 opc_t opc
, int nreg
);
587 struct ir3_instruction
* ir3_instr_clone(struct ir3_instruction
*instr
);
588 void ir3_instr_add_dep(struct ir3_instruction
*instr
, struct ir3_instruction
*dep
);
589 const char *ir3_instr_name(struct ir3_instruction
*instr
);
591 struct ir3_register
* ir3_reg_create(struct ir3_instruction
*instr
,
593 struct ir3_register
* ir3_reg_clone(struct ir3
*shader
,
594 struct ir3_register
*reg
);
596 void ir3_instr_set_address(struct ir3_instruction
*instr
,
597 struct ir3_instruction
*addr
);
599 static inline bool ir3_instr_check_mark(struct ir3_instruction
*instr
)
601 if (instr
->flags
& IR3_INSTR_MARK
)
602 return true; /* already visited */
603 instr
->flags
|= IR3_INSTR_MARK
;
607 void ir3_block_clear_mark(struct ir3_block
*block
);
608 void ir3_clear_mark(struct ir3
*shader
);
610 unsigned ir3_count_instructions(struct ir3
*ir
);
612 void ir3_find_ssa_uses(struct ir3
*ir
, void *mem_ctx
);
614 #include "util/set.h"
615 #define foreach_ssa_use(__use, __instr) \
616 for (struct ir3_instruction *__use = (void *)~0; \
617 __use && (__instr)->uses; __use = NULL) \
618 set_foreach ((__instr)->uses, __entry) \
619 if ((__use = (void *)__entry->key))
621 #define MAX_ARRAYS 16
629 static inline uint32_t regid(int num
, int comp
)
631 return (num
<< 2) | (comp
& 0x3);
634 static inline uint32_t reg_num(struct ir3_register
*reg
)
636 return reg
->num
>> 2;
639 static inline uint32_t reg_comp(struct ir3_register
*reg
)
641 return reg
->num
& 0x3;
644 #define INVALID_REG regid(63, 0)
645 #define VALIDREG(r) ((r) != INVALID_REG)
646 #define CONDREG(r, val) COND(VALIDREG(r), (val))
648 static inline bool is_flow(struct ir3_instruction
*instr
)
650 return (opc_cat(instr
->opc
) == 0);
653 static inline bool is_kill(struct ir3_instruction
*instr
)
655 return instr
->opc
== OPC_KILL
;
658 static inline bool is_nop(struct ir3_instruction
*instr
)
660 return instr
->opc
== OPC_NOP
;
663 static inline bool is_same_type_reg(struct ir3_register
*reg1
,
664 struct ir3_register
*reg2
)
666 unsigned type_reg1
= (reg1
->flags
& (IR3_REG_HIGH
| IR3_REG_HALF
));
667 unsigned type_reg2
= (reg2
->flags
& (IR3_REG_HIGH
| IR3_REG_HALF
));
669 if (type_reg1
^ type_reg2
)
675 /* Is it a non-transformative (ie. not type changing) mov? This can
676 * also include absneg.s/absneg.f, which for the most part can be
677 * treated as a mov (single src argument).
679 static inline bool is_same_type_mov(struct ir3_instruction
*instr
)
681 struct ir3_register
*dst
;
683 switch (instr
->opc
) {
685 if (instr
->cat1
.src_type
!= instr
->cat1
.dst_type
)
687 /* If the type of dest reg and src reg are different,
688 * it shouldn't be considered as same type mov
690 if (!is_same_type_reg(instr
->regs
[0], instr
->regs
[1]))
695 if (instr
->flags
& IR3_INSTR_SAT
)
697 /* If the type of dest reg and src reg are different,
698 * it shouldn't be considered as same type mov
700 if (!is_same_type_reg(instr
->regs
[0], instr
->regs
[1]))
707 dst
= instr
->regs
[0];
709 /* mov's that write to a0 or p0.x are special: */
710 if (dst
->num
== regid(REG_P0
, 0))
712 if (reg_num(dst
) == REG_A0
)
715 if (dst
->flags
& (IR3_REG_RELATIV
| IR3_REG_ARRAY
))
721 /* A move from const, which changes size but not type, can also be
722 * folded into dest instruction in some cases.
724 static inline bool is_const_mov(struct ir3_instruction
*instr
)
726 if (instr
->opc
!= OPC_MOV
)
729 if (!(instr
->regs
[1]->flags
& IR3_REG_CONST
))
732 type_t src_type
= instr
->cat1
.src_type
;
733 type_t dst_type
= instr
->cat1
.dst_type
;
735 return (type_float(src_type
) && type_float(dst_type
)) ||
736 (type_uint(src_type
) && type_uint(dst_type
)) ||
737 (type_sint(src_type
) && type_sint(dst_type
));
740 static inline bool is_alu(struct ir3_instruction
*instr
)
742 return (1 <= opc_cat(instr
->opc
)) && (opc_cat(instr
->opc
) <= 3);
745 static inline bool is_sfu(struct ir3_instruction
*instr
)
747 return (opc_cat(instr
->opc
) == 4);
750 static inline bool is_tex(struct ir3_instruction
*instr
)
752 return (opc_cat(instr
->opc
) == 5);
755 static inline bool is_tex_or_prefetch(struct ir3_instruction
*instr
)
757 return is_tex(instr
) || (instr
->opc
== OPC_META_TEX_PREFETCH
);
760 static inline bool is_mem(struct ir3_instruction
*instr
)
762 return (opc_cat(instr
->opc
) == 6);
765 static inline bool is_barrier(struct ir3_instruction
*instr
)
767 return (opc_cat(instr
->opc
) == 7);
771 is_half(struct ir3_instruction
*instr
)
773 return !!(instr
->regs
[0]->flags
& IR3_REG_HALF
);
777 is_high(struct ir3_instruction
*instr
)
779 return !!(instr
->regs
[0]->flags
& IR3_REG_HIGH
);
783 is_store(struct ir3_instruction
*instr
)
785 /* these instructions, the "destination" register is
786 * actually a source, the address to store to.
788 switch (instr
->opc
) {
803 static inline bool is_load(struct ir3_instruction
*instr
)
805 switch (instr
->opc
) {
815 /* probably some others too.. */
822 static inline bool is_input(struct ir3_instruction
*instr
)
824 /* in some cases, ldlv is used to fetch varying without
825 * interpolation.. fortunately inloc is the first src
826 * register in either case
828 switch (instr
->opc
) {
837 static inline bool is_bool(struct ir3_instruction
*instr
)
839 switch (instr
->opc
) {
849 static inline bool is_meta(struct ir3_instruction
*instr
)
851 return (opc_cat(instr
->opc
) == -1);
854 static inline unsigned dest_regs(struct ir3_instruction
*instr
)
856 if ((instr
->regs_count
== 0) || is_store(instr
) || is_flow(instr
))
859 return util_last_bit(instr
->regs
[0]->wrmask
);
862 static inline bool writes_addr0(struct ir3_instruction
*instr
)
864 if (instr
->regs_count
> 0) {
865 struct ir3_register
*dst
= instr
->regs
[0];
866 return dst
->num
== regid(REG_A0
, 0);
871 static inline bool writes_addr1(struct ir3_instruction
*instr
)
873 if (instr
->regs_count
> 0) {
874 struct ir3_register
*dst
= instr
->regs
[0];
875 return dst
->num
== regid(REG_A0
, 1);
880 static inline bool writes_pred(struct ir3_instruction
*instr
)
882 if (instr
->regs_count
> 0) {
883 struct ir3_register
*dst
= instr
->regs
[0];
884 return reg_num(dst
) == REG_P0
;
889 /* returns defining instruction for reg */
890 /* TODO better name */
891 static inline struct ir3_instruction
*ssa(struct ir3_register
*reg
)
893 if (reg
->flags
& (IR3_REG_SSA
| IR3_REG_ARRAY
)) {
899 static inline bool conflicts(struct ir3_instruction
*a
,
900 struct ir3_instruction
*b
)
902 return (a
&& b
) && (a
!= b
);
905 static inline bool reg_gpr(struct ir3_register
*r
)
907 if (r
->flags
& (IR3_REG_CONST
| IR3_REG_IMMED
))
909 if ((reg_num(r
) == REG_A0
) || (reg_num(r
) == REG_P0
))
914 static inline type_t
half_type(type_t type
)
917 case TYPE_F32
: return TYPE_F16
;
918 case TYPE_U32
: return TYPE_U16
;
919 case TYPE_S32
: return TYPE_S16
;
930 /* some cat2 instructions (ie. those which are not float) can embed an
933 static inline bool ir3_cat2_int(opc_t opc
)
973 static inline bool ir3_cat2_float(opc_t opc
)
996 static inline bool ir3_cat3_float(opc_t opc
)
1009 /* map cat2 instruction to valid abs/neg flags: */
1010 static inline unsigned ir3_cat2_absneg(opc_t opc
)
1027 return IR3_REG_FABS
| IR3_REG_FNEG
;
1048 return IR3_REG_SABS
| IR3_REG_SNEG
;
1062 return IR3_REG_BNOT
;
1069 /* map cat3 instructions to valid abs/neg flags: */
1070 static inline unsigned ir3_cat3_absneg(opc_t opc
)
1077 return IR3_REG_FNEG
;
1089 /* neg *may* work on 3rd src.. */
1099 #define MASK(n) ((1 << (n)) - 1)
1101 /* iterator for an instructions's sources (reg), also returns src #: */
1102 #define foreach_src_n(__srcreg, __n, __instr) \
1103 if ((__instr)->regs_count) \
1104 for (unsigned __cnt = (__instr)->regs_count - 1, __n = 0; __n < __cnt; __n++) \
1105 if ((__srcreg = (__instr)->regs[__n + 1]))
1107 /* iterator for an instructions's sources (reg): */
1108 #define foreach_src(__srcreg, __instr) \
1109 foreach_src_n(__srcreg, __i, __instr)
1111 static inline unsigned __ssa_src_cnt(struct ir3_instruction
*instr
)
1113 unsigned cnt
= instr
->regs_count
+ instr
->deps_count
;
1119 static inline struct ir3_instruction
* __ssa_src_n(struct ir3_instruction
*instr
, unsigned n
)
1121 if (n
== (instr
->regs_count
+ instr
->deps_count
))
1122 return instr
->address
;
1123 if (n
>= instr
->regs_count
)
1124 return instr
->deps
[n
- instr
->regs_count
];
1125 return ssa(instr
->regs
[n
]);
1128 static inline bool __is_false_dep(struct ir3_instruction
*instr
, unsigned n
)
1130 if (n
== (instr
->regs_count
+ instr
->deps_count
))
1132 if (n
>= instr
->regs_count
)
1137 #define __src_cnt(__instr) ((__instr)->address ? (__instr)->regs_count : (__instr)->regs_count - 1)
1139 /* iterator for an instruction's SSA sources (instr), also returns src #: */
1140 #define foreach_ssa_src_n(__srcinst, __n, __instr) \
1141 for (unsigned __cnt = __ssa_src_cnt(__instr), __n = 0; __n < __cnt; __n++) \
1142 if ((__srcinst = __ssa_src_n(__instr, __n)))
1144 /* iterator for an instruction's SSA sources (instr): */
1145 #define foreach_ssa_src(__srcinst, __instr) \
1146 foreach_ssa_src_n(__srcinst, __i, __instr)
1148 /* iterators for shader inputs: */
1149 #define foreach_input_n(__ininstr, __cnt, __ir) \
1150 for (unsigned __cnt = 0; __cnt < (__ir)->inputs_count; __cnt++) \
1151 if ((__ininstr = (__ir)->inputs[__cnt]))
1152 #define foreach_input(__ininstr, __ir) \
1153 foreach_input_n(__ininstr, __i, __ir)
1155 /* iterators for shader outputs: */
1156 #define foreach_output_n(__outinstr, __cnt, __ir) \
1157 for (unsigned __cnt = 0; __cnt < (__ir)->outputs_count; __cnt++) \
1158 if ((__outinstr = (__ir)->outputs[__cnt]))
1159 #define foreach_output(__outinstr, __ir) \
1160 foreach_output_n(__outinstr, __i, __ir)
1162 /* iterators for instructions: */
1163 #define foreach_instr(__instr, __list) \
1164 list_for_each_entry(struct ir3_instruction, __instr, __list, node)
1165 #define foreach_instr_rev(__instr, __list) \
1166 list_for_each_entry_rev(struct ir3_instruction, __instr, __list, node)
1167 #define foreach_instr_safe(__instr, __list) \
1168 list_for_each_entry_safe(struct ir3_instruction, __instr, __list, node)
1170 /* iterators for blocks: */
1171 #define foreach_block(__block, __list) \
1172 list_for_each_entry(struct ir3_block, __block, __list, node)
1173 #define foreach_block_safe(__block, __list) \
1174 list_for_each_entry_safe(struct ir3_block, __block, __list, node)
1176 /* iterators for arrays: */
1177 #define foreach_array(__array, __list) \
1178 list_for_each_entry(struct ir3_array, __array, __list, node)
1181 void ir3_print(struct ir3
*ir
);
1182 void ir3_print_instr(struct ir3_instruction
*instr
);
1184 /* delay calculation: */
1185 int ir3_delayslots(struct ir3_instruction
*assigner
,
1186 struct ir3_instruction
*consumer
, unsigned n
, bool soft
);
1187 unsigned ir3_delay_calc(struct ir3_block
*block
, struct ir3_instruction
*instr
,
1188 bool soft
, bool pred
);
1189 void ir3_remove_nops(struct ir3
*ir
);
1191 /* depth calculation: */
1192 struct ir3_shader_variant
;
1193 void ir3_insert_by_depth(struct ir3_instruction
*instr
, struct list_head
*list
);
1194 void ir3_depth(struct ir3
*ir
, struct ir3_shader_variant
*so
);
1196 /* fp16 conversion folding */
1197 void ir3_cf(struct ir3
*ir
);
1199 /* copy-propagate: */
1200 void ir3_cp(struct ir3
*ir
, struct ir3_shader_variant
*so
);
1202 /* group neighbors and insert mov's to resolve conflicts: */
1203 void ir3_group(struct ir3
*ir
);
1205 /* Sethi–Ullman numbering: */
1206 void ir3_sun(struct ir3
*ir
);
1209 void ir3_sched_add_deps(struct ir3
*ir
);
1210 int ir3_sched(struct ir3
*ir
);
1213 int ir3_postsched(struct ir3_context
*ctx
);
1215 bool ir3_a6xx_fixup_atomic_dests(struct ir3
*ir
, struct ir3_shader_variant
*so
);
1217 /* register assignment: */
1218 struct ir3_ra_reg_set
* ir3_ra_alloc_reg_set(struct ir3_compiler
*compiler
);
1219 int ir3_ra(struct ir3_shader_variant
*v
, struct ir3_instruction
**precolor
, unsigned nprecolor
);
1222 void ir3_legalize(struct ir3
*ir
, struct ir3_shader_variant
*so
, int *max_bary
);
1225 ir3_has_latency_to_hide(struct ir3
*ir
)
1227 /* VS/GS/TCS/TESS co-exist with frag shader invocations, but we don't
1228 * know the nature of the fragment shader. Just assume it will have
1231 if (ir
->type
!= MESA_SHADER_FRAGMENT
)
1234 foreach_block (block
, &ir
->block_list
) {
1235 foreach_instr (instr
, &block
->instr_list
) {
1236 if (is_tex_or_prefetch(instr
))
1239 if (is_load(instr
)) {
1240 switch (instr
->opc
) {
1255 /* ************************************************************************* */
1256 /* instruction helpers */
1258 /* creates SSA src of correct type (ie. half vs full precision) */
1259 static inline struct ir3_register
* __ssa_src(struct ir3_instruction
*instr
,
1260 struct ir3_instruction
*src
, unsigned flags
)
1262 struct ir3_register
*reg
;
1263 if (src
->regs
[0]->flags
& IR3_REG_HALF
)
1264 flags
|= IR3_REG_HALF
;
1265 reg
= ir3_reg_create(instr
, 0, IR3_REG_SSA
| flags
);
1267 reg
->wrmask
= src
->regs
[0]->wrmask
;
1271 static inline struct ir3_register
* __ssa_dst(struct ir3_instruction
*instr
)
1273 struct ir3_register
*reg
= ir3_reg_create(instr
, 0, 0);
1274 reg
->flags
|= IR3_REG_SSA
;
1278 static inline struct ir3_instruction
*
1279 create_immed_typed(struct ir3_block
*block
, uint32_t val
, type_t type
)
1281 struct ir3_instruction
*mov
;
1282 unsigned flags
= (type_size(type
) < 32) ? IR3_REG_HALF
: 0;
1284 mov
= ir3_instr_create(block
, OPC_MOV
);
1285 mov
->cat1
.src_type
= type
;
1286 mov
->cat1
.dst_type
= type
;
1287 __ssa_dst(mov
)->flags
|= flags
;
1288 ir3_reg_create(mov
, 0, IR3_REG_IMMED
| flags
)->uim_val
= val
;
1293 static inline struct ir3_instruction
*
1294 create_immed(struct ir3_block
*block
, uint32_t val
)
1296 return create_immed_typed(block
, val
, TYPE_U32
);
1299 static inline struct ir3_instruction
*
1300 create_uniform_typed(struct ir3_block
*block
, unsigned n
, type_t type
)
1302 struct ir3_instruction
*mov
;
1303 unsigned flags
= (type_size(type
) < 32) ? IR3_REG_HALF
: 0;
1305 mov
= ir3_instr_create(block
, OPC_MOV
);
1306 mov
->cat1
.src_type
= type
;
1307 mov
->cat1
.dst_type
= type
;
1308 __ssa_dst(mov
)->flags
|= flags
;
1309 ir3_reg_create(mov
, n
, IR3_REG_CONST
| flags
);
1314 static inline struct ir3_instruction
*
1315 create_uniform(struct ir3_block
*block
, unsigned n
)
1317 return create_uniform_typed(block
, n
, TYPE_F32
);
1320 static inline struct ir3_instruction
*
1321 create_uniform_indirect(struct ir3_block
*block
, int n
,
1322 struct ir3_instruction
*address
)
1324 struct ir3_instruction
*mov
;
1326 mov
= ir3_instr_create(block
, OPC_MOV
);
1327 mov
->cat1
.src_type
= TYPE_U32
;
1328 mov
->cat1
.dst_type
= TYPE_U32
;
1330 ir3_reg_create(mov
, 0, IR3_REG_CONST
| IR3_REG_RELATIV
)->array
.offset
= n
;
1332 ir3_instr_set_address(mov
, address
);
1337 static inline struct ir3_instruction
*
1338 ir3_MOV(struct ir3_block
*block
, struct ir3_instruction
*src
, type_t type
)
1340 struct ir3_instruction
*instr
= ir3_instr_create(block
, OPC_MOV
);
1342 if (src
->regs
[0]->flags
& IR3_REG_ARRAY
) {
1343 struct ir3_register
*src_reg
= __ssa_src(instr
, src
, IR3_REG_ARRAY
);
1344 src_reg
->array
= src
->regs
[0]->array
;
1346 __ssa_src(instr
, src
, src
->regs
[0]->flags
& IR3_REG_HIGH
);
1348 debug_assert(!(src
->regs
[0]->flags
& IR3_REG_RELATIV
));
1349 instr
->cat1
.src_type
= type
;
1350 instr
->cat1
.dst_type
= type
;
1354 static inline struct ir3_instruction
*
1355 ir3_COV(struct ir3_block
*block
, struct ir3_instruction
*src
,
1356 type_t src_type
, type_t dst_type
)
1358 struct ir3_instruction
*instr
= ir3_instr_create(block
, OPC_MOV
);
1359 unsigned dst_flags
= (type_size(dst_type
) < 32) ? IR3_REG_HALF
: 0;
1360 unsigned src_flags
= (type_size(src_type
) < 32) ? IR3_REG_HALF
: 0;
1362 debug_assert((src
->regs
[0]->flags
& IR3_REG_HALF
) == src_flags
);
1364 __ssa_dst(instr
)->flags
|= dst_flags
;
1365 __ssa_src(instr
, src
, 0);
1366 instr
->cat1
.src_type
= src_type
;
1367 instr
->cat1
.dst_type
= dst_type
;
1368 debug_assert(!(src
->regs
[0]->flags
& IR3_REG_ARRAY
));
1372 static inline struct ir3_instruction
*
1373 ir3_NOP(struct ir3_block
*block
)
1375 return ir3_instr_create(block
, OPC_NOP
);
1378 #define IR3_INSTR_0 0
1380 #define __INSTR0(flag, name, opc) \
1381 static inline struct ir3_instruction * \
1382 ir3_##name(struct ir3_block *block) \
1384 struct ir3_instruction *instr = \
1385 ir3_instr_create(block, opc); \
1386 instr->flags |= flag; \
1389 #define INSTR0F(f, name) __INSTR0(IR3_INSTR_##f, name##_##f, OPC_##name)
1390 #define INSTR0(name) __INSTR0(0, name, OPC_##name)
1392 #define __INSTR1(flag, name, opc) \
1393 static inline struct ir3_instruction * \
1394 ir3_##name(struct ir3_block *block, \
1395 struct ir3_instruction *a, unsigned aflags) \
1397 struct ir3_instruction *instr = \
1398 ir3_instr_create(block, opc); \
1400 __ssa_src(instr, a, aflags); \
1401 instr->flags |= flag; \
1404 #define INSTR1F(f, name) __INSTR1(IR3_INSTR_##f, name##_##f, OPC_##name)
1405 #define INSTR1(name) __INSTR1(0, name, OPC_##name)
1407 #define __INSTR2(flag, name, opc) \
1408 static inline struct ir3_instruction * \
1409 ir3_##name(struct ir3_block *block, \
1410 struct ir3_instruction *a, unsigned aflags, \
1411 struct ir3_instruction *b, unsigned bflags) \
1413 struct ir3_instruction *instr = \
1414 ir3_instr_create(block, opc); \
1416 __ssa_src(instr, a, aflags); \
1417 __ssa_src(instr, b, bflags); \
1418 instr->flags |= flag; \
1421 #define INSTR2F(f, name) __INSTR2(IR3_INSTR_##f, name##_##f, OPC_##name)
1422 #define INSTR2(name) __INSTR2(0, name, OPC_##name)
1424 #define __INSTR3(flag, name, opc) \
1425 static inline struct ir3_instruction * \
1426 ir3_##name(struct ir3_block *block, \
1427 struct ir3_instruction *a, unsigned aflags, \
1428 struct ir3_instruction *b, unsigned bflags, \
1429 struct ir3_instruction *c, unsigned cflags) \
1431 struct ir3_instruction *instr = \
1432 ir3_instr_create2(block, opc, 4); \
1434 __ssa_src(instr, a, aflags); \
1435 __ssa_src(instr, b, bflags); \
1436 __ssa_src(instr, c, cflags); \
1437 instr->flags |= flag; \
1440 #define INSTR3F(f, name) __INSTR3(IR3_INSTR_##f, name##_##f, OPC_##name)
1441 #define INSTR3(name) __INSTR3(0, name, OPC_##name)
1443 #define __INSTR4(flag, name, opc) \
1444 static inline struct ir3_instruction * \
1445 ir3_##name(struct ir3_block *block, \
1446 struct ir3_instruction *a, unsigned aflags, \
1447 struct ir3_instruction *b, unsigned bflags, \
1448 struct ir3_instruction *c, unsigned cflags, \
1449 struct ir3_instruction *d, unsigned dflags) \
1451 struct ir3_instruction *instr = \
1452 ir3_instr_create2(block, opc, 5); \
1454 __ssa_src(instr, a, aflags); \
1455 __ssa_src(instr, b, bflags); \
1456 __ssa_src(instr, c, cflags); \
1457 __ssa_src(instr, d, dflags); \
1458 instr->flags |= flag; \
1461 #define INSTR4F(f, name) __INSTR4(IR3_INSTR_##f, name##_##f, OPC_##name)
1462 #define INSTR4(name) __INSTR4(0, name, OPC_##name)
1464 /* cat0 instructions: */
1475 /* cat2 instructions, most 2 src but some 1 src: */
1523 /* cat3 instructions: */
1541 /* cat4 instructions: */
1553 /* cat5 instructions: */
1562 static inline struct ir3_instruction
*
1563 ir3_SAM(struct ir3_block
*block
, opc_t opc
, type_t type
,
1564 unsigned wrmask
, unsigned flags
, struct ir3_instruction
*samp_tex
,
1565 struct ir3_instruction
*src0
, struct ir3_instruction
*src1
)
1567 struct ir3_instruction
*sam
;
1569 sam
= ir3_instr_create(block
, opc
);
1570 sam
->flags
|= flags
;
1571 __ssa_dst(sam
)->wrmask
= wrmask
;
1572 if (flags
& IR3_INSTR_S2EN
) {
1573 __ssa_src(sam
, samp_tex
, IR3_REG_HALF
);
1576 __ssa_src(sam
, src0
, 0)->wrmask
= (1 << (src0
->regs_count
- 1)) - 1;
1579 __ssa_src(sam
, src1
, 0)->wrmask
=(1 << (src1
->regs_count
- 1)) - 1;
1581 sam
->cat5
.type
= type
;
1586 /* cat6 instructions: */
1601 INSTR2(ATOMIC_CMPXCHG
)
1611 INSTR3F(G
, ATOMIC_ADD
)
1612 INSTR3F(G
, ATOMIC_SUB
)
1613 INSTR3F(G
, ATOMIC_XCHG
)
1614 INSTR3F(G
, ATOMIC_INC
)
1615 INSTR3F(G
, ATOMIC_DEC
)
1616 INSTR3F(G
, ATOMIC_CMPXCHG
)
1617 INSTR3F(G
, ATOMIC_MIN
)
1618 INSTR3F(G
, ATOMIC_MAX
)
1619 INSTR3F(G
, ATOMIC_AND
)
1620 INSTR3F(G
, ATOMIC_OR
)
1621 INSTR3F(G
, ATOMIC_XOR
)
1626 INSTR4F(G
, ATOMIC_ADD
)
1627 INSTR4F(G
, ATOMIC_SUB
)
1628 INSTR4F(G
, ATOMIC_XCHG
)
1629 INSTR4F(G
, ATOMIC_INC
)
1630 INSTR4F(G
, ATOMIC_DEC
)
1631 INSTR4F(G
, ATOMIC_CMPXCHG
)
1632 INSTR4F(G
, ATOMIC_MIN
)
1633 INSTR4F(G
, ATOMIC_MAX
)
1634 INSTR4F(G
, ATOMIC_AND
)
1635 INSTR4F(G
, ATOMIC_OR
)
1636 INSTR4F(G
, ATOMIC_XOR
)
1641 /* cat7 instructions: */
1645 /* meta instructions: */
1646 INSTR0(META_TEX_PREFETCH
);
1648 /* ************************************************************************* */
1649 /* split this out or find some helper to use.. like main/bitset.h.. */
1652 #include "util/bitset.h"
1656 typedef BITSET_DECLARE(regmask_t
, 2 * MAX_REG
);
1659 __regmask_get(regmask_t
*regmask
, struct ir3_register
*reg
, unsigned n
)
1662 /* a6xx+ case, with merged register file, we track things in terms
1663 * of half-precision registers, with a full precisions register
1664 * using two half-precision slots:
1666 if (reg
->flags
& IR3_REG_HALF
) {
1667 return BITSET_TEST(*regmask
, n
);
1670 return BITSET_TEST(*regmask
, n
) || BITSET_TEST(*regmask
, n
+1);
1673 /* pre a6xx case, with separate register file for half and full
1676 if (reg
->flags
& IR3_REG_HALF
)
1678 return BITSET_TEST(*regmask
, n
);
1683 __regmask_set(regmask_t
*regmask
, struct ir3_register
*reg
, unsigned n
)
1686 /* a6xx+ case, with merged register file, we track things in terms
1687 * of half-precision registers, with a full precisions register
1688 * using two half-precision slots:
1690 if (reg
->flags
& IR3_REG_HALF
) {
1691 BITSET_SET(*regmask
, n
);
1694 BITSET_SET(*regmask
, n
);
1695 BITSET_SET(*regmask
, n
+1);
1698 /* pre a6xx case, with separate register file for half and full
1701 if (reg
->flags
& IR3_REG_HALF
)
1703 BITSET_SET(*regmask
, n
);
1707 static inline void regmask_init(regmask_t
*regmask
)
1709 memset(regmask
, 0, sizeof(*regmask
));
1712 static inline void regmask_set(regmask_t
*regmask
, struct ir3_register
*reg
)
1714 if (reg
->flags
& IR3_REG_RELATIV
) {
1715 for (unsigned i
= 0; i
< reg
->size
; i
++)
1716 __regmask_set(regmask
, reg
, reg
->array
.offset
+ i
);
1718 for (unsigned mask
= reg
->wrmask
, n
= reg
->num
; mask
; mask
>>= 1, n
++)
1720 __regmask_set(regmask
, reg
, n
);
1724 static inline void regmask_or(regmask_t
*dst
, regmask_t
*a
, regmask_t
*b
)
1727 for (i
= 0; i
< ARRAY_SIZE(*dst
); i
++)
1728 (*dst
)[i
] = (*a
)[i
] | (*b
)[i
];
1731 static inline bool regmask_get(regmask_t
*regmask
,
1732 struct ir3_register
*reg
)
1734 if (reg
->flags
& IR3_REG_RELATIV
) {
1735 for (unsigned i
= 0; i
< reg
->size
; i
++)
1736 if (__regmask_get(regmask
, reg
, reg
->array
.offset
+ i
))
1739 for (unsigned mask
= reg
->wrmask
, n
= reg
->num
; mask
; mask
>>= 1, n
++)
1741 if (__regmask_get(regmask
, reg
, n
))
1747 /* ************************************************************************* */