2 * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 #include "compiler/shader_enums.h"
32 #include "util/bitscan.h"
33 #include "util/list.h"
35 #include "util/u_debug.h"
37 #include "instr-a3xx.h"
39 /* low level intermediate representation of an adreno shader program */
43 struct ir3_instruction
;
49 uint16_t instrs_count
; /* expanded to account for rpt's */
50 uint16_t nops_count
; /* # of nop instructions, including nopN */
51 /* NOTE: max_reg, etc, does not include registers not touched
52 * by the shader (ie. vertex fetched via VFD_DECODE but not
55 int8_t max_reg
; /* highest GPR # used by shader */
59 /* number of sync bits: */
62 uint16_t last_baryf
; /* instruction # of last varying fetch */
67 IR3_REG_CONST
= 0x001,
68 IR3_REG_IMMED
= 0x002,
70 /* high registers are used for some things in compute shaders,
71 * for example. Seems to be for things that are global to all
72 * threads in a wave, so possibly these are global/shared by
73 * all the threads in the wave?
76 IR3_REG_RELATIV
= 0x010,
78 /* Most instructions, it seems, can do float abs/neg but not
79 * integer. The CP pass needs to know what is intended (int or
80 * float) in order to do the right thing. For this reason the
81 * abs/neg flags are split out into float and int variants. In
82 * addition, .b (bitwise) operations, the negate is actually a
83 * bitwise not, so split that out into a new flag to make it
92 IR3_REG_POS_INF
= 0x1000,
93 /* (ei) flag, end-input? Set on last bary, presumably to signal
94 * that the shader needs no more input:
97 /* meta-flags, for intermediate stages of IR, ie.
98 * before register assignment is done:
100 IR3_REG_SSA
= 0x4000, /* 'instr' is ptr to assigning instr */
101 IR3_REG_ARRAY
= 0x8000,
105 /* used for cat5 instructions, but also for internal/IR level
106 * tracking of what registers are read/written by an instruction.
107 * wrmask may be a bad name since it is used to represent both
108 * src and dst that touch multiple adjacent registers.
110 unsigned wrmask
: 16; /* up to vec16 */
112 /* for relative addressing, 32bits for array size is too small,
113 * but otoh we don't need to deal with disjoint sets, so instead
114 * use a simple size field (number of scalar components).
116 * Note the size field isn't important for relative const (since
117 * we don't have to do register allocation for constants).
121 bool merged
: 1; /* half-regs conflict with full regs (ie >= a6xx) */
124 * the component is in the low two bits of the reg #, so
125 * rN.x becomes: (N << 2) | x
140 /* For IR3_REG_SSA, src registers contain ptr back to assigning
143 * For IR3_REG_ARRAY, the pointer is back to the last dependent
144 * array access (although the net effect is the same, it points
145 * back to a previous instruction that we depend on).
147 struct ir3_instruction
*instr
;
151 * Stupid/simple growable array implementation:
153 #define DECLARE_ARRAY(type, name) \
154 unsigned name ## _count, name ## _sz; \
157 #define array_insert(ctx, arr, val) do { \
158 if (arr ## _count == arr ## _sz) { \
159 arr ## _sz = MAX2(2 * arr ## _sz, 16); \
160 arr = reralloc_size(ctx, arr, arr ## _sz * sizeof(arr[0])); \
162 arr[arr ##_count++] = val; \
165 struct ir3_instruction
{
166 struct ir3_block
*block
;
169 /* (sy) flag is set on first instruction, and after sample
170 * instructions (probably just on RAW hazard).
172 IR3_INSTR_SY
= 0x001,
173 /* (ss) flag is set on first instruction, and first instruction
174 * to depend on the result of "long" instructions (RAW hazard):
176 * rcp, rsq, log2, exp2, sin, cos, sqrt
178 * It seems to synchronize until all in-flight instructions are
179 * completed, for example:
182 * add.f hr2.z, (neg)hr2.z, hc0.y
183 * mul.f hr2.w, (neg)hr2.y, (neg)hr2.y
186 * mad.f16 hr2.w, hr2.z, hr2.z, hr2.w
188 * mad.f16 hr2.w, (neg)hr0.w, (neg)hr0.w, hr2.w
189 * (ss)(rpt2)mul.f hr1.x, (r)hr1.x, hr1.w
190 * (rpt2)mul.f hr0.x, (neg)(r)hr0.x, hr2.x
192 * The last mul.f does not have (ss) set, presumably because the
193 * (ss) on the previous instruction does the job.
195 * The blob driver also seems to set it on WAR hazards, although
196 * not really clear if this is needed or just blob compiler being
197 * sloppy. So far I haven't found a case where removing the (ss)
198 * causes problems for WAR hazard, but I could just be getting
202 * (ss)(rpt2)mad.f32 r3.y, (r)c9.x, r1.x, (r)r3.z
205 IR3_INSTR_SS
= 0x002,
206 /* (jp) flag is set on jump targets:
208 IR3_INSTR_JP
= 0x004,
209 IR3_INSTR_UL
= 0x008,
210 IR3_INSTR_3D
= 0x010,
215 IR3_INSTR_S2EN
= 0x200,
217 IR3_INSTR_SAT
= 0x800,
218 /* meta-flags, for intermediate stages of IR, ie.
219 * before register assignment is done:
221 IR3_INSTR_MARK
= 0x1000,
222 IR3_INSTR_UNUSED
= 0x2000,
230 struct ir3_register
**regs
;
236 struct ir3_block
*target
;
239 type_t src_type
, dst_type
;
259 int iim_val
: 3; /* for ldgb/stgb, # of components */
264 unsigned w
: 1; /* write */
265 unsigned r
: 1; /* read */
266 unsigned l
: 1; /* local */
267 unsigned g
: 1; /* global */
269 /* for meta-instructions, just used to hold extra data
270 * before instruction scheduling, etc
273 int off
; /* component/offset */
276 /* for output collects, this maps back to the entry in the
277 * ir3_shader_variant::outputs table.
283 unsigned input_offset
;
286 /* maps back to entry in ir3_shader_variant::inputs table: */
288 /* for sysvals, identifies the sysval type. Mostly so we can
289 * identify the special cases where a sysval should not be DCE'd
290 * (currently, just pre-fs texture fetch)
292 gl_system_value sysval
;
296 /* transient values used during various algorithms: */
298 /* The instruction depth is the max dependency distance to output.
300 * You can also think of it as the "cost", if we did any sort of
301 * optimization for register footprint. Ie. a value that is just
302 * result of moving a const to a reg would have a low cost, so to
303 * it could make sense to duplicate the instruction at various
304 * points where the result is needed to reduce register footprint.
307 /* When we get to the RA stage, we no longer need depth, but
308 * we do need instruction's position/name:
316 /* used for per-pass extra instruction data.
318 * TODO we should remove the per-pass data like this and 'use_count'
319 * and do something similar to what RA does w/ ir3_ra_instr_data..
320 * ie. use the ir3_count_instructions pass, and then use instr->ip
321 * to index into a table of pass-private data.
325 int sun
; /* Sethi–Ullman number, used by sched */
326 int use_count
; /* currently just updated/used by cp */
328 /* Used during CP and RA stages. For collect and shader inputs/
329 * outputs where we need a sequence of consecutive registers,
330 * keep track of each src instructions left (ie 'n-1') and right
331 * (ie 'n+1') neighbor. The front-end must insert enough mov's
332 * to ensure that each instruction has at most one left and at
333 * most one right neighbor. During the copy-propagation pass,
334 * we only remove mov's when we can preserve this constraint.
335 * And during the RA stage, we use the neighbor information to
336 * allocate a block of registers in one shot.
338 * TODO: maybe just add something like:
339 * struct ir3_instruction_ref {
340 * struct ir3_instruction *instr;
344 * Or can we get away without the refcnt stuff? It seems like
345 * it should be overkill.. the problem is if, potentially after
346 * already eliminating some mov's, if you have a single mov that
347 * needs to be grouped with it's neighbors in two different
348 * places (ex. shader output and a collect).
351 struct ir3_instruction
*left
, *right
;
352 uint16_t left_cnt
, right_cnt
;
355 /* an instruction can reference at most one address register amongst
356 * it's src/dst registers. Beyond that, you need to insert mov's.
358 * NOTE: do not write this directly, use ir3_instr_set_address()
360 struct ir3_instruction
*address
;
362 /* Tracking for additional dependent instructions. Used to handle
363 * barriers, WAR hazards for arrays/SSBOs/etc.
365 DECLARE_ARRAY(struct ir3_instruction
*, deps
);
368 * From PoV of instruction scheduling, not execution (ie. ignores global/
369 * local distinction):
370 * shared image atomic SSBO everything
371 * barrier()/ - R/W R/W R/W R/W X
372 * groupMemoryBarrier()
373 * memoryBarrier() - R/W R/W
374 * (but only images declared coherent?)
375 * memoryBarrierAtomic() - R/W
376 * memoryBarrierBuffer() - R/W
377 * memoryBarrierImage() - R/W
378 * memoryBarrierShared() - R/W
380 * TODO I think for SSBO/image/shared, in cases where we can determine
381 * which variable is accessed, we don't need to care about accesses to
382 * different variables (unless declared coherent??)
385 IR3_BARRIER_EVERYTHING
= 1 << 0,
386 IR3_BARRIER_SHARED_R
= 1 << 1,
387 IR3_BARRIER_SHARED_W
= 1 << 2,
388 IR3_BARRIER_IMAGE_R
= 1 << 3,
389 IR3_BARRIER_IMAGE_W
= 1 << 4,
390 IR3_BARRIER_BUFFER_R
= 1 << 5,
391 IR3_BARRIER_BUFFER_W
= 1 << 6,
392 IR3_BARRIER_ARRAY_R
= 1 << 7,
393 IR3_BARRIER_ARRAY_W
= 1 << 8,
394 } barrier_class
, barrier_conflict
;
396 /* Entry in ir3_block's instruction list: */
397 struct list_head node
;
404 static inline struct ir3_instruction
*
405 ir3_neighbor_first(struct ir3_instruction
*instr
)
408 while (instr
->cp
.left
) {
409 instr
= instr
->cp
.left
;
410 if (++cnt
> 0xffff) {
418 static inline int ir3_neighbor_count(struct ir3_instruction
*instr
)
422 debug_assert(!instr
->cp
.left
);
424 while (instr
->cp
.right
) {
426 instr
= instr
->cp
.right
;
437 struct ir3_compiler
*compiler
;
438 gl_shader_stage type
;
440 DECLARE_ARRAY(struct ir3_instruction
*, inputs
);
441 DECLARE_ARRAY(struct ir3_instruction
*, outputs
);
443 /* Track bary.f (and ldlv) instructions.. this is needed in
444 * scheduling to ensure that all varying fetches happen before
445 * any potential kill instructions. The hw gets grumpy if all
446 * threads in a group are killed before the last bary.f gets
447 * a chance to signal end of input (ei).
449 DECLARE_ARRAY(struct ir3_instruction
*, baryfs
);
451 /* Track all indirect instructions (read and write). To avoid
452 * deadlock scenario where an address register gets scheduled,
453 * but other dependent src instructions cannot be scheduled due
454 * to dependency on a *different* address register value, the
455 * scheduler needs to ensure that all dependencies other than
456 * the instruction other than the address register are scheduled
457 * before the one that writes the address register. Having a
458 * convenient list of instructions that reference some address
459 * register simplifies this.
461 DECLARE_ARRAY(struct ir3_instruction
*, indirects
);
463 /* and same for instructions that consume predicate register: */
464 DECLARE_ARRAY(struct ir3_instruction
*, predicates
);
466 /* Track texture sample instructions which need texture state
467 * patched in (for astc-srgb workaround):
469 DECLARE_ARRAY(struct ir3_instruction
*, astc_srgb
);
471 /* List of blocks: */
472 struct list_head block_list
;
474 /* List of ir3_array's: */
475 struct list_head array_list
;
477 unsigned max_sun
; /* max Sethi–Ullman number */
480 unsigned block_count
, instr_count
;
485 struct list_head node
;
489 struct nir_register
*r
;
491 /* To avoid array write's from getting DCE'd, keep track of the
492 * most recent write. Any array access depends on the most
493 * recent write. This way, nothing depends on writes after the
494 * last read. But all the writes that happen before that have
495 * something depending on them
497 struct ir3_instruction
*last_write
;
499 /* extra stuff used in RA pass: */
500 unsigned base
; /* base vreg name */
501 unsigned reg
; /* base physical reg */
502 uint16_t start_ip
, end_ip
;
505 struct ir3_array
* ir3_lookup_array(struct ir3
*ir
, unsigned id
);
508 struct list_head node
;
511 const struct nir_block
*nblock
;
513 struct list_head instr_list
; /* list of ir3_instruction */
515 /* each block has either one or two successors.. in case of
516 * two successors, 'condition' decides which one to follow.
517 * A block preceding an if/else has two successors.
519 struct ir3_instruction
*condition
;
520 struct ir3_block
*successors
[2];
522 struct set
*predecessors
; /* set of ir3_block */
524 uint16_t start_ip
, end_ip
;
526 /* Track instructions which do not write a register but other-
527 * wise must not be discarded (such as kill, stg, etc)
529 DECLARE_ARRAY(struct ir3_instruction
*, keeps
);
531 /* used for per-pass extra block data. Mainly used right
532 * now in RA step to track livein/liveout.
541 static inline uint32_t
542 block_id(struct ir3_block
*block
)
545 return block
->serialno
;
547 return (uint32_t)(unsigned long)block
;
551 struct ir3
* ir3_create(struct ir3_compiler
*compiler
, gl_shader_stage type
);
552 void ir3_destroy(struct ir3
*shader
);
553 void * ir3_assemble(struct ir3
*shader
,
554 struct ir3_info
*info
, uint32_t gpu_id
);
555 void * ir3_alloc(struct ir3
*shader
, int sz
);
557 struct ir3_block
* ir3_block_create(struct ir3
*shader
);
559 struct ir3_instruction
* ir3_instr_create(struct ir3_block
*block
, opc_t opc
);
560 struct ir3_instruction
* ir3_instr_create2(struct ir3_block
*block
,
561 opc_t opc
, int nreg
);
562 struct ir3_instruction
* ir3_instr_clone(struct ir3_instruction
*instr
);
563 void ir3_instr_add_dep(struct ir3_instruction
*instr
, struct ir3_instruction
*dep
);
564 const char *ir3_instr_name(struct ir3_instruction
*instr
);
566 struct ir3_register
* ir3_reg_create(struct ir3_instruction
*instr
,
568 struct ir3_register
* ir3_reg_clone(struct ir3
*shader
,
569 struct ir3_register
*reg
);
571 void ir3_instr_set_address(struct ir3_instruction
*instr
,
572 struct ir3_instruction
*addr
);
574 static inline bool ir3_instr_check_mark(struct ir3_instruction
*instr
)
576 if (instr
->flags
& IR3_INSTR_MARK
)
577 return true; /* already visited */
578 instr
->flags
|= IR3_INSTR_MARK
;
582 void ir3_block_clear_mark(struct ir3_block
*block
);
583 void ir3_clear_mark(struct ir3
*shader
);
585 unsigned ir3_count_instructions(struct ir3
*ir
);
587 static inline int ir3_instr_regno(struct ir3_instruction
*instr
,
588 struct ir3_register
*reg
)
591 for (i
= 0; i
< instr
->regs_count
; i
++)
592 if (reg
== instr
->regs
[i
])
598 #define MAX_ARRAYS 16
606 static inline uint32_t regid(int num
, int comp
)
608 return (num
<< 2) | (comp
& 0x3);
611 static inline uint32_t reg_num(struct ir3_register
*reg
)
613 return reg
->num
>> 2;
616 static inline uint32_t reg_comp(struct ir3_register
*reg
)
618 return reg
->num
& 0x3;
621 #define INVALID_REG regid(63, 0)
622 #define VALIDREG(r) ((r) != INVALID_REG)
623 #define CONDREG(r, val) COND(VALIDREG(r), (val))
625 static inline bool is_flow(struct ir3_instruction
*instr
)
627 return (opc_cat(instr
->opc
) == 0);
630 static inline bool is_kill(struct ir3_instruction
*instr
)
632 return instr
->opc
== OPC_KILL
;
635 static inline bool is_nop(struct ir3_instruction
*instr
)
637 return instr
->opc
== OPC_NOP
;
640 static inline bool is_same_type_reg(struct ir3_register
*reg1
,
641 struct ir3_register
*reg2
)
643 unsigned type_reg1
= (reg1
->flags
& (IR3_REG_HIGH
| IR3_REG_HALF
));
644 unsigned type_reg2
= (reg2
->flags
& (IR3_REG_HIGH
| IR3_REG_HALF
));
646 if (type_reg1
^ type_reg2
)
652 /* Is it a non-transformative (ie. not type changing) mov? This can
653 * also include absneg.s/absneg.f, which for the most part can be
654 * treated as a mov (single src argument).
656 static inline bool is_same_type_mov(struct ir3_instruction
*instr
)
658 struct ir3_register
*dst
;
660 switch (instr
->opc
) {
662 if (instr
->cat1
.src_type
!= instr
->cat1
.dst_type
)
664 /* If the type of dest reg and src reg are different,
665 * it shouldn't be considered as same type mov
667 if (!is_same_type_reg(instr
->regs
[0], instr
->regs
[1]))
672 if (instr
->flags
& IR3_INSTR_SAT
)
674 /* If the type of dest reg and src reg are different,
675 * it shouldn't be considered as same type mov
677 if (!is_same_type_reg(instr
->regs
[0], instr
->regs
[1]))
684 dst
= instr
->regs
[0];
686 /* mov's that write to a0.x or p0.x are special: */
687 if (dst
->num
== regid(REG_P0
, 0))
689 if (dst
->num
== regid(REG_A0
, 0))
692 if (dst
->flags
& (IR3_REG_RELATIV
| IR3_REG_ARRAY
))
698 static inline bool is_alu(struct ir3_instruction
*instr
)
700 return (1 <= opc_cat(instr
->opc
)) && (opc_cat(instr
->opc
) <= 3);
703 static inline bool is_sfu(struct ir3_instruction
*instr
)
705 return (opc_cat(instr
->opc
) == 4);
708 static inline bool is_tex(struct ir3_instruction
*instr
)
710 return (opc_cat(instr
->opc
) == 5);
713 static inline bool is_mem(struct ir3_instruction
*instr
)
715 return (opc_cat(instr
->opc
) == 6);
718 static inline bool is_barrier(struct ir3_instruction
*instr
)
720 return (opc_cat(instr
->opc
) == 7);
724 is_store(struct ir3_instruction
*instr
)
726 /* these instructions, the "destination" register is
727 * actually a source, the address to store to.
729 switch (instr
->opc
) {
744 static inline bool is_load(struct ir3_instruction
*instr
)
746 switch (instr
->opc
) {
756 /* probably some others too.. */
763 static inline bool is_input(struct ir3_instruction
*instr
)
765 /* in some cases, ldlv is used to fetch varying without
766 * interpolation.. fortunately inloc is the first src
767 * register in either case
769 switch (instr
->opc
) {
778 static inline bool is_bool(struct ir3_instruction
*instr
)
780 switch (instr
->opc
) {
790 static inline bool is_meta(struct ir3_instruction
*instr
)
792 return (opc_cat(instr
->opc
) == -1);
795 static inline unsigned dest_regs(struct ir3_instruction
*instr
)
797 if ((instr
->regs_count
== 0) || is_store(instr
) || is_flow(instr
))
800 return util_last_bit(instr
->regs
[0]->wrmask
);
803 static inline bool writes_addr(struct ir3_instruction
*instr
)
805 if (instr
->regs_count
> 0) {
806 struct ir3_register
*dst
= instr
->regs
[0];
807 return reg_num(dst
) == REG_A0
;
812 static inline bool writes_pred(struct ir3_instruction
*instr
)
814 if (instr
->regs_count
> 0) {
815 struct ir3_register
*dst
= instr
->regs
[0];
816 return reg_num(dst
) == REG_P0
;
821 /* returns defining instruction for reg */
822 /* TODO better name */
823 static inline struct ir3_instruction
*ssa(struct ir3_register
*reg
)
825 if (reg
->flags
& (IR3_REG_SSA
| IR3_REG_ARRAY
)) {
831 static inline bool conflicts(struct ir3_instruction
*a
,
832 struct ir3_instruction
*b
)
834 return (a
&& b
) && (a
!= b
);
837 static inline bool reg_gpr(struct ir3_register
*r
)
839 if (r
->flags
& (IR3_REG_CONST
| IR3_REG_IMMED
))
841 if ((reg_num(r
) == REG_A0
) || (reg_num(r
) == REG_P0
))
846 static inline type_t
half_type(type_t type
)
849 case TYPE_F32
: return TYPE_F16
;
850 case TYPE_U32
: return TYPE_U16
;
851 case TYPE_S32
: return TYPE_S16
;
862 /* some cat2 instructions (ie. those which are not float) can embed an
865 static inline bool ir3_cat2_int(opc_t opc
)
905 static inline bool ir3_cat2_float(opc_t opc
)
928 static inline bool ir3_cat3_float(opc_t opc
)
941 /* map cat2 instruction to valid abs/neg flags: */
942 static inline unsigned ir3_cat2_absneg(opc_t opc
)
959 return IR3_REG_FABS
| IR3_REG_FNEG
;
980 return IR3_REG_SABS
| IR3_REG_SNEG
;
1001 /* map cat3 instructions to valid abs/neg flags: */
1002 static inline unsigned ir3_cat3_absneg(opc_t opc
)
1009 return IR3_REG_FNEG
;
1021 /* neg *may* work on 3rd src.. */
1031 #define MASK(n) ((1 << (n)) - 1)
1033 /* iterator for an instructions's sources (reg), also returns src #: */
1034 #define foreach_src_n(__srcreg, __n, __instr) \
1035 if ((__instr)->regs_count) \
1036 for (unsigned __cnt = (__instr)->regs_count - 1, __n = 0; __n < __cnt; __n++) \
1037 if ((__srcreg = (__instr)->regs[__n + 1]))
1039 /* iterator for an instructions's sources (reg): */
1040 #define foreach_src(__srcreg, __instr) \
1041 foreach_src_n(__srcreg, __i, __instr)
1043 static inline unsigned __ssa_src_cnt(struct ir3_instruction
*instr
)
1045 unsigned cnt
= instr
->regs_count
+ instr
->deps_count
;
1051 static inline struct ir3_instruction
* __ssa_src_n(struct ir3_instruction
*instr
, unsigned n
)
1053 if (n
== (instr
->regs_count
+ instr
->deps_count
))
1054 return instr
->address
;
1055 if (n
>= instr
->regs_count
)
1056 return instr
->deps
[n
- instr
->regs_count
];
1057 return ssa(instr
->regs
[n
]);
1060 static inline bool __is_false_dep(struct ir3_instruction
*instr
, unsigned n
)
1062 if (n
== (instr
->regs_count
+ instr
->deps_count
))
1064 if (n
>= instr
->regs_count
)
1069 #define __src_cnt(__instr) ((__instr)->address ? (__instr)->regs_count : (__instr)->regs_count - 1)
1071 /* iterator for an instruction's SSA sources (instr), also returns src #: */
1072 #define foreach_ssa_src_n(__srcinst, __n, __instr) \
1073 for (unsigned __cnt = __ssa_src_cnt(__instr), __n = 0; __n < __cnt; __n++) \
1074 if ((__srcinst = __ssa_src_n(__instr, __n)))
1076 /* iterator for an instruction's SSA sources (instr): */
1077 #define foreach_ssa_src(__srcinst, __instr) \
1078 foreach_ssa_src_n(__srcinst, __i, __instr)
1080 /* iterators for shader inputs: */
1081 #define foreach_input_n(__ininstr, __cnt, __ir) \
1082 for (unsigned __cnt = 0; __cnt < (__ir)->inputs_count; __cnt++) \
1083 if ((__ininstr = (__ir)->inputs[__cnt]))
1084 #define foreach_input(__ininstr, __ir) \
1085 foreach_input_n(__ininstr, __i, __ir)
1087 /* iterators for shader outputs: */
1088 #define foreach_output_n(__outinstr, __cnt, __ir) \
1089 for (unsigned __cnt = 0; __cnt < (__ir)->outputs_count; __cnt++) \
1090 if ((__outinstr = (__ir)->outputs[__cnt]))
1091 #define foreach_output(__outinstr, __ir) \
1092 foreach_output_n(__outinstr, __i, __ir)
1094 /* iterators for instructions: */
1095 #define foreach_instr(__instr, __list) \
1096 list_for_each_entry(struct ir3_instruction, __instr, __list, node)
1097 #define foreach_instr_rev(__instr, __list) \
1098 list_for_each_entry_rev(struct ir3_instruction, __instr, __list, node)
1099 #define foreach_instr_safe(__instr, __list) \
1100 list_for_each_entry_safe(struct ir3_instruction, __instr, __list, node)
1102 /* iterators for blocks: */
1103 #define foreach_block(__block, __list) \
1104 list_for_each_entry(struct ir3_block, __block, __list, node)
1105 #define foreach_block_safe(__block, __list) \
1106 list_for_each_entry_safe(struct ir3_block, __block, __list, node)
1108 /* iterators for arrays: */
1109 #define foreach_array(__array, __list) \
1110 list_for_each_entry(struct ir3_array, __array, __list, node)
1113 void ir3_print(struct ir3
*ir
);
1114 void ir3_print_instr(struct ir3_instruction
*instr
);
1116 /* delay calculation: */
1117 int ir3_delayslots(struct ir3_instruction
*assigner
,
1118 struct ir3_instruction
*consumer
, unsigned n
);
1119 unsigned ir3_delay_calc(struct ir3_block
*block
, struct ir3_instruction
*instr
,
1120 bool soft
, bool pred
);
1121 void ir3_remove_nops(struct ir3
*ir
);
1123 /* depth calculation: */
1124 struct ir3_shader_variant
;
1125 void ir3_insert_by_depth(struct ir3_instruction
*instr
, struct list_head
*list
);
1126 void ir3_depth(struct ir3
*ir
, struct ir3_shader_variant
*so
);
1128 /* copy-propagate: */
1129 void ir3_cp(struct ir3
*ir
, struct ir3_shader_variant
*so
);
1131 /* group neighbors and insert mov's to resolve conflicts: */
1132 void ir3_group(struct ir3
*ir
);
1134 /* Sethi–Ullman numbering: */
1135 void ir3_sun(struct ir3
*ir
);
1138 void ir3_sched_add_deps(struct ir3
*ir
);
1139 int ir3_sched(struct ir3
*ir
);
1141 bool ir3_a6xx_fixup_atomic_dests(struct ir3
*ir
, struct ir3_shader_variant
*so
);
1143 /* register assignment: */
1144 struct ir3_ra_reg_set
* ir3_ra_alloc_reg_set(struct ir3_compiler
*compiler
);
1145 int ir3_ra(struct ir3_shader_variant
*v
, struct ir3_instruction
**precolor
, unsigned nprecolor
);
1148 void ir3_legalize(struct ir3
*ir
, struct ir3_shader_variant
*so
, int *max_bary
);
1150 /* ************************************************************************* */
1151 /* instruction helpers */
1153 /* creates SSA src of correct type (ie. half vs full precision) */
1154 static inline struct ir3_register
* __ssa_src(struct ir3_instruction
*instr
,
1155 struct ir3_instruction
*src
, unsigned flags
)
1157 struct ir3_register
*reg
;
1158 if (src
->regs
[0]->flags
& IR3_REG_HALF
)
1159 flags
|= IR3_REG_HALF
;
1160 reg
= ir3_reg_create(instr
, 0, IR3_REG_SSA
| flags
);
1162 reg
->wrmask
= src
->regs
[0]->wrmask
;
1166 static inline struct ir3_register
* __ssa_dst(struct ir3_instruction
*instr
)
1168 struct ir3_register
*reg
= ir3_reg_create(instr
, 0, 0);
1169 reg
->flags
|= IR3_REG_SSA
;
1173 static inline struct ir3_instruction
*
1174 create_immed_typed(struct ir3_block
*block
, uint32_t val
, type_t type
)
1176 struct ir3_instruction
*mov
;
1177 unsigned flags
= (type_size(type
) < 32) ? IR3_REG_HALF
: 0;
1179 mov
= ir3_instr_create(block
, OPC_MOV
);
1180 mov
->cat1
.src_type
= type
;
1181 mov
->cat1
.dst_type
= type
;
1182 __ssa_dst(mov
)->flags
|= flags
;
1183 ir3_reg_create(mov
, 0, IR3_REG_IMMED
)->uim_val
= val
;
1188 static inline struct ir3_instruction
*
1189 create_immed(struct ir3_block
*block
, uint32_t val
)
1191 return create_immed_typed(block
, val
, TYPE_U32
);
1194 static inline struct ir3_instruction
*
1195 create_uniform_typed(struct ir3_block
*block
, unsigned n
, type_t type
)
1197 struct ir3_instruction
*mov
;
1198 unsigned flags
= (type_size(type
) < 32) ? IR3_REG_HALF
: 0;
1200 mov
= ir3_instr_create(block
, OPC_MOV
);
1201 mov
->cat1
.src_type
= type
;
1202 mov
->cat1
.dst_type
= type
;
1203 __ssa_dst(mov
)->flags
|= flags
;
1204 ir3_reg_create(mov
, n
, IR3_REG_CONST
| flags
);
1209 static inline struct ir3_instruction
*
1210 create_uniform(struct ir3_block
*block
, unsigned n
)
1212 return create_uniform_typed(block
, n
, TYPE_F32
);
1215 static inline struct ir3_instruction
*
1216 create_uniform_indirect(struct ir3_block
*block
, int n
,
1217 struct ir3_instruction
*address
)
1219 struct ir3_instruction
*mov
;
1221 mov
= ir3_instr_create(block
, OPC_MOV
);
1222 mov
->cat1
.src_type
= TYPE_U32
;
1223 mov
->cat1
.dst_type
= TYPE_U32
;
1225 ir3_reg_create(mov
, 0, IR3_REG_CONST
| IR3_REG_RELATIV
)->array
.offset
= n
;
1227 ir3_instr_set_address(mov
, address
);
1232 static inline struct ir3_instruction
*
1233 ir3_MOV(struct ir3_block
*block
, struct ir3_instruction
*src
, type_t type
)
1235 struct ir3_instruction
*instr
= ir3_instr_create(block
, OPC_MOV
);
1237 if (src
->regs
[0]->flags
& IR3_REG_ARRAY
) {
1238 struct ir3_register
*src_reg
= __ssa_src(instr
, src
, IR3_REG_ARRAY
);
1239 src_reg
->array
= src
->regs
[0]->array
;
1241 __ssa_src(instr
, src
, src
->regs
[0]->flags
& IR3_REG_HIGH
);
1243 debug_assert(!(src
->regs
[0]->flags
& IR3_REG_RELATIV
));
1244 instr
->cat1
.src_type
= type
;
1245 instr
->cat1
.dst_type
= type
;
1249 static inline struct ir3_instruction
*
1250 ir3_COV(struct ir3_block
*block
, struct ir3_instruction
*src
,
1251 type_t src_type
, type_t dst_type
)
1253 struct ir3_instruction
*instr
= ir3_instr_create(block
, OPC_MOV
);
1254 unsigned dst_flags
= (type_size(dst_type
) < 32) ? IR3_REG_HALF
: 0;
1255 unsigned src_flags
= (type_size(src_type
) < 32) ? IR3_REG_HALF
: 0;
1257 debug_assert((src
->regs
[0]->flags
& IR3_REG_HALF
) == src_flags
);
1259 __ssa_dst(instr
)->flags
|= dst_flags
;
1260 __ssa_src(instr
, src
, 0);
1261 instr
->cat1
.src_type
= src_type
;
1262 instr
->cat1
.dst_type
= dst_type
;
1263 debug_assert(!(src
->regs
[0]->flags
& IR3_REG_ARRAY
));
1267 static inline struct ir3_instruction
*
1268 ir3_NOP(struct ir3_block
*block
)
1270 return ir3_instr_create(block
, OPC_NOP
);
1273 #define IR3_INSTR_0 0
1275 #define __INSTR0(flag, name, opc) \
1276 static inline struct ir3_instruction * \
1277 ir3_##name(struct ir3_block *block) \
1279 struct ir3_instruction *instr = \
1280 ir3_instr_create(block, opc); \
1281 instr->flags |= flag; \
1284 #define INSTR0F(f, name) __INSTR0(IR3_INSTR_##f, name##_##f, OPC_##name)
1285 #define INSTR0(name) __INSTR0(0, name, OPC_##name)
1287 #define __INSTR1(flag, name, opc) \
1288 static inline struct ir3_instruction * \
1289 ir3_##name(struct ir3_block *block, \
1290 struct ir3_instruction *a, unsigned aflags) \
1292 struct ir3_instruction *instr = \
1293 ir3_instr_create(block, opc); \
1295 __ssa_src(instr, a, aflags); \
1296 instr->flags |= flag; \
1299 #define INSTR1F(f, name) __INSTR1(IR3_INSTR_##f, name##_##f, OPC_##name)
1300 #define INSTR1(name) __INSTR1(0, name, OPC_##name)
1302 #define __INSTR2(flag, name, opc) \
1303 static inline struct ir3_instruction * \
1304 ir3_##name(struct ir3_block *block, \
1305 struct ir3_instruction *a, unsigned aflags, \
1306 struct ir3_instruction *b, unsigned bflags) \
1308 struct ir3_instruction *instr = \
1309 ir3_instr_create(block, opc); \
1311 __ssa_src(instr, a, aflags); \
1312 __ssa_src(instr, b, bflags); \
1313 instr->flags |= flag; \
1316 #define INSTR2F(f, name) __INSTR2(IR3_INSTR_##f, name##_##f, OPC_##name)
1317 #define INSTR2(name) __INSTR2(0, name, OPC_##name)
1319 #define __INSTR3(flag, name, opc) \
1320 static inline struct ir3_instruction * \
1321 ir3_##name(struct ir3_block *block, \
1322 struct ir3_instruction *a, unsigned aflags, \
1323 struct ir3_instruction *b, unsigned bflags, \
1324 struct ir3_instruction *c, unsigned cflags) \
1326 struct ir3_instruction *instr = \
1327 ir3_instr_create2(block, opc, 4); \
1329 __ssa_src(instr, a, aflags); \
1330 __ssa_src(instr, b, bflags); \
1331 __ssa_src(instr, c, cflags); \
1332 instr->flags |= flag; \
1335 #define INSTR3F(f, name) __INSTR3(IR3_INSTR_##f, name##_##f, OPC_##name)
1336 #define INSTR3(name) __INSTR3(0, name, OPC_##name)
1338 #define __INSTR4(flag, name, opc) \
1339 static inline struct ir3_instruction * \
1340 ir3_##name(struct ir3_block *block, \
1341 struct ir3_instruction *a, unsigned aflags, \
1342 struct ir3_instruction *b, unsigned bflags, \
1343 struct ir3_instruction *c, unsigned cflags, \
1344 struct ir3_instruction *d, unsigned dflags) \
1346 struct ir3_instruction *instr = \
1347 ir3_instr_create2(block, opc, 5); \
1349 __ssa_src(instr, a, aflags); \
1350 __ssa_src(instr, b, bflags); \
1351 __ssa_src(instr, c, cflags); \
1352 __ssa_src(instr, d, dflags); \
1353 instr->flags |= flag; \
1356 #define INSTR4F(f, name) __INSTR4(IR3_INSTR_##f, name##_##f, OPC_##name)
1357 #define INSTR4(name) __INSTR4(0, name, OPC_##name)
1359 /* cat0 instructions: */
1370 /* cat2 instructions, most 2 src but some 1 src: */
1418 /* cat3 instructions: */
1436 /* cat4 instructions: */
1445 /* cat5 instructions: */
1454 static inline struct ir3_instruction
*
1455 ir3_SAM(struct ir3_block
*block
, opc_t opc
, type_t type
,
1456 unsigned wrmask
, unsigned flags
, struct ir3_instruction
*samp_tex
,
1457 struct ir3_instruction
*src0
, struct ir3_instruction
*src1
)
1459 struct ir3_instruction
*sam
;
1461 sam
= ir3_instr_create(block
, opc
);
1462 sam
->flags
|= flags
| IR3_INSTR_S2EN
;
1463 __ssa_dst(sam
)->wrmask
= wrmask
;
1464 __ssa_src(sam
, samp_tex
, IR3_REG_HALF
);
1466 __ssa_src(sam
, src0
, 0)->wrmask
= (1 << (src0
->regs_count
- 1)) - 1;
1469 __ssa_src(sam
, src1
, 0)->wrmask
=(1 << (src1
->regs_count
- 1)) - 1;
1471 sam
->cat5
.type
= type
;
1476 /* cat6 instructions: */
1491 INSTR2(ATOMIC_CMPXCHG
)
1500 INSTR3F(G
, ATOMIC_ADD
)
1501 INSTR3F(G
, ATOMIC_SUB
)
1502 INSTR3F(G
, ATOMIC_XCHG
)
1503 INSTR3F(G
, ATOMIC_INC
)
1504 INSTR3F(G
, ATOMIC_DEC
)
1505 INSTR3F(G
, ATOMIC_CMPXCHG
)
1506 INSTR3F(G
, ATOMIC_MIN
)
1507 INSTR3F(G
, ATOMIC_MAX
)
1508 INSTR3F(G
, ATOMIC_AND
)
1509 INSTR3F(G
, ATOMIC_OR
)
1510 INSTR3F(G
, ATOMIC_XOR
)
1515 INSTR4F(G
, ATOMIC_ADD
)
1516 INSTR4F(G
, ATOMIC_SUB
)
1517 INSTR4F(G
, ATOMIC_XCHG
)
1518 INSTR4F(G
, ATOMIC_INC
)
1519 INSTR4F(G
, ATOMIC_DEC
)
1520 INSTR4F(G
, ATOMIC_CMPXCHG
)
1521 INSTR4F(G
, ATOMIC_MIN
)
1522 INSTR4F(G
, ATOMIC_MAX
)
1523 INSTR4F(G
, ATOMIC_AND
)
1524 INSTR4F(G
, ATOMIC_OR
)
1525 INSTR4F(G
, ATOMIC_XOR
)
1530 /* cat7 instructions: */
1534 /* meta instructions: */
1535 INSTR0(META_TEX_PREFETCH
);
1537 /* ************************************************************************* */
1538 /* split this out or find some helper to use.. like main/bitset.h.. */
1544 typedef uint8_t regmask_t
[2 * MAX_REG
/ 8];
1546 static inline unsigned regmask_idx(struct ir3_register
*reg
)
1548 unsigned num
= (reg
->flags
& IR3_REG_RELATIV
) ? reg
->array
.offset
: reg
->num
;
1549 debug_assert(num
< MAX_REG
);
1550 if (reg
->flags
& IR3_REG_HALF
) {
1560 static inline void regmask_init(regmask_t
*regmask
)
1562 memset(regmask
, 0, sizeof(*regmask
));
1565 static inline void regmask_set(regmask_t
*regmask
, struct ir3_register
*reg
)
1567 unsigned idx
= regmask_idx(reg
);
1568 if (reg
->flags
& IR3_REG_RELATIV
) {
1570 for (i
= 0; i
< reg
->size
; i
++, idx
++)
1571 (*regmask
)[idx
/ 8] |= 1 << (idx
% 8);
1574 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
1576 (*regmask
)[idx
/ 8] |= 1 << (idx
% 8);
1580 static inline void regmask_or(regmask_t
*dst
, regmask_t
*a
, regmask_t
*b
)
1583 for (i
= 0; i
< ARRAY_SIZE(*dst
); i
++)
1584 (*dst
)[i
] = (*a
)[i
] | (*b
)[i
];
1587 /* set bits in a if not set in b, conceptually:
1590 static inline void regmask_set_if_not(regmask_t
*a
,
1591 struct ir3_register
*reg
, regmask_t
*b
)
1593 unsigned idx
= regmask_idx(reg
);
1594 if (reg
->flags
& IR3_REG_RELATIV
) {
1596 for (i
= 0; i
< reg
->size
; i
++, idx
++)
1597 if (!((*b
)[idx
/ 8] & (1 << (idx
% 8))))
1598 (*a
)[idx
/ 8] |= 1 << (idx
% 8);
1601 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
1603 if (!((*b
)[idx
/ 8] & (1 << (idx
% 8))))
1604 (*a
)[idx
/ 8] |= 1 << (idx
% 8);
1608 static inline bool regmask_get(regmask_t
*regmask
,
1609 struct ir3_register
*reg
)
1611 unsigned idx
= regmask_idx(reg
);
1612 if (reg
->flags
& IR3_REG_RELATIV
) {
1614 for (i
= 0; i
< reg
->size
; i
++, idx
++)
1615 if ((*regmask
)[idx
/ 8] & (1 << (idx
% 8)))
1619 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
1621 if ((*regmask
)[idx
/ 8] & (1 << (idx
% 8)))
1627 /* ************************************************************************* */