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freedreno/ir3: add meta instruction for pre-fs texture fetch
[mesa.git] / src / freedreno / ir3 / ir3.h
1 /*
2 * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #ifndef IR3_H_
25 #define IR3_H_
26
27 #include <stdint.h>
28 #include <stdbool.h>
29
30 #include "compiler/shader_enums.h"
31
32 #include "util/bitscan.h"
33 #include "util/list.h"
34 #include "util/set.h"
35 #include "util/u_debug.h"
36
37 #include "instr-a3xx.h"
38
39 /* low level intermediate representation of an adreno shader program */
40
41 struct ir3_compiler;
42 struct ir3;
43 struct ir3_instruction;
44 struct ir3_block;
45
46 struct ir3_info {
47 uint32_t gpu_id;
48 uint16_t sizedwords;
49 uint16_t instrs_count; /* expanded to account for rpt's */
50 /* NOTE: max_reg, etc, does not include registers not touched
51 * by the shader (ie. vertex fetched via VFD_DECODE but not
52 * touched by shader)
53 */
54 int8_t max_reg; /* highest GPR # used by shader */
55 int8_t max_half_reg;
56 int16_t max_const;
57
58 /* number of sync bits: */
59 uint16_t ss, sy;
60 };
61
62 struct ir3_register {
63 enum {
64 IR3_REG_CONST = 0x001,
65 IR3_REG_IMMED = 0x002,
66 IR3_REG_HALF = 0x004,
67 /* high registers are used for some things in compute shaders,
68 * for example. Seems to be for things that are global to all
69 * threads in a wave, so possibly these are global/shared by
70 * all the threads in the wave?
71 */
72 IR3_REG_HIGH = 0x008,
73 IR3_REG_RELATIV= 0x010,
74 IR3_REG_R = 0x020,
75 /* Most instructions, it seems, can do float abs/neg but not
76 * integer. The CP pass needs to know what is intended (int or
77 * float) in order to do the right thing. For this reason the
78 * abs/neg flags are split out into float and int variants. In
79 * addition, .b (bitwise) operations, the negate is actually a
80 * bitwise not, so split that out into a new flag to make it
81 * more clear.
82 */
83 IR3_REG_FNEG = 0x040,
84 IR3_REG_FABS = 0x080,
85 IR3_REG_SNEG = 0x100,
86 IR3_REG_SABS = 0x200,
87 IR3_REG_BNOT = 0x400,
88 IR3_REG_EVEN = 0x800,
89 IR3_REG_POS_INF= 0x1000,
90 /* (ei) flag, end-input? Set on last bary, presumably to signal
91 * that the shader needs no more input:
92 */
93 IR3_REG_EI = 0x2000,
94 /* meta-flags, for intermediate stages of IR, ie.
95 * before register assignment is done:
96 */
97 IR3_REG_SSA = 0x4000, /* 'instr' is ptr to assigning instr */
98 IR3_REG_ARRAY = 0x8000,
99
100 } flags;
101
102 bool merged : 1; /* half-regs conflict with full regs (ie >= a6xx) */
103
104 /* normal registers:
105 * the component is in the low two bits of the reg #, so
106 * rN.x becomes: (N << 2) | x
107 */
108 uint16_t num;
109 union {
110 /* immediate: */
111 int32_t iim_val;
112 uint32_t uim_val;
113 float fim_val;
114 /* relative: */
115 struct {
116 uint16_t id;
117 int16_t offset;
118 } array;
119 };
120
121 /* For IR3_REG_SSA, src registers contain ptr back to assigning
122 * instruction.
123 *
124 * For IR3_REG_ARRAY, the pointer is back to the last dependent
125 * array access (although the net effect is the same, it points
126 * back to a previous instruction that we depend on).
127 */
128 struct ir3_instruction *instr;
129
130 union {
131 /* used for cat5 instructions, but also for internal/IR level
132 * tracking of what registers are read/written by an instruction.
133 * wrmask may be a bad name since it is used to represent both
134 * src and dst that touch multiple adjacent registers.
135 */
136 unsigned wrmask;
137 /* for relative addressing, 32bits for array size is too small,
138 * but otoh we don't need to deal with disjoint sets, so instead
139 * use a simple size field (number of scalar components).
140 */
141 unsigned size;
142 };
143 };
144
145 /*
146 * Stupid/simple growable array implementation:
147 */
148 #define DECLARE_ARRAY(type, name) \
149 unsigned name ## _count, name ## _sz; \
150 type * name;
151
152 #define array_insert(ctx, arr, val) do { \
153 if (arr ## _count == arr ## _sz) { \
154 arr ## _sz = MAX2(2 * arr ## _sz, 16); \
155 arr = reralloc_size(ctx, arr, arr ## _sz * sizeof(arr[0])); \
156 } \
157 arr[arr ##_count++] = val; \
158 } while (0)
159
160 struct ir3_instruction {
161 struct ir3_block *block;
162 opc_t opc;
163 enum {
164 /* (sy) flag is set on first instruction, and after sample
165 * instructions (probably just on RAW hazard).
166 */
167 IR3_INSTR_SY = 0x001,
168 /* (ss) flag is set on first instruction, and first instruction
169 * to depend on the result of "long" instructions (RAW hazard):
170 *
171 * rcp, rsq, log2, exp2, sin, cos, sqrt
172 *
173 * It seems to synchronize until all in-flight instructions are
174 * completed, for example:
175 *
176 * rsq hr1.w, hr1.w
177 * add.f hr2.z, (neg)hr2.z, hc0.y
178 * mul.f hr2.w, (neg)hr2.y, (neg)hr2.y
179 * rsq hr2.x, hr2.x
180 * (rpt1)nop
181 * mad.f16 hr2.w, hr2.z, hr2.z, hr2.w
182 * nop
183 * mad.f16 hr2.w, (neg)hr0.w, (neg)hr0.w, hr2.w
184 * (ss)(rpt2)mul.f hr1.x, (r)hr1.x, hr1.w
185 * (rpt2)mul.f hr0.x, (neg)(r)hr0.x, hr2.x
186 *
187 * The last mul.f does not have (ss) set, presumably because the
188 * (ss) on the previous instruction does the job.
189 *
190 * The blob driver also seems to set it on WAR hazards, although
191 * not really clear if this is needed or just blob compiler being
192 * sloppy. So far I haven't found a case where removing the (ss)
193 * causes problems for WAR hazard, but I could just be getting
194 * lucky:
195 *
196 * rcp r1.y, r3.y
197 * (ss)(rpt2)mad.f32 r3.y, (r)c9.x, r1.x, (r)r3.z
198 *
199 */
200 IR3_INSTR_SS = 0x002,
201 /* (jp) flag is set on jump targets:
202 */
203 IR3_INSTR_JP = 0x004,
204 IR3_INSTR_UL = 0x008,
205 IR3_INSTR_3D = 0x010,
206 IR3_INSTR_A = 0x020,
207 IR3_INSTR_O = 0x040,
208 IR3_INSTR_P = 0x080,
209 IR3_INSTR_S = 0x100,
210 IR3_INSTR_S2EN = 0x200,
211 IR3_INSTR_G = 0x400,
212 IR3_INSTR_SAT = 0x800,
213 /* meta-flags, for intermediate stages of IR, ie.
214 * before register assignment is done:
215 */
216 IR3_INSTR_MARK = 0x1000,
217 IR3_INSTR_UNUSED= 0x2000,
218 } flags;
219 uint8_t repeat;
220 uint8_t nop;
221 #ifdef DEBUG
222 unsigned regs_max;
223 #endif
224 unsigned regs_count;
225 struct ir3_register **regs;
226 union {
227 struct {
228 char inv;
229 char comp;
230 int immed;
231 struct ir3_block *target;
232 } cat0;
233 struct {
234 type_t src_type, dst_type;
235 } cat1;
236 struct {
237 enum {
238 IR3_COND_LT = 0,
239 IR3_COND_LE = 1,
240 IR3_COND_GT = 2,
241 IR3_COND_GE = 3,
242 IR3_COND_EQ = 4,
243 IR3_COND_NE = 5,
244 } condition;
245 } cat2;
246 struct {
247 unsigned samp, tex;
248 type_t type;
249 } cat5;
250 struct {
251 type_t type;
252 int src_offset;
253 int dst_offset;
254 int iim_val : 3; /* for ldgb/stgb, # of components */
255 unsigned d : 3;
256 bool typed : 1;
257 } cat6;
258 struct {
259 unsigned w : 1; /* write */
260 unsigned r : 1; /* read */
261 unsigned l : 1; /* local */
262 unsigned g : 1; /* global */
263 } cat7;
264 /* for meta-instructions, just used to hold extra data
265 * before instruction scheduling, etc
266 */
267 struct {
268 int off; /* component/offset */
269 } fo;
270 struct {
271 unsigned samp, tex;
272 unsigned input_offset;
273 } prefetch;
274 struct {
275 /* for sysvals, identifies the sysval type. Mostly so we can
276 * identify the special cases where a sysval should not be DCE'd
277 * (currently, just pre-fs texture fetch)
278 */
279 gl_system_value sysval;
280 } input;
281 };
282
283 /* transient values used during various algorithms: */
284 union {
285 /* The instruction depth is the max dependency distance to output.
286 *
287 * You can also think of it as the "cost", if we did any sort of
288 * optimization for register footprint. Ie. a value that is just
289 * result of moving a const to a reg would have a low cost, so to
290 * it could make sense to duplicate the instruction at various
291 * points where the result is needed to reduce register footprint.
292 */
293 unsigned depth;
294 /* When we get to the RA stage, we no longer need depth, but
295 * we do need instruction's position/name:
296 */
297 struct {
298 uint16_t ip;
299 uint16_t name;
300 };
301 };
302
303 /* used for per-pass extra instruction data.
304 *
305 * TODO we should remove the per-pass data like this and 'use_count'
306 * and do something similar to what RA does w/ ir3_ra_instr_data..
307 * ie. use the ir3_count_instructions pass, and then use instr->ip
308 * to index into a table of pass-private data.
309 */
310 void *data;
311
312 int sun; /* Sethi–Ullman number, used by sched */
313 int use_count; /* currently just updated/used by cp */
314
315 /* Used during CP and RA stages. For fanin and shader inputs/
316 * outputs where we need a sequence of consecutive registers,
317 * keep track of each src instructions left (ie 'n-1') and right
318 * (ie 'n+1') neighbor. The front-end must insert enough mov's
319 * to ensure that each instruction has at most one left and at
320 * most one right neighbor. During the copy-propagation pass,
321 * we only remove mov's when we can preserve this constraint.
322 * And during the RA stage, we use the neighbor information to
323 * allocate a block of registers in one shot.
324 *
325 * TODO: maybe just add something like:
326 * struct ir3_instruction_ref {
327 * struct ir3_instruction *instr;
328 * unsigned cnt;
329 * }
330 *
331 * Or can we get away without the refcnt stuff? It seems like
332 * it should be overkill.. the problem is if, potentially after
333 * already eliminating some mov's, if you have a single mov that
334 * needs to be grouped with it's neighbors in two different
335 * places (ex. shader output and a fanin).
336 */
337 struct {
338 struct ir3_instruction *left, *right;
339 uint16_t left_cnt, right_cnt;
340 } cp;
341
342 /* an instruction can reference at most one address register amongst
343 * it's src/dst registers. Beyond that, you need to insert mov's.
344 *
345 * NOTE: do not write this directly, use ir3_instr_set_address()
346 */
347 struct ir3_instruction *address;
348
349 /* Tracking for additional dependent instructions. Used to handle
350 * barriers, WAR hazards for arrays/SSBOs/etc.
351 */
352 DECLARE_ARRAY(struct ir3_instruction *, deps);
353
354 /*
355 * From PoV of instruction scheduling, not execution (ie. ignores global/
356 * local distinction):
357 * shared image atomic SSBO everything
358 * barrier()/ - R/W R/W R/W R/W X
359 * groupMemoryBarrier()
360 * memoryBarrier() - R/W R/W
361 * (but only images declared coherent?)
362 * memoryBarrierAtomic() - R/W
363 * memoryBarrierBuffer() - R/W
364 * memoryBarrierImage() - R/W
365 * memoryBarrierShared() - R/W
366 *
367 * TODO I think for SSBO/image/shared, in cases where we can determine
368 * which variable is accessed, we don't need to care about accesses to
369 * different variables (unless declared coherent??)
370 */
371 enum {
372 IR3_BARRIER_EVERYTHING = 1 << 0,
373 IR3_BARRIER_SHARED_R = 1 << 1,
374 IR3_BARRIER_SHARED_W = 1 << 2,
375 IR3_BARRIER_IMAGE_R = 1 << 3,
376 IR3_BARRIER_IMAGE_W = 1 << 4,
377 IR3_BARRIER_BUFFER_R = 1 << 5,
378 IR3_BARRIER_BUFFER_W = 1 << 6,
379 IR3_BARRIER_ARRAY_R = 1 << 7,
380 IR3_BARRIER_ARRAY_W = 1 << 8,
381 } barrier_class, barrier_conflict;
382
383 /* Entry in ir3_block's instruction list: */
384 struct list_head node;
385
386 #ifdef DEBUG
387 uint32_t serialno;
388 #endif
389 };
390
391 static inline struct ir3_instruction *
392 ir3_neighbor_first(struct ir3_instruction *instr)
393 {
394 int cnt = 0;
395 while (instr->cp.left) {
396 instr = instr->cp.left;
397 if (++cnt > 0xffff) {
398 debug_assert(0);
399 break;
400 }
401 }
402 return instr;
403 }
404
405 static inline int ir3_neighbor_count(struct ir3_instruction *instr)
406 {
407 int num = 1;
408
409 debug_assert(!instr->cp.left);
410
411 while (instr->cp.right) {
412 num++;
413 instr = instr->cp.right;
414 if (num > 0xffff) {
415 debug_assert(0);
416 break;
417 }
418 }
419
420 return num;
421 }
422
423 struct ir3 {
424 struct ir3_compiler *compiler;
425 gl_shader_stage type;
426
427 unsigned ninputs, noutputs;
428 struct ir3_instruction **inputs;
429 struct ir3_instruction **outputs;
430
431 /* Track bary.f (and ldlv) instructions.. this is needed in
432 * scheduling to ensure that all varying fetches happen before
433 * any potential kill instructions. The hw gets grumpy if all
434 * threads in a group are killed before the last bary.f gets
435 * a chance to signal end of input (ei).
436 */
437 DECLARE_ARRAY(struct ir3_instruction *, baryfs);
438
439 /* Track all indirect instructions (read and write). To avoid
440 * deadlock scenario where an address register gets scheduled,
441 * but other dependent src instructions cannot be scheduled due
442 * to dependency on a *different* address register value, the
443 * scheduler needs to ensure that all dependencies other than
444 * the instruction other than the address register are scheduled
445 * before the one that writes the address register. Having a
446 * convenient list of instructions that reference some address
447 * register simplifies this.
448 */
449 DECLARE_ARRAY(struct ir3_instruction *, indirects);
450
451 /* and same for instructions that consume predicate register: */
452 DECLARE_ARRAY(struct ir3_instruction *, predicates);
453
454 /* Track texture sample instructions which need texture state
455 * patched in (for astc-srgb workaround):
456 */
457 DECLARE_ARRAY(struct ir3_instruction *, astc_srgb);
458
459 /* List of blocks: */
460 struct list_head block_list;
461
462 /* List of ir3_array's: */
463 struct list_head array_list;
464
465 unsigned max_sun; /* max Sethi–Ullman number */
466
467 #ifdef DEBUG
468 unsigned block_count, instr_count;
469 #endif
470 };
471
472 struct ir3_array {
473 struct list_head node;
474 unsigned length;
475 unsigned id;
476
477 struct nir_register *r;
478
479 /* To avoid array write's from getting DCE'd, keep track of the
480 * most recent write. Any array access depends on the most
481 * recent write. This way, nothing depends on writes after the
482 * last read. But all the writes that happen before that have
483 * something depending on them
484 */
485 struct ir3_instruction *last_write;
486
487 /* extra stuff used in RA pass: */
488 unsigned base; /* base vreg name */
489 unsigned reg; /* base physical reg */
490 uint16_t start_ip, end_ip;
491 };
492
493 struct ir3_array * ir3_lookup_array(struct ir3 *ir, unsigned id);
494
495 struct ir3_block {
496 struct list_head node;
497 struct ir3 *shader;
498
499 const struct nir_block *nblock;
500
501 struct list_head instr_list; /* list of ir3_instruction */
502
503 /* each block has either one or two successors.. in case of
504 * two successors, 'condition' decides which one to follow.
505 * A block preceding an if/else has two successors.
506 */
507 struct ir3_instruction *condition;
508 struct ir3_block *successors[2];
509
510 struct set *predecessors; /* set of ir3_block */
511
512 uint16_t start_ip, end_ip;
513
514 /* Track instructions which do not write a register but other-
515 * wise must not be discarded (such as kill, stg, etc)
516 */
517 DECLARE_ARRAY(struct ir3_instruction *, keeps);
518
519 /* used for per-pass extra block data. Mainly used right
520 * now in RA step to track livein/liveout.
521 */
522 void *data;
523
524 #ifdef DEBUG
525 uint32_t serialno;
526 #endif
527 };
528
529 static inline uint32_t
530 block_id(struct ir3_block *block)
531 {
532 #ifdef DEBUG
533 return block->serialno;
534 #else
535 return (uint32_t)(unsigned long)block;
536 #endif
537 }
538
539 struct ir3 * ir3_create(struct ir3_compiler *compiler,
540 gl_shader_stage type, unsigned nin, unsigned nout);
541 void ir3_destroy(struct ir3 *shader);
542 void * ir3_assemble(struct ir3 *shader,
543 struct ir3_info *info, uint32_t gpu_id);
544 void * ir3_alloc(struct ir3 *shader, int sz);
545
546 struct ir3_block * ir3_block_create(struct ir3 *shader);
547
548 struct ir3_instruction * ir3_instr_create(struct ir3_block *block, opc_t opc);
549 struct ir3_instruction * ir3_instr_create2(struct ir3_block *block,
550 opc_t opc, int nreg);
551 struct ir3_instruction * ir3_instr_clone(struct ir3_instruction *instr);
552 void ir3_instr_add_dep(struct ir3_instruction *instr, struct ir3_instruction *dep);
553 const char *ir3_instr_name(struct ir3_instruction *instr);
554
555 struct ir3_register * ir3_reg_create(struct ir3_instruction *instr,
556 int num, int flags);
557 struct ir3_register * ir3_reg_clone(struct ir3 *shader,
558 struct ir3_register *reg);
559
560 void ir3_instr_set_address(struct ir3_instruction *instr,
561 struct ir3_instruction *addr);
562
563 static inline bool ir3_instr_check_mark(struct ir3_instruction *instr)
564 {
565 if (instr->flags & IR3_INSTR_MARK)
566 return true; /* already visited */
567 instr->flags |= IR3_INSTR_MARK;
568 return false;
569 }
570
571 void ir3_block_clear_mark(struct ir3_block *block);
572 void ir3_clear_mark(struct ir3 *shader);
573
574 unsigned ir3_count_instructions(struct ir3 *ir);
575
576 static inline int ir3_instr_regno(struct ir3_instruction *instr,
577 struct ir3_register *reg)
578 {
579 unsigned i;
580 for (i = 0; i < instr->regs_count; i++)
581 if (reg == instr->regs[i])
582 return i;
583 return -1;
584 }
585
586
587 #define MAX_ARRAYS 16
588
589 /* comp:
590 * 0 - x
591 * 1 - y
592 * 2 - z
593 * 3 - w
594 */
595 static inline uint32_t regid(int num, int comp)
596 {
597 return (num << 2) | (comp & 0x3);
598 }
599
600 static inline uint32_t reg_num(struct ir3_register *reg)
601 {
602 return reg->num >> 2;
603 }
604
605 static inline uint32_t reg_comp(struct ir3_register *reg)
606 {
607 return reg->num & 0x3;
608 }
609
610 static inline bool is_flow(struct ir3_instruction *instr)
611 {
612 return (opc_cat(instr->opc) == 0);
613 }
614
615 static inline bool is_kill(struct ir3_instruction *instr)
616 {
617 return instr->opc == OPC_KILL;
618 }
619
620 static inline bool is_nop(struct ir3_instruction *instr)
621 {
622 return instr->opc == OPC_NOP;
623 }
624
625 static inline bool is_same_type_reg(struct ir3_register *reg1,
626 struct ir3_register *reg2)
627 {
628 unsigned type_reg1 = (reg1->flags & (IR3_REG_HIGH | IR3_REG_HALF));
629 unsigned type_reg2 = (reg2->flags & (IR3_REG_HIGH | IR3_REG_HALF));
630
631 if (type_reg1 ^ type_reg2)
632 return false;
633 else
634 return true;
635 }
636
637 /* Is it a non-transformative (ie. not type changing) mov? This can
638 * also include absneg.s/absneg.f, which for the most part can be
639 * treated as a mov (single src argument).
640 */
641 static inline bool is_same_type_mov(struct ir3_instruction *instr)
642 {
643 struct ir3_register *dst;
644
645 switch (instr->opc) {
646 case OPC_MOV:
647 if (instr->cat1.src_type != instr->cat1.dst_type)
648 return false;
649 break;
650 case OPC_ABSNEG_F:
651 case OPC_ABSNEG_S:
652 if (instr->flags & IR3_INSTR_SAT)
653 return false;
654 /* If the type of dest reg and src reg are different,
655 * it shouldn't be considered as same type mov */
656 if (!is_same_type_reg(instr->regs[0], instr->regs[1]))
657 return false;
658 break;
659 default:
660 return false;
661 }
662
663 dst = instr->regs[0];
664
665 /* mov's that write to a0.x or p0.x are special: */
666 if (dst->num == regid(REG_P0, 0))
667 return false;
668 if (dst->num == regid(REG_A0, 0))
669 return false;
670
671 if (dst->flags & (IR3_REG_RELATIV | IR3_REG_ARRAY))
672 return false;
673
674 return true;
675 }
676
677 static inline bool is_alu(struct ir3_instruction *instr)
678 {
679 return (1 <= opc_cat(instr->opc)) && (opc_cat(instr->opc) <= 3);
680 }
681
682 static inline bool is_sfu(struct ir3_instruction *instr)
683 {
684 return (opc_cat(instr->opc) == 4);
685 }
686
687 static inline bool is_tex(struct ir3_instruction *instr)
688 {
689 return (opc_cat(instr->opc) == 5);
690 }
691
692 static inline bool is_mem(struct ir3_instruction *instr)
693 {
694 return (opc_cat(instr->opc) == 6);
695 }
696
697 static inline bool is_barrier(struct ir3_instruction *instr)
698 {
699 return (opc_cat(instr->opc) == 7);
700 }
701
702 static inline bool
703 is_store(struct ir3_instruction *instr)
704 {
705 /* these instructions, the "destination" register is
706 * actually a source, the address to store to.
707 */
708 switch (instr->opc) {
709 case OPC_STG:
710 case OPC_STGB:
711 case OPC_STIB:
712 case OPC_STP:
713 case OPC_STL:
714 case OPC_STLW:
715 case OPC_L2G:
716 case OPC_G2L:
717 return true;
718 default:
719 return false;
720 }
721 }
722
723 static inline bool is_load(struct ir3_instruction *instr)
724 {
725 switch (instr->opc) {
726 case OPC_LDG:
727 case OPC_LDGB:
728 case OPC_LDIB:
729 case OPC_LDL:
730 case OPC_LDP:
731 case OPC_L2G:
732 case OPC_LDLW:
733 case OPC_LDC:
734 case OPC_LDLV:
735 /* probably some others too.. */
736 return true;
737 default:
738 return false;
739 }
740 }
741
742 static inline bool is_input(struct ir3_instruction *instr)
743 {
744 /* in some cases, ldlv is used to fetch varying without
745 * interpolation.. fortunately inloc is the first src
746 * register in either case
747 */
748 switch (instr->opc) {
749 case OPC_LDLV:
750 case OPC_BARY_F:
751 return true;
752 default:
753 return false;
754 }
755 }
756
757 static inline bool is_bool(struct ir3_instruction *instr)
758 {
759 switch (instr->opc) {
760 case OPC_CMPS_F:
761 case OPC_CMPS_S:
762 case OPC_CMPS_U:
763 return true;
764 default:
765 return false;
766 }
767 }
768
769 static inline bool is_meta(struct ir3_instruction *instr)
770 {
771 /* TODO how should we count PHI (and maybe fan-in/out) which
772 * might actually contribute some instructions to the final
773 * result?
774 */
775 return (opc_cat(instr->opc) == -1);
776 }
777
778 static inline unsigned dest_regs(struct ir3_instruction *instr)
779 {
780 if ((instr->regs_count == 0) || is_store(instr))
781 return 0;
782
783 return util_last_bit(instr->regs[0]->wrmask);
784 }
785
786 static inline bool writes_addr(struct ir3_instruction *instr)
787 {
788 if (instr->regs_count > 0) {
789 struct ir3_register *dst = instr->regs[0];
790 return reg_num(dst) == REG_A0;
791 }
792 return false;
793 }
794
795 static inline bool writes_pred(struct ir3_instruction *instr)
796 {
797 if (instr->regs_count > 0) {
798 struct ir3_register *dst = instr->regs[0];
799 return reg_num(dst) == REG_P0;
800 }
801 return false;
802 }
803
804 /* returns defining instruction for reg */
805 /* TODO better name */
806 static inline struct ir3_instruction *ssa(struct ir3_register *reg)
807 {
808 if (reg->flags & (IR3_REG_SSA | IR3_REG_ARRAY)) {
809 return reg->instr;
810 }
811 return NULL;
812 }
813
814 static inline bool conflicts(struct ir3_instruction *a,
815 struct ir3_instruction *b)
816 {
817 return (a && b) && (a != b);
818 }
819
820 static inline bool reg_gpr(struct ir3_register *r)
821 {
822 if (r->flags & (IR3_REG_CONST | IR3_REG_IMMED))
823 return false;
824 if ((reg_num(r) == REG_A0) || (reg_num(r) == REG_P0))
825 return false;
826 return true;
827 }
828
829 static inline type_t half_type(type_t type)
830 {
831 switch (type) {
832 case TYPE_F32: return TYPE_F16;
833 case TYPE_U32: return TYPE_U16;
834 case TYPE_S32: return TYPE_S16;
835 case TYPE_F16:
836 case TYPE_U16:
837 case TYPE_S16:
838 return type;
839 default:
840 assert(0);
841 return ~0;
842 }
843 }
844
845 /* some cat2 instructions (ie. those which are not float) can embed an
846 * immediate:
847 */
848 static inline bool ir3_cat2_int(opc_t opc)
849 {
850 switch (opc) {
851 case OPC_ADD_U:
852 case OPC_ADD_S:
853 case OPC_SUB_U:
854 case OPC_SUB_S:
855 case OPC_CMPS_U:
856 case OPC_CMPS_S:
857 case OPC_MIN_U:
858 case OPC_MIN_S:
859 case OPC_MAX_U:
860 case OPC_MAX_S:
861 case OPC_CMPV_U:
862 case OPC_CMPV_S:
863 case OPC_MUL_U:
864 case OPC_MUL_S:
865 case OPC_MULL_U:
866 case OPC_CLZ_S:
867 case OPC_ABSNEG_S:
868 case OPC_AND_B:
869 case OPC_OR_B:
870 case OPC_NOT_B:
871 case OPC_XOR_B:
872 case OPC_BFREV_B:
873 case OPC_CLZ_B:
874 case OPC_SHL_B:
875 case OPC_SHR_B:
876 case OPC_ASHR_B:
877 case OPC_MGEN_B:
878 case OPC_GETBIT_B:
879 case OPC_CBITS_B:
880 case OPC_BARY_F:
881 return true;
882
883 default:
884 return false;
885 }
886 }
887
888 static inline bool ir3_cat2_float(opc_t opc)
889 {
890 switch (opc) {
891 case OPC_ADD_F:
892 case OPC_MIN_F:
893 case OPC_MAX_F:
894 case OPC_MUL_F:
895 case OPC_SIGN_F:
896 case OPC_CMPS_F:
897 case OPC_ABSNEG_F:
898 case OPC_CMPV_F:
899 case OPC_FLOOR_F:
900 case OPC_CEIL_F:
901 case OPC_RNDNE_F:
902 case OPC_RNDAZ_F:
903 case OPC_TRUNC_F:
904 return true;
905
906 default:
907 return false;
908 }
909 }
910
911 static inline bool ir3_cat3_float(opc_t opc)
912 {
913 switch (opc) {
914 case OPC_MAD_F16:
915 case OPC_MAD_F32:
916 case OPC_SEL_F16:
917 case OPC_SEL_F32:
918 return true;
919 default:
920 return false;
921 }
922 }
923
924 /* map cat2 instruction to valid abs/neg flags: */
925 static inline unsigned ir3_cat2_absneg(opc_t opc)
926 {
927 switch (opc) {
928 case OPC_ADD_F:
929 case OPC_MIN_F:
930 case OPC_MAX_F:
931 case OPC_MUL_F:
932 case OPC_SIGN_F:
933 case OPC_CMPS_F:
934 case OPC_ABSNEG_F:
935 case OPC_CMPV_F:
936 case OPC_FLOOR_F:
937 case OPC_CEIL_F:
938 case OPC_RNDNE_F:
939 case OPC_RNDAZ_F:
940 case OPC_TRUNC_F:
941 case OPC_BARY_F:
942 return IR3_REG_FABS | IR3_REG_FNEG;
943
944 case OPC_ADD_U:
945 case OPC_ADD_S:
946 case OPC_SUB_U:
947 case OPC_SUB_S:
948 case OPC_CMPS_U:
949 case OPC_CMPS_S:
950 case OPC_MIN_U:
951 case OPC_MIN_S:
952 case OPC_MAX_U:
953 case OPC_MAX_S:
954 case OPC_CMPV_U:
955 case OPC_CMPV_S:
956 case OPC_MUL_U:
957 case OPC_MUL_S:
958 case OPC_MULL_U:
959 case OPC_CLZ_S:
960 return 0;
961
962 case OPC_ABSNEG_S:
963 return IR3_REG_SABS | IR3_REG_SNEG;
964
965 case OPC_AND_B:
966 case OPC_OR_B:
967 case OPC_NOT_B:
968 case OPC_XOR_B:
969 case OPC_BFREV_B:
970 case OPC_CLZ_B:
971 case OPC_SHL_B:
972 case OPC_SHR_B:
973 case OPC_ASHR_B:
974 case OPC_MGEN_B:
975 case OPC_GETBIT_B:
976 case OPC_CBITS_B:
977 return IR3_REG_BNOT;
978
979 default:
980 return 0;
981 }
982 }
983
984 /* map cat3 instructions to valid abs/neg flags: */
985 static inline unsigned ir3_cat3_absneg(opc_t opc)
986 {
987 switch (opc) {
988 case OPC_MAD_F16:
989 case OPC_MAD_F32:
990 case OPC_SEL_F16:
991 case OPC_SEL_F32:
992 return IR3_REG_FNEG;
993
994 case OPC_MAD_U16:
995 case OPC_MADSH_U16:
996 case OPC_MAD_S16:
997 case OPC_MADSH_M16:
998 case OPC_MAD_U24:
999 case OPC_MAD_S24:
1000 case OPC_SEL_S16:
1001 case OPC_SEL_S32:
1002 case OPC_SAD_S16:
1003 case OPC_SAD_S32:
1004 /* neg *may* work on 3rd src.. */
1005
1006 case OPC_SEL_B16:
1007 case OPC_SEL_B32:
1008
1009 default:
1010 return 0;
1011 }
1012 }
1013
1014 #define MASK(n) ((1 << (n)) - 1)
1015
1016 /* iterator for an instructions's sources (reg), also returns src #: */
1017 #define foreach_src_n(__srcreg, __n, __instr) \
1018 if ((__instr)->regs_count) \
1019 for (unsigned __cnt = (__instr)->regs_count - 1, __n = 0; __n < __cnt; __n++) \
1020 if ((__srcreg = (__instr)->regs[__n + 1]))
1021
1022 /* iterator for an instructions's sources (reg): */
1023 #define foreach_src(__srcreg, __instr) \
1024 foreach_src_n(__srcreg, __i, __instr)
1025
1026 static inline unsigned __ssa_src_cnt(struct ir3_instruction *instr)
1027 {
1028 unsigned cnt = instr->regs_count + instr->deps_count;
1029 if (instr->address)
1030 cnt++;
1031 return cnt;
1032 }
1033
1034 static inline struct ir3_instruction * __ssa_src_n(struct ir3_instruction *instr, unsigned n)
1035 {
1036 if (n == (instr->regs_count + instr->deps_count))
1037 return instr->address;
1038 if (n >= instr->regs_count)
1039 return instr->deps[n - instr->regs_count];
1040 return ssa(instr->regs[n]);
1041 }
1042
1043 static inline bool __is_false_dep(struct ir3_instruction *instr, unsigned n)
1044 {
1045 if (n == (instr->regs_count + instr->deps_count))
1046 return false;
1047 if (n >= instr->regs_count)
1048 return true;
1049 return false;
1050 }
1051
1052 #define __src_cnt(__instr) ((__instr)->address ? (__instr)->regs_count : (__instr)->regs_count - 1)
1053
1054 /* iterator for an instruction's SSA sources (instr), also returns src #: */
1055 #define foreach_ssa_src_n(__srcinst, __n, __instr) \
1056 for (unsigned __cnt = __ssa_src_cnt(__instr), __n = 0; __n < __cnt; __n++) \
1057 if ((__srcinst = __ssa_src_n(__instr, __n)))
1058
1059 /* iterator for an instruction's SSA sources (instr): */
1060 #define foreach_ssa_src(__srcinst, __instr) \
1061 foreach_ssa_src_n(__srcinst, __i, __instr)
1062
1063
1064 /* dump: */
1065 void ir3_print(struct ir3 *ir);
1066 void ir3_print_instr(struct ir3_instruction *instr);
1067
1068 /* depth calculation: */
1069 struct ir3_shader_variant;
1070 int ir3_delayslots(struct ir3_instruction *assigner,
1071 struct ir3_instruction *consumer, unsigned n);
1072 void ir3_insert_by_depth(struct ir3_instruction *instr, struct list_head *list);
1073 void ir3_depth(struct ir3 *ir, struct ir3_shader_variant *so);
1074
1075 /* copy-propagate: */
1076 void ir3_cp(struct ir3 *ir, struct ir3_shader_variant *so);
1077
1078 /* group neighbors and insert mov's to resolve conflicts: */
1079 void ir3_group(struct ir3 *ir);
1080
1081 /* Sethi–Ullman numbering: */
1082 void ir3_sun(struct ir3 *ir);
1083
1084 /* scheduling: */
1085 void ir3_sched_add_deps(struct ir3 *ir);
1086 int ir3_sched(struct ir3 *ir);
1087
1088 void ir3_a6xx_fixup_atomic_dests(struct ir3 *ir, struct ir3_shader_variant *so);
1089
1090 /* register assignment: */
1091 struct ir3_ra_reg_set * ir3_ra_alloc_reg_set(struct ir3_compiler *compiler);
1092 int ir3_ra(struct ir3_shader_variant *v, struct ir3_instruction **precolor, unsigned nprecolor);
1093
1094 /* legalize: */
1095 void ir3_legalize(struct ir3 *ir, bool *has_ssbo, bool *need_pixlod, int *max_bary);
1096
1097 /* ************************************************************************* */
1098 /* instruction helpers */
1099
1100 static inline struct ir3_instruction *
1101 create_immed_typed(struct ir3_block *block, uint32_t val, type_t type)
1102 {
1103 struct ir3_instruction *mov;
1104 unsigned flags = (type_size(type) < 32) ? IR3_REG_HALF : 0;
1105
1106 mov = ir3_instr_create(block, OPC_MOV);
1107 mov->cat1.src_type = type;
1108 mov->cat1.dst_type = type;
1109 ir3_reg_create(mov, 0, flags);
1110 ir3_reg_create(mov, 0, IR3_REG_IMMED)->uim_val = val;
1111
1112 return mov;
1113 }
1114
1115 static inline struct ir3_instruction *
1116 create_immed(struct ir3_block *block, uint32_t val)
1117 {
1118 return create_immed_typed(block, val, TYPE_U32);
1119 }
1120
1121 static inline struct ir3_instruction *
1122 create_uniform_typed(struct ir3_block *block, unsigned n, type_t type)
1123 {
1124 struct ir3_instruction *mov;
1125 unsigned flags = (type_size(type) < 32) ? IR3_REG_HALF : 0;
1126
1127 mov = ir3_instr_create(block, OPC_MOV);
1128 mov->cat1.src_type = type;
1129 mov->cat1.dst_type = type;
1130 ir3_reg_create(mov, 0, flags);
1131 ir3_reg_create(mov, n, IR3_REG_CONST | flags);
1132
1133 return mov;
1134 }
1135
1136 static inline struct ir3_instruction *
1137 create_uniform(struct ir3_block *block, unsigned n)
1138 {
1139 return create_uniform_typed(block, n, TYPE_F32);
1140 }
1141
1142 static inline struct ir3_instruction *
1143 create_uniform_indirect(struct ir3_block *block, int n,
1144 struct ir3_instruction *address)
1145 {
1146 struct ir3_instruction *mov;
1147
1148 mov = ir3_instr_create(block, OPC_MOV);
1149 mov->cat1.src_type = TYPE_U32;
1150 mov->cat1.dst_type = TYPE_U32;
1151 ir3_reg_create(mov, 0, 0);
1152 ir3_reg_create(mov, 0, IR3_REG_CONST | IR3_REG_RELATIV)->array.offset = n;
1153
1154 ir3_instr_set_address(mov, address);
1155
1156 return mov;
1157 }
1158
1159 /* creates SSA src of correct type (ie. half vs full precision) */
1160 static inline struct ir3_register * __ssa_src(struct ir3_instruction *instr,
1161 struct ir3_instruction *src, unsigned flags)
1162 {
1163 struct ir3_register *reg;
1164 if (src->regs[0]->flags & IR3_REG_HALF)
1165 flags |= IR3_REG_HALF;
1166 reg = ir3_reg_create(instr, 0, IR3_REG_SSA | flags);
1167 reg->instr = src;
1168 reg->wrmask = src->regs[0]->wrmask;
1169 return reg;
1170 }
1171
1172 static inline struct ir3_instruction *
1173 ir3_MOV(struct ir3_block *block, struct ir3_instruction *src, type_t type)
1174 {
1175 struct ir3_instruction *instr = ir3_instr_create(block, OPC_MOV);
1176 ir3_reg_create(instr, 0, 0); /* dst */
1177 if (src->regs[0]->flags & IR3_REG_ARRAY) {
1178 struct ir3_register *src_reg = __ssa_src(instr, src, IR3_REG_ARRAY);
1179 src_reg->array = src->regs[0]->array;
1180 } else {
1181 __ssa_src(instr, src, src->regs[0]->flags & IR3_REG_HIGH);
1182 }
1183 debug_assert(!(src->regs[0]->flags & IR3_REG_RELATIV));
1184 instr->cat1.src_type = type;
1185 instr->cat1.dst_type = type;
1186 return instr;
1187 }
1188
1189 static inline struct ir3_instruction *
1190 ir3_COV(struct ir3_block *block, struct ir3_instruction *src,
1191 type_t src_type, type_t dst_type)
1192 {
1193 struct ir3_instruction *instr = ir3_instr_create(block, OPC_MOV);
1194 unsigned dst_flags = (type_size(dst_type) < 32) ? IR3_REG_HALF : 0;
1195 unsigned src_flags = (type_size(src_type) < 32) ? IR3_REG_HALF : 0;
1196
1197 debug_assert((src->regs[0]->flags & IR3_REG_HALF) == src_flags);
1198
1199 ir3_reg_create(instr, 0, dst_flags); /* dst */
1200 __ssa_src(instr, src, 0);
1201 instr->cat1.src_type = src_type;
1202 instr->cat1.dst_type = dst_type;
1203 debug_assert(!(src->regs[0]->flags & IR3_REG_ARRAY));
1204 return instr;
1205 }
1206
1207 static inline struct ir3_instruction *
1208 ir3_NOP(struct ir3_block *block)
1209 {
1210 return ir3_instr_create(block, OPC_NOP);
1211 }
1212
1213 #define IR3_INSTR_0 0
1214
1215 #define __INSTR0(flag, name, opc) \
1216 static inline struct ir3_instruction * \
1217 ir3_##name(struct ir3_block *block) \
1218 { \
1219 struct ir3_instruction *instr = \
1220 ir3_instr_create(block, opc); \
1221 instr->flags |= flag; \
1222 return instr; \
1223 }
1224 #define INSTR0F(f, name) __INSTR0(IR3_INSTR_##f, name##_##f, OPC_##name)
1225 #define INSTR0(name) __INSTR0(0, name, OPC_##name)
1226
1227 #define __INSTR1(flag, name, opc) \
1228 static inline struct ir3_instruction * \
1229 ir3_##name(struct ir3_block *block, \
1230 struct ir3_instruction *a, unsigned aflags) \
1231 { \
1232 struct ir3_instruction *instr = \
1233 ir3_instr_create(block, opc); \
1234 ir3_reg_create(instr, 0, 0); /* dst */ \
1235 __ssa_src(instr, a, aflags); \
1236 instr->flags |= flag; \
1237 return instr; \
1238 }
1239 #define INSTR1F(f, name) __INSTR1(IR3_INSTR_##f, name##_##f, OPC_##name)
1240 #define INSTR1(name) __INSTR1(0, name, OPC_##name)
1241
1242 #define __INSTR2(flag, name, opc) \
1243 static inline struct ir3_instruction * \
1244 ir3_##name(struct ir3_block *block, \
1245 struct ir3_instruction *a, unsigned aflags, \
1246 struct ir3_instruction *b, unsigned bflags) \
1247 { \
1248 struct ir3_instruction *instr = \
1249 ir3_instr_create(block, opc); \
1250 ir3_reg_create(instr, 0, 0); /* dst */ \
1251 __ssa_src(instr, a, aflags); \
1252 __ssa_src(instr, b, bflags); \
1253 instr->flags |= flag; \
1254 return instr; \
1255 }
1256 #define INSTR2F(f, name) __INSTR2(IR3_INSTR_##f, name##_##f, OPC_##name)
1257 #define INSTR2(name) __INSTR2(0, name, OPC_##name)
1258
1259 #define __INSTR3(flag, name, opc) \
1260 static inline struct ir3_instruction * \
1261 ir3_##name(struct ir3_block *block, \
1262 struct ir3_instruction *a, unsigned aflags, \
1263 struct ir3_instruction *b, unsigned bflags, \
1264 struct ir3_instruction *c, unsigned cflags) \
1265 { \
1266 struct ir3_instruction *instr = \
1267 ir3_instr_create2(block, opc, 4); \
1268 ir3_reg_create(instr, 0, 0); /* dst */ \
1269 __ssa_src(instr, a, aflags); \
1270 __ssa_src(instr, b, bflags); \
1271 __ssa_src(instr, c, cflags); \
1272 instr->flags |= flag; \
1273 return instr; \
1274 }
1275 #define INSTR3F(f, name) __INSTR3(IR3_INSTR_##f, name##_##f, OPC_##name)
1276 #define INSTR3(name) __INSTR3(0, name, OPC_##name)
1277
1278 #define __INSTR4(flag, name, opc) \
1279 static inline struct ir3_instruction * \
1280 ir3_##name(struct ir3_block *block, \
1281 struct ir3_instruction *a, unsigned aflags, \
1282 struct ir3_instruction *b, unsigned bflags, \
1283 struct ir3_instruction *c, unsigned cflags, \
1284 struct ir3_instruction *d, unsigned dflags) \
1285 { \
1286 struct ir3_instruction *instr = \
1287 ir3_instr_create2(block, opc, 5); \
1288 ir3_reg_create(instr, 0, 0); /* dst */ \
1289 __ssa_src(instr, a, aflags); \
1290 __ssa_src(instr, b, bflags); \
1291 __ssa_src(instr, c, cflags); \
1292 __ssa_src(instr, d, dflags); \
1293 instr->flags |= flag; \
1294 return instr; \
1295 }
1296 #define INSTR4F(f, name) __INSTR4(IR3_INSTR_##f, name##_##f, OPC_##name)
1297 #define INSTR4(name) __INSTR4(0, name, OPC_##name)
1298
1299 /* cat0 instructions: */
1300 INSTR0(BR)
1301 INSTR0(JUMP)
1302 INSTR1(KILL)
1303 INSTR0(END)
1304 INSTR0(CHSH)
1305 INSTR0(CHMASK)
1306
1307 /* cat2 instructions, most 2 src but some 1 src: */
1308 INSTR2(ADD_F)
1309 INSTR2(MIN_F)
1310 INSTR2(MAX_F)
1311 INSTR2(MUL_F)
1312 INSTR1(SIGN_F)
1313 INSTR2(CMPS_F)
1314 INSTR1(ABSNEG_F)
1315 INSTR2(CMPV_F)
1316 INSTR1(FLOOR_F)
1317 INSTR1(CEIL_F)
1318 INSTR1(RNDNE_F)
1319 INSTR1(RNDAZ_F)
1320 INSTR1(TRUNC_F)
1321 INSTR2(ADD_U)
1322 INSTR2(ADD_S)
1323 INSTR2(SUB_U)
1324 INSTR2(SUB_S)
1325 INSTR2(CMPS_U)
1326 INSTR2(CMPS_S)
1327 INSTR2(MIN_U)
1328 INSTR2(MIN_S)
1329 INSTR2(MAX_U)
1330 INSTR2(MAX_S)
1331 INSTR1(ABSNEG_S)
1332 INSTR2(AND_B)
1333 INSTR2(OR_B)
1334 INSTR1(NOT_B)
1335 INSTR2(XOR_B)
1336 INSTR2(CMPV_U)
1337 INSTR2(CMPV_S)
1338 INSTR2(MUL_U)
1339 INSTR2(MUL_S)
1340 INSTR2(MULL_U)
1341 INSTR1(BFREV_B)
1342 INSTR1(CLZ_S)
1343 INSTR1(CLZ_B)
1344 INSTR2(SHL_B)
1345 INSTR2(SHR_B)
1346 INSTR2(ASHR_B)
1347 INSTR2(BARY_F)
1348 INSTR2(MGEN_B)
1349 INSTR2(GETBIT_B)
1350 INSTR1(SETRM)
1351 INSTR1(CBITS_B)
1352 INSTR2(SHB)
1353 INSTR2(MSAD)
1354
1355 /* cat3 instructions: */
1356 INSTR3(MAD_U16)
1357 INSTR3(MADSH_U16)
1358 INSTR3(MAD_S16)
1359 INSTR3(MADSH_M16)
1360 INSTR3(MAD_U24)
1361 INSTR3(MAD_S24)
1362 INSTR3(MAD_F16)
1363 INSTR3(MAD_F32)
1364 INSTR3(SEL_B16)
1365 INSTR3(SEL_B32)
1366 INSTR3(SEL_S16)
1367 INSTR3(SEL_S32)
1368 INSTR3(SEL_F16)
1369 INSTR3(SEL_F32)
1370 INSTR3(SAD_S16)
1371 INSTR3(SAD_S32)
1372
1373 /* cat4 instructions: */
1374 INSTR1(RCP)
1375 INSTR1(RSQ)
1376 INSTR1(LOG2)
1377 INSTR1(EXP2)
1378 INSTR1(SIN)
1379 INSTR1(COS)
1380 INSTR1(SQRT)
1381
1382 /* cat5 instructions: */
1383 INSTR1(DSX)
1384 INSTR1(DSY)
1385 INSTR1F(3D, DSX)
1386 INSTR1F(3D, DSY)
1387 INSTR1(RGETPOS)
1388
1389 static inline struct ir3_instruction *
1390 ir3_SAM(struct ir3_block *block, opc_t opc, type_t type,
1391 unsigned wrmask, unsigned flags, struct ir3_instruction *samp_tex,
1392 struct ir3_instruction *src0, struct ir3_instruction *src1)
1393 {
1394 struct ir3_instruction *sam;
1395 struct ir3_register *reg;
1396
1397 sam = ir3_instr_create(block, opc);
1398 sam->flags |= flags | IR3_INSTR_S2EN;
1399 ir3_reg_create(sam, 0, 0)->wrmask = wrmask;
1400 __ssa_src(sam, samp_tex, IR3_REG_HALF);
1401 if (src0) {
1402 reg = ir3_reg_create(sam, 0, IR3_REG_SSA);
1403 reg->wrmask = (1 << (src0->regs_count - 1)) - 1;
1404 reg->instr = src0;
1405 }
1406 if (src1) {
1407 reg = ir3_reg_create(sam, 0, IR3_REG_SSA);
1408 reg->instr = src1;
1409 reg->wrmask = (1 << (src1->regs_count - 1)) - 1;
1410 }
1411 sam->cat5.type = type;
1412
1413 return sam;
1414 }
1415
1416 /* cat6 instructions: */
1417 INSTR2(LDLV)
1418 INSTR3(LDG)
1419 INSTR3(LDL)
1420 INSTR3(LDLW)
1421 INSTR3(STG)
1422 INSTR3(STL)
1423 INSTR3(STLW)
1424 INSTR1(RESINFO)
1425 INSTR1(RESFMT)
1426 INSTR2(ATOMIC_ADD)
1427 INSTR2(ATOMIC_SUB)
1428 INSTR2(ATOMIC_XCHG)
1429 INSTR2(ATOMIC_INC)
1430 INSTR2(ATOMIC_DEC)
1431 INSTR2(ATOMIC_CMPXCHG)
1432 INSTR2(ATOMIC_MIN)
1433 INSTR2(ATOMIC_MAX)
1434 INSTR2(ATOMIC_AND)
1435 INSTR2(ATOMIC_OR)
1436 INSTR2(ATOMIC_XOR)
1437 #if GPU >= 600
1438 INSTR3(STIB);
1439 INSTR2(LDIB);
1440 INSTR3F(G, ATOMIC_ADD)
1441 INSTR3F(G, ATOMIC_SUB)
1442 INSTR3F(G, ATOMIC_XCHG)
1443 INSTR3F(G, ATOMIC_INC)
1444 INSTR3F(G, ATOMIC_DEC)
1445 INSTR3F(G, ATOMIC_CMPXCHG)
1446 INSTR3F(G, ATOMIC_MIN)
1447 INSTR3F(G, ATOMIC_MAX)
1448 INSTR3F(G, ATOMIC_AND)
1449 INSTR3F(G, ATOMIC_OR)
1450 INSTR3F(G, ATOMIC_XOR)
1451 #elif GPU >= 400
1452 INSTR3(LDGB)
1453 INSTR4(STGB)
1454 INSTR4(STIB)
1455 INSTR4F(G, ATOMIC_ADD)
1456 INSTR4F(G, ATOMIC_SUB)
1457 INSTR4F(G, ATOMIC_XCHG)
1458 INSTR4F(G, ATOMIC_INC)
1459 INSTR4F(G, ATOMIC_DEC)
1460 INSTR4F(G, ATOMIC_CMPXCHG)
1461 INSTR4F(G, ATOMIC_MIN)
1462 INSTR4F(G, ATOMIC_MAX)
1463 INSTR4F(G, ATOMIC_AND)
1464 INSTR4F(G, ATOMIC_OR)
1465 INSTR4F(G, ATOMIC_XOR)
1466 #endif
1467
1468 /* cat7 instructions: */
1469 INSTR0(BAR)
1470 INSTR0(FENCE)
1471
1472 /* meta instructions: */
1473 INSTR0(META_TEX_PREFETCH);
1474
1475 /* ************************************************************************* */
1476 /* split this out or find some helper to use.. like main/bitset.h.. */
1477
1478 #include <string.h>
1479
1480 #define MAX_REG 256
1481
1482 typedef uint8_t regmask_t[2 * MAX_REG / 8];
1483
1484 static inline unsigned regmask_idx(struct ir3_register *reg)
1485 {
1486 unsigned num = (reg->flags & IR3_REG_RELATIV) ? reg->array.offset : reg->num;
1487 debug_assert(num < MAX_REG);
1488 if (reg->flags & IR3_REG_HALF) {
1489 if (reg->merged) {
1490 num /= 2;
1491 } else {
1492 num += MAX_REG;
1493 }
1494 }
1495 return num;
1496 }
1497
1498 static inline void regmask_init(regmask_t *regmask)
1499 {
1500 memset(regmask, 0, sizeof(*regmask));
1501 }
1502
1503 static inline void regmask_set(regmask_t *regmask, struct ir3_register *reg)
1504 {
1505 unsigned idx = regmask_idx(reg);
1506 if (reg->flags & IR3_REG_RELATIV) {
1507 unsigned i;
1508 for (i = 0; i < reg->size; i++, idx++)
1509 (*regmask)[idx / 8] |= 1 << (idx % 8);
1510 } else {
1511 unsigned mask;
1512 for (mask = reg->wrmask; mask; mask >>= 1, idx++)
1513 if (mask & 1)
1514 (*regmask)[idx / 8] |= 1 << (idx % 8);
1515 }
1516 }
1517
1518 static inline void regmask_or(regmask_t *dst, regmask_t *a, regmask_t *b)
1519 {
1520 unsigned i;
1521 for (i = 0; i < ARRAY_SIZE(*dst); i++)
1522 (*dst)[i] = (*a)[i] | (*b)[i];
1523 }
1524
1525 /* set bits in a if not set in b, conceptually:
1526 * a |= (reg & ~b)
1527 */
1528 static inline void regmask_set_if_not(regmask_t *a,
1529 struct ir3_register *reg, regmask_t *b)
1530 {
1531 unsigned idx = regmask_idx(reg);
1532 if (reg->flags & IR3_REG_RELATIV) {
1533 unsigned i;
1534 for (i = 0; i < reg->size; i++, idx++)
1535 if (!((*b)[idx / 8] & (1 << (idx % 8))))
1536 (*a)[idx / 8] |= 1 << (idx % 8);
1537 } else {
1538 unsigned mask;
1539 for (mask = reg->wrmask; mask; mask >>= 1, idx++)
1540 if (mask & 1)
1541 if (!((*b)[idx / 8] & (1 << (idx % 8))))
1542 (*a)[idx / 8] |= 1 << (idx % 8);
1543 }
1544 }
1545
1546 static inline bool regmask_get(regmask_t *regmask,
1547 struct ir3_register *reg)
1548 {
1549 unsigned idx = regmask_idx(reg);
1550 if (reg->flags & IR3_REG_RELATIV) {
1551 unsigned i;
1552 for (i = 0; i < reg->size; i++, idx++)
1553 if ((*regmask)[idx / 8] & (1 << (idx % 8)))
1554 return true;
1555 } else {
1556 unsigned mask;
1557 for (mask = reg->wrmask; mask; mask >>= 1, idx++)
1558 if (mask & 1)
1559 if ((*regmask)[idx / 8] & (1 << (idx % 8)))
1560 return true;
1561 }
1562 return false;
1563 }
1564
1565 /* ************************************************************************* */
1566
1567 #endif /* IR3_H_ */