2 * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 #include "compiler/shader_enums.h"
32 #include "util/bitscan.h"
33 #include "util/list.h"
35 #include "util/u_debug.h"
37 #include "instr-a3xx.h"
39 /* low level intermediate representation of an adreno shader program */
43 struct ir3_instruction
;
49 uint16_t instrs_count
; /* expanded to account for rpt's */
50 uint16_t nops_count
; /* # of nop instructions, including nopN */
51 /* NOTE: max_reg, etc, does not include registers not touched
52 * by the shader (ie. vertex fetched via VFD_DECODE but not
55 int8_t max_reg
; /* highest GPR # used by shader */
59 /* number of sync bits: */
65 IR3_REG_CONST
= 0x001,
66 IR3_REG_IMMED
= 0x002,
68 /* high registers are used for some things in compute shaders,
69 * for example. Seems to be for things that are global to all
70 * threads in a wave, so possibly these are global/shared by
71 * all the threads in the wave?
74 IR3_REG_RELATIV
= 0x010,
76 /* Most instructions, it seems, can do float abs/neg but not
77 * integer. The CP pass needs to know what is intended (int or
78 * float) in order to do the right thing. For this reason the
79 * abs/neg flags are split out into float and int variants. In
80 * addition, .b (bitwise) operations, the negate is actually a
81 * bitwise not, so split that out into a new flag to make it
90 IR3_REG_POS_INF
= 0x1000,
91 /* (ei) flag, end-input? Set on last bary, presumably to signal
92 * that the shader needs no more input:
95 /* meta-flags, for intermediate stages of IR, ie.
96 * before register assignment is done:
98 IR3_REG_SSA
= 0x4000, /* 'instr' is ptr to assigning instr */
99 IR3_REG_ARRAY
= 0x8000,
103 bool merged
: 1; /* half-regs conflict with full regs (ie >= a6xx) */
106 * the component is in the low two bits of the reg #, so
107 * rN.x becomes: (N << 2) | x
122 /* For IR3_REG_SSA, src registers contain ptr back to assigning
125 * For IR3_REG_ARRAY, the pointer is back to the last dependent
126 * array access (although the net effect is the same, it points
127 * back to a previous instruction that we depend on).
129 struct ir3_instruction
*instr
;
132 /* used for cat5 instructions, but also for internal/IR level
133 * tracking of what registers are read/written by an instruction.
134 * wrmask may be a bad name since it is used to represent both
135 * src and dst that touch multiple adjacent registers.
138 /* for relative addressing, 32bits for array size is too small,
139 * but otoh we don't need to deal with disjoint sets, so instead
140 * use a simple size field (number of scalar components).
147 * Stupid/simple growable array implementation:
149 #define DECLARE_ARRAY(type, name) \
150 unsigned name ## _count, name ## _sz; \
153 #define array_insert(ctx, arr, val) do { \
154 if (arr ## _count == arr ## _sz) { \
155 arr ## _sz = MAX2(2 * arr ## _sz, 16); \
156 arr = reralloc_size(ctx, arr, arr ## _sz * sizeof(arr[0])); \
158 arr[arr ##_count++] = val; \
161 struct ir3_instruction
{
162 struct ir3_block
*block
;
165 /* (sy) flag is set on first instruction, and after sample
166 * instructions (probably just on RAW hazard).
168 IR3_INSTR_SY
= 0x001,
169 /* (ss) flag is set on first instruction, and first instruction
170 * to depend on the result of "long" instructions (RAW hazard):
172 * rcp, rsq, log2, exp2, sin, cos, sqrt
174 * It seems to synchronize until all in-flight instructions are
175 * completed, for example:
178 * add.f hr2.z, (neg)hr2.z, hc0.y
179 * mul.f hr2.w, (neg)hr2.y, (neg)hr2.y
182 * mad.f16 hr2.w, hr2.z, hr2.z, hr2.w
184 * mad.f16 hr2.w, (neg)hr0.w, (neg)hr0.w, hr2.w
185 * (ss)(rpt2)mul.f hr1.x, (r)hr1.x, hr1.w
186 * (rpt2)mul.f hr0.x, (neg)(r)hr0.x, hr2.x
188 * The last mul.f does not have (ss) set, presumably because the
189 * (ss) on the previous instruction does the job.
191 * The blob driver also seems to set it on WAR hazards, although
192 * not really clear if this is needed or just blob compiler being
193 * sloppy. So far I haven't found a case where removing the (ss)
194 * causes problems for WAR hazard, but I could just be getting
198 * (ss)(rpt2)mad.f32 r3.y, (r)c9.x, r1.x, (r)r3.z
201 IR3_INSTR_SS
= 0x002,
202 /* (jp) flag is set on jump targets:
204 IR3_INSTR_JP
= 0x004,
205 IR3_INSTR_UL
= 0x008,
206 IR3_INSTR_3D
= 0x010,
211 IR3_INSTR_S2EN
= 0x200,
213 IR3_INSTR_SAT
= 0x800,
214 /* meta-flags, for intermediate stages of IR, ie.
215 * before register assignment is done:
217 IR3_INSTR_MARK
= 0x1000,
218 IR3_INSTR_UNUSED
= 0x2000,
226 struct ir3_register
**regs
;
232 struct ir3_block
*target
;
235 type_t src_type
, dst_type
;
255 int iim_val
: 3; /* for ldgb/stgb, # of components */
260 unsigned w
: 1; /* write */
261 unsigned r
: 1; /* read */
262 unsigned l
: 1; /* local */
263 unsigned g
: 1; /* global */
265 /* for meta-instructions, just used to hold extra data
266 * before instruction scheduling, etc
269 int off
; /* component/offset */
273 unsigned input_offset
;
276 /* for sysvals, identifies the sysval type. Mostly so we can
277 * identify the special cases where a sysval should not be DCE'd
278 * (currently, just pre-fs texture fetch)
280 gl_system_value sysval
;
284 /* transient values used during various algorithms: */
286 /* The instruction depth is the max dependency distance to output.
288 * You can also think of it as the "cost", if we did any sort of
289 * optimization for register footprint. Ie. a value that is just
290 * result of moving a const to a reg would have a low cost, so to
291 * it could make sense to duplicate the instruction at various
292 * points where the result is needed to reduce register footprint.
295 /* When we get to the RA stage, we no longer need depth, but
296 * we do need instruction's position/name:
304 /* used for per-pass extra instruction data.
306 * TODO we should remove the per-pass data like this and 'use_count'
307 * and do something similar to what RA does w/ ir3_ra_instr_data..
308 * ie. use the ir3_count_instructions pass, and then use instr->ip
309 * to index into a table of pass-private data.
313 int sun
; /* Sethi–Ullman number, used by sched */
314 int use_count
; /* currently just updated/used by cp */
316 /* Used during CP and RA stages. For collect and shader inputs/
317 * outputs where we need a sequence of consecutive registers,
318 * keep track of each src instructions left (ie 'n-1') and right
319 * (ie 'n+1') neighbor. The front-end must insert enough mov's
320 * to ensure that each instruction has at most one left and at
321 * most one right neighbor. During the copy-propagation pass,
322 * we only remove mov's when we can preserve this constraint.
323 * And during the RA stage, we use the neighbor information to
324 * allocate a block of registers in one shot.
326 * TODO: maybe just add something like:
327 * struct ir3_instruction_ref {
328 * struct ir3_instruction *instr;
332 * Or can we get away without the refcnt stuff? It seems like
333 * it should be overkill.. the problem is if, potentially after
334 * already eliminating some mov's, if you have a single mov that
335 * needs to be grouped with it's neighbors in two different
336 * places (ex. shader output and a collect).
339 struct ir3_instruction
*left
, *right
;
340 uint16_t left_cnt
, right_cnt
;
343 /* an instruction can reference at most one address register amongst
344 * it's src/dst registers. Beyond that, you need to insert mov's.
346 * NOTE: do not write this directly, use ir3_instr_set_address()
348 struct ir3_instruction
*address
;
350 /* Tracking for additional dependent instructions. Used to handle
351 * barriers, WAR hazards for arrays/SSBOs/etc.
353 DECLARE_ARRAY(struct ir3_instruction
*, deps
);
356 * From PoV of instruction scheduling, not execution (ie. ignores global/
357 * local distinction):
358 * shared image atomic SSBO everything
359 * barrier()/ - R/W R/W R/W R/W X
360 * groupMemoryBarrier()
361 * memoryBarrier() - R/W R/W
362 * (but only images declared coherent?)
363 * memoryBarrierAtomic() - R/W
364 * memoryBarrierBuffer() - R/W
365 * memoryBarrierImage() - R/W
366 * memoryBarrierShared() - R/W
368 * TODO I think for SSBO/image/shared, in cases where we can determine
369 * which variable is accessed, we don't need to care about accesses to
370 * different variables (unless declared coherent??)
373 IR3_BARRIER_EVERYTHING
= 1 << 0,
374 IR3_BARRIER_SHARED_R
= 1 << 1,
375 IR3_BARRIER_SHARED_W
= 1 << 2,
376 IR3_BARRIER_IMAGE_R
= 1 << 3,
377 IR3_BARRIER_IMAGE_W
= 1 << 4,
378 IR3_BARRIER_BUFFER_R
= 1 << 5,
379 IR3_BARRIER_BUFFER_W
= 1 << 6,
380 IR3_BARRIER_ARRAY_R
= 1 << 7,
381 IR3_BARRIER_ARRAY_W
= 1 << 8,
382 } barrier_class
, barrier_conflict
;
384 /* Entry in ir3_block's instruction list: */
385 struct list_head node
;
392 static inline struct ir3_instruction
*
393 ir3_neighbor_first(struct ir3_instruction
*instr
)
396 while (instr
->cp
.left
) {
397 instr
= instr
->cp
.left
;
398 if (++cnt
> 0xffff) {
406 static inline int ir3_neighbor_count(struct ir3_instruction
*instr
)
410 debug_assert(!instr
->cp
.left
);
412 while (instr
->cp
.right
) {
414 instr
= instr
->cp
.right
;
425 struct ir3_compiler
*compiler
;
426 gl_shader_stage type
;
428 unsigned ninputs
, noutputs
;
429 struct ir3_instruction
**inputs
;
430 struct ir3_instruction
**outputs
;
432 /* Track bary.f (and ldlv) instructions.. this is needed in
433 * scheduling to ensure that all varying fetches happen before
434 * any potential kill instructions. The hw gets grumpy if all
435 * threads in a group are killed before the last bary.f gets
436 * a chance to signal end of input (ei).
438 DECLARE_ARRAY(struct ir3_instruction
*, baryfs
);
440 /* Track all indirect instructions (read and write). To avoid
441 * deadlock scenario where an address register gets scheduled,
442 * but other dependent src instructions cannot be scheduled due
443 * to dependency on a *different* address register value, the
444 * scheduler needs to ensure that all dependencies other than
445 * the instruction other than the address register are scheduled
446 * before the one that writes the address register. Having a
447 * convenient list of instructions that reference some address
448 * register simplifies this.
450 DECLARE_ARRAY(struct ir3_instruction
*, indirects
);
452 /* and same for instructions that consume predicate register: */
453 DECLARE_ARRAY(struct ir3_instruction
*, predicates
);
455 /* Track texture sample instructions which need texture state
456 * patched in (for astc-srgb workaround):
458 DECLARE_ARRAY(struct ir3_instruction
*, astc_srgb
);
460 /* List of blocks: */
461 struct list_head block_list
;
463 /* List of ir3_array's: */
464 struct list_head array_list
;
466 unsigned max_sun
; /* max Sethi–Ullman number */
469 unsigned block_count
, instr_count
;
474 struct list_head node
;
478 struct nir_register
*r
;
480 /* To avoid array write's from getting DCE'd, keep track of the
481 * most recent write. Any array access depends on the most
482 * recent write. This way, nothing depends on writes after the
483 * last read. But all the writes that happen before that have
484 * something depending on them
486 struct ir3_instruction
*last_write
;
488 /* extra stuff used in RA pass: */
489 unsigned base
; /* base vreg name */
490 unsigned reg
; /* base physical reg */
491 uint16_t start_ip
, end_ip
;
494 struct ir3_array
* ir3_lookup_array(struct ir3
*ir
, unsigned id
);
497 struct list_head node
;
500 const struct nir_block
*nblock
;
502 struct list_head instr_list
; /* list of ir3_instruction */
504 /* each block has either one or two successors.. in case of
505 * two successors, 'condition' decides which one to follow.
506 * A block preceding an if/else has two successors.
508 struct ir3_instruction
*condition
;
509 struct ir3_block
*successors
[2];
511 struct set
*predecessors
; /* set of ir3_block */
513 uint16_t start_ip
, end_ip
;
515 /* Track instructions which do not write a register but other-
516 * wise must not be discarded (such as kill, stg, etc)
518 DECLARE_ARRAY(struct ir3_instruction
*, keeps
);
520 /* used for per-pass extra block data. Mainly used right
521 * now in RA step to track livein/liveout.
530 static inline uint32_t
531 block_id(struct ir3_block
*block
)
534 return block
->serialno
;
536 return (uint32_t)(unsigned long)block
;
540 struct ir3
* ir3_create(struct ir3_compiler
*compiler
,
541 gl_shader_stage type
, unsigned nin
, unsigned nout
);
542 void ir3_destroy(struct ir3
*shader
);
543 void * ir3_assemble(struct ir3
*shader
,
544 struct ir3_info
*info
, uint32_t gpu_id
);
545 void * ir3_alloc(struct ir3
*shader
, int sz
);
547 struct ir3_block
* ir3_block_create(struct ir3
*shader
);
549 struct ir3_instruction
* ir3_instr_create(struct ir3_block
*block
, opc_t opc
);
550 struct ir3_instruction
* ir3_instr_create2(struct ir3_block
*block
,
551 opc_t opc
, int nreg
);
552 struct ir3_instruction
* ir3_instr_clone(struct ir3_instruction
*instr
);
553 void ir3_instr_add_dep(struct ir3_instruction
*instr
, struct ir3_instruction
*dep
);
554 const char *ir3_instr_name(struct ir3_instruction
*instr
);
556 struct ir3_register
* ir3_reg_create(struct ir3_instruction
*instr
,
558 struct ir3_register
* ir3_reg_clone(struct ir3
*shader
,
559 struct ir3_register
*reg
);
561 void ir3_instr_set_address(struct ir3_instruction
*instr
,
562 struct ir3_instruction
*addr
);
564 static inline bool ir3_instr_check_mark(struct ir3_instruction
*instr
)
566 if (instr
->flags
& IR3_INSTR_MARK
)
567 return true; /* already visited */
568 instr
->flags
|= IR3_INSTR_MARK
;
572 void ir3_block_clear_mark(struct ir3_block
*block
);
573 void ir3_clear_mark(struct ir3
*shader
);
575 unsigned ir3_count_instructions(struct ir3
*ir
);
577 static inline int ir3_instr_regno(struct ir3_instruction
*instr
,
578 struct ir3_register
*reg
)
581 for (i
= 0; i
< instr
->regs_count
; i
++)
582 if (reg
== instr
->regs
[i
])
588 #define MAX_ARRAYS 16
596 static inline uint32_t regid(int num
, int comp
)
598 return (num
<< 2) | (comp
& 0x3);
601 static inline uint32_t reg_num(struct ir3_register
*reg
)
603 return reg
->num
>> 2;
606 static inline uint32_t reg_comp(struct ir3_register
*reg
)
608 return reg
->num
& 0x3;
611 static inline bool is_flow(struct ir3_instruction
*instr
)
613 return (opc_cat(instr
->opc
) == 0);
616 static inline bool is_kill(struct ir3_instruction
*instr
)
618 return instr
->opc
== OPC_KILL
|| instr
->opc
== OPC_CONDEND
;
621 static inline bool is_nop(struct ir3_instruction
*instr
)
623 return instr
->opc
== OPC_NOP
;
626 static inline bool is_same_type_reg(struct ir3_register
*reg1
,
627 struct ir3_register
*reg2
)
629 unsigned type_reg1
= (reg1
->flags
& (IR3_REG_HIGH
| IR3_REG_HALF
));
630 unsigned type_reg2
= (reg2
->flags
& (IR3_REG_HIGH
| IR3_REG_HALF
));
632 if (type_reg1
^ type_reg2
)
638 /* Is it a non-transformative (ie. not type changing) mov? This can
639 * also include absneg.s/absneg.f, which for the most part can be
640 * treated as a mov (single src argument).
642 static inline bool is_same_type_mov(struct ir3_instruction
*instr
)
644 struct ir3_register
*dst
;
646 switch (instr
->opc
) {
648 if (instr
->cat1
.src_type
!= instr
->cat1
.dst_type
)
650 /* If the type of dest reg and src reg are different,
651 * it shouldn't be considered as same type mov
653 if (!is_same_type_reg(instr
->regs
[0], instr
->regs
[1]))
658 if (instr
->flags
& IR3_INSTR_SAT
)
660 /* If the type of dest reg and src reg are different,
661 * it shouldn't be considered as same type mov
663 if (!is_same_type_reg(instr
->regs
[0], instr
->regs
[1]))
670 dst
= instr
->regs
[0];
672 /* mov's that write to a0.x or p0.x are special: */
673 if (dst
->num
== regid(REG_P0
, 0))
675 if (dst
->num
== regid(REG_A0
, 0))
678 if (dst
->flags
& (IR3_REG_RELATIV
| IR3_REG_ARRAY
))
684 static inline bool is_alu(struct ir3_instruction
*instr
)
686 return (1 <= opc_cat(instr
->opc
)) && (opc_cat(instr
->opc
) <= 3);
689 static inline bool is_sfu(struct ir3_instruction
*instr
)
691 return (opc_cat(instr
->opc
) == 4);
694 static inline bool is_tex(struct ir3_instruction
*instr
)
696 return (opc_cat(instr
->opc
) == 5);
699 static inline bool is_mem(struct ir3_instruction
*instr
)
701 return (opc_cat(instr
->opc
) == 6);
704 static inline bool is_barrier(struct ir3_instruction
*instr
)
706 return (opc_cat(instr
->opc
) == 7);
710 is_store(struct ir3_instruction
*instr
)
712 /* these instructions, the "destination" register is
713 * actually a source, the address to store to.
715 switch (instr
->opc
) {
730 static inline bool is_load(struct ir3_instruction
*instr
)
732 switch (instr
->opc
) {
742 /* probably some others too.. */
749 static inline bool is_input(struct ir3_instruction
*instr
)
751 /* in some cases, ldlv is used to fetch varying without
752 * interpolation.. fortunately inloc is the first src
753 * register in either case
755 switch (instr
->opc
) {
764 static inline bool is_bool(struct ir3_instruction
*instr
)
766 switch (instr
->opc
) {
776 static inline bool is_meta(struct ir3_instruction
*instr
)
778 return (opc_cat(instr
->opc
) == -1);
781 static inline unsigned dest_regs(struct ir3_instruction
*instr
)
783 if ((instr
->regs_count
== 0) || is_store(instr
))
786 return util_last_bit(instr
->regs
[0]->wrmask
);
789 static inline bool writes_addr(struct ir3_instruction
*instr
)
791 if (instr
->regs_count
> 0) {
792 struct ir3_register
*dst
= instr
->regs
[0];
793 return reg_num(dst
) == REG_A0
;
798 static inline bool writes_pred(struct ir3_instruction
*instr
)
800 if (instr
->regs_count
> 0) {
801 struct ir3_register
*dst
= instr
->regs
[0];
802 return reg_num(dst
) == REG_P0
;
807 /* returns defining instruction for reg */
808 /* TODO better name */
809 static inline struct ir3_instruction
*ssa(struct ir3_register
*reg
)
811 if (reg
->flags
& (IR3_REG_SSA
| IR3_REG_ARRAY
)) {
817 static inline bool conflicts(struct ir3_instruction
*a
,
818 struct ir3_instruction
*b
)
820 return (a
&& b
) && (a
!= b
);
823 static inline bool reg_gpr(struct ir3_register
*r
)
825 if (r
->flags
& (IR3_REG_CONST
| IR3_REG_IMMED
))
827 if ((reg_num(r
) == REG_A0
) || (reg_num(r
) == REG_P0
))
832 static inline type_t
half_type(type_t type
)
835 case TYPE_F32
: return TYPE_F16
;
836 case TYPE_U32
: return TYPE_U16
;
837 case TYPE_S32
: return TYPE_S16
;
848 /* some cat2 instructions (ie. those which are not float) can embed an
851 static inline bool ir3_cat2_int(opc_t opc
)
891 static inline bool ir3_cat2_float(opc_t opc
)
914 static inline bool ir3_cat3_float(opc_t opc
)
927 /* map cat2 instruction to valid abs/neg flags: */
928 static inline unsigned ir3_cat2_absneg(opc_t opc
)
945 return IR3_REG_FABS
| IR3_REG_FNEG
;
966 return IR3_REG_SABS
| IR3_REG_SNEG
;
987 /* map cat3 instructions to valid abs/neg flags: */
988 static inline unsigned ir3_cat3_absneg(opc_t opc
)
1007 /* neg *may* work on 3rd src.. */
1017 #define MASK(n) ((1 << (n)) - 1)
1019 /* iterator for an instructions's sources (reg), also returns src #: */
1020 #define foreach_src_n(__srcreg, __n, __instr) \
1021 if ((__instr)->regs_count) \
1022 for (unsigned __cnt = (__instr)->regs_count - 1, __n = 0; __n < __cnt; __n++) \
1023 if ((__srcreg = (__instr)->regs[__n + 1]))
1025 /* iterator for an instructions's sources (reg): */
1026 #define foreach_src(__srcreg, __instr) \
1027 foreach_src_n(__srcreg, __i, __instr)
1029 static inline unsigned __ssa_src_cnt(struct ir3_instruction
*instr
)
1031 unsigned cnt
= instr
->regs_count
+ instr
->deps_count
;
1037 static inline struct ir3_instruction
* __ssa_src_n(struct ir3_instruction
*instr
, unsigned n
)
1039 if (n
== (instr
->regs_count
+ instr
->deps_count
))
1040 return instr
->address
;
1041 if (n
>= instr
->regs_count
)
1042 return instr
->deps
[n
- instr
->regs_count
];
1043 return ssa(instr
->regs
[n
]);
1046 static inline bool __is_false_dep(struct ir3_instruction
*instr
, unsigned n
)
1048 if (n
== (instr
->regs_count
+ instr
->deps_count
))
1050 if (n
>= instr
->regs_count
)
1055 #define __src_cnt(__instr) ((__instr)->address ? (__instr)->regs_count : (__instr)->regs_count - 1)
1057 /* iterator for an instruction's SSA sources (instr), also returns src #: */
1058 #define foreach_ssa_src_n(__srcinst, __n, __instr) \
1059 for (unsigned __cnt = __ssa_src_cnt(__instr), __n = 0; __n < __cnt; __n++) \
1060 if ((__srcinst = __ssa_src_n(__instr, __n)))
1062 /* iterator for an instruction's SSA sources (instr): */
1063 #define foreach_ssa_src(__srcinst, __instr) \
1064 foreach_ssa_src_n(__srcinst, __i, __instr)
1066 /* iterators for shader inputs: */
1067 #define foreach_input_n(__ininstr, __cnt, __ir) \
1068 for (unsigned __cnt = 0; __cnt < (__ir)->ninputs; __cnt++) \
1069 if ((__ininstr = (__ir)->inputs[__cnt]))
1070 #define foreach_input(__ininstr, __ir) \
1071 foreach_input_n(__ininstr, __i, __ir)
1073 /* iterators for shader outputs: */
1074 #define foreach_output_n(__outinstr, __cnt, __ir) \
1075 for (unsigned __cnt = 0; __cnt < (__ir)->noutputs; __cnt++) \
1076 if ((__outinstr = (__ir)->outputs[__cnt]))
1077 #define foreach_output(__outinstr, __ir) \
1078 foreach_output_n(__outinstr, __i, __ir)
1081 void ir3_print(struct ir3
*ir
);
1082 void ir3_print_instr(struct ir3_instruction
*instr
);
1084 /* depth calculation: */
1085 struct ir3_shader_variant
;
1086 int ir3_delayslots(struct ir3_instruction
*assigner
,
1087 struct ir3_instruction
*consumer
, unsigned n
);
1088 void ir3_insert_by_depth(struct ir3_instruction
*instr
, struct list_head
*list
);
1089 void ir3_depth(struct ir3
*ir
, struct ir3_shader_variant
*so
);
1091 /* copy-propagate: */
1092 void ir3_cp(struct ir3
*ir
, struct ir3_shader_variant
*so
);
1094 /* group neighbors and insert mov's to resolve conflicts: */
1095 void ir3_group(struct ir3
*ir
);
1097 /* Sethi–Ullman numbering: */
1098 void ir3_sun(struct ir3
*ir
);
1101 void ir3_sched_add_deps(struct ir3
*ir
);
1102 int ir3_sched(struct ir3
*ir
);
1104 void ir3_a6xx_fixup_atomic_dests(struct ir3
*ir
, struct ir3_shader_variant
*so
);
1106 /* register assignment: */
1107 struct ir3_ra_reg_set
* ir3_ra_alloc_reg_set(struct ir3_compiler
*compiler
);
1108 int ir3_ra(struct ir3_shader_variant
*v
, struct ir3_instruction
**precolor
, unsigned nprecolor
);
1111 void ir3_legalize(struct ir3
*ir
, bool *has_ssbo
, bool *need_pixlod
, int *max_bary
);
1113 /* ************************************************************************* */
1114 /* instruction helpers */
1116 /* creates SSA src of correct type (ie. half vs full precision) */
1117 static inline struct ir3_register
* __ssa_src(struct ir3_instruction
*instr
,
1118 struct ir3_instruction
*src
, unsigned flags
)
1120 struct ir3_register
*reg
;
1121 if (src
->regs
[0]->flags
& IR3_REG_HALF
)
1122 flags
|= IR3_REG_HALF
;
1123 reg
= ir3_reg_create(instr
, 0, IR3_REG_SSA
| flags
);
1125 reg
->wrmask
= src
->regs
[0]->wrmask
;
1129 static inline struct ir3_register
* __ssa_dst(struct ir3_instruction
*instr
)
1131 struct ir3_register
*reg
= ir3_reg_create(instr
, 0, 0);
1132 reg
->flags
|= IR3_REG_SSA
;
1136 static inline struct ir3_instruction
*
1137 create_immed_typed(struct ir3_block
*block
, uint32_t val
, type_t type
)
1139 struct ir3_instruction
*mov
;
1140 unsigned flags
= (type_size(type
) < 32) ? IR3_REG_HALF
: 0;
1142 mov
= ir3_instr_create(block
, OPC_MOV
);
1143 mov
->cat1
.src_type
= type
;
1144 mov
->cat1
.dst_type
= type
;
1145 __ssa_dst(mov
)->flags
|= flags
;
1146 ir3_reg_create(mov
, 0, IR3_REG_IMMED
)->uim_val
= val
;
1151 static inline struct ir3_instruction
*
1152 create_immed(struct ir3_block
*block
, uint32_t val
)
1154 return create_immed_typed(block
, val
, TYPE_U32
);
1157 static inline struct ir3_instruction
*
1158 create_uniform_typed(struct ir3_block
*block
, unsigned n
, type_t type
)
1160 struct ir3_instruction
*mov
;
1161 unsigned flags
= (type_size(type
) < 32) ? IR3_REG_HALF
: 0;
1163 mov
= ir3_instr_create(block
, OPC_MOV
);
1164 mov
->cat1
.src_type
= type
;
1165 mov
->cat1
.dst_type
= type
;
1166 __ssa_dst(mov
)->flags
|= flags
;
1167 ir3_reg_create(mov
, n
, IR3_REG_CONST
| flags
);
1172 static inline struct ir3_instruction
*
1173 create_uniform(struct ir3_block
*block
, unsigned n
)
1175 return create_uniform_typed(block
, n
, TYPE_F32
);
1178 static inline struct ir3_instruction
*
1179 create_uniform_indirect(struct ir3_block
*block
, int n
,
1180 struct ir3_instruction
*address
)
1182 struct ir3_instruction
*mov
;
1184 mov
= ir3_instr_create(block
, OPC_MOV
);
1185 mov
->cat1
.src_type
= TYPE_U32
;
1186 mov
->cat1
.dst_type
= TYPE_U32
;
1188 ir3_reg_create(mov
, 0, IR3_REG_CONST
| IR3_REG_RELATIV
)->array
.offset
= n
;
1190 ir3_instr_set_address(mov
, address
);
1195 static inline struct ir3_instruction
*
1196 ir3_MOV(struct ir3_block
*block
, struct ir3_instruction
*src
, type_t type
)
1198 struct ir3_instruction
*instr
= ir3_instr_create(block
, OPC_MOV
);
1200 if (src
->regs
[0]->flags
& IR3_REG_ARRAY
) {
1201 struct ir3_register
*src_reg
= __ssa_src(instr
, src
, IR3_REG_ARRAY
);
1202 src_reg
->array
= src
->regs
[0]->array
;
1204 __ssa_src(instr
, src
, src
->regs
[0]->flags
& IR3_REG_HIGH
);
1206 debug_assert(!(src
->regs
[0]->flags
& IR3_REG_RELATIV
));
1207 instr
->cat1
.src_type
= type
;
1208 instr
->cat1
.dst_type
= type
;
1212 static inline struct ir3_instruction
*
1213 ir3_COV(struct ir3_block
*block
, struct ir3_instruction
*src
,
1214 type_t src_type
, type_t dst_type
)
1216 struct ir3_instruction
*instr
= ir3_instr_create(block
, OPC_MOV
);
1217 unsigned dst_flags
= (type_size(dst_type
) < 32) ? IR3_REG_HALF
: 0;
1218 unsigned src_flags
= (type_size(src_type
) < 32) ? IR3_REG_HALF
: 0;
1220 debug_assert((src
->regs
[0]->flags
& IR3_REG_HALF
) == src_flags
);
1222 __ssa_dst(instr
)->flags
|= dst_flags
;
1223 __ssa_src(instr
, src
, 0);
1224 instr
->cat1
.src_type
= src_type
;
1225 instr
->cat1
.dst_type
= dst_type
;
1226 debug_assert(!(src
->regs
[0]->flags
& IR3_REG_ARRAY
));
1230 static inline struct ir3_instruction
*
1231 ir3_NOP(struct ir3_block
*block
)
1233 return ir3_instr_create(block
, OPC_NOP
);
1236 #define IR3_INSTR_0 0
1238 #define __INSTR0(flag, name, opc) \
1239 static inline struct ir3_instruction * \
1240 ir3_##name(struct ir3_block *block) \
1242 struct ir3_instruction *instr = \
1243 ir3_instr_create(block, opc); \
1244 instr->flags |= flag; \
1247 #define INSTR0F(f, name) __INSTR0(IR3_INSTR_##f, name##_##f, OPC_##name)
1248 #define INSTR0(name) __INSTR0(0, name, OPC_##name)
1250 #define __INSTR1(flag, name, opc) \
1251 static inline struct ir3_instruction * \
1252 ir3_##name(struct ir3_block *block, \
1253 struct ir3_instruction *a, unsigned aflags) \
1255 struct ir3_instruction *instr = \
1256 ir3_instr_create(block, opc); \
1258 __ssa_src(instr, a, aflags); \
1259 instr->flags |= flag; \
1262 #define INSTR1F(f, name) __INSTR1(IR3_INSTR_##f, name##_##f, OPC_##name)
1263 #define INSTR1(name) __INSTR1(0, name, OPC_##name)
1265 #define __INSTR2(flag, name, opc) \
1266 static inline struct ir3_instruction * \
1267 ir3_##name(struct ir3_block *block, \
1268 struct ir3_instruction *a, unsigned aflags, \
1269 struct ir3_instruction *b, unsigned bflags) \
1271 struct ir3_instruction *instr = \
1272 ir3_instr_create(block, opc); \
1274 __ssa_src(instr, a, aflags); \
1275 __ssa_src(instr, b, bflags); \
1276 instr->flags |= flag; \
1279 #define INSTR2F(f, name) __INSTR2(IR3_INSTR_##f, name##_##f, OPC_##name)
1280 #define INSTR2(name) __INSTR2(0, name, OPC_##name)
1282 #define __INSTR3(flag, name, opc) \
1283 static inline struct ir3_instruction * \
1284 ir3_##name(struct ir3_block *block, \
1285 struct ir3_instruction *a, unsigned aflags, \
1286 struct ir3_instruction *b, unsigned bflags, \
1287 struct ir3_instruction *c, unsigned cflags) \
1289 struct ir3_instruction *instr = \
1290 ir3_instr_create2(block, opc, 4); \
1292 __ssa_src(instr, a, aflags); \
1293 __ssa_src(instr, b, bflags); \
1294 __ssa_src(instr, c, cflags); \
1295 instr->flags |= flag; \
1298 #define INSTR3F(f, name) __INSTR3(IR3_INSTR_##f, name##_##f, OPC_##name)
1299 #define INSTR3(name) __INSTR3(0, name, OPC_##name)
1301 #define __INSTR4(flag, name, opc) \
1302 static inline struct ir3_instruction * \
1303 ir3_##name(struct ir3_block *block, \
1304 struct ir3_instruction *a, unsigned aflags, \
1305 struct ir3_instruction *b, unsigned bflags, \
1306 struct ir3_instruction *c, unsigned cflags, \
1307 struct ir3_instruction *d, unsigned dflags) \
1309 struct ir3_instruction *instr = \
1310 ir3_instr_create2(block, opc, 5); \
1312 __ssa_src(instr, a, aflags); \
1313 __ssa_src(instr, b, bflags); \
1314 __ssa_src(instr, c, cflags); \
1315 __ssa_src(instr, d, dflags); \
1316 instr->flags |= flag; \
1319 #define INSTR4F(f, name) __INSTR4(IR3_INSTR_##f, name##_##f, OPC_##name)
1320 #define INSTR4(name) __INSTR4(0, name, OPC_##name)
1322 /* cat0 instructions: */
1332 /* cat2 instructions, most 2 src but some 1 src: */
1380 /* cat3 instructions: */
1398 /* cat4 instructions: */
1407 /* cat5 instructions: */
1414 static inline struct ir3_instruction
*
1415 ir3_SAM(struct ir3_block
*block
, opc_t opc
, type_t type
,
1416 unsigned wrmask
, unsigned flags
, struct ir3_instruction
*samp_tex
,
1417 struct ir3_instruction
*src0
, struct ir3_instruction
*src1
)
1419 struct ir3_instruction
*sam
;
1421 sam
= ir3_instr_create(block
, opc
);
1422 sam
->flags
|= flags
| IR3_INSTR_S2EN
;
1423 __ssa_dst(sam
)->wrmask
= wrmask
;
1424 __ssa_src(sam
, samp_tex
, IR3_REG_HALF
);
1426 __ssa_src(sam
, src0
, 0)->wrmask
= (1 << (src0
->regs_count
- 1)) - 1;
1429 __ssa_src(sam
, src1
, 0)->wrmask
=(1 << (src1
->regs_count
- 1)) - 1;
1431 sam
->cat5
.type
= type
;
1436 /* cat6 instructions: */
1451 INSTR2(ATOMIC_CMPXCHG
)
1460 INSTR3F(G
, ATOMIC_ADD
)
1461 INSTR3F(G
, ATOMIC_SUB
)
1462 INSTR3F(G
, ATOMIC_XCHG
)
1463 INSTR3F(G
, ATOMIC_INC
)
1464 INSTR3F(G
, ATOMIC_DEC
)
1465 INSTR3F(G
, ATOMIC_CMPXCHG
)
1466 INSTR3F(G
, ATOMIC_MIN
)
1467 INSTR3F(G
, ATOMIC_MAX
)
1468 INSTR3F(G
, ATOMIC_AND
)
1469 INSTR3F(G
, ATOMIC_OR
)
1470 INSTR3F(G
, ATOMIC_XOR
)
1475 INSTR4F(G
, ATOMIC_ADD
)
1476 INSTR4F(G
, ATOMIC_SUB
)
1477 INSTR4F(G
, ATOMIC_XCHG
)
1478 INSTR4F(G
, ATOMIC_INC
)
1479 INSTR4F(G
, ATOMIC_DEC
)
1480 INSTR4F(G
, ATOMIC_CMPXCHG
)
1481 INSTR4F(G
, ATOMIC_MIN
)
1482 INSTR4F(G
, ATOMIC_MAX
)
1483 INSTR4F(G
, ATOMIC_AND
)
1484 INSTR4F(G
, ATOMIC_OR
)
1485 INSTR4F(G
, ATOMIC_XOR
)
1490 /* cat7 instructions: */
1494 /* meta instructions: */
1495 INSTR0(META_TEX_PREFETCH
);
1497 /* ************************************************************************* */
1498 /* split this out or find some helper to use.. like main/bitset.h.. */
1504 typedef uint8_t regmask_t
[2 * MAX_REG
/ 8];
1506 static inline unsigned regmask_idx(struct ir3_register
*reg
)
1508 unsigned num
= (reg
->flags
& IR3_REG_RELATIV
) ? reg
->array
.offset
: reg
->num
;
1509 debug_assert(num
< MAX_REG
);
1510 if (reg
->flags
& IR3_REG_HALF
) {
1520 static inline void regmask_init(regmask_t
*regmask
)
1522 memset(regmask
, 0, sizeof(*regmask
));
1525 static inline void regmask_set(regmask_t
*regmask
, struct ir3_register
*reg
)
1527 unsigned idx
= regmask_idx(reg
);
1528 if (reg
->flags
& IR3_REG_RELATIV
) {
1530 for (i
= 0; i
< reg
->size
; i
++, idx
++)
1531 (*regmask
)[idx
/ 8] |= 1 << (idx
% 8);
1534 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
1536 (*regmask
)[idx
/ 8] |= 1 << (idx
% 8);
1540 static inline void regmask_or(regmask_t
*dst
, regmask_t
*a
, regmask_t
*b
)
1543 for (i
= 0; i
< ARRAY_SIZE(*dst
); i
++)
1544 (*dst
)[i
] = (*a
)[i
] | (*b
)[i
];
1547 /* set bits in a if not set in b, conceptually:
1550 static inline void regmask_set_if_not(regmask_t
*a
,
1551 struct ir3_register
*reg
, regmask_t
*b
)
1553 unsigned idx
= regmask_idx(reg
);
1554 if (reg
->flags
& IR3_REG_RELATIV
) {
1556 for (i
= 0; i
< reg
->size
; i
++, idx
++)
1557 if (!((*b
)[idx
/ 8] & (1 << (idx
% 8))))
1558 (*a
)[idx
/ 8] |= 1 << (idx
% 8);
1561 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
1563 if (!((*b
)[idx
/ 8] & (1 << (idx
% 8))))
1564 (*a
)[idx
/ 8] |= 1 << (idx
% 8);
1568 static inline bool regmask_get(regmask_t
*regmask
,
1569 struct ir3_register
*reg
)
1571 unsigned idx
= regmask_idx(reg
);
1572 if (reg
->flags
& IR3_REG_RELATIV
) {
1574 for (i
= 0; i
< reg
->size
; i
++, idx
++)
1575 if ((*regmask
)[idx
/ 8] & (1 << (idx
% 8)))
1579 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
1581 if ((*regmask
)[idx
/ 8] & (1 << (idx
% 8)))
1587 /* ************************************************************************* */