2 * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 #include "compiler/shader_enums.h"
32 #include "util/bitscan.h"
33 #include "util/list.h"
35 #include "util/u_debug.h"
37 #include "instr-a3xx.h"
39 /* low level intermediate representation of an adreno shader program */
43 struct ir3_instruction
;
49 uint16_t instrs_count
; /* expanded to account for rpt's */
50 uint16_t nops_count
; /* # of nop instructions, including nopN */
53 /* NOTE: max_reg, etc, does not include registers not touched
54 * by the shader (ie. vertex fetched via VFD_DECODE but not
57 int8_t max_reg
; /* highest GPR # used by shader */
61 /* number of sync bits: */
64 /* estimate of number of cycles stalled on (ss) */
67 uint16_t last_baryf
; /* instruction # of last varying fetch */
72 IR3_REG_CONST
= 0x001,
73 IR3_REG_IMMED
= 0x002,
75 /* high registers are used for some things in compute shaders,
76 * for example. Seems to be for things that are global to all
77 * threads in a wave, so possibly these are global/shared by
78 * all the threads in the wave?
81 IR3_REG_RELATIV
= 0x010,
83 /* Most instructions, it seems, can do float abs/neg but not
84 * integer. The CP pass needs to know what is intended (int or
85 * float) in order to do the right thing. For this reason the
86 * abs/neg flags are split out into float and int variants. In
87 * addition, .b (bitwise) operations, the negate is actually a
88 * bitwise not, so split that out into a new flag to make it
97 IR3_REG_POS_INF
= 0x1000,
98 /* (ei) flag, end-input? Set on last bary, presumably to signal
99 * that the shader needs no more input:
102 /* meta-flags, for intermediate stages of IR, ie.
103 * before register assignment is done:
105 IR3_REG_SSA
= 0x4000, /* 'instr' is ptr to assigning instr */
106 IR3_REG_ARRAY
= 0x8000,
110 /* used for cat5 instructions, but also for internal/IR level
111 * tracking of what registers are read/written by an instruction.
112 * wrmask may be a bad name since it is used to represent both
113 * src and dst that touch multiple adjacent registers.
115 unsigned wrmask
: 16; /* up to vec16 */
117 /* for relative addressing, 32bits for array size is too small,
118 * but otoh we don't need to deal with disjoint sets, so instead
119 * use a simple size field (number of scalar components).
121 * Note the size field isn't important for relative const (since
122 * we don't have to do register allocation for constants).
126 bool merged
: 1; /* half-regs conflict with full regs (ie >= a6xx) */
129 * the component is in the low two bits of the reg #, so
130 * rN.x becomes: (N << 2) | x
145 /* For IR3_REG_SSA, src registers contain ptr back to assigning
148 * For IR3_REG_ARRAY, the pointer is back to the last dependent
149 * array access (although the net effect is the same, it points
150 * back to a previous instruction that we depend on).
152 struct ir3_instruction
*instr
;
156 * Stupid/simple growable array implementation:
158 #define DECLARE_ARRAY(type, name) \
159 unsigned name ## _count, name ## _sz; \
162 #define array_insert(ctx, arr, val) do { \
163 if (arr ## _count == arr ## _sz) { \
164 arr ## _sz = MAX2(2 * arr ## _sz, 16); \
165 arr = reralloc_size(ctx, arr, arr ## _sz * sizeof(arr[0])); \
167 arr[arr ##_count++] = val; \
170 struct ir3_instruction
{
171 struct ir3_block
*block
;
174 /* (sy) flag is set on first instruction, and after sample
175 * instructions (probably just on RAW hazard).
177 IR3_INSTR_SY
= 0x001,
178 /* (ss) flag is set on first instruction, and first instruction
179 * to depend on the result of "long" instructions (RAW hazard):
181 * rcp, rsq, log2, exp2, sin, cos, sqrt
183 * It seems to synchronize until all in-flight instructions are
184 * completed, for example:
187 * add.f hr2.z, (neg)hr2.z, hc0.y
188 * mul.f hr2.w, (neg)hr2.y, (neg)hr2.y
191 * mad.f16 hr2.w, hr2.z, hr2.z, hr2.w
193 * mad.f16 hr2.w, (neg)hr0.w, (neg)hr0.w, hr2.w
194 * (ss)(rpt2)mul.f hr1.x, (r)hr1.x, hr1.w
195 * (rpt2)mul.f hr0.x, (neg)(r)hr0.x, hr2.x
197 * The last mul.f does not have (ss) set, presumably because the
198 * (ss) on the previous instruction does the job.
200 * The blob driver also seems to set it on WAR hazards, although
201 * not really clear if this is needed or just blob compiler being
202 * sloppy. So far I haven't found a case where removing the (ss)
203 * causes problems for WAR hazard, but I could just be getting
207 * (ss)(rpt2)mad.f32 r3.y, (r)c9.x, r1.x, (r)r3.z
210 IR3_INSTR_SS
= 0x002,
211 /* (jp) flag is set on jump targets:
213 IR3_INSTR_JP
= 0x004,
214 IR3_INSTR_UL
= 0x008,
215 IR3_INSTR_3D
= 0x010,
220 IR3_INSTR_S2EN
= 0x200,
222 IR3_INSTR_SAT
= 0x800,
223 /* (cat5/cat6) Bindless */
224 IR3_INSTR_B
= 0x1000,
225 /* (cat5-only) Get some parts of the encoding from a1.x */
226 IR3_INSTR_A1EN
= 0x2000,
227 /* meta-flags, for intermediate stages of IR, ie.
228 * before register assignment is done:
230 IR3_INSTR_MARK
= 0x4000,
231 IR3_INSTR_UNUSED
= 0x8000,
239 struct ir3_register
**regs
;
245 struct ir3_block
*target
;
248 type_t src_type
, dst_type
;
262 unsigned tex_base
: 3;
269 int iim_val
: 3; /* for ldgb/stgb, # of components */
275 unsigned w
: 1; /* write */
276 unsigned r
: 1; /* read */
277 unsigned l
: 1; /* local */
278 unsigned g
: 1; /* global */
280 /* for meta-instructions, just used to hold extra data
281 * before instruction scheduling, etc
284 int off
; /* component/offset */
287 /* for output collects, this maps back to the entry in the
288 * ir3_shader_variant::outputs table.
294 unsigned input_offset
;
295 unsigned samp_base
: 3;
296 unsigned tex_base
: 3;
299 /* maps back to entry in ir3_shader_variant::inputs table: */
301 /* for sysvals, identifies the sysval type. Mostly so we can
302 * identify the special cases where a sysval should not be DCE'd
303 * (currently, just pre-fs texture fetch)
305 gl_system_value sysval
;
309 /* transient values used during various algorithms: */
311 /* The instruction depth is the max dependency distance to output.
313 * You can also think of it as the "cost", if we did any sort of
314 * optimization for register footprint. Ie. a value that is just
315 * result of moving a const to a reg would have a low cost, so to
316 * it could make sense to duplicate the instruction at various
317 * points where the result is needed to reduce register footprint.
320 /* When we get to the RA stage, we no longer need depth, but
321 * we do need instruction's position/name:
329 /* used for per-pass extra instruction data.
331 * TODO we should remove the per-pass data like this and 'use_count'
332 * and do something similar to what RA does w/ ir3_ra_instr_data..
333 * ie. use the ir3_count_instructions pass, and then use instr->ip
334 * to index into a table of pass-private data.
339 * Valid if pass calls ir3_find_ssa_uses().. see foreach_ssa_use()
343 int sun
; /* Sethi–Ullman number, used by sched */
344 int use_count
; /* currently just updated/used by cp */
346 /* Used during CP and RA stages. For collect and shader inputs/
347 * outputs where we need a sequence of consecutive registers,
348 * keep track of each src instructions left (ie 'n-1') and right
349 * (ie 'n+1') neighbor. The front-end must insert enough mov's
350 * to ensure that each instruction has at most one left and at
351 * most one right neighbor. During the copy-propagation pass,
352 * we only remove mov's when we can preserve this constraint.
353 * And during the RA stage, we use the neighbor information to
354 * allocate a block of registers in one shot.
356 * TODO: maybe just add something like:
357 * struct ir3_instruction_ref {
358 * struct ir3_instruction *instr;
362 * Or can we get away without the refcnt stuff? It seems like
363 * it should be overkill.. the problem is if, potentially after
364 * already eliminating some mov's, if you have a single mov that
365 * needs to be grouped with it's neighbors in two different
366 * places (ex. shader output and a collect).
369 struct ir3_instruction
*left
, *right
;
370 uint16_t left_cnt
, right_cnt
;
373 /* an instruction can reference at most one address register amongst
374 * it's src/dst registers. Beyond that, you need to insert mov's.
376 * NOTE: do not write this directly, use ir3_instr_set_address()
378 struct ir3_instruction
*address
;
380 /* Tracking for additional dependent instructions. Used to handle
381 * barriers, WAR hazards for arrays/SSBOs/etc.
383 DECLARE_ARRAY(struct ir3_instruction
*, deps
);
386 * From PoV of instruction scheduling, not execution (ie. ignores global/
387 * local distinction):
388 * shared image atomic SSBO everything
389 * barrier()/ - R/W R/W R/W R/W X
390 * groupMemoryBarrier()
391 * memoryBarrier() - R/W R/W
392 * (but only images declared coherent?)
393 * memoryBarrierAtomic() - R/W
394 * memoryBarrierBuffer() - R/W
395 * memoryBarrierImage() - R/W
396 * memoryBarrierShared() - R/W
398 * TODO I think for SSBO/image/shared, in cases where we can determine
399 * which variable is accessed, we don't need to care about accesses to
400 * different variables (unless declared coherent??)
403 IR3_BARRIER_EVERYTHING
= 1 << 0,
404 IR3_BARRIER_SHARED_R
= 1 << 1,
405 IR3_BARRIER_SHARED_W
= 1 << 2,
406 IR3_BARRIER_IMAGE_R
= 1 << 3,
407 IR3_BARRIER_IMAGE_W
= 1 << 4,
408 IR3_BARRIER_BUFFER_R
= 1 << 5,
409 IR3_BARRIER_BUFFER_W
= 1 << 6,
410 IR3_BARRIER_ARRAY_R
= 1 << 7,
411 IR3_BARRIER_ARRAY_W
= 1 << 8,
412 } barrier_class
, barrier_conflict
;
414 /* Entry in ir3_block's instruction list: */
415 struct list_head node
;
421 // TODO only computerator/assembler:
425 static inline struct ir3_instruction
*
426 ir3_neighbor_first(struct ir3_instruction
*instr
)
429 while (instr
->cp
.left
) {
430 instr
= instr
->cp
.left
;
431 if (++cnt
> 0xffff) {
439 static inline int ir3_neighbor_count(struct ir3_instruction
*instr
)
443 debug_assert(!instr
->cp
.left
);
445 while (instr
->cp
.right
) {
447 instr
= instr
->cp
.right
;
458 struct ir3_compiler
*compiler
;
459 gl_shader_stage type
;
461 DECLARE_ARRAY(struct ir3_instruction
*, inputs
);
462 DECLARE_ARRAY(struct ir3_instruction
*, outputs
);
464 /* Track bary.f (and ldlv) instructions.. this is needed in
465 * scheduling to ensure that all varying fetches happen before
466 * any potential kill instructions. The hw gets grumpy if all
467 * threads in a group are killed before the last bary.f gets
468 * a chance to signal end of input (ei).
470 DECLARE_ARRAY(struct ir3_instruction
*, baryfs
);
472 /* Track all indirect instructions (read and write). To avoid
473 * deadlock scenario where an address register gets scheduled,
474 * but other dependent src instructions cannot be scheduled due
475 * to dependency on a *different* address register value, the
476 * scheduler needs to ensure that all dependencies other than
477 * the instruction other than the address register are scheduled
478 * before the one that writes the address register. Having a
479 * convenient list of instructions that reference some address
480 * register simplifies this.
482 DECLARE_ARRAY(struct ir3_instruction
*, a0_users
);
485 DECLARE_ARRAY(struct ir3_instruction
*, a1_users
);
487 /* and same for instructions that consume predicate register: */
488 DECLARE_ARRAY(struct ir3_instruction
*, predicates
);
490 /* Track texture sample instructions which need texture state
491 * patched in (for astc-srgb workaround):
493 DECLARE_ARRAY(struct ir3_instruction
*, astc_srgb
);
495 /* List of blocks: */
496 struct list_head block_list
;
498 /* List of ir3_array's: */
499 struct list_head array_list
;
501 unsigned max_sun
; /* max Sethi–Ullman number */
504 unsigned block_count
, instr_count
;
509 struct list_head node
;
513 struct nir_register
*r
;
515 /* To avoid array write's from getting DCE'd, keep track of the
516 * most recent write. Any array access depends on the most
517 * recent write. This way, nothing depends on writes after the
518 * last read. But all the writes that happen before that have
519 * something depending on them
521 struct ir3_instruction
*last_write
;
523 /* extra stuff used in RA pass: */
524 unsigned base
; /* base vreg name */
525 unsigned reg
; /* base physical reg */
526 uint16_t start_ip
, end_ip
;
528 /* Indicates if half-precision */
532 struct ir3_array
* ir3_lookup_array(struct ir3
*ir
, unsigned id
);
535 struct list_head node
;
538 const struct nir_block
*nblock
;
540 struct list_head instr_list
; /* list of ir3_instruction */
542 /* each block has either one or two successors.. in case of
543 * two successors, 'condition' decides which one to follow.
544 * A block preceding an if/else has two successors.
546 struct ir3_instruction
*condition
;
547 struct ir3_block
*successors
[2];
549 struct set
*predecessors
; /* set of ir3_block */
551 uint16_t start_ip
, end_ip
;
553 /* Track instructions which do not write a register but other-
554 * wise must not be discarded (such as kill, stg, etc)
556 DECLARE_ARRAY(struct ir3_instruction
*, keeps
);
558 /* used for per-pass extra block data. Mainly used right
559 * now in RA step to track livein/liveout.
568 static inline uint32_t
569 block_id(struct ir3_block
*block
)
572 return block
->serialno
;
574 return (uint32_t)(unsigned long)block
;
578 struct ir3
* ir3_create(struct ir3_compiler
*compiler
, gl_shader_stage type
);
579 void ir3_destroy(struct ir3
*shader
);
580 void * ir3_assemble(struct ir3
*shader
,
581 struct ir3_info
*info
, uint32_t gpu_id
);
582 void * ir3_alloc(struct ir3
*shader
, int sz
);
584 struct ir3_block
* ir3_block_create(struct ir3
*shader
);
586 struct ir3_instruction
* ir3_instr_create(struct ir3_block
*block
, opc_t opc
);
587 struct ir3_instruction
* ir3_instr_create2(struct ir3_block
*block
,
588 opc_t opc
, int nreg
);
589 struct ir3_instruction
* ir3_instr_clone(struct ir3_instruction
*instr
);
590 void ir3_instr_add_dep(struct ir3_instruction
*instr
, struct ir3_instruction
*dep
);
591 const char *ir3_instr_name(struct ir3_instruction
*instr
);
593 struct ir3_register
* ir3_reg_create(struct ir3_instruction
*instr
,
595 struct ir3_register
* ir3_reg_clone(struct ir3
*shader
,
596 struct ir3_register
*reg
);
598 void ir3_instr_set_address(struct ir3_instruction
*instr
,
599 struct ir3_instruction
*addr
);
601 static inline bool ir3_instr_check_mark(struct ir3_instruction
*instr
)
603 if (instr
->flags
& IR3_INSTR_MARK
)
604 return true; /* already visited */
605 instr
->flags
|= IR3_INSTR_MARK
;
609 void ir3_block_clear_mark(struct ir3_block
*block
);
610 void ir3_clear_mark(struct ir3
*shader
);
612 unsigned ir3_count_instructions(struct ir3
*ir
);
614 void ir3_find_ssa_uses(struct ir3
*ir
, void *mem_ctx
, bool falsedeps
);
616 #include "util/set.h"
617 #define foreach_ssa_use(__use, __instr) \
618 for (struct ir3_instruction *__use = (void *)~0; \
619 __use && (__instr)->uses; __use = NULL) \
620 set_foreach ((__instr)->uses, __entry) \
621 if ((__use = (void *)__entry->key))
623 #define MAX_ARRAYS 16
631 static inline uint32_t regid(int num
, int comp
)
633 return (num
<< 2) | (comp
& 0x3);
636 static inline uint32_t reg_num(struct ir3_register
*reg
)
638 return reg
->num
>> 2;
641 static inline uint32_t reg_comp(struct ir3_register
*reg
)
643 return reg
->num
& 0x3;
646 #define INVALID_REG regid(63, 0)
647 #define VALIDREG(r) ((r) != INVALID_REG)
648 #define CONDREG(r, val) COND(VALIDREG(r), (val))
650 static inline bool is_flow(struct ir3_instruction
*instr
)
652 return (opc_cat(instr
->opc
) == 0);
655 static inline bool is_kill(struct ir3_instruction
*instr
)
657 return instr
->opc
== OPC_KILL
;
660 static inline bool is_nop(struct ir3_instruction
*instr
)
662 return instr
->opc
== OPC_NOP
;
665 static inline bool is_same_type_reg(struct ir3_register
*reg1
,
666 struct ir3_register
*reg2
)
668 unsigned type_reg1
= (reg1
->flags
& (IR3_REG_HIGH
| IR3_REG_HALF
));
669 unsigned type_reg2
= (reg2
->flags
& (IR3_REG_HIGH
| IR3_REG_HALF
));
671 if (type_reg1
^ type_reg2
)
677 /* Is it a non-transformative (ie. not type changing) mov? This can
678 * also include absneg.s/absneg.f, which for the most part can be
679 * treated as a mov (single src argument).
681 static inline bool is_same_type_mov(struct ir3_instruction
*instr
)
683 struct ir3_register
*dst
;
685 switch (instr
->opc
) {
687 if (instr
->cat1
.src_type
!= instr
->cat1
.dst_type
)
689 /* If the type of dest reg and src reg are different,
690 * it shouldn't be considered as same type mov
692 if (!is_same_type_reg(instr
->regs
[0], instr
->regs
[1]))
697 if (instr
->flags
& IR3_INSTR_SAT
)
699 /* If the type of dest reg and src reg are different,
700 * it shouldn't be considered as same type mov
702 if (!is_same_type_reg(instr
->regs
[0], instr
->regs
[1]))
709 dst
= instr
->regs
[0];
711 /* mov's that write to a0 or p0.x are special: */
712 if (dst
->num
== regid(REG_P0
, 0))
714 if (reg_num(dst
) == REG_A0
)
717 if (dst
->flags
& (IR3_REG_RELATIV
| IR3_REG_ARRAY
))
723 /* A move from const, which changes size but not type, can also be
724 * folded into dest instruction in some cases.
726 static inline bool is_const_mov(struct ir3_instruction
*instr
)
728 if (instr
->opc
!= OPC_MOV
)
731 if (!(instr
->regs
[1]->flags
& IR3_REG_CONST
))
734 type_t src_type
= instr
->cat1
.src_type
;
735 type_t dst_type
= instr
->cat1
.dst_type
;
737 return (type_float(src_type
) && type_float(dst_type
)) ||
738 (type_uint(src_type
) && type_uint(dst_type
)) ||
739 (type_sint(src_type
) && type_sint(dst_type
));
742 static inline bool is_alu(struct ir3_instruction
*instr
)
744 return (1 <= opc_cat(instr
->opc
)) && (opc_cat(instr
->opc
) <= 3);
747 static inline bool is_sfu(struct ir3_instruction
*instr
)
749 return (opc_cat(instr
->opc
) == 4);
752 static inline bool is_tex(struct ir3_instruction
*instr
)
754 return (opc_cat(instr
->opc
) == 5);
757 static inline bool is_tex_or_prefetch(struct ir3_instruction
*instr
)
759 return is_tex(instr
) || (instr
->opc
== OPC_META_TEX_PREFETCH
);
762 static inline bool is_mem(struct ir3_instruction
*instr
)
764 return (opc_cat(instr
->opc
) == 6);
767 static inline bool is_barrier(struct ir3_instruction
*instr
)
769 return (opc_cat(instr
->opc
) == 7);
773 is_half(struct ir3_instruction
*instr
)
775 return !!(instr
->regs
[0]->flags
& IR3_REG_HALF
);
779 is_high(struct ir3_instruction
*instr
)
781 return !!(instr
->regs
[0]->flags
& IR3_REG_HIGH
);
785 is_store(struct ir3_instruction
*instr
)
787 /* these instructions, the "destination" register is
788 * actually a source, the address to store to.
790 switch (instr
->opc
) {
805 static inline bool is_load(struct ir3_instruction
*instr
)
807 switch (instr
->opc
) {
817 /* probably some others too.. */
824 static inline bool is_input(struct ir3_instruction
*instr
)
826 /* in some cases, ldlv is used to fetch varying without
827 * interpolation.. fortunately inloc is the first src
828 * register in either case
830 switch (instr
->opc
) {
839 static inline bool is_bool(struct ir3_instruction
*instr
)
841 switch (instr
->opc
) {
851 static inline bool is_meta(struct ir3_instruction
*instr
)
853 return (opc_cat(instr
->opc
) == -1);
856 static inline unsigned dest_regs(struct ir3_instruction
*instr
)
858 if ((instr
->regs_count
== 0) || is_store(instr
) || is_flow(instr
))
861 return util_last_bit(instr
->regs
[0]->wrmask
);
864 static inline bool writes_addr0(struct ir3_instruction
*instr
)
866 if (instr
->regs_count
> 0) {
867 struct ir3_register
*dst
= instr
->regs
[0];
868 return dst
->num
== regid(REG_A0
, 0);
873 static inline bool writes_addr1(struct ir3_instruction
*instr
)
875 if (instr
->regs_count
> 0) {
876 struct ir3_register
*dst
= instr
->regs
[0];
877 return dst
->num
== regid(REG_A0
, 1);
882 static inline bool writes_pred(struct ir3_instruction
*instr
)
884 if (instr
->regs_count
> 0) {
885 struct ir3_register
*dst
= instr
->regs
[0];
886 return reg_num(dst
) == REG_P0
;
891 /* returns defining instruction for reg */
892 /* TODO better name */
893 static inline struct ir3_instruction
*ssa(struct ir3_register
*reg
)
895 if (reg
->flags
& (IR3_REG_SSA
| IR3_REG_ARRAY
)) {
901 static inline bool conflicts(struct ir3_instruction
*a
,
902 struct ir3_instruction
*b
)
904 return (a
&& b
) && (a
!= b
);
907 static inline bool reg_gpr(struct ir3_register
*r
)
909 if (r
->flags
& (IR3_REG_CONST
| IR3_REG_IMMED
))
911 if ((reg_num(r
) == REG_A0
) || (reg_num(r
) == REG_P0
))
916 static inline type_t
half_type(type_t type
)
919 case TYPE_F32
: return TYPE_F16
;
920 case TYPE_U32
: return TYPE_U16
;
921 case TYPE_S32
: return TYPE_S16
;
932 /* some cat2 instructions (ie. those which are not float) can embed an
935 static inline bool ir3_cat2_int(opc_t opc
)
975 static inline bool ir3_cat2_float(opc_t opc
)
998 static inline bool ir3_cat3_float(opc_t opc
)
1011 /* map cat2 instruction to valid abs/neg flags: */
1012 static inline unsigned ir3_cat2_absneg(opc_t opc
)
1029 return IR3_REG_FABS
| IR3_REG_FNEG
;
1050 return IR3_REG_SABS
| IR3_REG_SNEG
;
1064 return IR3_REG_BNOT
;
1071 /* map cat3 instructions to valid abs/neg flags: */
1072 static inline unsigned ir3_cat3_absneg(opc_t opc
)
1079 return IR3_REG_FNEG
;
1091 /* neg *may* work on 3rd src.. */
1101 #define MASK(n) ((1 << (n)) - 1)
1103 /* iterator for an instructions's sources (reg), also returns src #: */
1104 #define foreach_src_n(__srcreg, __n, __instr) \
1105 if ((__instr)->regs_count) \
1106 for (unsigned __cnt = (__instr)->regs_count - 1, __n = 0; __n < __cnt; __n++) \
1107 if ((__srcreg = (__instr)->regs[__n + 1]))
1109 /* iterator for an instructions's sources (reg): */
1110 #define foreach_src(__srcreg, __instr) \
1111 foreach_src_n(__srcreg, __i, __instr)
1113 static inline unsigned __ssa_src_cnt(struct ir3_instruction
*instr
)
1115 unsigned cnt
= instr
->regs_count
+ instr
->deps_count
;
1121 static inline struct ir3_instruction
**
1122 __ssa_srcp_n(struct ir3_instruction
*instr
, unsigned n
)
1124 if (n
== (instr
->regs_count
+ instr
->deps_count
))
1125 return &instr
->address
;
1126 if (n
>= instr
->regs_count
)
1127 return &instr
->deps
[n
- instr
->regs_count
];
1128 if (ssa(instr
->regs
[n
]))
1129 return &instr
->regs
[n
]->instr
;
1133 static inline bool __is_false_dep(struct ir3_instruction
*instr
, unsigned n
)
1135 if (n
== (instr
->regs_count
+ instr
->deps_count
))
1137 if (n
>= instr
->regs_count
)
1142 #define foreach_ssa_srcp_n(__srcp, __n, __instr) \
1143 for (struct ir3_instruction **__srcp = (void *)~0; __srcp; __srcp = NULL) \
1144 for (unsigned __cnt = __ssa_src_cnt(__instr), __n = 0; __n < __cnt; __n++) \
1145 if ((__srcp = __ssa_srcp_n(__instr, __n)))
1147 #define foreach_ssa_srcp(__srcp, __instr) \
1148 foreach_ssa_srcp_n(__srcp, __i, __instr)
1150 /* iterator for an instruction's SSA sources (instr), also returns src #: */
1151 #define foreach_ssa_src_n(__srcinst, __n, __instr) \
1152 foreach_ssa_srcp_n(__srcp, __n, __instr) \
1153 if ((__srcinst = *__srcp))
1155 /* iterator for an instruction's SSA sources (instr): */
1156 #define foreach_ssa_src(__srcinst, __instr) \
1157 foreach_ssa_src_n(__srcinst, __i, __instr)
1159 /* iterators for shader inputs: */
1160 #define foreach_input_n(__ininstr, __cnt, __ir) \
1161 for (unsigned __cnt = 0; __cnt < (__ir)->inputs_count; __cnt++) \
1162 if ((__ininstr = (__ir)->inputs[__cnt]))
1163 #define foreach_input(__ininstr, __ir) \
1164 foreach_input_n(__ininstr, __i, __ir)
1166 /* iterators for shader outputs: */
1167 #define foreach_output_n(__outinstr, __cnt, __ir) \
1168 for (unsigned __cnt = 0; __cnt < (__ir)->outputs_count; __cnt++) \
1169 if ((__outinstr = (__ir)->outputs[__cnt]))
1170 #define foreach_output(__outinstr, __ir) \
1171 foreach_output_n(__outinstr, __i, __ir)
1173 /* iterators for instructions: */
1174 #define foreach_instr(__instr, __list) \
1175 list_for_each_entry(struct ir3_instruction, __instr, __list, node)
1176 #define foreach_instr_rev(__instr, __list) \
1177 list_for_each_entry_rev(struct ir3_instruction, __instr, __list, node)
1178 #define foreach_instr_safe(__instr, __list) \
1179 list_for_each_entry_safe(struct ir3_instruction, __instr, __list, node)
1181 /* iterators for blocks: */
1182 #define foreach_block(__block, __list) \
1183 list_for_each_entry(struct ir3_block, __block, __list, node)
1184 #define foreach_block_safe(__block, __list) \
1185 list_for_each_entry_safe(struct ir3_block, __block, __list, node)
1187 /* iterators for arrays: */
1188 #define foreach_array(__array, __list) \
1189 list_for_each_entry(struct ir3_array, __array, __list, node)
1192 void ir3_print(struct ir3
*ir
);
1193 void ir3_print_instr(struct ir3_instruction
*instr
);
1195 /* delay calculation: */
1196 int ir3_delayslots(struct ir3_instruction
*assigner
,
1197 struct ir3_instruction
*consumer
, unsigned n
, bool soft
);
1198 unsigned ir3_delay_calc(struct ir3_block
*block
, struct ir3_instruction
*instr
,
1199 bool soft
, bool pred
);
1200 void ir3_remove_nops(struct ir3
*ir
);
1202 /* depth calculation: */
1203 struct ir3_shader_variant
;
1204 void ir3_depth(struct ir3
*ir
, struct ir3_shader_variant
*so
);
1206 /* fp16 conversion folding */
1207 void ir3_cf(struct ir3
*ir
);
1209 /* copy-propagate: */
1210 void ir3_cp(struct ir3
*ir
, struct ir3_shader_variant
*so
);
1212 /* group neighbors and insert mov's to resolve conflicts: */
1213 void ir3_group(struct ir3
*ir
);
1215 /* Sethi–Ullman numbering: */
1216 void ir3_sun(struct ir3
*ir
);
1219 void ir3_sched_add_deps(struct ir3
*ir
);
1220 int ir3_sched(struct ir3
*ir
);
1223 int ir3_postsched(struct ir3_context
*ctx
);
1225 bool ir3_a6xx_fixup_atomic_dests(struct ir3
*ir
, struct ir3_shader_variant
*so
);
1227 /* register assignment: */
1228 struct ir3_ra_reg_set
* ir3_ra_alloc_reg_set(struct ir3_compiler
*compiler
);
1229 int ir3_ra(struct ir3_shader_variant
*v
, struct ir3_instruction
**precolor
, unsigned nprecolor
);
1232 void ir3_legalize(struct ir3
*ir
, struct ir3_shader_variant
*so
, int *max_bary
);
1235 ir3_has_latency_to_hide(struct ir3
*ir
)
1237 /* VS/GS/TCS/TESS co-exist with frag shader invocations, but we don't
1238 * know the nature of the fragment shader. Just assume it will have
1241 if (ir
->type
!= MESA_SHADER_FRAGMENT
)
1244 foreach_block (block
, &ir
->block_list
) {
1245 foreach_instr (instr
, &block
->instr_list
) {
1246 if (is_tex_or_prefetch(instr
))
1249 if (is_load(instr
)) {
1250 switch (instr
->opc
) {
1265 /* ************************************************************************* */
1266 /* instruction helpers */
1268 /* creates SSA src of correct type (ie. half vs full precision) */
1269 static inline struct ir3_register
* __ssa_src(struct ir3_instruction
*instr
,
1270 struct ir3_instruction
*src
, unsigned flags
)
1272 struct ir3_register
*reg
;
1273 if (src
->regs
[0]->flags
& IR3_REG_HALF
)
1274 flags
|= IR3_REG_HALF
;
1275 reg
= ir3_reg_create(instr
, 0, IR3_REG_SSA
| flags
);
1277 reg
->wrmask
= src
->regs
[0]->wrmask
;
1281 static inline struct ir3_register
* __ssa_dst(struct ir3_instruction
*instr
)
1283 struct ir3_register
*reg
= ir3_reg_create(instr
, 0, 0);
1284 reg
->flags
|= IR3_REG_SSA
;
1288 static inline struct ir3_instruction
*
1289 create_immed_typed(struct ir3_block
*block
, uint32_t val
, type_t type
)
1291 struct ir3_instruction
*mov
;
1292 unsigned flags
= (type_size(type
) < 32) ? IR3_REG_HALF
: 0;
1294 mov
= ir3_instr_create(block
, OPC_MOV
);
1295 mov
->cat1
.src_type
= type
;
1296 mov
->cat1
.dst_type
= type
;
1297 __ssa_dst(mov
)->flags
|= flags
;
1298 ir3_reg_create(mov
, 0, IR3_REG_IMMED
| flags
)->uim_val
= val
;
1303 static inline struct ir3_instruction
*
1304 create_immed(struct ir3_block
*block
, uint32_t val
)
1306 return create_immed_typed(block
, val
, TYPE_U32
);
1309 static inline struct ir3_instruction
*
1310 create_uniform_typed(struct ir3_block
*block
, unsigned n
, type_t type
)
1312 struct ir3_instruction
*mov
;
1313 unsigned flags
= (type_size(type
) < 32) ? IR3_REG_HALF
: 0;
1315 mov
= ir3_instr_create(block
, OPC_MOV
);
1316 mov
->cat1
.src_type
= type
;
1317 mov
->cat1
.dst_type
= type
;
1318 __ssa_dst(mov
)->flags
|= flags
;
1319 ir3_reg_create(mov
, n
, IR3_REG_CONST
| flags
);
1324 static inline struct ir3_instruction
*
1325 create_uniform(struct ir3_block
*block
, unsigned n
)
1327 return create_uniform_typed(block
, n
, TYPE_F32
);
1330 static inline struct ir3_instruction
*
1331 create_uniform_indirect(struct ir3_block
*block
, int n
,
1332 struct ir3_instruction
*address
)
1334 struct ir3_instruction
*mov
;
1336 mov
= ir3_instr_create(block
, OPC_MOV
);
1337 mov
->cat1
.src_type
= TYPE_U32
;
1338 mov
->cat1
.dst_type
= TYPE_U32
;
1340 ir3_reg_create(mov
, 0, IR3_REG_CONST
| IR3_REG_RELATIV
)->array
.offset
= n
;
1342 ir3_instr_set_address(mov
, address
);
1347 static inline struct ir3_instruction
*
1348 ir3_MOV(struct ir3_block
*block
, struct ir3_instruction
*src
, type_t type
)
1350 struct ir3_instruction
*instr
= ir3_instr_create(block
, OPC_MOV
);
1352 if (src
->regs
[0]->flags
& IR3_REG_ARRAY
) {
1353 struct ir3_register
*src_reg
= __ssa_src(instr
, src
, IR3_REG_ARRAY
);
1354 src_reg
->array
= src
->regs
[0]->array
;
1356 __ssa_src(instr
, src
, src
->regs
[0]->flags
& IR3_REG_HIGH
);
1358 debug_assert(!(src
->regs
[0]->flags
& IR3_REG_RELATIV
));
1359 instr
->cat1
.src_type
= type
;
1360 instr
->cat1
.dst_type
= type
;
1364 static inline struct ir3_instruction
*
1365 ir3_COV(struct ir3_block
*block
, struct ir3_instruction
*src
,
1366 type_t src_type
, type_t dst_type
)
1368 struct ir3_instruction
*instr
= ir3_instr_create(block
, OPC_MOV
);
1369 unsigned dst_flags
= (type_size(dst_type
) < 32) ? IR3_REG_HALF
: 0;
1370 unsigned src_flags
= (type_size(src_type
) < 32) ? IR3_REG_HALF
: 0;
1372 debug_assert((src
->regs
[0]->flags
& IR3_REG_HALF
) == src_flags
);
1374 __ssa_dst(instr
)->flags
|= dst_flags
;
1375 __ssa_src(instr
, src
, 0);
1376 instr
->cat1
.src_type
= src_type
;
1377 instr
->cat1
.dst_type
= dst_type
;
1378 debug_assert(!(src
->regs
[0]->flags
& IR3_REG_ARRAY
));
1382 static inline struct ir3_instruction
*
1383 ir3_NOP(struct ir3_block
*block
)
1385 return ir3_instr_create(block
, OPC_NOP
);
1388 #define IR3_INSTR_0 0
1390 #define __INSTR0(flag, name, opc) \
1391 static inline struct ir3_instruction * \
1392 ir3_##name(struct ir3_block *block) \
1394 struct ir3_instruction *instr = \
1395 ir3_instr_create(block, opc); \
1396 instr->flags |= flag; \
1399 #define INSTR0F(f, name) __INSTR0(IR3_INSTR_##f, name##_##f, OPC_##name)
1400 #define INSTR0(name) __INSTR0(0, name, OPC_##name)
1402 #define __INSTR1(flag, name, opc) \
1403 static inline struct ir3_instruction * \
1404 ir3_##name(struct ir3_block *block, \
1405 struct ir3_instruction *a, unsigned aflags) \
1407 struct ir3_instruction *instr = \
1408 ir3_instr_create(block, opc); \
1410 __ssa_src(instr, a, aflags); \
1411 instr->flags |= flag; \
1414 #define INSTR1F(f, name) __INSTR1(IR3_INSTR_##f, name##_##f, OPC_##name)
1415 #define INSTR1(name) __INSTR1(0, name, OPC_##name)
1417 #define __INSTR2(flag, name, opc) \
1418 static inline struct ir3_instruction * \
1419 ir3_##name(struct ir3_block *block, \
1420 struct ir3_instruction *a, unsigned aflags, \
1421 struct ir3_instruction *b, unsigned bflags) \
1423 struct ir3_instruction *instr = \
1424 ir3_instr_create(block, opc); \
1426 __ssa_src(instr, a, aflags); \
1427 __ssa_src(instr, b, bflags); \
1428 instr->flags |= flag; \
1431 #define INSTR2F(f, name) __INSTR2(IR3_INSTR_##f, name##_##f, OPC_##name)
1432 #define INSTR2(name) __INSTR2(0, name, OPC_##name)
1434 #define __INSTR3(flag, name, opc) \
1435 static inline struct ir3_instruction * \
1436 ir3_##name(struct ir3_block *block, \
1437 struct ir3_instruction *a, unsigned aflags, \
1438 struct ir3_instruction *b, unsigned bflags, \
1439 struct ir3_instruction *c, unsigned cflags) \
1441 struct ir3_instruction *instr = \
1442 ir3_instr_create2(block, opc, 4); \
1444 __ssa_src(instr, a, aflags); \
1445 __ssa_src(instr, b, bflags); \
1446 __ssa_src(instr, c, cflags); \
1447 instr->flags |= flag; \
1450 #define INSTR3F(f, name) __INSTR3(IR3_INSTR_##f, name##_##f, OPC_##name)
1451 #define INSTR3(name) __INSTR3(0, name, OPC_##name)
1453 #define __INSTR4(flag, name, opc) \
1454 static inline struct ir3_instruction * \
1455 ir3_##name(struct ir3_block *block, \
1456 struct ir3_instruction *a, unsigned aflags, \
1457 struct ir3_instruction *b, unsigned bflags, \
1458 struct ir3_instruction *c, unsigned cflags, \
1459 struct ir3_instruction *d, unsigned dflags) \
1461 struct ir3_instruction *instr = \
1462 ir3_instr_create2(block, opc, 5); \
1464 __ssa_src(instr, a, aflags); \
1465 __ssa_src(instr, b, bflags); \
1466 __ssa_src(instr, c, cflags); \
1467 __ssa_src(instr, d, dflags); \
1468 instr->flags |= flag; \
1471 #define INSTR4F(f, name) __INSTR4(IR3_INSTR_##f, name##_##f, OPC_##name)
1472 #define INSTR4(name) __INSTR4(0, name, OPC_##name)
1474 /* cat0 instructions: */
1485 /* cat2 instructions, most 2 src but some 1 src: */
1533 /* cat3 instructions: */
1542 /* NOTE: SEL_B32 checks for zero vs nonzero */
1552 /* cat4 instructions: */
1564 /* cat5 instructions: */
1573 static inline struct ir3_instruction
*
1574 ir3_SAM(struct ir3_block
*block
, opc_t opc
, type_t type
,
1575 unsigned wrmask
, unsigned flags
, struct ir3_instruction
*samp_tex
,
1576 struct ir3_instruction
*src0
, struct ir3_instruction
*src1
)
1578 struct ir3_instruction
*sam
;
1580 sam
= ir3_instr_create(block
, opc
);
1581 sam
->flags
|= flags
;
1582 __ssa_dst(sam
)->wrmask
= wrmask
;
1583 if (flags
& IR3_INSTR_S2EN
) {
1584 __ssa_src(sam
, samp_tex
, IR3_REG_HALF
);
1587 __ssa_src(sam
, src0
, 0)->wrmask
= (1 << (src0
->regs_count
- 1)) - 1;
1590 __ssa_src(sam
, src1
, 0)->wrmask
=(1 << (src1
->regs_count
- 1)) - 1;
1592 sam
->cat5
.type
= type
;
1597 /* cat6 instructions: */
1612 INSTR2(ATOMIC_CMPXCHG
)
1622 INSTR3F(G
, ATOMIC_ADD
)
1623 INSTR3F(G
, ATOMIC_SUB
)
1624 INSTR3F(G
, ATOMIC_XCHG
)
1625 INSTR3F(G
, ATOMIC_INC
)
1626 INSTR3F(G
, ATOMIC_DEC
)
1627 INSTR3F(G
, ATOMIC_CMPXCHG
)
1628 INSTR3F(G
, ATOMIC_MIN
)
1629 INSTR3F(G
, ATOMIC_MAX
)
1630 INSTR3F(G
, ATOMIC_AND
)
1631 INSTR3F(G
, ATOMIC_OR
)
1632 INSTR3F(G
, ATOMIC_XOR
)
1637 INSTR4F(G
, ATOMIC_ADD
)
1638 INSTR4F(G
, ATOMIC_SUB
)
1639 INSTR4F(G
, ATOMIC_XCHG
)
1640 INSTR4F(G
, ATOMIC_INC
)
1641 INSTR4F(G
, ATOMIC_DEC
)
1642 INSTR4F(G
, ATOMIC_CMPXCHG
)
1643 INSTR4F(G
, ATOMIC_MIN
)
1644 INSTR4F(G
, ATOMIC_MAX
)
1645 INSTR4F(G
, ATOMIC_AND
)
1646 INSTR4F(G
, ATOMIC_OR
)
1647 INSTR4F(G
, ATOMIC_XOR
)
1652 /* cat7 instructions: */
1656 /* meta instructions: */
1657 INSTR0(META_TEX_PREFETCH
);
1659 /* ************************************************************************* */
1660 /* split this out or find some helper to use.. like main/bitset.h.. */
1663 #include "util/bitset.h"
1667 typedef BITSET_DECLARE(regmask_t
, 2 * MAX_REG
);
1670 __regmask_get(regmask_t
*regmask
, struct ir3_register
*reg
, unsigned n
)
1673 /* a6xx+ case, with merged register file, we track things in terms
1674 * of half-precision registers, with a full precisions register
1675 * using two half-precision slots:
1677 if (reg
->flags
& IR3_REG_HALF
) {
1678 return BITSET_TEST(*regmask
, n
);
1681 return BITSET_TEST(*regmask
, n
) || BITSET_TEST(*regmask
, n
+1);
1684 /* pre a6xx case, with separate register file for half and full
1687 if (reg
->flags
& IR3_REG_HALF
)
1689 return BITSET_TEST(*regmask
, n
);
1694 __regmask_set(regmask_t
*regmask
, struct ir3_register
*reg
, unsigned n
)
1697 /* a6xx+ case, with merged register file, we track things in terms
1698 * of half-precision registers, with a full precisions register
1699 * using two half-precision slots:
1701 if (reg
->flags
& IR3_REG_HALF
) {
1702 BITSET_SET(*regmask
, n
);
1705 BITSET_SET(*regmask
, n
);
1706 BITSET_SET(*regmask
, n
+1);
1709 /* pre a6xx case, with separate register file for half and full
1712 if (reg
->flags
& IR3_REG_HALF
)
1714 BITSET_SET(*regmask
, n
);
1718 static inline void regmask_init(regmask_t
*regmask
)
1720 memset(regmask
, 0, sizeof(*regmask
));
1723 static inline void regmask_set(regmask_t
*regmask
, struct ir3_register
*reg
)
1725 if (reg
->flags
& IR3_REG_RELATIV
) {
1726 for (unsigned i
= 0; i
< reg
->size
; i
++)
1727 __regmask_set(regmask
, reg
, reg
->array
.offset
+ i
);
1729 for (unsigned mask
= reg
->wrmask
, n
= reg
->num
; mask
; mask
>>= 1, n
++)
1731 __regmask_set(regmask
, reg
, n
);
1735 static inline void regmask_or(regmask_t
*dst
, regmask_t
*a
, regmask_t
*b
)
1738 for (i
= 0; i
< ARRAY_SIZE(*dst
); i
++)
1739 (*dst
)[i
] = (*a
)[i
] | (*b
)[i
];
1742 static inline bool regmask_get(regmask_t
*regmask
,
1743 struct ir3_register
*reg
)
1745 if (reg
->flags
& IR3_REG_RELATIV
) {
1746 for (unsigned i
= 0; i
< reg
->size
; i
++)
1747 if (__regmask_get(regmask
, reg
, reg
->array
.offset
+ i
))
1750 for (unsigned mask
= reg
->wrmask
, n
= reg
->num
; mask
; mask
>>= 1, n
++)
1752 if (__regmask_get(regmask
, reg
, n
))
1758 /* ************************************************************************* */