src/freedreno/ir3/ir3_a6xx.c

   1 /*
   2  * Copyright (C) 2017-2018 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #define GPU 600
  28
  29 #include "ir3_context.h"
  30 #include "ir3_image.h"
  31
  32 /*
  33  * Handlers for instructions changed/added in a6xx:
  34  *
  35  * Starting with a6xx, isam and stbi is used for SSBOs as well; stbi and the
  36  * atomic instructions (used for both SSBO and image) use a new instruction
  37  * encoding compared to a4xx/a5xx.
  38  */
  39
  40
  41 /* src[] = { buffer_index, offset }. No const_index */
  42 static void
  43 emit_intrinsic_load_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
  44                 struct ir3_instruction **dst)
  45 {
  46         struct ir3_block *b = ctx->block;
  47         struct ir3_instruction *offset;
  48         struct ir3_instruction *ldib;
  49
  50         /* can this be non-const buffer_index?  how do we handle that? */
  51         int ibo_idx = ir3_ssbo_to_ibo(ctx->so->shader, nir_src_as_uint(intr->src[0]));
  52
  53         offset = ir3_get_src(ctx, &intr->src[2])[0];
  54
  55         ldib = ir3_LDIB(b, create_immed(b, ibo_idx), 0, offset, 0);
  56         ldib->regs[0]->wrmask = MASK(intr->num_components);
  57         ldib->cat6.iim_val = intr->num_components;
  58         ldib->cat6.d = 1;
  59         ldib->cat6.type = TYPE_U32;
  60         ldib->barrier_class = IR3_BARRIER_BUFFER_R;
  61         ldib->barrier_conflict = IR3_BARRIER_BUFFER_W;
  62
  63         ir3_split_dest(b, dst, ldib, 0, intr->num_components);
  64 }
  65
  66 /* src[] = { value, block_index, offset }. const_index[] = { write_mask } */
  67 static void
  68 emit_intrinsic_store_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr)
  69 {
  70         struct ir3_block *b = ctx->block;
  71         struct ir3_instruction *stib, *val, *offset;
  72         /* TODO handle wrmask properly, see _store_shared().. but I think
  73          * it is more a PITA than that, since blob ends up loading the
  74          * masked components and writing them back out.
  75          */
  76         unsigned wrmask = intr->const_index[0];
  77         unsigned ncomp = ffs(~wrmask) - 1;
  78
  79         /* can this be non-const buffer_index?  how do we handle that? */
  80         int ibo_idx = ir3_ssbo_to_ibo(ctx->so->shader, nir_src_as_uint(intr->src[1]));
  81
  82         /* src0 is offset, src1 is value:
  83          */
  84         val = ir3_create_collect(ctx, ir3_get_src(ctx, &intr->src[0]), ncomp);
  85         offset = ir3_get_src(ctx, &intr->src[3])[0];
  86
  87         stib = ir3_STIB(b, create_immed(b, ibo_idx), 0, offset, 0, val, 0);
  88         stib->cat6.iim_val = ncomp;
  89         stib->cat6.d = 1;
  90         stib->cat6.type = TYPE_U32;
  91         stib->barrier_class = IR3_BARRIER_BUFFER_W;
  92         stib->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
  93
  94         array_insert(b, b->keeps, stib);
  95 }
  96
  97 /*
  98  * SSBO atomic intrinsics
  99  *
 100  * All of the SSBO atomic memory operations read a value from memory,
 101  * compute a new value using one of the operations below, write the new
 102  * value to memory, and return the original value read.
 103  *
 104  * All operations take 3 sources except CompSwap that takes 4. These
 105  * sources represent:
 106  *
 107  * 0: The SSBO buffer index.
 108  * 1: The offset into the SSBO buffer of the variable that the atomic
 109  *    operation will operate on.
 110  * 2: The data parameter to the atomic function (i.e. the value to add
 111  *    in ssbo_atomic_add, etc).
 112  * 3: For CompSwap only: the second data parameter.
 113  */
 114 static struct ir3_instruction *
 115 emit_intrinsic_atomic_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr)
 116 {
 117         struct ir3_block *b = ctx->block;
 118         struct ir3_instruction *atomic, *ibo, *src0, *src1, *data, *dummy;
 119         type_t type = TYPE_U32;
 120
 121         /* can this be non-const buffer_index?  how do we handle that? */
 122         int ibo_idx = ir3_ssbo_to_ibo(ctx->so->shader,
 123                         nir_src_as_uint(intr->src[0]));
 124         ibo = create_immed(b, ibo_idx);
 125
 126         data   = ir3_get_src(ctx, &intr->src[2])[0];
 127
 128         /* So this gets a bit creative:
 129          *
 130          *    src0    - vecN offset/coords
 131          *    src1.x  - is actually destination register
 132          *    src1.y  - is 'data' except for cmpxchg where src2.y is 'compare'
 133          *    src1.z  - is 'data' for cmpxchg
 134          *
 135          * The combining src and dest kinda doesn't work out so well with how
 136          * scheduling and RA work.  So for now we create a dummy src2.x, and
 137          * then in a later fixup path, insert an extra MOV out of src1.x.
 138          * See ir3_a6xx_fixup_atomic_dests().
 139          *
 140          * Note that nir already multiplies the offset by four
 141          */
 142         dummy = create_immed(b, 0);
 143
 144         if (intr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap_ir3) {
 145                 src0 = ir3_get_src(ctx, &intr->src[4])[0];
 146                 struct ir3_instruction *compare = ir3_get_src(ctx, &intr->src[3])[0];
 147                 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
 148                         dummy, compare, data
 149                 }, 3);
 150         } else {
 151                 src0 = ir3_get_src(ctx, &intr->src[3])[0];
 152                 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
 153                         dummy, data
 154                 }, 2);
 155         }
 156
 157         switch (intr->intrinsic) {
 158         case nir_intrinsic_ssbo_atomic_add_ir3:
 159                 atomic = ir3_ATOMIC_ADD_G(b, ibo, 0, src0, 0, src1, 0);
 160                 break;
 161         case nir_intrinsic_ssbo_atomic_imin_ir3:
 162                 atomic = ir3_ATOMIC_MIN_G(b, ibo, 0, src0, 0, src1, 0);
 163                 type = TYPE_S32;
 164                 break;
 165         case nir_intrinsic_ssbo_atomic_umin_ir3:
 166                 atomic = ir3_ATOMIC_MIN_G(b, ibo, 0, src0, 0, src1, 0);
 167                 break;
 168         case nir_intrinsic_ssbo_atomic_imax_ir3:
 169                 atomic = ir3_ATOMIC_MAX_G(b, ibo, 0, src0, 0, src1, 0);
 170                 type = TYPE_S32;
 171                 break;
 172         case nir_intrinsic_ssbo_atomic_umax_ir3:
 173                 atomic = ir3_ATOMIC_MAX_G(b, ibo, 0, src0, 0, src1, 0);
 174                 break;
 175         case nir_intrinsic_ssbo_atomic_and_ir3:
 176                 atomic = ir3_ATOMIC_AND_G(b, ibo, 0, src0, 0, src1, 0);
 177                 break;
 178         case nir_intrinsic_ssbo_atomic_or_ir3:
 179                 atomic = ir3_ATOMIC_OR_G(b, ibo, 0, src0, 0, src1, 0);
 180                 break;
 181         case nir_intrinsic_ssbo_atomic_xor_ir3:
 182                 atomic = ir3_ATOMIC_XOR_G(b, ibo, 0, src0, 0, src1, 0);
 183                 break;
 184         case nir_intrinsic_ssbo_atomic_exchange_ir3:
 185                 atomic = ir3_ATOMIC_XCHG_G(b, ibo, 0, src0, 0, src1, 0);
 186                 break;
 187         case nir_intrinsic_ssbo_atomic_comp_swap_ir3:
 188                 atomic = ir3_ATOMIC_CMPXCHG_G(b, ibo, 0, src0, 0, src1, 0);
 189                 break;
 190         default:
 191                 unreachable("boo");
 192         }
 193
 194         atomic->cat6.iim_val = 1;
 195         atomic->cat6.d = 1;
 196         atomic->cat6.type = type;
 197         atomic->barrier_class = IR3_BARRIER_BUFFER_W;
 198         atomic->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
 199
 200         /* even if nothing consume the result, we can't DCE the instruction: */
 201         array_insert(b, b->keeps, atomic);
 202
 203         return atomic;
 204 }
 205
 206 /* src[] = { deref, coord, sample_index, value }. const_index[] = {} */
 207 static void
 208 emit_intrinsic_store_image(struct ir3_context *ctx, nir_intrinsic_instr *intr)
 209 {
 210         struct ir3_block *b = ctx->block;
 211         const nir_variable *var = nir_intrinsic_get_var(intr, 0);
 212         struct ir3_instruction *stib;
 213         struct ir3_instruction * const *value = ir3_get_src(ctx, &intr->src[3]);
 214         struct ir3_instruction * const *coords = ir3_get_src(ctx, &intr->src[1]);
 215         unsigned ncoords = ir3_get_image_coords(var, NULL);
 216         unsigned slot = ir3_get_image_slot(nir_src_as_deref(intr->src[0]));
 217         unsigned ibo_idx = ir3_image_to_ibo(ctx->so->shader, slot);
 218         unsigned ncomp = ir3_get_num_components_for_glformat(var->data.image.format);
 219
 220         /* src0 is offset, src1 is value:
 221          */
 222         stib = ir3_STIB(b, create_immed(b, ibo_idx), 0,
 223                         ir3_create_collect(ctx, coords, ncoords), 0,
 224                         ir3_create_collect(ctx, value, ncomp), 0);
 225         stib->cat6.iim_val = ncomp;
 226         stib->cat6.d = ncoords;
 227         stib->cat6.type = ir3_get_image_type(var);
 228         stib->cat6.typed = true;
 229         stib->barrier_class = IR3_BARRIER_IMAGE_W;
 230         stib->barrier_conflict = IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W;
 231
 232         array_insert(b, b->keeps, stib);
 233 }
 234
 235 /* src[] = { deref, coord, sample_index, value, compare }. const_index[] = {} */
 236 static struct ir3_instruction *
 237 emit_intrinsic_atomic_image(struct ir3_context *ctx, nir_intrinsic_instr *intr)
 238 {
 239         struct ir3_block *b = ctx->block;
 240         const nir_variable *var = nir_intrinsic_get_var(intr, 0);
 241         struct ir3_instruction *atomic, *ibo, *src0, *src1, *dummy;
 242         struct ir3_instruction * const *coords = ir3_get_src(ctx, &intr->src[1]);
 243         struct ir3_instruction *value = ir3_get_src(ctx, &intr->src[3])[0];
 244         unsigned ncoords = ir3_get_image_coords(var, NULL);
 245         unsigned slot = ir3_get_image_slot(nir_src_as_deref(intr->src[0]));
 246         unsigned ibo_idx = ir3_image_to_ibo(ctx->so->shader, slot);
 247
 248         ibo = create_immed(b, ibo_idx);
 249
 250         /* So this gets a bit creative:
 251          *
 252          *    src0    - vecN offset/coords
 253          *    src1.x  - is actually destination register
 254          *    src1.y  - is 'value' except for cmpxchg where src2.y is 'compare'
 255          *    src1.z  - is 'value' for cmpxchg
 256          *
 257          * The combining src and dest kinda doesn't work out so well with how
 258          * scheduling and RA work.  So for now we create a dummy src2.x, and
 259          * then in a later fixup path, insert an extra MOV out of src1.x.
 260          * See ir3_a6xx_fixup_atomic_dests().
 261          */
 262         dummy = create_immed(b, 0);
 263         src0 = ir3_create_collect(ctx, coords, ncoords);
 264
 265         if (intr->intrinsic == nir_intrinsic_image_deref_atomic_comp_swap) {
 266                 struct ir3_instruction *compare = ir3_get_src(ctx, &intr->src[4])[0];
 267                 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
 268                         dummy, compare, value
 269                 }, 3);
 270         } else {
 271                 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
 272                         dummy, value
 273                 }, 2);
 274         }
 275
 276         switch (intr->intrinsic) {
 277         case nir_intrinsic_image_deref_atomic_add:
 278                 atomic = ir3_ATOMIC_ADD_G(b, ibo, 0, src0, 0, src1, 0);
 279                 break;
 280         case nir_intrinsic_image_deref_atomic_imin:
 281         case nir_intrinsic_image_deref_atomic_umin:
 282                 atomic = ir3_ATOMIC_MIN_G(b, ibo, 0, src0, 0, src1, 0);
 283                 break;
 284         case nir_intrinsic_image_deref_atomic_imax:
 285         case nir_intrinsic_image_deref_atomic_umax:
 286                 atomic = ir3_ATOMIC_MAX_G(b, ibo, 0, src0, 0, src1, 0);
 287                 break;
 288         case nir_intrinsic_image_deref_atomic_and:
 289                 atomic = ir3_ATOMIC_AND_G(b, ibo, 0, src0, 0, src1, 0);
 290                 break;
 291         case nir_intrinsic_image_deref_atomic_or:
 292                 atomic = ir3_ATOMIC_OR_G(b, ibo, 0, src0, 0, src1, 0);
 293                 break;
 294         case nir_intrinsic_image_deref_atomic_xor:
 295                 atomic = ir3_ATOMIC_XOR_G(b, ibo, 0, src0, 0, src1, 0);
 296                 break;
 297         case nir_intrinsic_image_deref_atomic_exchange:
 298                 atomic = ir3_ATOMIC_XCHG_G(b, ibo, 0, src0, 0, src1, 0);
 299                 break;
 300         case nir_intrinsic_image_deref_atomic_comp_swap:
 301                 atomic = ir3_ATOMIC_CMPXCHG_G(b, ibo, 0, src0, 0, src1, 0);
 302                 break;
 303         default:
 304                 unreachable("boo");
 305         }
 306
 307         atomic->cat6.iim_val = 1;
 308         atomic->cat6.d = ncoords;
 309         atomic->cat6.type = ir3_get_image_type(var);
 310         atomic->cat6.typed = true;
 311         atomic->barrier_class = IR3_BARRIER_IMAGE_W;
 312         atomic->barrier_conflict = IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W;
 313
 314         /* even if nothing consume the result, we can't DCE the instruction: */
 315         array_insert(b, b->keeps, atomic);
 316
 317         return atomic;
 318 }
 319
 320 const struct ir3_context_funcs ir3_a6xx_funcs = {
 321                 .emit_intrinsic_load_ssbo = emit_intrinsic_load_ssbo,
 322                 .emit_intrinsic_store_ssbo = emit_intrinsic_store_ssbo,
 323                 .emit_intrinsic_atomic_ssbo = emit_intrinsic_atomic_ssbo,
 324                 .emit_intrinsic_store_image = emit_intrinsic_store_image,
 325                 .emit_intrinsic_atomic_image = emit_intrinsic_atomic_image,
 326 };
 327
 328 /*
 329  * Special pass to run after instruction scheduling to insert an
 330  * extra mov from src1.x to dst.  This way the other compiler passes
 331  * can ignore this quirk of the new instruction encoding.
 332  *
 333  * This should run after RA.
 334  */
 335
 336 static struct ir3_instruction *
 337 get_atomic_dest_mov(struct ir3_instruction *atomic)
 338 {
 339         struct ir3_instruction *mov;
 340
 341         /* if we've already created the mov-out, then re-use it: */
 342         if (atomic->data)
 343                 return atomic->data;
 344
 345         /* We are already out of SSA here, so we can't use the nice builders: */
 346         mov = ir3_instr_create(atomic->block, OPC_MOV);
 347         ir3_reg_create(mov, 0, 0);    /* dst */
 348         ir3_reg_create(mov, 0, 0);    /* src */
 349
 350         mov->cat1.src_type = TYPE_U32;
 351         mov->cat1.dst_type = TYPE_U32;
 352
 353         /* extract back out the 'dummy' which serves as stand-in for dest: */
 354         struct ir3_instruction *src = atomic->regs[3]->instr;
 355         debug_assert(src->opc == OPC_META_COLLECT);
 356
 357         *mov->regs[0] = *atomic->regs[0];
 358         *mov->regs[1] = *src->regs[1]->instr->regs[0];
 359
 360         mov->flags |= IR3_INSTR_SY;
 361
 362         /* it will have already been appended to the end of the block, which
 363          * isn't where we want it, so fix-up the location:
 364          */
 365         list_delinit(&mov->node);
 366         list_add(&mov->node, &atomic->node);
 367
 368         return atomic->data = mov;
 369 }
 370
 371 bool
 372 ir3_a6xx_fixup_atomic_dests(struct ir3 *ir, struct ir3_shader_variant *so)
 373 {
 374         bool progress = false;
 375
 376         if (ir3_shader_nibo(so) == 0)
 377                 return false;
 378
 379         foreach_block (block, &ir->block_list) {
 380                 foreach_instr (instr, &block->instr_list) {
 381                         instr->data = NULL;
 382                 }
 383         }
 384
 385         foreach_block (block, &ir->block_list) {
 386                 foreach_instr_safe (instr, &block->instr_list) {
 387                         struct ir3_register *reg;
 388
 389                         foreach_src(reg, instr) {
 390                                 struct ir3_instruction *src = reg->instr;
 391
 392                                 if (!src)
 393                                         continue;
 394
 395                                 if (is_atomic(src->opc) && (src->flags & IR3_INSTR_G)) {
 396                                         reg->instr = get_atomic_dest_mov(src);
 397                                         progress = true;
 398                                 }
 399                         }
 400                 }
 401         }
 402
 403         /* we also need to fixup shader outputs: */
 404         struct ir3_instruction *out;
 405         foreach_output_n (out, n, ir) {
 406                 if (is_atomic(out->opc) && (out->flags & IR3_INSTR_G)) {
 407                         ir->outputs[n] = get_atomic_dest_mov(out);
 408                         progress = true;
 409                 }
 410         }
 411
 412         return progress;
 413 }