src/freedreno/ir3/ir3_compiler.c

   1 /*
   2  * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #include "util/ralloc.h"
  28
  29 #include "ir3_compiler.h"
  30
  31 static const struct debug_named_value shader_debug_options[] = {
  32         {"vs",         IR3_DBG_SHADER_VS,  "Print shader disasm for vertex shaders"},
  33         {"tcs",        IR3_DBG_SHADER_TCS, "Print shader disasm for tess ctrl shaders"},
  34         {"tes",        IR3_DBG_SHADER_TES, "Print shader disasm for tess eval shaders"},
  35         {"gs",         IR3_DBG_SHADER_GS,  "Print shader disasm for geometry shaders"},
  36         {"fs",         IR3_DBG_SHADER_FS,  "Print shader disasm for fragment shaders"},
  37         {"cs",         IR3_DBG_SHADER_CS,  "Print shader disasm for compute shaders"},
  38         {"disasm",     IR3_DBG_DISASM,     "Dump NIR and adreno shader disassembly"},
  39         {"optmsgs",    IR3_DBG_OPTMSGS,    "Enable optimizer debug messages"},
  40         {"forces2en",  IR3_DBG_FORCES2EN,  "Force s2en mode for tex sampler instructions"},
  41         {"nouboopt",   IR3_DBG_NOUBOOPT,   "Disable lowering UBO to uniform"},
  42         {"nofp16",     IR3_DBG_NOFP16,     "Don't lower mediump to fp16"},
  43         {"nocache",    IR3_DBG_NOCACHE,    "Disable shader cache"},
  44 #ifdef DEBUG
  45         /* DEBUG-only options: */
  46         {"schedmsgs",  IR3_DBG_SCHEDMSGS,  "Enable scheduler debug messages"},
  47         {"ramsgs",     IR3_DBG_RAMSGS,     "Enable register-allocation debug messages"},
  48 #endif
  49         DEBUG_NAMED_VALUE_END
  50 };
  51
  52 DEBUG_GET_ONCE_FLAGS_OPTION(ir3_shader_debug, "IR3_SHADER_DEBUG", shader_debug_options, 0)
  53
  54 enum ir3_shader_debug ir3_shader_debug = 0;
  55
  56 void
  57 ir3_compiler_destroy(struct ir3_compiler *compiler)
  58 {
  59         ralloc_free(compiler);
  60 }
  61
  62 struct ir3_compiler *
  63 ir3_compiler_create(struct fd_device *dev, uint32_t gpu_id)
  64 {
  65         struct ir3_compiler *compiler = rzalloc(NULL, struct ir3_compiler);
  66
  67         ir3_shader_debug = debug_get_option_ir3_shader_debug();
  68
  69         compiler->dev = dev;
  70         compiler->gpu_id = gpu_id;
  71         compiler->set = ir3_ra_alloc_reg_set(compiler, false);
  72
  73         if (compiler->gpu_id >= 600) {
  74                 compiler->mergedregs_set = ir3_ra_alloc_reg_set(compiler, true);
  75                 compiler->samgq_workaround = true;
  76                 /* a6xx split the pipeline state into geometry and fragment state, in
  77                  * order to let the VS run ahead of the FS. As a result there are now
  78                  * separate const files for the the fragment shader and everything
  79                  * else, and separate limits. There seems to be a shared limit, but
  80                  * it's higher than the vert or frag limits.
  81                  *
  82                  * TODO: The shared limit seems to be different on different on
  83                  * different models.
  84                  */
  85                 compiler->max_const_pipeline = 640;
  86                 compiler->max_const_frag = 512;
  87                 compiler->max_const_geom = 512;
  88                 compiler->max_const_safe = 128;
  89
  90                 /* Compute shaders don't share a const file with the FS. Instead they
  91                  * have their own file, which is smaller than the FS one.
  92                  *
  93                  * TODO: is this true on earlier gen's?
  94                  */
  95                 compiler->max_const_compute = 256;
  96
  97                 if (compiler->gpu_id == 650)
  98                         compiler->tess_use_shared = true;
  99         } else {
 100                 compiler->max_const_pipeline = 512;
 101                 compiler->max_const_geom = 512;
 102                 compiler->max_const_frag = 512;
 103                 compiler->max_const_compute = 512;
 104
 105                 /* Note: this will have to change if/when we support tess+GS on
 106                  * earlier gen's.
 107                  */
 108                 compiler->max_const_safe = 256;
 109         }
 110
 111         if (compiler->gpu_id >= 400) {
 112                 /* need special handling for "flat" */
 113                 compiler->flat_bypass = true;
 114                 compiler->levels_add_one = false;
 115                 compiler->unminify_coords = false;
 116                 compiler->txf_ms_with_isaml = false;
 117                 compiler->array_index_add_half = true;
 118                 compiler->instr_align = 16;
 119                 compiler->const_upload_unit = 4;
 120         } else {
 121                 /* no special handling for "flat" */
 122                 compiler->flat_bypass = false;
 123                 compiler->levels_add_one = true;
 124                 compiler->unminify_coords = true;
 125                 compiler->txf_ms_with_isaml = true;
 126                 compiler->array_index_add_half = false;
 127                 compiler->instr_align = 4;
 128                 compiler->const_upload_unit = 8;
 129         }
 130
 131         ir3_disk_cache_init(compiler);
 132
 133         return compiler;
 134 }