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freedreno/ir3: rework setup_{input,output} to make struct varyings work
[mesa.git] / src / freedreno / ir3 / ir3_compiler_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include <stdarg.h>
28
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
36 #include "ir3_nir.h"
37
38 #include "instr-a3xx.h"
39 #include "ir3.h"
40 #include "ir3_context.h"
41
42 void
43 ir3_handle_bindless_cat6(struct ir3_instruction *instr, nir_src rsrc)
44 {
45 nir_intrinsic_instr *intrin = ir3_bindless_resource(rsrc);
46 if (!intrin)
47 return;
48
49 instr->flags |= IR3_INSTR_B;
50 instr->cat6.base = nir_intrinsic_desc_set(intrin);
51 }
52
53 static struct ir3_instruction *
54 create_input(struct ir3_context *ctx, unsigned compmask)
55 {
56 struct ir3_instruction *in;
57
58 in = ir3_instr_create(ctx->in_block, OPC_META_INPUT);
59 in->input.sysval = ~0;
60 __ssa_dst(in)->wrmask = compmask;
61
62 array_insert(ctx->ir, ctx->ir->inputs, in);
63
64 return in;
65 }
66
67 static struct ir3_instruction *
68 create_frag_input(struct ir3_context *ctx, struct ir3_instruction *coord, unsigned n)
69 {
70 struct ir3_block *block = ctx->block;
71 struct ir3_instruction *instr;
72 /* packed inloc is fixed up later: */
73 struct ir3_instruction *inloc = create_immed(block, n);
74
75 if (coord) {
76 instr = ir3_BARY_F(block, inloc, 0, coord, 0);
77 } else if (ctx->compiler->flat_bypass) {
78 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
79 instr->cat6.type = TYPE_U32;
80 instr->cat6.iim_val = 1;
81 } else {
82 instr = ir3_BARY_F(block, inloc, 0, ctx->ij[IJ_PERSP_PIXEL], 0);
83 instr->regs[2]->wrmask = 0x3;
84 }
85
86 return instr;
87 }
88
89 static struct ir3_instruction *
90 create_driver_param(struct ir3_context *ctx, enum ir3_driver_param dp)
91 {
92 /* first four vec4 sysval's reserved for UBOs: */
93 /* NOTE: dp is in scalar, but there can be >4 dp components: */
94 struct ir3_const_state *const_state = ir3_const_state(ctx->so);
95 unsigned n = const_state->offsets.driver_param;
96 unsigned r = regid(n + dp / 4, dp % 4);
97 return create_uniform(ctx->block, r);
98 }
99
100 /*
101 * Adreno's comparisons produce a 1 for true and 0 for false, in either 16 or
102 * 32-bit registers. We use NIR's 1-bit integers to represent bools, and
103 * trust that we will only see and/or/xor on those 1-bit values, so we can
104 * safely store NIR i1s in a 32-bit reg while always containing either a 1 or
105 * 0.
106 */
107
108 /*
109 * alu/sfu instructions:
110 */
111
112 static struct ir3_instruction *
113 create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
114 unsigned src_bitsize, nir_op op)
115 {
116 type_t src_type, dst_type;
117
118 switch (op) {
119 case nir_op_f2f32:
120 case nir_op_f2f16_rtne:
121 case nir_op_f2f16_rtz:
122 case nir_op_f2f16:
123 case nir_op_f2i32:
124 case nir_op_f2i16:
125 case nir_op_f2i8:
126 case nir_op_f2u32:
127 case nir_op_f2u16:
128 case nir_op_f2u8:
129 switch (src_bitsize) {
130 case 32:
131 src_type = TYPE_F32;
132 break;
133 case 16:
134 src_type = TYPE_F16;
135 break;
136 default:
137 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
138 }
139 break;
140
141 case nir_op_i2f32:
142 case nir_op_i2f16:
143 case nir_op_i2i32:
144 case nir_op_i2i16:
145 case nir_op_i2i8:
146 switch (src_bitsize) {
147 case 32:
148 src_type = TYPE_S32;
149 break;
150 case 16:
151 src_type = TYPE_S16;
152 break;
153 case 8:
154 src_type = TYPE_S8;
155 break;
156 default:
157 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
158 }
159 break;
160
161 case nir_op_u2f32:
162 case nir_op_u2f16:
163 case nir_op_u2u32:
164 case nir_op_u2u16:
165 case nir_op_u2u8:
166 switch (src_bitsize) {
167 case 32:
168 src_type = TYPE_U32;
169 break;
170 case 16:
171 src_type = TYPE_U16;
172 break;
173 case 8:
174 src_type = TYPE_U8;
175 break;
176 default:
177 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
178 }
179 break;
180
181 case nir_op_b2f16:
182 case nir_op_b2f32:
183 case nir_op_b2i8:
184 case nir_op_b2i16:
185 case nir_op_b2i32:
186 src_type = TYPE_U32;
187 break;
188
189 default:
190 ir3_context_error(ctx, "invalid conversion op: %u", op);
191 }
192
193 switch (op) {
194 case nir_op_f2f32:
195 case nir_op_i2f32:
196 case nir_op_u2f32:
197 case nir_op_b2f32:
198 dst_type = TYPE_F32;
199 break;
200
201 case nir_op_f2f16_rtne:
202 case nir_op_f2f16_rtz:
203 case nir_op_f2f16:
204 case nir_op_i2f16:
205 case nir_op_u2f16:
206 case nir_op_b2f16:
207 dst_type = TYPE_F16;
208 break;
209
210 case nir_op_f2i32:
211 case nir_op_i2i32:
212 case nir_op_b2i32:
213 dst_type = TYPE_S32;
214 break;
215
216 case nir_op_f2i16:
217 case nir_op_i2i16:
218 case nir_op_b2i16:
219 dst_type = TYPE_S16;
220 break;
221
222 case nir_op_f2i8:
223 case nir_op_i2i8:
224 case nir_op_b2i8:
225 dst_type = TYPE_S8;
226 break;
227
228 case nir_op_f2u32:
229 case nir_op_u2u32:
230 dst_type = TYPE_U32;
231 break;
232
233 case nir_op_f2u16:
234 case nir_op_u2u16:
235 dst_type = TYPE_U16;
236 break;
237
238 case nir_op_f2u8:
239 case nir_op_u2u8:
240 dst_type = TYPE_U8;
241 break;
242
243 default:
244 ir3_context_error(ctx, "invalid conversion op: %u", op);
245 }
246
247 if (src_type == dst_type)
248 return src;
249
250 struct ir3_instruction *cov =
251 ir3_COV(ctx->block, src, src_type, dst_type);
252
253 if (op == nir_op_f2f16_rtne)
254 cov->regs[0]->flags |= IR3_REG_EVEN;
255
256 return cov;
257 }
258
259 static void
260 emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
261 {
262 const nir_op_info *info = &nir_op_infos[alu->op];
263 struct ir3_instruction **dst, *src[info->num_inputs];
264 unsigned bs[info->num_inputs]; /* bit size */
265 struct ir3_block *b = ctx->block;
266 unsigned dst_sz, wrmask;
267 type_t dst_type = nir_dest_bit_size(alu->dest.dest) == 16 ?
268 TYPE_U16 : TYPE_U32;
269
270 if (alu->dest.dest.is_ssa) {
271 dst_sz = alu->dest.dest.ssa.num_components;
272 wrmask = (1 << dst_sz) - 1;
273 } else {
274 dst_sz = alu->dest.dest.reg.reg->num_components;
275 wrmask = alu->dest.write_mask;
276 }
277
278 dst = ir3_get_dst(ctx, &alu->dest.dest, dst_sz);
279
280 /* Vectors are special in that they have non-scalarized writemasks,
281 * and just take the first swizzle channel for each argument in
282 * order into each writemask channel.
283 */
284 if ((alu->op == nir_op_vec2) ||
285 (alu->op == nir_op_vec3) ||
286 (alu->op == nir_op_vec4)) {
287
288 for (int i = 0; i < info->num_inputs; i++) {
289 nir_alu_src *asrc = &alu->src[i];
290
291 compile_assert(ctx, !asrc->abs);
292 compile_assert(ctx, !asrc->negate);
293
294 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[0]];
295 if (!src[i])
296 src[i] = create_immed_typed(ctx->block, 0, dst_type);
297 dst[i] = ir3_MOV(b, src[i], dst_type);
298 }
299
300 ir3_put_dst(ctx, &alu->dest.dest);
301 return;
302 }
303
304 /* We also get mov's with more than one component for mov's so
305 * handle those specially:
306 */
307 if (alu->op == nir_op_mov) {
308 nir_alu_src *asrc = &alu->src[0];
309 struct ir3_instruction *const *src0 = ir3_get_src(ctx, &asrc->src);
310
311 for (unsigned i = 0; i < dst_sz; i++) {
312 if (wrmask & (1 << i)) {
313 dst[i] = ir3_MOV(b, src0[asrc->swizzle[i]], dst_type);
314 } else {
315 dst[i] = NULL;
316 }
317 }
318
319 ir3_put_dst(ctx, &alu->dest.dest);
320 return;
321 }
322
323 /* General case: We can just grab the one used channel per src. */
324 for (int i = 0; i < info->num_inputs; i++) {
325 unsigned chan = ffs(alu->dest.write_mask) - 1;
326 nir_alu_src *asrc = &alu->src[i];
327
328 compile_assert(ctx, !asrc->abs);
329 compile_assert(ctx, !asrc->negate);
330
331 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
332 bs[i] = nir_src_bit_size(asrc->src);
333
334 compile_assert(ctx, src[i]);
335 }
336
337 switch (alu->op) {
338 case nir_op_f2f32:
339 case nir_op_f2f16_rtne:
340 case nir_op_f2f16_rtz:
341 case nir_op_f2f16:
342 case nir_op_f2i32:
343 case nir_op_f2i16:
344 case nir_op_f2i8:
345 case nir_op_f2u32:
346 case nir_op_f2u16:
347 case nir_op_f2u8:
348 case nir_op_i2f32:
349 case nir_op_i2f16:
350 case nir_op_i2i32:
351 case nir_op_i2i16:
352 case nir_op_i2i8:
353 case nir_op_u2f32:
354 case nir_op_u2f16:
355 case nir_op_u2u32:
356 case nir_op_u2u16:
357 case nir_op_u2u8:
358 case nir_op_b2f16:
359 case nir_op_b2f32:
360 case nir_op_b2i8:
361 case nir_op_b2i16:
362 case nir_op_b2i32:
363 dst[0] = create_cov(ctx, src[0], bs[0], alu->op);
364 break;
365
366 case nir_op_fquantize2f16:
367 dst[0] = create_cov(ctx,
368 create_cov(ctx, src[0], 32, nir_op_f2f16),
369 16, nir_op_f2f32);
370 break;
371 case nir_op_f2b1:
372 dst[0] = ir3_CMPS_F(b,
373 src[0], 0,
374 create_immed_typed(b, 0, bs[0] == 16 ? TYPE_F16 : TYPE_F32), 0);
375 dst[0]->cat2.condition = IR3_COND_NE;
376 break;
377
378 case nir_op_i2b1:
379 /* i2b1 will appear when translating from nir_load_ubo or
380 * nir_intrinsic_load_ssbo, where any non-zero value is true.
381 */
382 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
383 dst[0]->cat2.condition = IR3_COND_NE;
384 break;
385
386 case nir_op_b2b1:
387 /* b2b1 will appear when translating from
388 *
389 * - nir_intrinsic_load_shared of a 32-bit 0/~0 value.
390 * - nir_intrinsic_load_constant of a 32-bit 0/~0 value
391 *
392 * A negate can turn those into a 1 or 0 for us.
393 */
394 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
395 break;
396
397 case nir_op_b2b32:
398 /* b2b32 will appear when converting our 1-bit bools to a store_shared
399 * argument.
400 *
401 * A negate can turn those into a ~0 for us.
402 */
403 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
404 break;
405
406 case nir_op_fneg:
407 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
408 break;
409 case nir_op_fabs:
410 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
411 break;
412 case nir_op_fmax:
413 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
414 break;
415 case nir_op_fmin:
416 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
417 break;
418 case nir_op_fsat:
419 /* if there is just a single use of the src, and it supports
420 * (sat) bit, we can just fold the (sat) flag back to the
421 * src instruction and create a mov. This is easier for cp
422 * to eliminate.
423 *
424 * NOTE: a3xx definitely seen not working with flat bary.f. Same test
425 * uses ldlv on a4xx+, so not definitive. Seems rare enough to apply
426 * everywhere.
427 *
428 * TODO probably opc_cat==4 is ok too
429 */
430 if (alu->src[0].src.is_ssa &&
431 src[0]->opc != OPC_BARY_F &&
432 (list_length(&alu->src[0].src.ssa->uses) == 1) &&
433 ((opc_cat(src[0]->opc) == 2) || (opc_cat(src[0]->opc) == 3))) {
434 src[0]->flags |= IR3_INSTR_SAT;
435 dst[0] = ir3_MOV(b, src[0], dst_type);
436 } else {
437 /* otherwise generate a max.f that saturates.. blob does
438 * similar (generating a cat2 mov using max.f)
439 */
440 dst[0] = ir3_MAX_F(b, src[0], 0, src[0], 0);
441 dst[0]->flags |= IR3_INSTR_SAT;
442 }
443 break;
444 case nir_op_fmul:
445 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
446 break;
447 case nir_op_fadd:
448 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
449 break;
450 case nir_op_fsub:
451 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
452 break;
453 case nir_op_ffma:
454 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
455 break;
456 case nir_op_fddx:
457 case nir_op_fddx_coarse:
458 dst[0] = ir3_DSX(b, src[0], 0);
459 dst[0]->cat5.type = TYPE_F32;
460 break;
461 case nir_op_fddx_fine:
462 dst[0] = ir3_DSXPP_MACRO(b, src[0], 0);
463 dst[0]->cat5.type = TYPE_F32;
464 break;
465 case nir_op_fddy:
466 case nir_op_fddy_coarse:
467 dst[0] = ir3_DSY(b, src[0], 0);
468 dst[0]->cat5.type = TYPE_F32;
469 break;
470 break;
471 case nir_op_fddy_fine:
472 dst[0] = ir3_DSYPP_MACRO(b, src[0], 0);
473 dst[0]->cat5.type = TYPE_F32;
474 break;
475 case nir_op_flt:
476 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
477 dst[0]->cat2.condition = IR3_COND_LT;
478 break;
479 case nir_op_fge:
480 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
481 dst[0]->cat2.condition = IR3_COND_GE;
482 break;
483 case nir_op_feq:
484 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
485 dst[0]->cat2.condition = IR3_COND_EQ;
486 break;
487 case nir_op_fneu:
488 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
489 dst[0]->cat2.condition = IR3_COND_NE;
490 break;
491 case nir_op_fceil:
492 dst[0] = ir3_CEIL_F(b, src[0], 0);
493 break;
494 case nir_op_ffloor:
495 dst[0] = ir3_FLOOR_F(b, src[0], 0);
496 break;
497 case nir_op_ftrunc:
498 dst[0] = ir3_TRUNC_F(b, src[0], 0);
499 break;
500 case nir_op_fround_even:
501 dst[0] = ir3_RNDNE_F(b, src[0], 0);
502 break;
503 case nir_op_fsign:
504 dst[0] = ir3_SIGN_F(b, src[0], 0);
505 break;
506
507 case nir_op_fsin:
508 dst[0] = ir3_SIN(b, src[0], 0);
509 break;
510 case nir_op_fcos:
511 dst[0] = ir3_COS(b, src[0], 0);
512 break;
513 case nir_op_frsq:
514 dst[0] = ir3_RSQ(b, src[0], 0);
515 break;
516 case nir_op_frcp:
517 dst[0] = ir3_RCP(b, src[0], 0);
518 break;
519 case nir_op_flog2:
520 dst[0] = ir3_LOG2(b, src[0], 0);
521 break;
522 case nir_op_fexp2:
523 dst[0] = ir3_EXP2(b, src[0], 0);
524 break;
525 case nir_op_fsqrt:
526 dst[0] = ir3_SQRT(b, src[0], 0);
527 break;
528
529 case nir_op_iabs:
530 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
531 break;
532 case nir_op_iadd:
533 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
534 break;
535 case nir_op_iand:
536 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
537 break;
538 case nir_op_imax:
539 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
540 break;
541 case nir_op_umax:
542 dst[0] = ir3_MAX_U(b, src[0], 0, src[1], 0);
543 break;
544 case nir_op_imin:
545 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
546 break;
547 case nir_op_umin:
548 dst[0] = ir3_MIN_U(b, src[0], 0, src[1], 0);
549 break;
550 case nir_op_umul_low:
551 dst[0] = ir3_MULL_U(b, src[0], 0, src[1], 0);
552 break;
553 case nir_op_imadsh_mix16:
554 dst[0] = ir3_MADSH_M16(b, src[0], 0, src[1], 0, src[2], 0);
555 break;
556 case nir_op_imad24_ir3:
557 dst[0] = ir3_MAD_S24(b, src[0], 0, src[1], 0, src[2], 0);
558 break;
559 case nir_op_imul24:
560 dst[0] = ir3_MUL_S24(b, src[0], 0, src[1], 0);
561 break;
562 case nir_op_ineg:
563 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
564 break;
565 case nir_op_inot:
566 if (bs[0] == 1) {
567 dst[0] = ir3_SUB_U(b, create_immed(ctx->block, 1), 0, src[0], 0);
568 } else {
569 dst[0] = ir3_NOT_B(b, src[0], 0);
570 }
571 break;
572 case nir_op_ior:
573 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
574 break;
575 case nir_op_ishl:
576 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
577 break;
578 case nir_op_ishr:
579 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
580 break;
581 case nir_op_isub:
582 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
583 break;
584 case nir_op_ixor:
585 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
586 break;
587 case nir_op_ushr:
588 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
589 break;
590 case nir_op_ilt:
591 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
592 dst[0]->cat2.condition = IR3_COND_LT;
593 break;
594 case nir_op_ige:
595 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
596 dst[0]->cat2.condition = IR3_COND_GE;
597 break;
598 case nir_op_ieq:
599 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
600 dst[0]->cat2.condition = IR3_COND_EQ;
601 break;
602 case nir_op_ine:
603 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
604 dst[0]->cat2.condition = IR3_COND_NE;
605 break;
606 case nir_op_ult:
607 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
608 dst[0]->cat2.condition = IR3_COND_LT;
609 break;
610 case nir_op_uge:
611 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
612 dst[0]->cat2.condition = IR3_COND_GE;
613 break;
614
615 case nir_op_bcsel: {
616 struct ir3_instruction *cond = src[0];
617
618 /* If src[0] is a negation (likely as a result of an ir3_b2n(cond)),
619 * we can ignore that and use original cond, since the nonzero-ness of
620 * cond stays the same.
621 */
622 if (cond->opc == OPC_ABSNEG_S &&
623 cond->flags == 0 &&
624 (cond->regs[1]->flags & (IR3_REG_SNEG | IR3_REG_SABS)) == IR3_REG_SNEG) {
625 cond = cond->regs[1]->instr;
626 }
627
628 compile_assert(ctx, bs[1] == bs[2]);
629 /* The condition's size has to match the other two arguments' size, so
630 * convert down if necessary.
631 */
632 if (bs[1] == 16) {
633 struct hash_entry *prev_entry =
634 _mesa_hash_table_search(ctx->sel_cond_conversions, src[0]);
635 if (prev_entry) {
636 cond = prev_entry->data;
637 } else {
638 cond = ir3_COV(b, cond, TYPE_U32, TYPE_U16);
639 _mesa_hash_table_insert(ctx->sel_cond_conversions, src[0], cond);
640 }
641 }
642
643 if (bs[1] != 16)
644 dst[0] = ir3_SEL_B32(b, src[1], 0, cond, 0, src[2], 0);
645 else
646 dst[0] = ir3_SEL_B16(b, src[1], 0, cond, 0, src[2], 0);
647 break;
648 }
649 case nir_op_bit_count: {
650 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
651 // double check on earlier gen's. Once half-precision support is
652 // in place, this should probably move to a NIR lowering pass:
653 struct ir3_instruction *hi, *lo;
654
655 hi = ir3_COV(b, ir3_SHR_B(b, src[0], 0, create_immed(b, 16), 0),
656 TYPE_U32, TYPE_U16);
657 lo = ir3_COV(b, src[0], TYPE_U32, TYPE_U16);
658
659 hi = ir3_CBITS_B(b, hi, 0);
660 lo = ir3_CBITS_B(b, lo, 0);
661
662 // TODO maybe the builders should default to making dst half-precision
663 // if the src's were half precision, to make this less awkward.. otoh
664 // we should probably just do this lowering in NIR.
665 hi->regs[0]->flags |= IR3_REG_HALF;
666 lo->regs[0]->flags |= IR3_REG_HALF;
667
668 dst[0] = ir3_ADD_S(b, hi, 0, lo, 0);
669 dst[0]->regs[0]->flags |= IR3_REG_HALF;
670 dst[0] = ir3_COV(b, dst[0], TYPE_U16, TYPE_U32);
671 break;
672 }
673 case nir_op_ifind_msb: {
674 struct ir3_instruction *cmp;
675 dst[0] = ir3_CLZ_S(b, src[0], 0);
676 cmp = ir3_CMPS_S(b, dst[0], 0, create_immed(b, 0), 0);
677 cmp->cat2.condition = IR3_COND_GE;
678 dst[0] = ir3_SEL_B32(b,
679 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
680 cmp, 0, dst[0], 0);
681 break;
682 }
683 case nir_op_ufind_msb:
684 dst[0] = ir3_CLZ_B(b, src[0], 0);
685 dst[0] = ir3_SEL_B32(b,
686 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
687 src[0], 0, dst[0], 0);
688 break;
689 case nir_op_find_lsb:
690 dst[0] = ir3_BFREV_B(b, src[0], 0);
691 dst[0] = ir3_CLZ_B(b, dst[0], 0);
692 break;
693 case nir_op_bitfield_reverse:
694 dst[0] = ir3_BFREV_B(b, src[0], 0);
695 break;
696
697 default:
698 ir3_context_error(ctx, "Unhandled ALU op: %s\n",
699 nir_op_infos[alu->op].name);
700 break;
701 }
702
703 if (nir_alu_type_get_base_type(info->output_type) == nir_type_bool) {
704 assert(nir_dest_bit_size(alu->dest.dest) == 1 ||
705 alu->op == nir_op_b2b32);
706 assert(dst_sz == 1);
707 } else {
708 /* 1-bit values stored in 32-bit registers are only valid for certain
709 * ALU ops.
710 */
711 switch (alu->op) {
712 case nir_op_iand:
713 case nir_op_ior:
714 case nir_op_ixor:
715 case nir_op_inot:
716 case nir_op_bcsel:
717 break;
718 default:
719 compile_assert(ctx, nir_dest_bit_size(alu->dest.dest) != 1);
720 }
721 }
722
723 ir3_put_dst(ctx, &alu->dest.dest);
724 }
725
726 static void
727 emit_intrinsic_load_ubo_ldc(struct ir3_context *ctx, nir_intrinsic_instr *intr,
728 struct ir3_instruction **dst)
729 {
730 struct ir3_block *b = ctx->block;
731
732 unsigned ncomp = intr->num_components;
733 struct ir3_instruction *offset = ir3_get_src(ctx, &intr->src[1])[0];
734 struct ir3_instruction *idx = ir3_get_src(ctx, &intr->src[0])[0];
735 struct ir3_instruction *ldc = ir3_LDC(b, idx, 0, offset, 0);
736 ldc->regs[0]->wrmask = MASK(ncomp);
737 ldc->cat6.iim_val = ncomp;
738 ldc->cat6.d = nir_intrinsic_component(intr);
739 ldc->cat6.type = TYPE_U32;
740
741 ir3_handle_bindless_cat6(ldc, intr->src[0]);
742 if (ldc->flags & IR3_INSTR_B)
743 ctx->so->bindless_ubo = true;
744
745 ir3_split_dest(b, dst, ldc, 0, ncomp);
746 }
747
748
749 /* handles direct/indirect UBO reads: */
750 static void
751 emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
752 struct ir3_instruction **dst)
753 {
754 struct ir3_block *b = ctx->block;
755 struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
756 const struct ir3_const_state *const_state = ir3_const_state(ctx->so);
757 unsigned ubo = regid(const_state->offsets.ubo, 0);
758 const unsigned ptrsz = ir3_pointer_size(ctx->compiler);
759
760 int off = 0;
761
762 /* First src is ubo index, which could either be an immed or not: */
763 src0 = ir3_get_src(ctx, &intr->src[0])[0];
764 if (is_same_type_mov(src0) &&
765 (src0->regs[1]->flags & IR3_REG_IMMED)) {
766 base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz));
767 base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1);
768 } else {
769 base_lo = create_uniform_indirect(b, ubo, TYPE_U32, ir3_get_addr0(ctx, src0, ptrsz));
770 base_hi = create_uniform_indirect(b, ubo + 1, TYPE_U32, ir3_get_addr0(ctx, src0, ptrsz));
771
772 /* NOTE: since relative addressing is used, make sure constlen is
773 * at least big enough to cover all the UBO addresses, since the
774 * assembler won't know what the max address reg is.
775 */
776 ctx->so->constlen = MAX2(ctx->so->constlen,
777 const_state->offsets.ubo + (ctx->s->info.num_ubos * ptrsz));
778 }
779
780 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
781 addr = base_lo;
782
783 if (nir_src_is_const(intr->src[1])) {
784 off += nir_src_as_uint(intr->src[1]);
785 } else {
786 /* For load_ubo_indirect, second src is indirect offset: */
787 src1 = ir3_get_src(ctx, &intr->src[1])[0];
788
789 /* and add offset to addr: */
790 addr = ir3_ADD_S(b, addr, 0, src1, 0);
791 }
792
793 /* if offset is to large to encode in the ldg, split it out: */
794 if ((off + (intr->num_components * 4)) > 1024) {
795 /* split out the minimal amount to improve the odds that
796 * cp can fit the immediate in the add.s instruction:
797 */
798 unsigned off2 = off + (intr->num_components * 4) - 1024;
799 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
800 off -= off2;
801 }
802
803 if (ptrsz == 2) {
804 struct ir3_instruction *carry;
805
806 /* handle 32b rollover, ie:
807 * if (addr < base_lo)
808 * base_hi++
809 */
810 carry = ir3_CMPS_U(b, addr, 0, base_lo, 0);
811 carry->cat2.condition = IR3_COND_LT;
812 base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0);
813
814 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ addr, base_hi }, 2);
815 }
816
817 for (int i = 0; i < intr->num_components; i++) {
818 struct ir3_instruction *load =
819 ir3_LDG(b, addr, 0, create_immed(b, 1), 0, /* num components */
820 create_immed(b, off + i * 4), 0);
821 load->cat6.type = TYPE_U32;
822 dst[i] = load;
823 }
824 }
825
826 /* src[] = { block_index } */
827 static void
828 emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
829 struct ir3_instruction **dst)
830 {
831 if (ir3_bindless_resource(intr->src[0])) {
832 struct ir3_block *b = ctx->block;
833 struct ir3_instruction *ibo = ir3_ssbo_to_ibo(ctx, intr->src[0]);
834 struct ir3_instruction *resinfo = ir3_RESINFO(b, ibo, 0);
835 resinfo->cat6.iim_val = 1;
836 resinfo->cat6.d = 1;
837 resinfo->cat6.type = TYPE_U32;
838 resinfo->cat6.typed = false;
839 /* resinfo has no writemask and always writes out 3 components */
840 resinfo->regs[0]->wrmask = MASK(3);
841 ir3_handle_bindless_cat6(resinfo, intr->src[0]);
842 struct ir3_instruction *resinfo_dst;
843 ir3_split_dest(b, &resinfo_dst, resinfo, 0, 1);
844 /* Unfortunately resinfo returns the array length, i.e. in dwords,
845 * while NIR expects us to return the size in bytes.
846 *
847 * TODO: fix this in NIR.
848 */
849 *dst = ir3_SHL_B(b, resinfo_dst, 0, create_immed(b, 2), 0);
850 return;
851 }
852
853 /* SSBO size stored as a const starting at ssbo_sizes: */
854 const struct ir3_const_state *const_state = ir3_const_state(ctx->so);
855 unsigned blk_idx = nir_src_as_uint(intr->src[0]);
856 unsigned idx = regid(const_state->offsets.ssbo_sizes, 0) +
857 const_state->ssbo_size.off[blk_idx];
858
859 debug_assert(const_state->ssbo_size.mask & (1 << blk_idx));
860
861 dst[0] = create_uniform(ctx->block, idx);
862 }
863
864 /* src[] = { offset }. const_index[] = { base } */
865 static void
866 emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr,
867 struct ir3_instruction **dst)
868 {
869 struct ir3_block *b = ctx->block;
870 struct ir3_instruction *ldl, *offset;
871 unsigned base;
872
873 offset = ir3_get_src(ctx, &intr->src[0])[0];
874 base = nir_intrinsic_base(intr);
875
876 ldl = ir3_LDL(b, offset, 0,
877 create_immed(b, intr->num_components), 0,
878 create_immed(b, base), 0);
879
880 ldl->cat6.type = utype_dst(intr->dest);
881 ldl->regs[0]->wrmask = MASK(intr->num_components);
882
883 ldl->barrier_class = IR3_BARRIER_SHARED_R;
884 ldl->barrier_conflict = IR3_BARRIER_SHARED_W;
885
886 ir3_split_dest(b, dst, ldl, 0, intr->num_components);
887 }
888
889 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
890 static void
891 emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
892 {
893 struct ir3_block *b = ctx->block;
894 struct ir3_instruction *stl, *offset;
895 struct ir3_instruction * const *value;
896 unsigned base, wrmask, ncomp;
897
898 value = ir3_get_src(ctx, &intr->src[0]);
899 offset = ir3_get_src(ctx, &intr->src[1])[0];
900
901 base = nir_intrinsic_base(intr);
902 wrmask = nir_intrinsic_write_mask(intr);
903 ncomp = ffs(~wrmask) - 1;
904
905 assert(wrmask == BITFIELD_MASK(intr->num_components));
906
907 stl = ir3_STL(b, offset, 0,
908 ir3_create_collect(ctx, value, ncomp), 0,
909 create_immed(b, ncomp), 0);
910 stl->cat6.dst_offset = base;
911 stl->cat6.type = utype_src(intr->src[0]);
912 stl->barrier_class = IR3_BARRIER_SHARED_W;
913 stl->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
914
915 array_insert(b, b->keeps, stl);
916 }
917
918 /* src[] = { offset }. const_index[] = { base } */
919 static void
920 emit_intrinsic_load_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr,
921 struct ir3_instruction **dst)
922 {
923 struct ir3_block *b = ctx->block;
924 struct ir3_instruction *load, *offset;
925 unsigned base;
926
927 offset = ir3_get_src(ctx, &intr->src[0])[0];
928 base = nir_intrinsic_base(intr);
929
930 load = ir3_LDLW(b, offset, 0,
931 create_immed(b, intr->num_components), 0,
932 create_immed(b, base), 0);
933
934 /* for a650, use LDL for tess ctrl inputs: */
935 if (ctx->so->type == MESA_SHADER_TESS_CTRL && ctx->compiler->tess_use_shared)
936 load->opc = OPC_LDL;
937
938 load->cat6.type = utype_dst(intr->dest);
939 load->regs[0]->wrmask = MASK(intr->num_components);
940
941 load->barrier_class = IR3_BARRIER_SHARED_R;
942 load->barrier_conflict = IR3_BARRIER_SHARED_W;
943
944 ir3_split_dest(b, dst, load, 0, intr->num_components);
945 }
946
947 /* src[] = { value, offset }. const_index[] = { base } */
948 static void
949 emit_intrinsic_store_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr)
950 {
951 struct ir3_block *b = ctx->block;
952 struct ir3_instruction *store, *offset;
953 struct ir3_instruction * const *value;
954
955 value = ir3_get_src(ctx, &intr->src[0]);
956 offset = ir3_get_src(ctx, &intr->src[1])[0];
957
958 store = ir3_STLW(b, offset, 0,
959 ir3_create_collect(ctx, value, intr->num_components), 0,
960 create_immed(b, intr->num_components), 0);
961
962 /* for a650, use STL for vertex outputs used by tess ctrl shader: */
963 if (ctx->so->type == MESA_SHADER_VERTEX && ctx->so->key.tessellation &&
964 ctx->compiler->tess_use_shared)
965 store->opc = OPC_STL;
966
967 store->cat6.dst_offset = nir_intrinsic_base(intr);
968 store->cat6.type = utype_src(intr->src[0]);
969 store->barrier_class = IR3_BARRIER_SHARED_W;
970 store->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
971
972 array_insert(b, b->keeps, store);
973 }
974
975 /*
976 * CS shared variable atomic intrinsics
977 *
978 * All of the shared variable atomic memory operations read a value from
979 * memory, compute a new value using one of the operations below, write the
980 * new value to memory, and return the original value read.
981 *
982 * All operations take 2 sources except CompSwap that takes 3. These
983 * sources represent:
984 *
985 * 0: The offset into the shared variable storage region that the atomic
986 * operation will operate on.
987 * 1: The data parameter to the atomic function (i.e. the value to add
988 * in shared_atomic_add, etc).
989 * 2: For CompSwap only: the second data parameter.
990 */
991 static struct ir3_instruction *
992 emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
993 {
994 struct ir3_block *b = ctx->block;
995 struct ir3_instruction *atomic, *src0, *src1;
996 type_t type = TYPE_U32;
997
998 src0 = ir3_get_src(ctx, &intr->src[0])[0]; /* offset */
999 src1 = ir3_get_src(ctx, &intr->src[1])[0]; /* value */
1000
1001 switch (intr->intrinsic) {
1002 case nir_intrinsic_shared_atomic_add:
1003 atomic = ir3_ATOMIC_ADD(b, src0, 0, src1, 0);
1004 break;
1005 case nir_intrinsic_shared_atomic_imin:
1006 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
1007 type = TYPE_S32;
1008 break;
1009 case nir_intrinsic_shared_atomic_umin:
1010 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
1011 break;
1012 case nir_intrinsic_shared_atomic_imax:
1013 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
1014 type = TYPE_S32;
1015 break;
1016 case nir_intrinsic_shared_atomic_umax:
1017 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
1018 break;
1019 case nir_intrinsic_shared_atomic_and:
1020 atomic = ir3_ATOMIC_AND(b, src0, 0, src1, 0);
1021 break;
1022 case nir_intrinsic_shared_atomic_or:
1023 atomic = ir3_ATOMIC_OR(b, src0, 0, src1, 0);
1024 break;
1025 case nir_intrinsic_shared_atomic_xor:
1026 atomic = ir3_ATOMIC_XOR(b, src0, 0, src1, 0);
1027 break;
1028 case nir_intrinsic_shared_atomic_exchange:
1029 atomic = ir3_ATOMIC_XCHG(b, src0, 0, src1, 0);
1030 break;
1031 case nir_intrinsic_shared_atomic_comp_swap:
1032 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1033 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1034 ir3_get_src(ctx, &intr->src[2])[0],
1035 src1,
1036 }, 2);
1037 atomic = ir3_ATOMIC_CMPXCHG(b, src0, 0, src1, 0);
1038 break;
1039 default:
1040 unreachable("boo");
1041 }
1042
1043 atomic->cat6.iim_val = 1;
1044 atomic->cat6.d = 1;
1045 atomic->cat6.type = type;
1046 atomic->barrier_class = IR3_BARRIER_SHARED_W;
1047 atomic->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
1048
1049 /* even if nothing consume the result, we can't DCE the instruction: */
1050 array_insert(b, b->keeps, atomic);
1051
1052 return atomic;
1053 }
1054
1055 struct tex_src_info {
1056 /* For prefetch */
1057 unsigned tex_base, samp_base, tex_idx, samp_idx;
1058 /* For normal tex instructions */
1059 unsigned base, combined_idx, a1_val, flags;
1060 struct ir3_instruction *samp_tex;
1061 };
1062
1063 /* TODO handle actual indirect/dynamic case.. which is going to be weird
1064 * to handle with the image_mapping table..
1065 */
1066 static struct tex_src_info
1067 get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1068 {
1069 struct ir3_block *b = ctx->block;
1070 struct tex_src_info info = { 0 };
1071 nir_intrinsic_instr *bindless_tex = ir3_bindless_resource(intr->src[0]);
1072 ctx->so->bindless_tex = true;
1073
1074 if (bindless_tex) {
1075 /* Bindless case */
1076 info.flags |= IR3_INSTR_B;
1077
1078 /* Gather information required to determine which encoding to
1079 * choose as well as for prefetch.
1080 */
1081 info.tex_base = nir_intrinsic_desc_set(bindless_tex);
1082 bool tex_const = nir_src_is_const(bindless_tex->src[0]);
1083 if (tex_const)
1084 info.tex_idx = nir_src_as_uint(bindless_tex->src[0]);
1085 info.samp_idx = 0;
1086
1087 /* Choose encoding. */
1088 if (tex_const && info.tex_idx < 256) {
1089 if (info.tex_idx < 16) {
1090 /* Everything fits within the instruction */
1091 info.base = info.tex_base;
1092 info.combined_idx = info.samp_idx | (info.tex_idx << 4);
1093 } else {
1094 info.base = info.tex_base;
1095 info.a1_val = info.tex_idx << 3;
1096 info.combined_idx = 0;
1097 info.flags |= IR3_INSTR_A1EN;
1098 }
1099 info.samp_tex = NULL;
1100 } else {
1101 info.flags |= IR3_INSTR_S2EN;
1102 info.base = info.tex_base;
1103
1104 /* Note: the indirect source is now a vec2 instead of hvec2 */
1105 struct ir3_instruction *texture, *sampler;
1106
1107 texture = ir3_get_src(ctx, &intr->src[0])[0];
1108 sampler = create_immed(b, 0);
1109 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1110 texture,
1111 sampler,
1112 }, 2);
1113 }
1114 } else {
1115 info.flags |= IR3_INSTR_S2EN;
1116 unsigned slot = nir_src_as_uint(intr->src[0]);
1117 unsigned tex_idx = ir3_image_to_tex(&ctx->so->image_mapping, slot);
1118 struct ir3_instruction *texture, *sampler;
1119
1120 texture = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1121 sampler = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1122
1123 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1124 sampler,
1125 texture,
1126 }, 2);
1127 }
1128
1129 return info;
1130 }
1131
1132 static struct ir3_instruction *
1133 emit_sam(struct ir3_context *ctx, opc_t opc, struct tex_src_info info,
1134 type_t type, unsigned wrmask, struct ir3_instruction *src0,
1135 struct ir3_instruction *src1)
1136 {
1137 struct ir3_instruction *sam, *addr;
1138 if (info.flags & IR3_INSTR_A1EN) {
1139 addr = ir3_get_addr1(ctx, info.a1_val);
1140 }
1141 sam = ir3_SAM(ctx->block, opc, type, 0b1111, info.flags,
1142 info.samp_tex, src0, src1);
1143 if (info.flags & IR3_INSTR_A1EN) {
1144 ir3_instr_set_address(sam, addr);
1145 }
1146 if (info.flags & IR3_INSTR_B) {
1147 sam->cat5.tex_base = info.base;
1148 sam->cat5.samp = info.combined_idx;
1149 }
1150 return sam;
1151 }
1152
1153 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1154 static void
1155 emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1156 struct ir3_instruction **dst)
1157 {
1158 struct ir3_block *b = ctx->block;
1159 struct tex_src_info info = get_image_samp_tex_src(ctx, intr);
1160 struct ir3_instruction *sam;
1161 struct ir3_instruction * const *src0 = ir3_get_src(ctx, &intr->src[1]);
1162 struct ir3_instruction *coords[4];
1163 unsigned flags, ncoords = ir3_get_image_coords(intr, &flags);
1164 type_t type = ir3_get_type_for_image_intrinsic(intr);
1165
1166 /* hmm, this seems a bit odd, but it is what blob does and (at least
1167 * a5xx) just faults on bogus addresses otherwise:
1168 */
1169 if (flags & IR3_INSTR_3D) {
1170 flags &= ~IR3_INSTR_3D;
1171 flags |= IR3_INSTR_A;
1172 }
1173 info.flags |= flags;
1174
1175 for (unsigned i = 0; i < ncoords; i++)
1176 coords[i] = src0[i];
1177
1178 if (ncoords == 1)
1179 coords[ncoords++] = create_immed(b, 0);
1180
1181 sam = emit_sam(ctx, OPC_ISAM, info, type, 0b1111,
1182 ir3_create_collect(ctx, coords, ncoords), NULL);
1183
1184 sam->barrier_class = IR3_BARRIER_IMAGE_R;
1185 sam->barrier_conflict = IR3_BARRIER_IMAGE_W;
1186
1187 ir3_split_dest(b, dst, sam, 0, 4);
1188 }
1189
1190 /* A4xx version of image_size, see ir3_a6xx.c for newer resinfo version. */
1191 void
1192 emit_intrinsic_image_size_tex(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1193 struct ir3_instruction **dst)
1194 {
1195 struct ir3_block *b = ctx->block;
1196 struct tex_src_info info = get_image_samp_tex_src(ctx, intr);
1197 struct ir3_instruction *sam, *lod;
1198 unsigned flags, ncoords = ir3_get_image_coords(intr, &flags);
1199 type_t dst_type = nir_dest_bit_size(intr->dest) == 16 ?
1200 TYPE_U16 : TYPE_U32;
1201
1202 info.flags |= flags;
1203 assert(nir_src_as_uint(intr->src[1]) == 0);
1204 lod = create_immed(b, 0);
1205 sam = emit_sam(ctx, OPC_GETSIZE, info, dst_type, 0b1111, lod, NULL);
1206
1207 /* Array size actually ends up in .w rather than .z. This doesn't
1208 * matter for miplevel 0, but for higher mips the value in z is
1209 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1210 * returned, which means that we have to add 1 to it for arrays for
1211 * a3xx.
1212 *
1213 * Note use a temporary dst and then copy, since the size of the dst
1214 * array that is passed in is based on nir's understanding of the
1215 * result size, not the hardware's
1216 */
1217 struct ir3_instruction *tmp[4];
1218
1219 ir3_split_dest(b, tmp, sam, 0, 4);
1220
1221 /* get_size instruction returns size in bytes instead of texels
1222 * for imageBuffer, so we need to divide it by the pixel size
1223 * of the image format.
1224 *
1225 * TODO: This is at least true on a5xx. Check other gens.
1226 */
1227 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF) {
1228 /* Since all the possible values the divisor can take are
1229 * power-of-two (4, 8, or 16), the division is implemented
1230 * as a shift-right.
1231 * During shader setup, the log2 of the image format's
1232 * bytes-per-pixel should have been emitted in 2nd slot of
1233 * image_dims. See ir3_shader::emit_image_dims().
1234 */
1235 const struct ir3_const_state *const_state =
1236 ir3_const_state(ctx->so);
1237 unsigned cb = regid(const_state->offsets.image_dims, 0) +
1238 const_state->image_dims.off[nir_src_as_uint(intr->src[0])];
1239 struct ir3_instruction *aux = create_uniform(b, cb + 1);
1240
1241 tmp[0] = ir3_SHR_B(b, tmp[0], 0, aux, 0);
1242 }
1243
1244 for (unsigned i = 0; i < ncoords; i++)
1245 dst[i] = tmp[i];
1246
1247 if (flags & IR3_INSTR_A) {
1248 if (ctx->compiler->levels_add_one) {
1249 dst[ncoords-1] = ir3_ADD_U(b, tmp[3], 0, create_immed(b, 1), 0);
1250 } else {
1251 dst[ncoords-1] = ir3_MOV(b, tmp[3], TYPE_U32);
1252 }
1253 }
1254 }
1255
1256 static void
1257 emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1258 {
1259 struct ir3_block *b = ctx->block;
1260 struct ir3_instruction *barrier;
1261
1262 switch (intr->intrinsic) {
1263 case nir_intrinsic_control_barrier:
1264 barrier = ir3_BAR(b);
1265 barrier->cat7.g = true;
1266 barrier->cat7.l = true;
1267 barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY;
1268 barrier->barrier_class = IR3_BARRIER_EVERYTHING;
1269 break;
1270 case nir_intrinsic_memory_barrier:
1271 barrier = ir3_FENCE(b);
1272 barrier->cat7.g = true;
1273 barrier->cat7.r = true;
1274 barrier->cat7.w = true;
1275 barrier->cat7.l = true;
1276 barrier->barrier_class = IR3_BARRIER_IMAGE_W |
1277 IR3_BARRIER_BUFFER_W;
1278 barrier->barrier_conflict =
1279 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1280 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1281 break;
1282 case nir_intrinsic_memory_barrier_buffer:
1283 barrier = ir3_FENCE(b);
1284 barrier->cat7.g = true;
1285 barrier->cat7.r = true;
1286 barrier->cat7.w = true;
1287 barrier->barrier_class = IR3_BARRIER_BUFFER_W;
1288 barrier->barrier_conflict = IR3_BARRIER_BUFFER_R |
1289 IR3_BARRIER_BUFFER_W;
1290 break;
1291 case nir_intrinsic_memory_barrier_image:
1292 // TODO double check if this should have .g set
1293 barrier = ir3_FENCE(b);
1294 barrier->cat7.g = true;
1295 barrier->cat7.r = true;
1296 barrier->cat7.w = true;
1297 barrier->barrier_class = IR3_BARRIER_IMAGE_W;
1298 barrier->barrier_conflict = IR3_BARRIER_IMAGE_R |
1299 IR3_BARRIER_IMAGE_W;
1300 break;
1301 case nir_intrinsic_memory_barrier_shared:
1302 barrier = ir3_FENCE(b);
1303 barrier->cat7.g = true;
1304 barrier->cat7.l = true;
1305 barrier->cat7.r = true;
1306 barrier->cat7.w = true;
1307 barrier->barrier_class = IR3_BARRIER_SHARED_W;
1308 barrier->barrier_conflict = IR3_BARRIER_SHARED_R |
1309 IR3_BARRIER_SHARED_W;
1310 break;
1311 case nir_intrinsic_group_memory_barrier:
1312 barrier = ir3_FENCE(b);
1313 barrier->cat7.g = true;
1314 barrier->cat7.l = true;
1315 barrier->cat7.r = true;
1316 barrier->cat7.w = true;
1317 barrier->barrier_class = IR3_BARRIER_SHARED_W |
1318 IR3_BARRIER_IMAGE_W |
1319 IR3_BARRIER_BUFFER_W;
1320 barrier->barrier_conflict =
1321 IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W |
1322 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1323 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1324 break;
1325 default:
1326 unreachable("boo");
1327 }
1328
1329 /* make sure barrier doesn't get DCE'd */
1330 array_insert(b, b->keeps, barrier);
1331 }
1332
1333 static void add_sysval_input_compmask(struct ir3_context *ctx,
1334 gl_system_value slot, unsigned compmask,
1335 struct ir3_instruction *instr)
1336 {
1337 struct ir3_shader_variant *so = ctx->so;
1338 unsigned n = so->inputs_count++;
1339
1340 assert(instr->opc == OPC_META_INPUT);
1341 instr->input.inidx = n;
1342 instr->input.sysval = slot;
1343
1344 so->inputs[n].sysval = true;
1345 so->inputs[n].slot = slot;
1346 so->inputs[n].compmask = compmask;
1347 so->total_in++;
1348 }
1349
1350 static struct ir3_instruction *
1351 create_sysval_input(struct ir3_context *ctx, gl_system_value slot,
1352 unsigned compmask)
1353 {
1354 assert(compmask);
1355 struct ir3_instruction *sysval = create_input(ctx, compmask);
1356 add_sysval_input_compmask(ctx, slot, compmask, sysval);
1357 return sysval;
1358 }
1359
1360 static struct ir3_instruction *
1361 get_barycentric(struct ir3_context *ctx, enum ir3_bary bary)
1362 {
1363 static const gl_system_value sysval_base = SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL;
1364
1365 STATIC_ASSERT(sysval_base + IJ_PERSP_PIXEL == SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL);
1366 STATIC_ASSERT(sysval_base + IJ_PERSP_SAMPLE == SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE);
1367 STATIC_ASSERT(sysval_base + IJ_PERSP_CENTROID == SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID);
1368 STATIC_ASSERT(sysval_base + IJ_PERSP_SIZE == SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE);
1369 STATIC_ASSERT(sysval_base + IJ_LINEAR_PIXEL == SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL);
1370 STATIC_ASSERT(sysval_base + IJ_LINEAR_CENTROID == SYSTEM_VALUE_BARYCENTRIC_LINEAR_CENTROID);
1371 STATIC_ASSERT(sysval_base + IJ_LINEAR_SAMPLE == SYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLE);
1372
1373 if (!ctx->ij[bary]) {
1374 struct ir3_instruction *xy[2];
1375 struct ir3_instruction *ij;
1376
1377 ij = create_sysval_input(ctx, sysval_base + bary, 0x3);
1378 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1379
1380 ctx->ij[bary] = ir3_create_collect(ctx, xy, 2);
1381 }
1382
1383 return ctx->ij[bary];
1384 }
1385
1386 /* TODO: make this a common NIR helper?
1387 * there is a nir_system_value_from_intrinsic but it takes nir_intrinsic_op so it
1388 * can't be extended to work with this
1389 */
1390 static gl_system_value
1391 nir_intrinsic_barycentric_sysval(nir_intrinsic_instr *intr)
1392 {
1393 enum glsl_interp_mode interp_mode = nir_intrinsic_interp_mode(intr);
1394 gl_system_value sysval;
1395
1396 switch (intr->intrinsic) {
1397 case nir_intrinsic_load_barycentric_pixel:
1398 if (interp_mode == INTERP_MODE_NOPERSPECTIVE)
1399 sysval = SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL;
1400 else
1401 sysval = SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL;
1402 break;
1403 case nir_intrinsic_load_barycentric_centroid:
1404 if (interp_mode == INTERP_MODE_NOPERSPECTIVE)
1405 sysval = SYSTEM_VALUE_BARYCENTRIC_LINEAR_CENTROID;
1406 else
1407 sysval = SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID;
1408 break;
1409 case nir_intrinsic_load_barycentric_sample:
1410 if (interp_mode == INTERP_MODE_NOPERSPECTIVE)
1411 sysval = SYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLE;
1412 else
1413 sysval = SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE;
1414 break;
1415 default:
1416 unreachable("invalid barycentric intrinsic");
1417 }
1418
1419 return sysval;
1420 }
1421
1422 static void
1423 emit_intrinsic_barycentric(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1424 struct ir3_instruction **dst)
1425 {
1426 gl_system_value sysval = nir_intrinsic_barycentric_sysval(intr);
1427
1428 if (!ctx->so->key.msaa) {
1429 if (sysval == SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE)
1430 sysval = SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL;
1431 if (sysval == SYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLE)
1432 sysval = SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL;
1433 }
1434
1435 enum ir3_bary bary = sysval - SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL;
1436
1437 struct ir3_instruction *ij = get_barycentric(ctx, bary);
1438 ir3_split_dest(ctx->block, dst, ij, 0, 2);
1439 }
1440
1441 static struct ir3_instruction *
1442 get_frag_coord(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1443 {
1444 if (!ctx->frag_coord) {
1445 struct ir3_block *b = ctx->in_block;
1446 struct ir3_instruction *xyzw[4];
1447 struct ir3_instruction *hw_frag_coord;
1448
1449 hw_frag_coord = create_sysval_input(ctx, SYSTEM_VALUE_FRAG_COORD, 0xf);
1450 ir3_split_dest(b, xyzw, hw_frag_coord, 0, 4);
1451
1452 /* for frag_coord.xy, we get unsigned values.. we need
1453 * to subtract (integer) 8 and divide by 16 (right-
1454 * shift by 4) then convert to float:
1455 *
1456 * sub.s tmp, src, 8
1457 * shr.b tmp, tmp, 4
1458 * mov.u32f32 dst, tmp
1459 *
1460 */
1461 for (int i = 0; i < 2; i++) {
1462 xyzw[i] = ir3_COV(b, xyzw[i], TYPE_U32, TYPE_F32);
1463 xyzw[i] = ir3_MUL_F(b, xyzw[i], 0, create_immed(b, fui(1.0 / 16.0)), 0);
1464 }
1465
1466 ctx->frag_coord = ir3_create_collect(ctx, xyzw, 4);
1467 }
1468
1469 ctx->so->fragcoord_compmask |=
1470 nir_ssa_def_components_read(&intr->dest.ssa);
1471
1472 return ctx->frag_coord;
1473 }
1474
1475 static void setup_input(struct ir3_context *ctx, nir_intrinsic_instr *intr);
1476 static void setup_output(struct ir3_context *ctx, nir_intrinsic_instr *intr);
1477
1478 static void
1479 emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1480 {
1481 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1482 struct ir3_instruction **dst;
1483 struct ir3_instruction * const *src;
1484 struct ir3_block *b = ctx->block;
1485 unsigned dest_components = nir_intrinsic_dest_components(intr);
1486 int idx;
1487
1488 if (info->has_dest) {
1489 dst = ir3_get_dst(ctx, &intr->dest, dest_components);
1490 } else {
1491 dst = NULL;
1492 }
1493
1494 const struct ir3_const_state *const_state = ir3_const_state(ctx->so);
1495 const unsigned primitive_param = const_state->offsets.primitive_param * 4;
1496 const unsigned primitive_map = const_state->offsets.primitive_map * 4;
1497
1498 switch (intr->intrinsic) {
1499 case nir_intrinsic_load_uniform:
1500 idx = nir_intrinsic_base(intr);
1501 if (nir_src_is_const(intr->src[0])) {
1502 idx += nir_src_as_uint(intr->src[0]);
1503 for (int i = 0; i < dest_components; i++) {
1504 dst[i] = create_uniform_typed(b, idx + i,
1505 nir_dest_bit_size(intr->dest) == 16 ? TYPE_F16 : TYPE_F32);
1506 }
1507 } else {
1508 src = ir3_get_src(ctx, &intr->src[0]);
1509 for (int i = 0; i < dest_components; i++) {
1510 dst[i] = create_uniform_indirect(b, idx + i,
1511 nir_dest_bit_size(intr->dest) == 16 ? TYPE_F16 : TYPE_F32,
1512 ir3_get_addr0(ctx, src[0], 1));
1513 }
1514 /* NOTE: if relative addressing is used, we set
1515 * constlen in the compiler (to worst-case value)
1516 * since we don't know in the assembler what the max
1517 * addr reg value can be:
1518 */
1519 ctx->so->constlen = MAX2(ctx->so->constlen,
1520 const_state->ubo_state.size / 16);
1521 }
1522 break;
1523
1524 case nir_intrinsic_load_vs_primitive_stride_ir3:
1525 dst[0] = create_uniform(b, primitive_param + 0);
1526 break;
1527 case nir_intrinsic_load_vs_vertex_stride_ir3:
1528 dst[0] = create_uniform(b, primitive_param + 1);
1529 break;
1530 case nir_intrinsic_load_hs_patch_stride_ir3:
1531 dst[0] = create_uniform(b, primitive_param + 2);
1532 break;
1533 case nir_intrinsic_load_patch_vertices_in:
1534 dst[0] = create_uniform(b, primitive_param + 3);
1535 break;
1536 case nir_intrinsic_load_tess_param_base_ir3:
1537 dst[0] = create_uniform(b, primitive_param + 4);
1538 dst[1] = create_uniform(b, primitive_param + 5);
1539 break;
1540 case nir_intrinsic_load_tess_factor_base_ir3:
1541 dst[0] = create_uniform(b, primitive_param + 6);
1542 dst[1] = create_uniform(b, primitive_param + 7);
1543 break;
1544
1545 case nir_intrinsic_load_primitive_location_ir3:
1546 idx = nir_intrinsic_driver_location(intr);
1547 dst[0] = create_uniform(b, primitive_map + idx);
1548 break;
1549
1550 case nir_intrinsic_load_gs_header_ir3:
1551 dst[0] = ctx->gs_header;
1552 break;
1553 case nir_intrinsic_load_tcs_header_ir3:
1554 dst[0] = ctx->tcs_header;
1555 break;
1556
1557 case nir_intrinsic_load_primitive_id:
1558 dst[0] = ctx->primitive_id;
1559 break;
1560
1561 case nir_intrinsic_load_tess_coord:
1562 if (!ctx->tess_coord) {
1563 ctx->tess_coord =
1564 create_sysval_input(ctx, SYSTEM_VALUE_TESS_COORD, 0x3);
1565 }
1566 ir3_split_dest(b, dst, ctx->tess_coord, 0, 2);
1567
1568 /* Unused, but ir3_put_dst() below wants to free something */
1569 dst[2] = create_immed(b, 0);
1570 break;
1571
1572 case nir_intrinsic_end_patch_ir3:
1573 assert(ctx->so->type == MESA_SHADER_TESS_CTRL);
1574 struct ir3_instruction *end = ir3_PREDE(b);
1575 array_insert(b, b->keeps, end);
1576
1577 end->barrier_class = IR3_BARRIER_EVERYTHING;
1578 end->barrier_conflict = IR3_BARRIER_EVERYTHING;
1579 break;
1580
1581 case nir_intrinsic_store_global_ir3: {
1582 struct ir3_instruction *value, *addr, *offset;
1583 unsigned ncomp = nir_intrinsic_src_components(intr, 0);
1584
1585 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1586 ir3_get_src(ctx, &intr->src[1])[0],
1587 ir3_get_src(ctx, &intr->src[1])[1]
1588 }, 2);
1589
1590 offset = ir3_get_src(ctx, &intr->src[2])[0];
1591
1592 value = ir3_create_collect(ctx, ir3_get_src(ctx, &intr->src[0]), ncomp);
1593
1594 struct ir3_instruction *stg =
1595 ir3_STG_G(ctx->block, addr, 0, value, 0,
1596 create_immed(ctx->block, ncomp), 0, offset, 0);
1597 stg->cat6.type = TYPE_U32;
1598 stg->cat6.iim_val = 1;
1599
1600 array_insert(b, b->keeps, stg);
1601
1602 stg->barrier_class = IR3_BARRIER_BUFFER_W;
1603 stg->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1604 break;
1605 }
1606
1607 case nir_intrinsic_load_global_ir3: {
1608 struct ir3_instruction *addr, *offset;
1609
1610 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1611 ir3_get_src(ctx, &intr->src[0])[0],
1612 ir3_get_src(ctx, &intr->src[0])[1]
1613 }, 2);
1614
1615 offset = ir3_get_src(ctx, &intr->src[1])[0];
1616
1617 struct ir3_instruction *load =
1618 ir3_LDG(b, addr, 0, create_immed(ctx->block, dest_components),
1619 0, offset, 0);
1620 load->cat6.type = TYPE_U32;
1621 load->regs[0]->wrmask = MASK(dest_components);
1622
1623 load->barrier_class = IR3_BARRIER_BUFFER_R;
1624 load->barrier_conflict = IR3_BARRIER_BUFFER_W;
1625
1626 ir3_split_dest(b, dst, load, 0, dest_components);
1627 break;
1628 }
1629
1630 case nir_intrinsic_load_ubo:
1631 emit_intrinsic_load_ubo(ctx, intr, dst);
1632 break;
1633 case nir_intrinsic_load_ubo_vec4:
1634 emit_intrinsic_load_ubo_ldc(ctx, intr, dst);
1635 break;
1636 case nir_intrinsic_load_frag_coord:
1637 ir3_split_dest(b, dst, get_frag_coord(ctx, intr), 0, 4);
1638 break;
1639 case nir_intrinsic_load_sample_pos_from_id: {
1640 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
1641 * but that doesn't seem necessary.
1642 */
1643 struct ir3_instruction *offset =
1644 ir3_RGETPOS(b, ir3_get_src(ctx, &intr->src[0])[0], 0);
1645 offset->regs[0]->wrmask = 0x3;
1646 offset->cat5.type = TYPE_F32;
1647
1648 ir3_split_dest(b, dst, offset, 0, 2);
1649
1650 break;
1651 }
1652 case nir_intrinsic_load_size_ir3:
1653 if (!ctx->ij[IJ_PERSP_SIZE]) {
1654 ctx->ij[IJ_PERSP_SIZE] =
1655 create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE, 0x1);
1656 }
1657 dst[0] = ctx->ij[IJ_PERSP_SIZE];
1658 break;
1659 case nir_intrinsic_load_barycentric_centroid:
1660 case nir_intrinsic_load_barycentric_sample:
1661 case nir_intrinsic_load_barycentric_pixel:
1662 emit_intrinsic_barycentric(ctx, intr, dst);
1663 break;
1664 case nir_intrinsic_load_interpolated_input:
1665 case nir_intrinsic_load_input:
1666 setup_input(ctx, intr);
1667 break;
1668 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1669 * pass and replaced by an ir3-specifc version that adds the
1670 * dword-offset in the last source.
1671 */
1672 case nir_intrinsic_load_ssbo_ir3:
1673 ctx->funcs->emit_intrinsic_load_ssbo(ctx, intr, dst);
1674 break;
1675 case nir_intrinsic_store_ssbo_ir3:
1676 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1677 !ctx->s->info.fs.early_fragment_tests)
1678 ctx->so->no_earlyz = true;
1679 ctx->funcs->emit_intrinsic_store_ssbo(ctx, intr);
1680 break;
1681 case nir_intrinsic_get_buffer_size:
1682 emit_intrinsic_ssbo_size(ctx, intr, dst);
1683 break;
1684 case nir_intrinsic_ssbo_atomic_add_ir3:
1685 case nir_intrinsic_ssbo_atomic_imin_ir3:
1686 case nir_intrinsic_ssbo_atomic_umin_ir3:
1687 case nir_intrinsic_ssbo_atomic_imax_ir3:
1688 case nir_intrinsic_ssbo_atomic_umax_ir3:
1689 case nir_intrinsic_ssbo_atomic_and_ir3:
1690 case nir_intrinsic_ssbo_atomic_or_ir3:
1691 case nir_intrinsic_ssbo_atomic_xor_ir3:
1692 case nir_intrinsic_ssbo_atomic_exchange_ir3:
1693 case nir_intrinsic_ssbo_atomic_comp_swap_ir3:
1694 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1695 !ctx->s->info.fs.early_fragment_tests)
1696 ctx->so->no_earlyz = true;
1697 dst[0] = ctx->funcs->emit_intrinsic_atomic_ssbo(ctx, intr);
1698 break;
1699 case nir_intrinsic_load_shared:
1700 emit_intrinsic_load_shared(ctx, intr, dst);
1701 break;
1702 case nir_intrinsic_store_shared:
1703 emit_intrinsic_store_shared(ctx, intr);
1704 break;
1705 case nir_intrinsic_shared_atomic_add:
1706 case nir_intrinsic_shared_atomic_imin:
1707 case nir_intrinsic_shared_atomic_umin:
1708 case nir_intrinsic_shared_atomic_imax:
1709 case nir_intrinsic_shared_atomic_umax:
1710 case nir_intrinsic_shared_atomic_and:
1711 case nir_intrinsic_shared_atomic_or:
1712 case nir_intrinsic_shared_atomic_xor:
1713 case nir_intrinsic_shared_atomic_exchange:
1714 case nir_intrinsic_shared_atomic_comp_swap:
1715 dst[0] = emit_intrinsic_atomic_shared(ctx, intr);
1716 break;
1717 case nir_intrinsic_image_load:
1718 emit_intrinsic_load_image(ctx, intr, dst);
1719 break;
1720 case nir_intrinsic_bindless_image_load:
1721 /* Bindless uses the IBO state, which doesn't have swizzle filled out,
1722 * so using isam doesn't work.
1723 *
1724 * TODO: can we use isam if we fill out more fields?
1725 */
1726 ctx->funcs->emit_intrinsic_load_image(ctx, intr, dst);
1727 break;
1728 case nir_intrinsic_image_store:
1729 case nir_intrinsic_bindless_image_store:
1730 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1731 !ctx->s->info.fs.early_fragment_tests)
1732 ctx->so->no_earlyz = true;
1733 ctx->funcs->emit_intrinsic_store_image(ctx, intr);
1734 break;
1735 case nir_intrinsic_image_size:
1736 case nir_intrinsic_bindless_image_size:
1737 ctx->funcs->emit_intrinsic_image_size(ctx, intr, dst);
1738 break;
1739 case nir_intrinsic_image_atomic_add:
1740 case nir_intrinsic_bindless_image_atomic_add:
1741 case nir_intrinsic_image_atomic_imin:
1742 case nir_intrinsic_bindless_image_atomic_imin:
1743 case nir_intrinsic_image_atomic_umin:
1744 case nir_intrinsic_bindless_image_atomic_umin:
1745 case nir_intrinsic_image_atomic_imax:
1746 case nir_intrinsic_bindless_image_atomic_imax:
1747 case nir_intrinsic_image_atomic_umax:
1748 case nir_intrinsic_bindless_image_atomic_umax:
1749 case nir_intrinsic_image_atomic_and:
1750 case nir_intrinsic_bindless_image_atomic_and:
1751 case nir_intrinsic_image_atomic_or:
1752 case nir_intrinsic_bindless_image_atomic_or:
1753 case nir_intrinsic_image_atomic_xor:
1754 case nir_intrinsic_bindless_image_atomic_xor:
1755 case nir_intrinsic_image_atomic_exchange:
1756 case nir_intrinsic_bindless_image_atomic_exchange:
1757 case nir_intrinsic_image_atomic_comp_swap:
1758 case nir_intrinsic_bindless_image_atomic_comp_swap:
1759 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1760 !ctx->s->info.fs.early_fragment_tests)
1761 ctx->so->no_earlyz = true;
1762 dst[0] = ctx->funcs->emit_intrinsic_atomic_image(ctx, intr);
1763 break;
1764 case nir_intrinsic_control_barrier:
1765 case nir_intrinsic_memory_barrier:
1766 case nir_intrinsic_group_memory_barrier:
1767 case nir_intrinsic_memory_barrier_buffer:
1768 case nir_intrinsic_memory_barrier_image:
1769 case nir_intrinsic_memory_barrier_shared:
1770 emit_intrinsic_barrier(ctx, intr);
1771 /* note that blk ptr no longer valid, make that obvious: */
1772 b = NULL;
1773 break;
1774 case nir_intrinsic_store_output:
1775 setup_output(ctx, intr);
1776 break;
1777 case nir_intrinsic_load_base_vertex:
1778 case nir_intrinsic_load_first_vertex:
1779 if (!ctx->basevertex) {
1780 ctx->basevertex = create_driver_param(ctx, IR3_DP_VTXID_BASE);
1781 }
1782 dst[0] = ctx->basevertex;
1783 break;
1784 case nir_intrinsic_load_draw_id:
1785 if (!ctx->draw_id) {
1786 ctx->draw_id = create_driver_param(ctx, IR3_DP_DRAWID);
1787 }
1788 dst[0] = ctx->draw_id;
1789 break;
1790 case nir_intrinsic_load_base_instance:
1791 if (!ctx->base_instance) {
1792 ctx->base_instance = create_driver_param(ctx, IR3_DP_INSTID_BASE);
1793 }
1794 dst[0] = ctx->base_instance;
1795 break;
1796 case nir_intrinsic_load_view_index:
1797 if (!ctx->view_index) {
1798 ctx->view_index = create_sysval_input(ctx, SYSTEM_VALUE_VIEW_INDEX, 0x1);
1799 }
1800 dst[0] = ctx->view_index;
1801 break;
1802 case nir_intrinsic_load_vertex_id_zero_base:
1803 case nir_intrinsic_load_vertex_id:
1804 if (!ctx->vertex_id) {
1805 gl_system_value sv = (intr->intrinsic == nir_intrinsic_load_vertex_id) ?
1806 SYSTEM_VALUE_VERTEX_ID : SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1807 ctx->vertex_id = create_sysval_input(ctx, sv, 0x1);
1808 }
1809 dst[0] = ctx->vertex_id;
1810 break;
1811 case nir_intrinsic_load_instance_id:
1812 if (!ctx->instance_id) {
1813 ctx->instance_id = create_sysval_input(ctx, SYSTEM_VALUE_INSTANCE_ID, 0x1);
1814 }
1815 dst[0] = ctx->instance_id;
1816 break;
1817 case nir_intrinsic_load_sample_id:
1818 ctx->so->per_samp = true;
1819 /* fall-thru */
1820 case nir_intrinsic_load_sample_id_no_per_sample:
1821 if (!ctx->samp_id) {
1822 ctx->samp_id = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_ID, 0x1);
1823 ctx->samp_id->regs[0]->flags |= IR3_REG_HALF;
1824 }
1825 dst[0] = ir3_COV(b, ctx->samp_id, TYPE_U16, TYPE_U32);
1826 break;
1827 case nir_intrinsic_load_sample_mask_in:
1828 if (!ctx->samp_mask_in) {
1829 ctx->samp_mask_in = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_MASK_IN, 0x1);
1830 }
1831 dst[0] = ctx->samp_mask_in;
1832 break;
1833 case nir_intrinsic_load_user_clip_plane:
1834 idx = nir_intrinsic_ucp_id(intr);
1835 for (int i = 0; i < dest_components; i++) {
1836 unsigned n = idx * 4 + i;
1837 dst[i] = create_driver_param(ctx, IR3_DP_UCP0_X + n);
1838 }
1839 break;
1840 case nir_intrinsic_load_front_face:
1841 if (!ctx->frag_face) {
1842 ctx->so->frag_face = true;
1843 ctx->frag_face = create_sysval_input(ctx, SYSTEM_VALUE_FRONT_FACE, 0x1);
1844 ctx->frag_face->regs[0]->flags |= IR3_REG_HALF;
1845 }
1846 /* for fragface, we get -1 for back and 0 for front. However this is
1847 * the inverse of what nir expects (where ~0 is true).
1848 */
1849 dst[0] = ir3_CMPS_S(b,
1850 ctx->frag_face, 0,
1851 create_immed_typed(b, 0, TYPE_U16), 0);
1852 dst[0]->cat2.condition = IR3_COND_EQ;
1853 break;
1854 case nir_intrinsic_load_local_invocation_id:
1855 if (!ctx->local_invocation_id) {
1856 ctx->local_invocation_id =
1857 create_sysval_input(ctx, SYSTEM_VALUE_LOCAL_INVOCATION_ID, 0x7);
1858 }
1859 ir3_split_dest(b, dst, ctx->local_invocation_id, 0, 3);
1860 break;
1861 case nir_intrinsic_load_work_group_id:
1862 if (!ctx->work_group_id) {
1863 ctx->work_group_id =
1864 create_sysval_input(ctx, SYSTEM_VALUE_WORK_GROUP_ID, 0x7);
1865 ctx->work_group_id->regs[0]->flags |= IR3_REG_HIGH;
1866 }
1867 ir3_split_dest(b, dst, ctx->work_group_id, 0, 3);
1868 break;
1869 case nir_intrinsic_load_num_work_groups:
1870 for (int i = 0; i < dest_components; i++) {
1871 dst[i] = create_driver_param(ctx, IR3_DP_NUM_WORK_GROUPS_X + i);
1872 }
1873 break;
1874 case nir_intrinsic_load_local_group_size:
1875 for (int i = 0; i < dest_components; i++) {
1876 dst[i] = create_driver_param(ctx, IR3_DP_LOCAL_GROUP_SIZE_X + i);
1877 }
1878 break;
1879 case nir_intrinsic_discard_if:
1880 case nir_intrinsic_discard: {
1881 struct ir3_instruction *cond, *kill;
1882
1883 if (intr->intrinsic == nir_intrinsic_discard_if) {
1884 /* conditional discard: */
1885 src = ir3_get_src(ctx, &intr->src[0]);
1886 cond = src[0];
1887 } else {
1888 /* unconditional discard: */
1889 cond = create_immed(b, 1);
1890 }
1891
1892 /* NOTE: only cmps.*.* can write p0.x: */
1893 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1894 cond->cat2.condition = IR3_COND_NE;
1895
1896 /* condition always goes in predicate register: */
1897 cond->regs[0]->num = regid(REG_P0, 0);
1898 cond->regs[0]->flags &= ~IR3_REG_SSA;
1899
1900 kill = ir3_KILL(b, cond, 0);
1901 kill->regs[1]->num = regid(REG_P0, 0);
1902 array_insert(ctx->ir, ctx->ir->predicates, kill);
1903
1904 array_insert(b, b->keeps, kill);
1905 ctx->so->has_kill = true;
1906
1907 break;
1908 }
1909
1910 case nir_intrinsic_cond_end_ir3: {
1911 struct ir3_instruction *cond, *kill;
1912
1913 src = ir3_get_src(ctx, &intr->src[0]);
1914 cond = src[0];
1915
1916 /* NOTE: only cmps.*.* can write p0.x: */
1917 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1918 cond->cat2.condition = IR3_COND_NE;
1919
1920 /* condition always goes in predicate register: */
1921 cond->regs[0]->num = regid(REG_P0, 0);
1922
1923 kill = ir3_PREDT(b, cond, 0);
1924
1925 kill->barrier_class = IR3_BARRIER_EVERYTHING;
1926 kill->barrier_conflict = IR3_BARRIER_EVERYTHING;
1927
1928 array_insert(ctx->ir, ctx->ir->predicates, kill);
1929 array_insert(b, b->keeps, kill);
1930 break;
1931 }
1932
1933 case nir_intrinsic_load_shared_ir3:
1934 emit_intrinsic_load_shared_ir3(ctx, intr, dst);
1935 break;
1936 case nir_intrinsic_store_shared_ir3:
1937 emit_intrinsic_store_shared_ir3(ctx, intr);
1938 break;
1939 case nir_intrinsic_bindless_resource_ir3:
1940 dst[0] = ir3_get_src(ctx, &intr->src[0])[0];
1941 break;
1942 default:
1943 ir3_context_error(ctx, "Unhandled intrinsic type: %s\n",
1944 nir_intrinsic_infos[intr->intrinsic].name);
1945 break;
1946 }
1947
1948 if (info->has_dest)
1949 ir3_put_dst(ctx, &intr->dest);
1950 }
1951
1952 static void
1953 emit_load_const(struct ir3_context *ctx, nir_load_const_instr *instr)
1954 {
1955 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &instr->def,
1956 instr->def.num_components);
1957
1958 if (instr->def.bit_size == 16) {
1959 for (int i = 0; i < instr->def.num_components; i++)
1960 dst[i] = create_immed_typed(ctx->block,
1961 instr->value[i].u16,
1962 TYPE_U16);
1963 } else {
1964 for (int i = 0; i < instr->def.num_components; i++)
1965 dst[i] = create_immed_typed(ctx->block,
1966 instr->value[i].u32,
1967 TYPE_U32);
1968 }
1969
1970 }
1971
1972 static void
1973 emit_undef(struct ir3_context *ctx, nir_ssa_undef_instr *undef)
1974 {
1975 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &undef->def,
1976 undef->def.num_components);
1977 type_t type = (undef->def.bit_size == 16) ? TYPE_U16 : TYPE_U32;
1978
1979 /* backend doesn't want undefined instructions, so just plug
1980 * in 0.0..
1981 */
1982 for (int i = 0; i < undef->def.num_components; i++)
1983 dst[i] = create_immed_typed(ctx->block, fui(0.0), type);
1984 }
1985
1986 /*
1987 * texture fetch/sample instructions:
1988 */
1989
1990 static type_t
1991 get_tex_dest_type(nir_tex_instr *tex)
1992 {
1993 type_t type;
1994
1995 switch (nir_alu_type_get_base_type(tex->dest_type)) {
1996 case nir_type_invalid:
1997 case nir_type_float:
1998 type = nir_dest_bit_size(tex->dest) == 16 ? TYPE_F16 : TYPE_F32;
1999 break;
2000 case nir_type_int:
2001 type = nir_dest_bit_size(tex->dest) == 16 ? TYPE_S16 : TYPE_S32;
2002 break;
2003 case nir_type_uint:
2004 case nir_type_bool:
2005 type = nir_dest_bit_size(tex->dest) == 16 ? TYPE_U16 : TYPE_U32;
2006 break;
2007 default:
2008 unreachable("bad dest_type");
2009 }
2010
2011 return type;
2012 }
2013
2014 static void
2015 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
2016 {
2017 unsigned coords = glsl_get_sampler_dim_coordinate_components(tex->sampler_dim);
2018 unsigned flags = 0;
2019
2020 /* note: would use tex->coord_components.. except txs.. also,
2021 * since array index goes after shadow ref, we don't want to
2022 * count it:
2023 */
2024 if (coords == 3)
2025 flags |= IR3_INSTR_3D;
2026
2027 if (tex->is_shadow && tex->op != nir_texop_lod)
2028 flags |= IR3_INSTR_S;
2029
2030 if (tex->is_array && tex->op != nir_texop_lod)
2031 flags |= IR3_INSTR_A;
2032
2033 *flagsp = flags;
2034 *coordsp = coords;
2035 }
2036
2037 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
2038 * or immediate (in which case it will get lowered later to a non .s2en
2039 * version of the tex instruction which encode tex/samp as immediates:
2040 */
2041 static struct tex_src_info
2042 get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
2043 {
2044 struct ir3_block *b = ctx->block;
2045 struct tex_src_info info = { 0 };
2046 int texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_handle);
2047 int sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_handle);
2048 struct ir3_instruction *texture, *sampler;
2049
2050 if (texture_idx >= 0 || sampler_idx >= 0) {
2051 /* Bindless case */
2052 info.flags |= IR3_INSTR_B;
2053
2054 /* Gather information required to determine which encoding to
2055 * choose as well as for prefetch.
2056 */
2057 nir_intrinsic_instr *bindless_tex = NULL;
2058 bool tex_const;
2059 if (texture_idx >= 0) {
2060 ctx->so->bindless_tex = true;
2061 bindless_tex = ir3_bindless_resource(tex->src[texture_idx].src);
2062 assert(bindless_tex);
2063 info.tex_base = nir_intrinsic_desc_set(bindless_tex);
2064 tex_const = nir_src_is_const(bindless_tex->src[0]);
2065 if (tex_const)
2066 info.tex_idx = nir_src_as_uint(bindless_tex->src[0]);
2067 } else {
2068 /* To simplify some of the logic below, assume the index is
2069 * constant 0 when it's not enabled.
2070 */
2071 tex_const = true;
2072 info.tex_idx = 0;
2073 }
2074 nir_intrinsic_instr *bindless_samp = NULL;
2075 bool samp_const;
2076 if (sampler_idx >= 0) {
2077 ctx->so->bindless_samp = true;
2078 bindless_samp = ir3_bindless_resource(tex->src[sampler_idx].src);
2079 assert(bindless_samp);
2080 info.samp_base = nir_intrinsic_desc_set(bindless_samp);
2081 samp_const = nir_src_is_const(bindless_samp->src[0]);
2082 if (samp_const)
2083 info.samp_idx = nir_src_as_uint(bindless_samp->src[0]);
2084 } else {
2085 samp_const = true;
2086 info.samp_idx = 0;
2087 }
2088
2089 /* Choose encoding. */
2090 if (tex_const && samp_const && info.tex_idx < 256 && info.samp_idx < 256) {
2091 if (info.tex_idx < 16 && info.samp_idx < 16 &&
2092 (!bindless_tex || !bindless_samp || info.tex_base == info.samp_base)) {
2093 /* Everything fits within the instruction */
2094 info.base = info.tex_base;
2095 info.combined_idx = info.samp_idx | (info.tex_idx << 4);
2096 } else {
2097 info.base = info.tex_base;
2098 info.a1_val = info.tex_idx << 3 | info.samp_base;
2099 info.combined_idx = info.samp_idx;
2100 info.flags |= IR3_INSTR_A1EN;
2101 }
2102 info.samp_tex = NULL;
2103 } else {
2104 info.flags |= IR3_INSTR_S2EN;
2105 /* In the indirect case, we only use a1.x to store the sampler
2106 * base if it differs from the texture base.
2107 */
2108 if (!bindless_tex || !bindless_samp || info.tex_base == info.samp_base) {
2109 info.base = info.tex_base;
2110 } else {
2111 info.base = info.tex_base;
2112 info.a1_val = info.samp_base;
2113 info.flags |= IR3_INSTR_A1EN;
2114 }
2115
2116 /* Note: the indirect source is now a vec2 instead of hvec2, and
2117 * for some reason the texture and sampler are swapped.
2118 */
2119 struct ir3_instruction *texture, *sampler;
2120
2121 if (bindless_tex) {
2122 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
2123 } else {
2124 texture = create_immed(b, 0);
2125 }
2126
2127 if (bindless_samp) {
2128 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
2129 } else {
2130 sampler = create_immed(b, 0);
2131 }
2132 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2133 texture,
2134 sampler,
2135 }, 2);
2136 }
2137 } else {
2138 info.flags |= IR3_INSTR_S2EN;
2139 texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_offset);
2140 sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset);
2141 if (texture_idx >= 0) {
2142 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
2143 texture = ir3_COV(ctx->block, texture, TYPE_U32, TYPE_U16);
2144 } else {
2145 /* TODO what to do for dynamic case? I guess we only need the
2146 * max index for astc srgb workaround so maybe not a problem
2147 * to worry about if we don't enable indirect samplers for
2148 * a4xx?
2149 */
2150 ctx->max_texture_index = MAX2(ctx->max_texture_index, tex->texture_index);
2151 texture = create_immed_typed(ctx->block, tex->texture_index, TYPE_U16);
2152 info.tex_idx = tex->texture_index;
2153 }
2154
2155 if (sampler_idx >= 0) {
2156 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
2157 sampler = ir3_COV(ctx->block, sampler, TYPE_U32, TYPE_U16);
2158 } else {
2159 sampler = create_immed_typed(ctx->block, tex->sampler_index, TYPE_U16);
2160 info.samp_idx = tex->texture_index;
2161 }
2162
2163 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2164 sampler,
2165 texture,
2166 }, 2);
2167 }
2168
2169 return info;
2170 }
2171
2172 static void
2173 emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
2174 {
2175 struct ir3_block *b = ctx->block;
2176 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
2177 struct ir3_instruction * const *coord, * const *off, * const *ddx, * const *ddy;
2178 struct ir3_instruction *lod, *compare, *proj, *sample_index;
2179 struct tex_src_info info = { 0 };
2180 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
2181 unsigned i, coords, flags, ncomp;
2182 unsigned nsrc0 = 0, nsrc1 = 0;
2183 type_t type;
2184 opc_t opc = 0;
2185
2186 ncomp = nir_dest_num_components(tex->dest);
2187
2188 coord = off = ddx = ddy = NULL;
2189 lod = proj = compare = sample_index = NULL;
2190
2191 dst = ir3_get_dst(ctx, &tex->dest, ncomp);
2192
2193 for (unsigned i = 0; i < tex->num_srcs; i++) {
2194 switch (tex->src[i].src_type) {
2195 case nir_tex_src_coord:
2196 coord = ir3_get_src(ctx, &tex->src[i].src);
2197 break;
2198 case nir_tex_src_bias:
2199 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
2200 has_bias = true;
2201 break;
2202 case nir_tex_src_lod:
2203 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
2204 has_lod = true;
2205 break;
2206 case nir_tex_src_comparator: /* shadow comparator */
2207 compare = ir3_get_src(ctx, &tex->src[i].src)[0];
2208 break;
2209 case nir_tex_src_projector:
2210 proj = ir3_get_src(ctx, &tex->src[i].src)[0];
2211 has_proj = true;
2212 break;
2213 case nir_tex_src_offset:
2214 off = ir3_get_src(ctx, &tex->src[i].src);
2215 has_off = true;
2216 break;
2217 case nir_tex_src_ddx:
2218 ddx = ir3_get_src(ctx, &tex->src[i].src);
2219 break;
2220 case nir_tex_src_ddy:
2221 ddy = ir3_get_src(ctx, &tex->src[i].src);
2222 break;
2223 case nir_tex_src_ms_index:
2224 sample_index = ir3_get_src(ctx, &tex->src[i].src)[0];
2225 break;
2226 case nir_tex_src_texture_offset:
2227 case nir_tex_src_sampler_offset:
2228 case nir_tex_src_texture_handle:
2229 case nir_tex_src_sampler_handle:
2230 /* handled in get_tex_samp_src() */
2231 break;
2232 default:
2233 ir3_context_error(ctx, "Unhandled NIR tex src type: %d\n",
2234 tex->src[i].src_type);
2235 return;
2236 }
2237 }
2238
2239 switch (tex->op) {
2240 case nir_texop_tex_prefetch:
2241 compile_assert(ctx, !has_bias);
2242 compile_assert(ctx, !has_lod);
2243 compile_assert(ctx, !compare);
2244 compile_assert(ctx, !has_proj);
2245 compile_assert(ctx, !has_off);
2246 compile_assert(ctx, !ddx);
2247 compile_assert(ctx, !ddy);
2248 compile_assert(ctx, !sample_index);
2249 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_texture_offset) < 0);
2250 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset) < 0);
2251
2252 if (ctx->so->num_sampler_prefetch < ctx->prefetch_limit) {
2253 opc = OPC_META_TEX_PREFETCH;
2254 ctx->so->num_sampler_prefetch++;
2255 break;
2256 }
2257 /* fallthru */
2258 case nir_texop_tex: opc = has_lod ? OPC_SAML : OPC_SAM; break;
2259 case nir_texop_txb: opc = OPC_SAMB; break;
2260 case nir_texop_txl: opc = OPC_SAML; break;
2261 case nir_texop_txd: opc = OPC_SAMGQ; break;
2262 case nir_texop_txf: opc = OPC_ISAML; break;
2263 case nir_texop_lod: opc = OPC_GETLOD; break;
2264 case nir_texop_tg4:
2265 /* NOTE: a4xx might need to emulate gather w/ txf (this is
2266 * what blob does, seems gather is broken?), and a3xx did
2267 * not support it (but probably could also emulate).
2268 */
2269 switch (tex->component) {
2270 case 0: opc = OPC_GATHER4R; break;
2271 case 1: opc = OPC_GATHER4G; break;
2272 case 2: opc = OPC_GATHER4B; break;
2273 case 3: opc = OPC_GATHER4A; break;
2274 }
2275 break;
2276 case nir_texop_txf_ms_fb:
2277 case nir_texop_txf_ms: opc = OPC_ISAMM; break;
2278 default:
2279 ir3_context_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
2280 return;
2281 }
2282
2283 tex_info(tex, &flags, &coords);
2284
2285 /*
2286 * lay out the first argument in the proper order:
2287 * - actual coordinates first
2288 * - shadow reference
2289 * - array index
2290 * - projection w
2291 * - starting at offset 4, dpdx.xy, dpdy.xy
2292 *
2293 * bias/lod go into the second arg
2294 */
2295
2296 /* insert tex coords: */
2297 for (i = 0; i < coords; i++)
2298 src0[i] = coord[i];
2299
2300 nsrc0 = i;
2301
2302 /* scale up integer coords for TXF based on the LOD */
2303 if (ctx->compiler->unminify_coords && (opc == OPC_ISAML)) {
2304 assert(has_lod);
2305 for (i = 0; i < coords; i++)
2306 src0[i] = ir3_SHL_B(b, src0[i], 0, lod, 0);
2307 }
2308
2309 if (coords == 1) {
2310 /* hw doesn't do 1d, so we treat it as 2d with
2311 * height of 1, and patch up the y coord.
2312 */
2313 if (is_isam(opc)) {
2314 src0[nsrc0++] = create_immed(b, 0);
2315 } else {
2316 src0[nsrc0++] = create_immed(b, fui(0.5));
2317 }
2318 }
2319
2320 if (tex->is_shadow && tex->op != nir_texop_lod)
2321 src0[nsrc0++] = compare;
2322
2323 if (tex->is_array && tex->op != nir_texop_lod) {
2324 struct ir3_instruction *idx = coord[coords];
2325
2326 /* the array coord for cube arrays needs 0.5 added to it */
2327 if (ctx->compiler->array_index_add_half && !is_isam(opc))
2328 idx = ir3_ADD_F(b, idx, 0, create_immed(b, fui(0.5)), 0);
2329
2330 src0[nsrc0++] = idx;
2331 }
2332
2333 if (has_proj) {
2334 src0[nsrc0++] = proj;
2335 flags |= IR3_INSTR_P;
2336 }
2337
2338 /* pad to 4, then ddx/ddy: */
2339 if (tex->op == nir_texop_txd) {
2340 while (nsrc0 < 4)
2341 src0[nsrc0++] = create_immed(b, fui(0.0));
2342 for (i = 0; i < coords; i++)
2343 src0[nsrc0++] = ddx[i];
2344 if (coords < 2)
2345 src0[nsrc0++] = create_immed(b, fui(0.0));
2346 for (i = 0; i < coords; i++)
2347 src0[nsrc0++] = ddy[i];
2348 if (coords < 2)
2349 src0[nsrc0++] = create_immed(b, fui(0.0));
2350 }
2351
2352 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
2353 * with scaled x coord according to requested sample:
2354 */
2355 if (opc == OPC_ISAMM) {
2356 if (ctx->compiler->txf_ms_with_isaml) {
2357 /* the samples are laid out in x dimension as
2358 * 0 1 2 3
2359 * x_ms = (x << ms) + sample_index;
2360 */
2361 struct ir3_instruction *ms;
2362 ms = create_immed(b, (ctx->samples >> (2 * tex->texture_index)) & 3);
2363
2364 src0[0] = ir3_SHL_B(b, src0[0], 0, ms, 0);
2365 src0[0] = ir3_ADD_U(b, src0[0], 0, sample_index, 0);
2366
2367 opc = OPC_ISAML;
2368 } else {
2369 src0[nsrc0++] = sample_index;
2370 }
2371 }
2372
2373 /*
2374 * second argument (if applicable):
2375 * - offsets
2376 * - lod
2377 * - bias
2378 */
2379 if (has_off | has_lod | has_bias) {
2380 if (has_off) {
2381 unsigned off_coords = coords;
2382 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2383 off_coords--;
2384 for (i = 0; i < off_coords; i++)
2385 src1[nsrc1++] = off[i];
2386 if (off_coords < 2)
2387 src1[nsrc1++] = create_immed(b, fui(0.0));
2388 flags |= IR3_INSTR_O;
2389 }
2390
2391 if (has_lod | has_bias)
2392 src1[nsrc1++] = lod;
2393 }
2394
2395 type = get_tex_dest_type(tex);
2396
2397 if (opc == OPC_GETLOD)
2398 type = TYPE_S32;
2399
2400
2401 if (tex->op == nir_texop_txf_ms_fb) {
2402 /* only expect a single txf_ms_fb per shader: */
2403 compile_assert(ctx, !ctx->so->fb_read);
2404 compile_assert(ctx, ctx->so->type == MESA_SHADER_FRAGMENT);
2405
2406 ctx->so->fb_read = true;
2407 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2408 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2409 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2410 }, 2);
2411 info.flags = IR3_INSTR_S2EN;
2412
2413 ctx->so->num_samp++;
2414 } else {
2415 info = get_tex_samp_tex_src(ctx, tex);
2416 }
2417
2418 struct ir3_instruction *col0 = ir3_create_collect(ctx, src0, nsrc0);
2419 struct ir3_instruction *col1 = ir3_create_collect(ctx, src1, nsrc1);
2420
2421 if (opc == OPC_META_TEX_PREFETCH) {
2422 int idx = nir_tex_instr_src_index(tex, nir_tex_src_coord);
2423
2424 compile_assert(ctx, tex->src[idx].src.is_ssa);
2425
2426 sam = ir3_META_TEX_PREFETCH(b);
2427 __ssa_dst(sam)->wrmask = MASK(ncomp); /* dst */
2428 __ssa_src(sam, get_barycentric(ctx, IJ_PERSP_PIXEL), 0);
2429 sam->prefetch.input_offset =
2430 ir3_nir_coord_offset(tex->src[idx].src.ssa);
2431 /* make sure not to add irrelevant flags like S2EN */
2432 sam->flags = flags | (info.flags & IR3_INSTR_B);
2433 sam->prefetch.tex = info.tex_idx;
2434 sam->prefetch.samp = info.samp_idx;
2435 sam->prefetch.tex_base = info.tex_base;
2436 sam->prefetch.samp_base = info.samp_base;
2437 } else {
2438 info.flags |= flags;
2439 sam = emit_sam(ctx, opc, info, type, MASK(ncomp), col0, col1);
2440 }
2441
2442 if ((ctx->astc_srgb & (1 << tex->texture_index)) && !nir_tex_instr_is_query(tex)) {
2443 assert(opc != OPC_META_TEX_PREFETCH);
2444
2445 /* only need first 3 components: */
2446 sam->regs[0]->wrmask = 0x7;
2447 ir3_split_dest(b, dst, sam, 0, 3);
2448
2449 /* we need to sample the alpha separately with a non-ASTC
2450 * texture state:
2451 */
2452 sam = ir3_SAM(b, opc, type, 0b1000, flags | info.flags,
2453 info.samp_tex, col0, col1);
2454
2455 array_insert(ctx->ir, ctx->ir->astc_srgb, sam);
2456
2457 /* fixup .w component: */
2458 ir3_split_dest(b, &dst[3], sam, 3, 1);
2459 } else {
2460 /* normal (non-workaround) case: */
2461 ir3_split_dest(b, dst, sam, 0, ncomp);
2462 }
2463
2464 /* GETLOD returns results in 4.8 fixed point */
2465 if (opc == OPC_GETLOD) {
2466 struct ir3_instruction *factor = create_immed(b, fui(1.0 / 256));
2467
2468 compile_assert(ctx, tex->dest_type == nir_type_float);
2469 for (i = 0; i < 2; i++) {
2470 dst[i] = ir3_MUL_F(b, ir3_COV(b, dst[i], TYPE_S32, TYPE_F32), 0,
2471 factor, 0);
2472 }
2473 }
2474
2475 ir3_put_dst(ctx, &tex->dest);
2476 }
2477
2478 static void
2479 emit_tex_info(struct ir3_context *ctx, nir_tex_instr *tex, unsigned idx)
2480 {
2481 struct ir3_block *b = ctx->block;
2482 struct ir3_instruction **dst, *sam;
2483 type_t dst_type = get_tex_dest_type(tex);
2484 struct tex_src_info info = get_tex_samp_tex_src(ctx, tex);
2485
2486 dst = ir3_get_dst(ctx, &tex->dest, 1);
2487
2488 sam = emit_sam(ctx, OPC_GETINFO, info, dst_type, 1 << idx, NULL, NULL);
2489
2490 /* even though there is only one component, since it ends
2491 * up in .y/.z/.w rather than .x, we need a split_dest()
2492 */
2493 ir3_split_dest(b, dst, sam, idx, 1);
2494
2495 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2496 * the value in TEX_CONST_0 is zero-based.
2497 */
2498 if (ctx->compiler->levels_add_one)
2499 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
2500
2501 ir3_put_dst(ctx, &tex->dest);
2502 }
2503
2504 static void
2505 emit_tex_txs(struct ir3_context *ctx, nir_tex_instr *tex)
2506 {
2507 struct ir3_block *b = ctx->block;
2508 struct ir3_instruction **dst, *sam;
2509 struct ir3_instruction *lod;
2510 unsigned flags, coords;
2511 type_t dst_type = get_tex_dest_type(tex);
2512 struct tex_src_info info = get_tex_samp_tex_src(ctx, tex);
2513
2514 tex_info(tex, &flags, &coords);
2515 info.flags |= flags;
2516
2517 /* Actually we want the number of dimensions, not coordinates. This
2518 * distinction only matters for cubes.
2519 */
2520 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2521 coords = 2;
2522
2523 dst = ir3_get_dst(ctx, &tex->dest, 4);
2524
2525 int lod_idx = nir_tex_instr_src_index(tex, nir_tex_src_lod);
2526 compile_assert(ctx, lod_idx >= 0);
2527
2528 lod = ir3_get_src(ctx, &tex->src[lod_idx].src)[0];
2529
2530 sam = emit_sam(ctx, OPC_GETSIZE, info, dst_type, 0b1111, lod, NULL);
2531 ir3_split_dest(b, dst, sam, 0, 4);
2532
2533 /* Array size actually ends up in .w rather than .z. This doesn't
2534 * matter for miplevel 0, but for higher mips the value in z is
2535 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2536 * returned, which means that we have to add 1 to it for arrays.
2537 */
2538 if (tex->is_array) {
2539 if (ctx->compiler->levels_add_one) {
2540 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
2541 } else {
2542 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
2543 }
2544 }
2545
2546 ir3_put_dst(ctx, &tex->dest);
2547 }
2548
2549 static void
2550 emit_jump(struct ir3_context *ctx, nir_jump_instr *jump)
2551 {
2552 switch (jump->type) {
2553 case nir_jump_break:
2554 case nir_jump_continue:
2555 case nir_jump_return:
2556 /* I *think* we can simply just ignore this, and use the
2557 * successor block link to figure out where we need to
2558 * jump to for break/continue
2559 */
2560 break;
2561 default:
2562 ir3_context_error(ctx, "Unhandled NIR jump type: %d\n", jump->type);
2563 break;
2564 }
2565 }
2566
2567 static void
2568 emit_instr(struct ir3_context *ctx, nir_instr *instr)
2569 {
2570 switch (instr->type) {
2571 case nir_instr_type_alu:
2572 emit_alu(ctx, nir_instr_as_alu(instr));
2573 break;
2574 case nir_instr_type_deref:
2575 /* ignored, handled as part of the intrinsic they are src to */
2576 break;
2577 case nir_instr_type_intrinsic:
2578 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2579 break;
2580 case nir_instr_type_load_const:
2581 emit_load_const(ctx, nir_instr_as_load_const(instr));
2582 break;
2583 case nir_instr_type_ssa_undef:
2584 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
2585 break;
2586 case nir_instr_type_tex: {
2587 nir_tex_instr *tex = nir_instr_as_tex(instr);
2588 /* couple tex instructions get special-cased:
2589 */
2590 switch (tex->op) {
2591 case nir_texop_txs:
2592 emit_tex_txs(ctx, tex);
2593 break;
2594 case nir_texop_query_levels:
2595 emit_tex_info(ctx, tex, 2);
2596 break;
2597 case nir_texop_texture_samples:
2598 emit_tex_info(ctx, tex, 3);
2599 break;
2600 default:
2601 emit_tex(ctx, tex);
2602 break;
2603 }
2604 break;
2605 }
2606 case nir_instr_type_jump:
2607 emit_jump(ctx, nir_instr_as_jump(instr));
2608 break;
2609 case nir_instr_type_phi:
2610 /* we have converted phi webs to regs in NIR by now */
2611 ir3_context_error(ctx, "Unexpected NIR instruction type: %d\n", instr->type);
2612 break;
2613 case nir_instr_type_call:
2614 case nir_instr_type_parallel_copy:
2615 ir3_context_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
2616 break;
2617 }
2618 }
2619
2620 static struct ir3_block *
2621 get_block(struct ir3_context *ctx, const nir_block *nblock)
2622 {
2623 struct ir3_block *block;
2624 struct hash_entry *hentry;
2625
2626 hentry = _mesa_hash_table_search(ctx->block_ht, nblock);
2627 if (hentry)
2628 return hentry->data;
2629
2630 block = ir3_block_create(ctx->ir);
2631 block->nblock = nblock;
2632 _mesa_hash_table_insert(ctx->block_ht, nblock, block);
2633
2634 set_foreach(nblock->predecessors, sentry) {
2635 _mesa_set_add(block->predecessors, get_block(ctx, sentry->key));
2636 }
2637
2638 return block;
2639 }
2640
2641 static void
2642 emit_block(struct ir3_context *ctx, nir_block *nblock)
2643 {
2644 struct ir3_block *block = get_block(ctx, nblock);
2645
2646 for (int i = 0; i < ARRAY_SIZE(block->successors); i++) {
2647 if (nblock->successors[i]) {
2648 block->successors[i] =
2649 get_block(ctx, nblock->successors[i]);
2650 }
2651 }
2652
2653 ctx->block = block;
2654 list_addtail(&block->node, &ctx->ir->block_list);
2655
2656 /* re-emit addr register in each block if needed: */
2657 for (int i = 0; i < ARRAY_SIZE(ctx->addr0_ht); i++) {
2658 _mesa_hash_table_destroy(ctx->addr0_ht[i], NULL);
2659 ctx->addr0_ht[i] = NULL;
2660 }
2661
2662 _mesa_hash_table_u64_destroy(ctx->addr1_ht, NULL);
2663 ctx->addr1_ht = NULL;
2664
2665 nir_foreach_instr (instr, nblock) {
2666 ctx->cur_instr = instr;
2667 emit_instr(ctx, instr);
2668 ctx->cur_instr = NULL;
2669 if (ctx->error)
2670 return;
2671 }
2672
2673 _mesa_hash_table_clear(ctx->sel_cond_conversions, NULL);
2674 }
2675
2676 static void emit_cf_list(struct ir3_context *ctx, struct exec_list *list);
2677
2678 static void
2679 emit_if(struct ir3_context *ctx, nir_if *nif)
2680 {
2681 struct ir3_instruction *condition = ir3_get_src(ctx, &nif->condition)[0];
2682
2683 ctx->block->condition = ir3_get_predicate(ctx, condition);
2684
2685 emit_cf_list(ctx, &nif->then_list);
2686 emit_cf_list(ctx, &nif->else_list);
2687 }
2688
2689 static void
2690 emit_loop(struct ir3_context *ctx, nir_loop *nloop)
2691 {
2692 emit_cf_list(ctx, &nloop->body);
2693 ctx->so->loops++;
2694 }
2695
2696 static void
2697 stack_push(struct ir3_context *ctx)
2698 {
2699 ctx->stack++;
2700 ctx->max_stack = MAX2(ctx->max_stack, ctx->stack);
2701 }
2702
2703 static void
2704 stack_pop(struct ir3_context *ctx)
2705 {
2706 compile_assert(ctx, ctx->stack > 0);
2707 ctx->stack--;
2708 }
2709
2710 static void
2711 emit_cf_list(struct ir3_context *ctx, struct exec_list *list)
2712 {
2713 foreach_list_typed (nir_cf_node, node, node, list) {
2714 switch (node->type) {
2715 case nir_cf_node_block:
2716 emit_block(ctx, nir_cf_node_as_block(node));
2717 break;
2718 case nir_cf_node_if:
2719 stack_push(ctx);
2720 emit_if(ctx, nir_cf_node_as_if(node));
2721 stack_pop(ctx);
2722 break;
2723 case nir_cf_node_loop:
2724 stack_push(ctx);
2725 emit_loop(ctx, nir_cf_node_as_loop(node));
2726 stack_pop(ctx);
2727 break;
2728 case nir_cf_node_function:
2729 ir3_context_error(ctx, "TODO\n");
2730 break;
2731 }
2732 }
2733 }
2734
2735 /* emit stream-out code. At this point, the current block is the original
2736 * (nir) end block, and nir ensures that all flow control paths terminate
2737 * into the end block. We re-purpose the original end block to generate
2738 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2739 * block holding stream-out write instructions, followed by the new end
2740 * block:
2741 *
2742 * blockOrigEnd {
2743 * p0.x = (vtxcnt < maxvtxcnt)
2744 * // succs: blockStreamOut, blockNewEnd
2745 * }
2746 * blockStreamOut {
2747 * // preds: blockOrigEnd
2748 * ... stream-out instructions ...
2749 * // succs: blockNewEnd
2750 * }
2751 * blockNewEnd {
2752 * // preds: blockOrigEnd, blockStreamOut
2753 * }
2754 */
2755 static void
2756 emit_stream_out(struct ir3_context *ctx)
2757 {
2758 struct ir3 *ir = ctx->ir;
2759 struct ir3_stream_output_info *strmout =
2760 &ctx->so->shader->stream_output;
2761 struct ir3_block *orig_end_block, *stream_out_block, *new_end_block;
2762 struct ir3_instruction *vtxcnt, *maxvtxcnt, *cond;
2763 struct ir3_instruction *bases[IR3_MAX_SO_BUFFERS];
2764
2765 /* create vtxcnt input in input block at top of shader,
2766 * so that it is seen as live over the entire duration
2767 * of the shader:
2768 */
2769 vtxcnt = create_sysval_input(ctx, SYSTEM_VALUE_VERTEX_CNT, 0x1);
2770 maxvtxcnt = create_driver_param(ctx, IR3_DP_VTXCNT_MAX);
2771
2772 /* at this point, we are at the original 'end' block,
2773 * re-purpose this block to stream-out condition, then
2774 * append stream-out block and new-end block
2775 */
2776 orig_end_block = ctx->block;
2777
2778 // maybe w/ store_global intrinsic, we could do this
2779 // stuff in nir->nir pass
2780
2781 stream_out_block = ir3_block_create(ir);
2782 list_addtail(&stream_out_block->node, &ir->block_list);
2783
2784 new_end_block = ir3_block_create(ir);
2785 list_addtail(&new_end_block->node, &ir->block_list);
2786
2787 orig_end_block->successors[0] = stream_out_block;
2788 orig_end_block->successors[1] = new_end_block;
2789
2790 stream_out_block->successors[0] = new_end_block;
2791 _mesa_set_add(stream_out_block->predecessors, orig_end_block);
2792
2793 _mesa_set_add(new_end_block->predecessors, orig_end_block);
2794 _mesa_set_add(new_end_block->predecessors, stream_out_block);
2795
2796 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2797 cond = ir3_CMPS_S(ctx->block, vtxcnt, 0, maxvtxcnt, 0);
2798 cond->regs[0]->num = regid(REG_P0, 0);
2799 cond->regs[0]->flags &= ~IR3_REG_SSA;
2800 cond->cat2.condition = IR3_COND_LT;
2801
2802 /* condition goes on previous block to the conditional,
2803 * since it is used to pick which of the two successor
2804 * paths to take:
2805 */
2806 orig_end_block->condition = cond;
2807
2808 /* switch to stream_out_block to generate the stream-out
2809 * instructions:
2810 */
2811 ctx->block = stream_out_block;
2812
2813 /* Calculate base addresses based on vtxcnt. Instructions
2814 * generated for bases not used in following loop will be
2815 * stripped out in the backend.
2816 */
2817 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
2818 const struct ir3_const_state *const_state =
2819 ir3_const_state(ctx->so);
2820 unsigned stride = strmout->stride[i];
2821 struct ir3_instruction *base, *off;
2822
2823 base = create_uniform(ctx->block, regid(const_state->offsets.tfbo, i));
2824
2825 /* 24-bit should be enough: */
2826 off = ir3_MUL_U24(ctx->block, vtxcnt, 0,
2827 create_immed(ctx->block, stride * 4), 0);
2828
2829 bases[i] = ir3_ADD_S(ctx->block, off, 0, base, 0);
2830 }
2831
2832 /* Generate the per-output store instructions: */
2833 for (unsigned i = 0; i < strmout->num_outputs; i++) {
2834 for (unsigned j = 0; j < strmout->output[i].num_components; j++) {
2835 unsigned c = j + strmout->output[i].start_component;
2836 struct ir3_instruction *base, *out, *stg;
2837
2838 base = bases[strmout->output[i].output_buffer];
2839 out = ctx->outputs[regid(strmout->output[i].register_index, c)];
2840
2841 stg = ir3_STG(ctx->block, base, 0, out, 0,
2842 create_immed(ctx->block, 1), 0);
2843 stg->cat6.type = TYPE_U32;
2844 stg->cat6.dst_offset = (strmout->output[i].dst_offset + j) * 4;
2845
2846 array_insert(ctx->block, ctx->block->keeps, stg);
2847 }
2848 }
2849
2850 /* and finally switch to the new_end_block: */
2851 ctx->block = new_end_block;
2852 }
2853
2854 static void
2855 emit_function(struct ir3_context *ctx, nir_function_impl *impl)
2856 {
2857 nir_metadata_require(impl, nir_metadata_block_index);
2858
2859 compile_assert(ctx, ctx->stack == 0);
2860
2861 emit_cf_list(ctx, &impl->body);
2862 emit_block(ctx, impl->end_block);
2863
2864 compile_assert(ctx, ctx->stack == 0);
2865
2866 /* at this point, we should have a single empty block,
2867 * into which we emit the 'end' instruction.
2868 */
2869 compile_assert(ctx, list_is_empty(&ctx->block->instr_list));
2870
2871 /* If stream-out (aka transform-feedback) enabled, emit the
2872 * stream-out instructions, followed by a new empty block (into
2873 * which the 'end' instruction lands).
2874 *
2875 * NOTE: it is done in this order, rather than inserting before
2876 * we emit end_block, because NIR guarantees that all blocks
2877 * flow into end_block, and that end_block has no successors.
2878 * So by re-purposing end_block as the first block of stream-
2879 * out, we guarantee that all exit paths flow into the stream-
2880 * out instructions.
2881 */
2882 if ((ctx->compiler->gpu_id < 500) &&
2883 (ctx->so->shader->stream_output.num_outputs > 0) &&
2884 !ctx->so->binning_pass) {
2885 debug_assert(ctx->so->type == MESA_SHADER_VERTEX);
2886 emit_stream_out(ctx);
2887 }
2888
2889 /* Vertex shaders in a tessellation or geometry pipeline treat END as a
2890 * NOP and has an epilogue that writes the VS outputs to local storage, to
2891 * be read by the HS. Then it resets execution mask (chmask) and chains
2892 * to the next shader (chsh).
2893 */
2894 if ((ctx->so->type == MESA_SHADER_VERTEX &&
2895 (ctx->so->key.has_gs || ctx->so->key.tessellation)) ||
2896 (ctx->so->type == MESA_SHADER_TESS_EVAL && ctx->so->key.has_gs)) {
2897 struct ir3_instruction *chmask =
2898 ir3_CHMASK(ctx->block);
2899 chmask->barrier_class = IR3_BARRIER_EVERYTHING;
2900 chmask->barrier_conflict = IR3_BARRIER_EVERYTHING;
2901
2902 struct ir3_instruction *chsh =
2903 ir3_CHSH(ctx->block);
2904 chsh->barrier_class = IR3_BARRIER_EVERYTHING;
2905 chsh->barrier_conflict = IR3_BARRIER_EVERYTHING;
2906 } else {
2907 ir3_END(ctx->block);
2908 }
2909 }
2910
2911 static void
2912 setup_input(struct ir3_context *ctx, nir_intrinsic_instr *intr)
2913 {
2914 struct ir3_shader_variant *so = ctx->so;
2915 struct ir3_instruction *coord = NULL;
2916
2917 if (intr->intrinsic == nir_intrinsic_load_interpolated_input)
2918 coord = ir3_create_collect(ctx, ir3_get_src(ctx, &intr->src[0]), 2);
2919
2920 compile_assert(ctx, nir_src_is_const(intr->src[coord ? 1 : 0]));
2921
2922 unsigned frac = nir_intrinsic_component(intr);
2923 unsigned offset = nir_src_as_uint(intr->src[coord ? 1 : 0]);
2924 unsigned ncomp = nir_intrinsic_dest_components(intr);
2925 unsigned n = nir_intrinsic_base(intr) + offset;
2926 unsigned slot = nir_intrinsic_io_semantics(intr).location + offset;
2927 unsigned compmask;
2928
2929 /* Inputs are loaded using ldlw or ldg for other stages. */
2930 compile_assert(ctx, ctx->so->type == MESA_SHADER_FRAGMENT ||
2931 ctx->so->type == MESA_SHADER_VERTEX);
2932
2933 if (ctx->so->type == MESA_SHADER_FRAGMENT)
2934 compmask = BITFIELD_MASK(ncomp) << frac;
2935 else
2936 compmask = BITFIELD_MASK(ncomp + frac);
2937
2938 /* for a4xx+ rasterflat */
2939 if (so->inputs[n].rasterflat && ctx->so->key.rasterflat)
2940 coord = NULL;
2941
2942 so->total_in += util_bitcount(compmask & ~so->inputs[n].compmask);
2943
2944 so->inputs[n].slot = slot;
2945 so->inputs[n].compmask |= compmask;
2946 so->inputs_count = MAX2(so->inputs_count, n + 1);
2947 so->inputs[n].flat = !coord;
2948
2949 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2950 compile_assert(ctx, slot != VARYING_SLOT_POS);
2951
2952 so->inputs[n].bary = true;
2953
2954 for (int i = 0; i < ncomp; i++) {
2955 unsigned idx = (n * 4) + i + frac;
2956 ctx->last_dst[i] = create_frag_input(ctx, coord, idx);
2957 }
2958 } else {
2959 struct ir3_instruction *input = NULL;
2960
2961 foreach_input (in, ctx->ir) {
2962 if (in->input.inidx == n) {
2963 input = in;
2964 break;
2965 }
2966 }
2967
2968 if (!input) {
2969 input = create_input(ctx, compmask);
2970 input->input.inidx = n;
2971 } else {
2972 /* For aliased inputs, just append to the wrmask.. ie. if we
2973 * first see a vec2 index at slot N, and then later a vec4,
2974 * the wrmask of the resulting overlapped vec2 and vec4 is 0xf
2975 */
2976 input->regs[0]->wrmask |= compmask;
2977 }
2978
2979 for (int i = 0; i < ncomp + frac; i++) {
2980 unsigned idx = (n * 4) + i;
2981 compile_assert(ctx, idx < ctx->ninputs);
2982
2983 /* fixup the src wrmask to avoid validation fail */
2984 if (ctx->inputs[idx] && (ctx->inputs[idx] != input)) {
2985 ctx->inputs[idx]->regs[1]->wrmask = input->regs[0]->wrmask;
2986 continue;
2987 }
2988
2989 ir3_split_dest(ctx->block, &ctx->inputs[idx], input, i, 1);
2990 }
2991
2992 for (int i = 0; i < ncomp; i++) {
2993 unsigned idx = (n * 4) + i + frac;
2994 ctx->last_dst[i] = ctx->inputs[idx];
2995 }
2996 }
2997 }
2998
2999 /* Initially we assign non-packed inloc's for varyings, as we don't really
3000 * know up-front which components will be unused. After all the compilation
3001 * stages we scan the shader to see which components are actually used, and
3002 * re-pack the inlocs to eliminate unneeded varyings.
3003 */
3004 static void
3005 pack_inlocs(struct ir3_context *ctx)
3006 {
3007 struct ir3_shader_variant *so = ctx->so;
3008 uint8_t used_components[so->inputs_count];
3009
3010 memset(used_components, 0, sizeof(used_components));
3011
3012 /*
3013 * First Step: scan shader to find which bary.f/ldlv remain:
3014 */
3015
3016 foreach_block (block, &ctx->ir->block_list) {
3017 foreach_instr (instr, &block->instr_list) {
3018 if (is_input(instr)) {
3019 unsigned inloc = instr->regs[1]->iim_val;
3020 unsigned i = inloc / 4;
3021 unsigned j = inloc % 4;
3022
3023 compile_assert(ctx, instr->regs[1]->flags & IR3_REG_IMMED);
3024 compile_assert(ctx, i < so->inputs_count);
3025
3026 used_components[i] |= 1 << j;
3027 } else if (instr->opc == OPC_META_TEX_PREFETCH) {
3028 for (int n = 0; n < 2; n++) {
3029 unsigned inloc = instr->prefetch.input_offset + n;
3030 unsigned i = inloc / 4;
3031 unsigned j = inloc % 4;
3032
3033 compile_assert(ctx, i < so->inputs_count);
3034
3035 used_components[i] |= 1 << j;
3036 }
3037 }
3038 }
3039 }
3040
3041 /*
3042 * Second Step: reassign varying inloc/slots:
3043 */
3044
3045 unsigned actual_in = 0;
3046 unsigned inloc = 0;
3047
3048 for (unsigned i = 0; i < so->inputs_count; i++) {
3049 unsigned compmask = 0, maxcomp = 0;
3050
3051 so->inputs[i].inloc = inloc;
3052 so->inputs[i].bary = false;
3053
3054 for (unsigned j = 0; j < 4; j++) {
3055 if (!(used_components[i] & (1 << j)))
3056 continue;
3057
3058 compmask |= (1 << j);
3059 actual_in++;
3060 maxcomp = j + 1;
3061
3062 /* at this point, since used_components[i] mask is only
3063 * considering varyings (ie. not sysvals) we know this
3064 * is a varying:
3065 */
3066 so->inputs[i].bary = true;
3067 }
3068
3069 if (so->inputs[i].bary) {
3070 so->varying_in++;
3071 so->inputs[i].compmask = (1 << maxcomp) - 1;
3072 inloc += maxcomp;
3073 }
3074 }
3075
3076 /*
3077 * Third Step: reassign packed inloc's:
3078 */
3079
3080 foreach_block (block, &ctx->ir->block_list) {
3081 foreach_instr (instr, &block->instr_list) {
3082 if (is_input(instr)) {
3083 unsigned inloc = instr->regs[1]->iim_val;
3084 unsigned i = inloc / 4;
3085 unsigned j = inloc % 4;
3086
3087 instr->regs[1]->iim_val = so->inputs[i].inloc + j;
3088 } else if (instr->opc == OPC_META_TEX_PREFETCH) {
3089 unsigned i = instr->prefetch.input_offset / 4;
3090 unsigned j = instr->prefetch.input_offset % 4;
3091 instr->prefetch.input_offset = so->inputs[i].inloc + j;
3092 }
3093 }
3094 }
3095 }
3096
3097 static void
3098 setup_output(struct ir3_context *ctx, nir_intrinsic_instr *intr)
3099 {
3100 struct ir3_shader_variant *so = ctx->so;
3101 nir_io_semantics io = nir_intrinsic_io_semantics(intr);
3102
3103 compile_assert(ctx, nir_src_is_const(intr->src[1]));
3104
3105 unsigned offset = nir_src_as_uint(intr->src[1]);
3106 unsigned n = nir_intrinsic_base(intr) + offset;
3107 unsigned frac = nir_intrinsic_component(intr);
3108 unsigned ncomp = nir_intrinsic_src_components(intr, 0);
3109 unsigned slot = io.location + offset;
3110
3111 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
3112 switch (slot) {
3113 case FRAG_RESULT_DEPTH:
3114 so->writes_pos = true;
3115 break;
3116 case FRAG_RESULT_COLOR:
3117 so->color0_mrt = 1;
3118 break;
3119 case FRAG_RESULT_SAMPLE_MASK:
3120 so->writes_smask = true;
3121 break;
3122 case FRAG_RESULT_STENCIL:
3123 so->writes_stencilref = true;
3124 break;
3125 default:
3126 slot += io.dual_source_blend_index; /* For dual-src blend */
3127 if (slot >= FRAG_RESULT_DATA0)
3128 break;
3129 ir3_context_error(ctx, "unknown FS output name: %s\n",
3130 gl_frag_result_name(slot));
3131 }
3132 } else if (ctx->so->type == MESA_SHADER_VERTEX ||
3133 ctx->so->type == MESA_SHADER_TESS_EVAL ||
3134 ctx->so->type == MESA_SHADER_GEOMETRY) {
3135 switch (slot) {
3136 case VARYING_SLOT_POS:
3137 so->writes_pos = true;
3138 break;
3139 case VARYING_SLOT_PSIZ:
3140 so->writes_psize = true;
3141 break;
3142 case VARYING_SLOT_PRIMITIVE_ID:
3143 case VARYING_SLOT_LAYER:
3144 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3:
3145 debug_assert(ctx->so->type == MESA_SHADER_GEOMETRY);
3146 /* fall through */
3147 case VARYING_SLOT_COL0:
3148 case VARYING_SLOT_COL1:
3149 case VARYING_SLOT_BFC0:
3150 case VARYING_SLOT_BFC1:
3151 case VARYING_SLOT_FOGC:
3152 case VARYING_SLOT_CLIP_DIST0:
3153 case VARYING_SLOT_CLIP_DIST1:
3154 case VARYING_SLOT_CLIP_VERTEX:
3155 break;
3156 default:
3157 if (slot >= VARYING_SLOT_VAR0)
3158 break;
3159 if ((VARYING_SLOT_TEX0 <= slot) && (slot <= VARYING_SLOT_TEX7))
3160 break;
3161 ir3_context_error(ctx, "unknown %s shader output name: %s\n",
3162 _mesa_shader_stage_to_string(ctx->so->type),
3163 gl_varying_slot_name(slot));
3164 }
3165 } else {
3166 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
3167 }
3168
3169
3170 so->outputs_count = MAX2(so->outputs_count, n + 1);
3171 compile_assert(ctx, so->outputs_count < ARRAY_SIZE(so->outputs));
3172
3173 so->outputs[n].slot = slot;
3174
3175 for (int i = 0; i < ncomp; i++) {
3176 unsigned idx = (n * 4) + i + frac;
3177 compile_assert(ctx, idx < ctx->noutputs);
3178 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
3179 }
3180
3181 /* if varying packing doesn't happen, we could end up in a situation
3182 * with "holes" in the output, and since the per-generation code that
3183 * sets up varying linkage registers doesn't expect to have more than
3184 * one varying per vec4 slot, pad the holes.
3185 *
3186 * Note that this should probably generate a performance warning of
3187 * some sort.
3188 */
3189 for (int i = 0; i < frac; i++) {
3190 unsigned idx = (n * 4) + i;
3191 if (!ctx->outputs[idx]) {
3192 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
3193 }
3194 }
3195
3196 struct ir3_instruction * const *src = ir3_get_src(ctx, &intr->src[0]);
3197 for (int i = 0; i < ncomp; i++) {
3198 unsigned idx = (n * 4) + i + frac;
3199 ctx->outputs[idx] = src[i];
3200 }
3201 }
3202
3203 static void
3204 emit_instructions(struct ir3_context *ctx)
3205 {
3206 nir_function_impl *fxn = nir_shader_get_entrypoint(ctx->s);
3207
3208 /* some varying setup which can't be done in setup_input(): */
3209 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
3210 nir_foreach_shader_in_variable (var, ctx->s) {
3211 /* if any varyings have 'sample' qualifer, that triggers us
3212 * to run in per-sample mode:
3213 */
3214 if (var->data.sample)
3215 ctx->so->per_samp = true;
3216
3217 /* set rasterflat flag for front/back color */
3218 if (var->data.interpolation == INTERP_MODE_NONE) {
3219 switch (var->data.location) {
3220 case VARYING_SLOT_COL0:
3221 case VARYING_SLOT_COL1:
3222 case VARYING_SLOT_BFC0:
3223 case VARYING_SLOT_BFC1:
3224 ctx->so->inputs[var->data.driver_location].rasterflat = true;
3225 break;
3226 default:
3227 break;
3228 }
3229 }
3230 }
3231 }
3232
3233 /* TODO: for GS/HS/DS, load_input isn't used. but ctx->s->num_inputs is non-zero
3234 * likely the same for num_outputs in cases where store_output isn't used
3235 */
3236 ctx->so->inputs_count = ctx->s->num_inputs;
3237 ctx->ninputs = ctx->s->num_inputs * 4;
3238 ctx->noutputs = ctx->s->num_outputs * 4;
3239 ctx->inputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->ninputs);
3240 ctx->outputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->noutputs);
3241
3242 ctx->ir = ir3_create(ctx->compiler, ctx->so);
3243
3244 /* Create inputs in first block: */
3245 ctx->block = get_block(ctx, nir_start_block(fxn));
3246 ctx->in_block = ctx->block;
3247
3248 /* for fragment shader, the vcoord input register is used as the
3249 * base for bary.f varying fetch instrs:
3250 *
3251 * TODO defer creating ctx->ij_pixel and corresponding sysvals
3252 * until emit_intrinsic when we know they are actually needed.
3253 * For now, we defer creating ctx->ij_centroid, etc, since we
3254 * only need ij_pixel for "old style" varying inputs (ie.
3255 * tgsi_to_nir)
3256 */
3257 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
3258 ctx->ij[IJ_PERSP_PIXEL] = create_input(ctx, 0x3);
3259 }
3260
3261 /* Defer add_sysval_input() stuff until after setup_inputs(),
3262 * because sysvals need to be appended after varyings:
3263 */
3264 if (ctx->ij[IJ_PERSP_PIXEL]) {
3265 add_sysval_input_compmask(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL,
3266 0x3, ctx->ij[IJ_PERSP_PIXEL]);
3267 }
3268
3269
3270 /* Tesselation shaders always need primitive ID for indexing the
3271 * BO. Geometry shaders don't always need it but when they do it has be
3272 * delivered and unclobbered in the VS. To make things easy, we always
3273 * make room for it in VS/DS.
3274 */
3275 bool has_tess = ctx->so->key.tessellation != IR3_TESS_NONE;
3276 bool has_gs = ctx->so->key.has_gs;
3277 switch (ctx->so->type) {
3278 case MESA_SHADER_VERTEX:
3279 if (has_tess) {
3280 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3281 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3282 } else if (has_gs) {
3283 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3284 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3285 }
3286 break;
3287 case MESA_SHADER_TESS_CTRL:
3288 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3289 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3290 break;
3291 case MESA_SHADER_TESS_EVAL:
3292 if (has_gs)
3293 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3294 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3295 break;
3296 case MESA_SHADER_GEOMETRY:
3297 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3298 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3299 break;
3300 default:
3301 break;
3302 }
3303
3304 /* Find # of samplers. Just assume that we'll be reading from images.. if
3305 * it is write-only we don't have to count it, but after lowering derefs
3306 * is too late to compact indices for that.
3307 */
3308 ctx->so->num_samp = util_last_bit(ctx->s->info.textures_used) + ctx->s->info.num_images;
3309
3310 /* NOTE: need to do something more clever when we support >1 fxn */
3311 nir_foreach_register (reg, &fxn->registers) {
3312 ir3_declare_array(ctx, reg);
3313 }
3314 /* And emit the body: */
3315 ctx->impl = fxn;
3316 emit_function(ctx, fxn);
3317 }
3318
3319 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3320 * need to assign the tex state indexes for these after we know the
3321 * max tex index.
3322 */
3323 static void
3324 fixup_astc_srgb(struct ir3_context *ctx)
3325 {
3326 struct ir3_shader_variant *so = ctx->so;
3327 /* indexed by original tex idx, value is newly assigned alpha sampler
3328 * state tex idx. Zero is invalid since there is at least one sampler
3329 * if we get here.
3330 */
3331 unsigned alt_tex_state[16] = {0};
3332 unsigned tex_idx = ctx->max_texture_index + 1;
3333 unsigned idx = 0;
3334
3335 so->astc_srgb.base = tex_idx;
3336
3337 for (unsigned i = 0; i < ctx->ir->astc_srgb_count; i++) {
3338 struct ir3_instruction *sam = ctx->ir->astc_srgb[i];
3339
3340 compile_assert(ctx, sam->cat5.tex < ARRAY_SIZE(alt_tex_state));
3341
3342 if (alt_tex_state[sam->cat5.tex] == 0) {
3343 /* assign new alternate/alpha tex state slot: */
3344 alt_tex_state[sam->cat5.tex] = tex_idx++;
3345 so->astc_srgb.orig_idx[idx++] = sam->cat5.tex;
3346 so->astc_srgb.count++;
3347 }
3348
3349 sam->cat5.tex = alt_tex_state[sam->cat5.tex];
3350 }
3351 }
3352
3353 static void
3354 fixup_binning_pass(struct ir3_context *ctx)
3355 {
3356 struct ir3_shader_variant *so = ctx->so;
3357 struct ir3 *ir = ctx->ir;
3358 unsigned i, j;
3359
3360 /* first pass, remove unused outputs from the IR level outputs: */
3361 for (i = 0, j = 0; i < ir->outputs_count; i++) {
3362 struct ir3_instruction *out = ir->outputs[i];
3363 assert(out->opc == OPC_META_COLLECT);
3364 unsigned outidx = out->collect.outidx;
3365 unsigned slot = so->outputs[outidx].slot;
3366
3367 /* throw away everything but first position/psize */
3368 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3369 ir->outputs[j] = ir->outputs[i];
3370 j++;
3371 }
3372 }
3373 ir->outputs_count = j;
3374
3375 /* second pass, cleanup the unused slots in ir3_shader_variant::outputs
3376 * table:
3377 */
3378 for (i = 0, j = 0; i < so->outputs_count; i++) {
3379 unsigned slot = so->outputs[i].slot;
3380
3381 /* throw away everything but first position/psize */
3382 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3383 so->outputs[j] = so->outputs[i];
3384
3385 /* fixup outidx to point to new output table entry: */
3386 foreach_output (out, ir) {
3387 if (out->collect.outidx == i) {
3388 out->collect.outidx = j;
3389 break;
3390 }
3391 }
3392
3393 j++;
3394 }
3395 }
3396 so->outputs_count = j;
3397 }
3398
3399 static void
3400 collect_tex_prefetches(struct ir3_context *ctx, struct ir3 *ir)
3401 {
3402 unsigned idx = 0;
3403
3404 /* Collect sampling instructions eligible for pre-dispatch. */
3405 foreach_block (block, &ir->block_list) {
3406 foreach_instr_safe (instr, &block->instr_list) {
3407 if (instr->opc == OPC_META_TEX_PREFETCH) {
3408 assert(idx < ARRAY_SIZE(ctx->so->sampler_prefetch));
3409 struct ir3_sampler_prefetch *fetch =
3410 &ctx->so->sampler_prefetch[idx];
3411 idx++;
3412
3413 if (instr->flags & IR3_INSTR_B) {
3414 fetch->cmd = IR3_SAMPLER_BINDLESS_PREFETCH_CMD;
3415 /* In bindless mode, the index is actually the base */
3416 fetch->tex_id = instr->prefetch.tex_base;
3417 fetch->samp_id = instr->prefetch.samp_base;
3418 fetch->tex_bindless_id = instr->prefetch.tex;
3419 fetch->samp_bindless_id = instr->prefetch.samp;
3420 } else {
3421 fetch->cmd = IR3_SAMPLER_PREFETCH_CMD;
3422 fetch->tex_id = instr->prefetch.tex;
3423 fetch->samp_id = instr->prefetch.samp;
3424 }
3425 fetch->wrmask = instr->regs[0]->wrmask;
3426 fetch->dst = instr->regs[0]->num;
3427 fetch->src = instr->prefetch.input_offset;
3428
3429 /* These are the limits on a5xx/a6xx, we might need to
3430 * revisit if SP_FS_PREFETCH[n] changes on later gens:
3431 */
3432 assert(fetch->dst <= 0x3f);
3433 assert(fetch->tex_id <= 0x1f);
3434 assert(fetch->samp_id < 0xf);
3435
3436 ctx->so->total_in =
3437 MAX2(ctx->so->total_in, instr->prefetch.input_offset + 2);
3438
3439 fetch->half_precision = !!(instr->regs[0]->flags & IR3_REG_HALF);
3440
3441 /* Remove the prefetch placeholder instruction: */
3442 list_delinit(&instr->node);
3443 }
3444 }
3445 }
3446 }
3447
3448 int
3449 ir3_compile_shader_nir(struct ir3_compiler *compiler,
3450 struct ir3_shader_variant *so)
3451 {
3452 struct ir3_context *ctx;
3453 struct ir3 *ir;
3454 int ret = 0, max_bary;
3455 bool progress;
3456
3457 assert(!so->ir);
3458
3459 ctx = ir3_context_init(compiler, so);
3460 if (!ctx) {
3461 DBG("INIT failed!");
3462 ret = -1;
3463 goto out;
3464 }
3465
3466 emit_instructions(ctx);
3467
3468 if (ctx->error) {
3469 DBG("EMIT failed!");
3470 ret = -1;
3471 goto out;
3472 }
3473
3474 ir = so->ir = ctx->ir;
3475
3476 assert((ctx->noutputs % 4) == 0);
3477
3478 /* Setup IR level outputs, which are "collects" that gather
3479 * the scalar components of outputs.
3480 */
3481 for (unsigned i = 0; i < ctx->noutputs; i += 4) {
3482 unsigned ncomp = 0;
3483 /* figure out the # of components written:
3484 *
3485 * TODO do we need to handle holes, ie. if .x and .z
3486 * components written, but .y component not written?
3487 */
3488 for (unsigned j = 0; j < 4; j++) {
3489 if (!ctx->outputs[i + j])
3490 break;
3491 ncomp++;
3492 }
3493
3494 /* Note that in some stages, like TCS, store_output is
3495 * lowered to memory writes, so no components of the
3496 * are "written" from the PoV of traditional store-
3497 * output instructions:
3498 */
3499 if (!ncomp)
3500 continue;
3501
3502 struct ir3_instruction *out =
3503 ir3_create_collect(ctx, &ctx->outputs[i], ncomp);
3504
3505 int outidx = i / 4;
3506 assert(outidx < so->outputs_count);
3507
3508 /* stash index into so->outputs[] so we can map the
3509 * output back to slot/etc later:
3510 */
3511 out->collect.outidx = outidx;
3512
3513 array_insert(ir, ir->outputs, out);
3514 }
3515
3516 /* Set up the gs header as an output for the vertex shader so it won't
3517 * clobber it for the tess ctrl shader.
3518 *
3519 * TODO this could probably be done more cleanly in a nir pass.
3520 */
3521 if (ctx->so->type == MESA_SHADER_VERTEX ||
3522 (ctx->so->key.has_gs && ctx->so->type == MESA_SHADER_TESS_EVAL)) {
3523 if (ctx->primitive_id) {
3524 unsigned n = so->outputs_count++;
3525 so->outputs[n].slot = VARYING_SLOT_PRIMITIVE_ID;
3526
3527 struct ir3_instruction *out =
3528 ir3_create_collect(ctx, &ctx->primitive_id, 1);
3529 out->collect.outidx = n;
3530 array_insert(ir, ir->outputs, out);
3531 }
3532
3533 if (ctx->gs_header) {
3534 unsigned n = so->outputs_count++;
3535 so->outputs[n].slot = VARYING_SLOT_GS_HEADER_IR3;
3536 struct ir3_instruction *out =
3537 ir3_create_collect(ctx, &ctx->gs_header, 1);
3538 out->collect.outidx = n;
3539 array_insert(ir, ir->outputs, out);
3540 }
3541
3542 if (ctx->tcs_header) {
3543 unsigned n = so->outputs_count++;
3544 so->outputs[n].slot = VARYING_SLOT_TCS_HEADER_IR3;
3545 struct ir3_instruction *out =
3546 ir3_create_collect(ctx, &ctx->tcs_header, 1);
3547 out->collect.outidx = n;
3548 array_insert(ir, ir->outputs, out);
3549 }
3550 }
3551
3552 /* for a6xx+, binning and draw pass VS use same VBO state, so we
3553 * need to make sure not to remove any inputs that are used by
3554 * the nonbinning VS.
3555 */
3556 if (ctx->compiler->gpu_id >= 600 && so->binning_pass &&
3557 so->type == MESA_SHADER_VERTEX) {
3558 for (int i = 0; i < ctx->ninputs; i++) {
3559 struct ir3_instruction *in = ctx->inputs[i];
3560
3561 if (!in)
3562 continue;
3563
3564 unsigned n = i / 4;
3565 unsigned c = i % 4;
3566
3567 debug_assert(n < so->nonbinning->inputs_count);
3568
3569 if (so->nonbinning->inputs[n].sysval)
3570 continue;
3571
3572 /* be sure to keep inputs, even if only used in VS */
3573 if (so->nonbinning->inputs[n].compmask & (1 << c))
3574 array_insert(in->block, in->block->keeps, in);
3575 }
3576 }
3577
3578 /* at this point, for binning pass, throw away unneeded outputs: */
3579 if (so->binning_pass && (ctx->compiler->gpu_id < 600))
3580 fixup_binning_pass(ctx);
3581
3582 ir3_debug_print(ir, "AFTER: nir->ir3");
3583 ir3_validate(ir);
3584
3585 do {
3586 progress = false;
3587
3588 progress |= IR3_PASS(ir, ir3_cf);
3589 progress |= IR3_PASS(ir, ir3_cp, so);
3590 progress |= IR3_PASS(ir, ir3_dce, so);
3591 } while (progress);
3592
3593 /* at this point, for binning pass, throw away unneeded outputs:
3594 * Note that for a6xx and later, we do this after ir3_cp to ensure
3595 * that the uniform/constant layout for BS and VS matches, so that
3596 * we can re-use same VS_CONST state group.
3597 */
3598 if (so->binning_pass && (ctx->compiler->gpu_id >= 600)) {
3599 fixup_binning_pass(ctx);
3600 /* cleanup the result of removing unneeded outputs: */
3601 while (IR3_PASS(ir, ir3_dce, so)) {}
3602 }
3603
3604 IR3_PASS(ir, ir3_sched_add_deps);
3605
3606 /* Group left/right neighbors, inserting mov's where needed to
3607 * solve conflicts:
3608 */
3609 IR3_PASS(ir, ir3_group);
3610
3611 /* At this point, all the dead code should be long gone: */
3612 assert(!IR3_PASS(ir, ir3_dce, so));
3613
3614 ret = ir3_sched(ir);
3615 if (ret) {
3616 DBG("SCHED failed!");
3617 goto out;
3618 }
3619
3620 ir3_debug_print(ir, "AFTER: ir3_sched");
3621
3622 if (IR3_PASS(ir, ir3_cp_postsched)) {
3623 /* cleanup the result of removing unneeded mov's: */
3624 while (IR3_PASS(ir, ir3_dce, so)) {}
3625 }
3626
3627 /* Pre-assign VS inputs on a6xx+ binning pass shader, to align
3628 * with draw pass VS, so binning and draw pass can both use the
3629 * same VBO state.
3630 *
3631 * Note that VS inputs are expected to be full precision.
3632 */
3633 bool pre_assign_inputs = (ir->compiler->gpu_id >= 600) &&
3634 (ir->type == MESA_SHADER_VERTEX) &&
3635 so->binning_pass;
3636
3637 if (pre_assign_inputs) {
3638 for (unsigned i = 0; i < ctx->ninputs; i++) {
3639 struct ir3_instruction *instr = ctx->inputs[i];
3640
3641 if (!instr)
3642 continue;
3643
3644 unsigned n = i / 4;
3645 unsigned c = i % 4;
3646 unsigned regid = so->nonbinning->inputs[n].regid + c;
3647
3648 instr->regs[0]->num = regid;
3649 }
3650
3651 ret = ir3_ra(so, ctx->inputs, ctx->ninputs);
3652 } else if (ctx->tcs_header) {
3653 /* We need to have these values in the same registers between VS and TCS
3654 * since the VS chains to TCS and doesn't get the sysvals redelivered.
3655 */
3656
3657 ctx->tcs_header->regs[0]->num = regid(0, 0);
3658 ctx->primitive_id->regs[0]->num = regid(0, 1);
3659 struct ir3_instruction *precolor[] = { ctx->tcs_header, ctx->primitive_id };
3660 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3661 } else if (ctx->gs_header) {
3662 /* We need to have these values in the same registers between producer
3663 * (VS or DS) and GS since the producer chains to GS and doesn't get
3664 * the sysvals redelivered.
3665 */
3666
3667 ctx->gs_header->regs[0]->num = regid(0, 0);
3668 ctx->primitive_id->regs[0]->num = regid(0, 1);
3669 struct ir3_instruction *precolor[] = { ctx->gs_header, ctx->primitive_id };
3670 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3671 } else if (so->num_sampler_prefetch) {
3672 assert(so->type == MESA_SHADER_FRAGMENT);
3673 struct ir3_instruction *precolor[2];
3674 int idx = 0;
3675
3676 foreach_input (instr, ir) {
3677 if (instr->input.sysval != SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL)
3678 continue;
3679
3680 assert(idx < ARRAY_SIZE(precolor));
3681
3682 precolor[idx] = instr;
3683 instr->regs[0]->num = idx;
3684
3685 idx++;
3686 }
3687 ret = ir3_ra(so, precolor, idx);
3688 } else {
3689 ret = ir3_ra(so, NULL, 0);
3690 }
3691
3692 if (ret) {
3693 DBG("RA failed!");
3694 goto out;
3695 }
3696
3697 IR3_PASS(ir, ir3_postsched, so);
3698
3699 if (compiler->gpu_id >= 600) {
3700 IR3_PASS(ir, ir3_a6xx_fixup_atomic_dests, so);
3701 }
3702
3703 if (so->type == MESA_SHADER_FRAGMENT)
3704 pack_inlocs(ctx);
3705
3706 /*
3707 * Fixup inputs/outputs to point to the actual registers assigned:
3708 *
3709 * 1) initialize to r63.x (invalid/unused)
3710 * 2) iterate IR level inputs/outputs and update the variants
3711 * inputs/outputs table based on the assigned registers for
3712 * the remaining inputs/outputs.
3713 */
3714
3715 for (unsigned i = 0; i < so->inputs_count; i++)
3716 so->inputs[i].regid = INVALID_REG;
3717 for (unsigned i = 0; i < so->outputs_count; i++)
3718 so->outputs[i].regid = INVALID_REG;
3719
3720 foreach_output (out, ir) {
3721 assert(out->opc == OPC_META_COLLECT);
3722 unsigned outidx = out->collect.outidx;
3723
3724 so->outputs[outidx].regid = out->regs[0]->num;
3725 so->outputs[outidx].half = !!(out->regs[0]->flags & IR3_REG_HALF);
3726 }
3727
3728 foreach_input (in, ir) {
3729 assert(in->opc == OPC_META_INPUT);
3730 unsigned inidx = in->input.inidx;
3731
3732 if (pre_assign_inputs && !so->inputs[inidx].sysval) {
3733 if (VALIDREG(so->nonbinning->inputs[inidx].regid)) {
3734 compile_assert(ctx, in->regs[0]->num ==
3735 so->nonbinning->inputs[inidx].regid);
3736 compile_assert(ctx, !!(in->regs[0]->flags & IR3_REG_HALF) ==
3737 so->nonbinning->inputs[inidx].half);
3738 }
3739 so->inputs[inidx].regid = so->nonbinning->inputs[inidx].regid;
3740 so->inputs[inidx].half = so->nonbinning->inputs[inidx].half;
3741 } else {
3742 so->inputs[inidx].regid = in->regs[0]->num;
3743 so->inputs[inidx].half = !!(in->regs[0]->flags & IR3_REG_HALF);
3744 }
3745 }
3746
3747 if (ctx->astc_srgb)
3748 fixup_astc_srgb(ctx);
3749
3750 /* We need to do legalize after (for frag shader's) the "bary.f"
3751 * offsets (inloc) have been assigned.
3752 */
3753 IR3_PASS(ir, ir3_legalize, so, &max_bary);
3754
3755 /* Set (ss)(sy) on first TCS and GEOMETRY instructions, since we don't
3756 * know what we might have to wait on when coming in from VS chsh.
3757 */
3758 if (so->type == MESA_SHADER_TESS_CTRL ||
3759 so->type == MESA_SHADER_GEOMETRY ) {
3760 foreach_block (block, &ir->block_list) {
3761 foreach_instr (instr, &block->instr_list) {
3762 instr->flags |= IR3_INSTR_SS | IR3_INSTR_SY;
3763 break;
3764 }
3765 }
3766 }
3767
3768 so->branchstack = ctx->max_stack;
3769
3770 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3771 if (so->type == MESA_SHADER_FRAGMENT)
3772 so->total_in = max_bary + 1;
3773
3774 /* Collect sampling instructions eligible for pre-dispatch. */
3775 collect_tex_prefetches(ctx, ir);
3776
3777 if (so->type == MESA_SHADER_FRAGMENT &&
3778 ctx->s->info.fs.needs_helper_invocations)
3779 so->need_pixlod = true;
3780
3781 out:
3782 if (ret) {
3783 if (so->ir)
3784 ir3_destroy(so->ir);
3785 so->ir = NULL;
3786 }
3787 ir3_context_free(ctx);
3788
3789 return ret;
3790 }