2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
38 #include "instr-a3xx.h"
40 #include "ir3_context.h"
43 static struct ir3_instruction
*
44 create_indirect_load(struct ir3_context
*ctx
, unsigned arrsz
, int n
,
45 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
47 struct ir3_block
*block
= ctx
->block
;
48 struct ir3_instruction
*mov
;
49 struct ir3_register
*src
;
51 mov
= ir3_instr_create(block
, OPC_MOV
);
52 mov
->cat1
.src_type
= TYPE_U32
;
53 mov
->cat1
.dst_type
= TYPE_U32
;
54 ir3_reg_create(mov
, 0, 0);
55 src
= ir3_reg_create(mov
, 0, IR3_REG_SSA
| IR3_REG_RELATIV
);
58 src
->array
.offset
= n
;
60 ir3_instr_set_address(mov
, address
);
65 static struct ir3_instruction
*
66 create_input_compmask(struct ir3_context
*ctx
, unsigned n
, unsigned compmask
)
68 struct ir3_instruction
*in
;
70 in
= ir3_instr_create(ctx
->in_block
, OPC_META_INPUT
);
71 in
->inout
.block
= ctx
->in_block
;
72 ir3_reg_create(in
, n
, 0);
74 in
->regs
[0]->wrmask
= compmask
;
79 static struct ir3_instruction
*
80 create_input(struct ir3_context
*ctx
, unsigned n
)
82 return create_input_compmask(ctx
, n
, 0x1);
85 static struct ir3_instruction
*
86 create_frag_input(struct ir3_context
*ctx
, bool use_ldlv
, unsigned n
)
88 struct ir3_block
*block
= ctx
->block
;
89 struct ir3_instruction
*instr
;
90 /* packed inloc is fixed up later: */
91 struct ir3_instruction
*inloc
= create_immed(block
, n
);
94 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
95 instr
->cat6
.type
= TYPE_U32
;
96 instr
->cat6
.iim_val
= 1;
98 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->ij_pixel
, 0);
99 instr
->regs
[2]->wrmask
= 0x3;
105 static struct ir3_instruction
*
106 create_driver_param(struct ir3_context
*ctx
, enum ir3_driver_param dp
)
108 /* first four vec4 sysval's reserved for UBOs: */
109 /* NOTE: dp is in scalar, but there can be >4 dp components: */
110 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
111 unsigned n
= const_state
->offsets
.driver_param
;
112 unsigned r
= regid(n
+ dp
/ 4, dp
% 4);
113 return create_uniform(ctx
->block
, r
);
117 * Adreno uses uint rather than having dedicated bool type,
118 * which (potentially) requires some conversion, in particular
119 * when using output of an bool instr to int input, or visa
123 * -------+---------+-------+-
127 * To convert from an adreno bool (uint) to nir, use:
129 * absneg.s dst, (neg)src
131 * To convert back in the other direction:
133 * absneg.s dst, (abs)arc
135 * The CP step can clean up the absneg.s that cancel each other
136 * out, and with a slight bit of extra cleverness (to recognize
137 * the instructions which produce either a 0 or 1) can eliminate
138 * the absneg.s's completely when an instruction that wants
139 * 0/1 consumes the result. For example, when a nir 'bcsel'
140 * consumes the result of 'feq'. So we should be able to get by
141 * without a boolean resolve step, and without incuring any
142 * extra penalty in instruction count.
145 /* NIR bool -> native (adreno): */
146 static struct ir3_instruction
*
147 ir3_b2n(struct ir3_block
*block
, struct ir3_instruction
*instr
)
149 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SABS
);
152 /* native (adreno) -> NIR bool: */
153 static struct ir3_instruction
*
154 ir3_n2b(struct ir3_block
*block
, struct ir3_instruction
*instr
)
156 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SNEG
);
160 * alu/sfu instructions:
163 static struct ir3_instruction
*
164 create_cov(struct ir3_context
*ctx
, struct ir3_instruction
*src
,
165 unsigned src_bitsize
, nir_op op
)
167 type_t src_type
, dst_type
;
171 case nir_op_f2f16_rtne
:
172 case nir_op_f2f16_rtz
:
180 switch (src_bitsize
) {
188 ir3_context_error(ctx
, "invalid src bit size: %u", src_bitsize
);
197 switch (src_bitsize
) {
208 ir3_context_error(ctx
, "invalid src bit size: %u", src_bitsize
);
217 switch (src_bitsize
) {
228 ir3_context_error(ctx
, "invalid src bit size: %u", src_bitsize
);
233 ir3_context_error(ctx
, "invalid conversion op: %u", op
);
243 case nir_op_f2f16_rtne
:
244 case nir_op_f2f16_rtz
:
246 /* TODO how to handle rounding mode? */
283 ir3_context_error(ctx
, "invalid conversion op: %u", op
);
286 return ir3_COV(ctx
->block
, src
, src_type
, dst_type
);
290 emit_alu(struct ir3_context
*ctx
, nir_alu_instr
*alu
)
292 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
293 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
294 unsigned bs
[info
->num_inputs
]; /* bit size */
295 struct ir3_block
*b
= ctx
->block
;
296 unsigned dst_sz
, wrmask
;
297 type_t dst_type
= nir_dest_bit_size(alu
->dest
.dest
) < 32 ?
300 if (alu
->dest
.dest
.is_ssa
) {
301 dst_sz
= alu
->dest
.dest
.ssa
.num_components
;
302 wrmask
= (1 << dst_sz
) - 1;
304 dst_sz
= alu
->dest
.dest
.reg
.reg
->num_components
;
305 wrmask
= alu
->dest
.write_mask
;
308 dst
= ir3_get_dst(ctx
, &alu
->dest
.dest
, dst_sz
);
310 /* Vectors are special in that they have non-scalarized writemasks,
311 * and just take the first swizzle channel for each argument in
312 * order into each writemask channel.
314 if ((alu
->op
== nir_op_vec2
) ||
315 (alu
->op
== nir_op_vec3
) ||
316 (alu
->op
== nir_op_vec4
)) {
318 for (int i
= 0; i
< info
->num_inputs
; i
++) {
319 nir_alu_src
*asrc
= &alu
->src
[i
];
321 compile_assert(ctx
, !asrc
->abs
);
322 compile_assert(ctx
, !asrc
->negate
);
324 src
[i
] = ir3_get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
326 src
[i
] = create_immed_typed(ctx
->block
, 0, dst_type
);
327 dst
[i
] = ir3_MOV(b
, src
[i
], dst_type
);
330 ir3_put_dst(ctx
, &alu
->dest
.dest
);
334 /* We also get mov's with more than one component for mov's so
335 * handle those specially:
337 if (alu
->op
== nir_op_mov
) {
338 nir_alu_src
*asrc
= &alu
->src
[0];
339 struct ir3_instruction
*const *src0
= ir3_get_src(ctx
, &asrc
->src
);
341 for (unsigned i
= 0; i
< dst_sz
; i
++) {
342 if (wrmask
& (1 << i
)) {
343 dst
[i
] = ir3_MOV(b
, src0
[asrc
->swizzle
[i
]], dst_type
);
349 ir3_put_dst(ctx
, &alu
->dest
.dest
);
353 /* General case: We can just grab the one used channel per src. */
354 for (int i
= 0; i
< info
->num_inputs
; i
++) {
355 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
356 nir_alu_src
*asrc
= &alu
->src
[i
];
358 compile_assert(ctx
, !asrc
->abs
);
359 compile_assert(ctx
, !asrc
->negate
);
361 src
[i
] = ir3_get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
362 bs
[i
] = nir_src_bit_size(asrc
->src
);
364 compile_assert(ctx
, src
[i
]);
369 case nir_op_f2f16_rtne
:
370 case nir_op_f2f16_rtz
:
388 dst
[0] = create_cov(ctx
, src
[0], bs
[0], alu
->op
);
391 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, create_immed(b
, fui(0.0)), 0);
392 dst
[0]->cat2
.condition
= IR3_COND_NE
;
393 dst
[0] = ir3_n2b(b
, dst
[0]);
396 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F16
);
399 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F32
);
404 dst
[0] = ir3_b2n(b
, src
[0]);
407 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
408 dst
[0]->cat2
.condition
= IR3_COND_NE
;
409 dst
[0] = ir3_n2b(b
, dst
[0]);
413 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
416 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
419 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
422 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
425 /* if there is just a single use of the src, and it supports
426 * (sat) bit, we can just fold the (sat) flag back to the
427 * src instruction and create a mov. This is easier for cp
430 * TODO probably opc_cat==4 is ok too
432 if (alu
->src
[0].src
.is_ssa
&&
433 (list_length(&alu
->src
[0].src
.ssa
->uses
) == 1) &&
434 ((opc_cat(src
[0]->opc
) == 2) || (opc_cat(src
[0]->opc
) == 3))) {
435 src
[0]->flags
|= IR3_INSTR_SAT
;
436 dst
[0] = ir3_MOV(b
, src
[0], dst_type
);
438 /* otherwise generate a max.f that saturates.. blob does
439 * similar (generating a cat2 mov using max.f)
441 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[0], 0);
442 dst
[0]->flags
|= IR3_INSTR_SAT
;
446 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
449 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
452 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
455 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
458 dst
[0] = ir3_DSX(b
, src
[0], 0);
459 dst
[0]->cat5
.type
= TYPE_F32
;
462 dst
[0] = ir3_DSY(b
, src
[0], 0);
463 dst
[0]->cat5
.type
= TYPE_F32
;
467 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
468 dst
[0]->cat2
.condition
= IR3_COND_LT
;
469 dst
[0] = ir3_n2b(b
, dst
[0]);
472 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
473 dst
[0]->cat2
.condition
= IR3_COND_GE
;
474 dst
[0] = ir3_n2b(b
, dst
[0]);
477 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
478 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
479 dst
[0] = ir3_n2b(b
, dst
[0]);
482 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
483 dst
[0]->cat2
.condition
= IR3_COND_NE
;
484 dst
[0] = ir3_n2b(b
, dst
[0]);
487 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
490 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
493 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
495 case nir_op_fround_even
:
496 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
499 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
503 dst
[0] = ir3_SIN(b
, src
[0], 0);
506 dst
[0] = ir3_COS(b
, src
[0], 0);
509 dst
[0] = ir3_RSQ(b
, src
[0], 0);
512 dst
[0] = ir3_RCP(b
, src
[0], 0);
515 dst
[0] = ir3_LOG2(b
, src
[0], 0);
518 dst
[0] = ir3_EXP2(b
, src
[0], 0);
521 dst
[0] = ir3_SQRT(b
, src
[0], 0);
525 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
528 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
531 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
534 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
537 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
540 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
543 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
545 case nir_op_umul_low
:
546 dst
[0] = ir3_MULL_U(b
, src
[0], 0, src
[1], 0);
548 case nir_op_imadsh_mix16
:
549 dst
[0] = ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0, src
[2], 0);
552 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
555 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
558 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
561 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
564 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
567 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
570 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
573 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
576 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
577 dst
[0]->cat2
.condition
= IR3_COND_LT
;
578 dst
[0] = ir3_n2b(b
, dst
[0]);
581 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
582 dst
[0]->cat2
.condition
= IR3_COND_GE
;
583 dst
[0] = ir3_n2b(b
, dst
[0]);
586 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
587 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
588 dst
[0] = ir3_n2b(b
, dst
[0]);
591 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
592 dst
[0]->cat2
.condition
= IR3_COND_NE
;
593 dst
[0] = ir3_n2b(b
, dst
[0]);
596 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
597 dst
[0]->cat2
.condition
= IR3_COND_LT
;
598 dst
[0] = ir3_n2b(b
, dst
[0]);
601 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
602 dst
[0]->cat2
.condition
= IR3_COND_GE
;
603 dst
[0] = ir3_n2b(b
, dst
[0]);
606 case nir_op_b32csel
: {
607 struct ir3_instruction
*cond
= ir3_b2n(b
, src
[0]);
608 compile_assert(ctx
, bs
[1] == bs
[2]);
609 /* the boolean condition is 32b even if src[1] and src[2] are
610 * half-precision, but sel.b16 wants all three src's to be the
614 cond
= ir3_COV(b
, cond
, TYPE_U32
, TYPE_U16
);
615 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, cond
, 0, src
[2], 0);
618 case nir_op_bit_count
: {
619 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
620 // double check on earlier gen's. Once half-precision support is
621 // in place, this should probably move to a NIR lowering pass:
622 struct ir3_instruction
*hi
, *lo
;
624 hi
= ir3_COV(b
, ir3_SHR_B(b
, src
[0], 0, create_immed(b
, 16), 0),
626 lo
= ir3_COV(b
, src
[0], TYPE_U32
, TYPE_U16
);
628 hi
= ir3_CBITS_B(b
, hi
, 0);
629 lo
= ir3_CBITS_B(b
, lo
, 0);
631 // TODO maybe the builders should default to making dst half-precision
632 // if the src's were half precision, to make this less awkward.. otoh
633 // we should probably just do this lowering in NIR.
634 hi
->regs
[0]->flags
|= IR3_REG_HALF
;
635 lo
->regs
[0]->flags
|= IR3_REG_HALF
;
637 dst
[0] = ir3_ADD_S(b
, hi
, 0, lo
, 0);
638 dst
[0]->regs
[0]->flags
|= IR3_REG_HALF
;
639 dst
[0] = ir3_COV(b
, dst
[0], TYPE_U16
, TYPE_U32
);
642 case nir_op_ifind_msb
: {
643 struct ir3_instruction
*cmp
;
644 dst
[0] = ir3_CLZ_S(b
, src
[0], 0);
645 cmp
= ir3_CMPS_S(b
, dst
[0], 0, create_immed(b
, 0), 0);
646 cmp
->cat2
.condition
= IR3_COND_GE
;
647 dst
[0] = ir3_SEL_B32(b
,
648 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
652 case nir_op_ufind_msb
:
653 dst
[0] = ir3_CLZ_B(b
, src
[0], 0);
654 dst
[0] = ir3_SEL_B32(b
,
655 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
656 src
[0], 0, dst
[0], 0);
658 case nir_op_find_lsb
:
659 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
660 dst
[0] = ir3_CLZ_B(b
, dst
[0], 0);
662 case nir_op_bitfield_reverse
:
663 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
667 ir3_context_error(ctx
, "Unhandled ALU op: %s\n",
668 nir_op_infos
[alu
->op
].name
);
672 ir3_put_dst(ctx
, &alu
->dest
.dest
);
675 /* handles direct/indirect UBO reads: */
677 emit_intrinsic_load_ubo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
678 struct ir3_instruction
**dst
)
680 struct ir3_block
*b
= ctx
->block
;
681 struct ir3_instruction
*base_lo
, *base_hi
, *addr
, *src0
, *src1
;
682 /* UBO addresses are the first driver params, but subtract 2 here to
683 * account for nir_lower_uniforms_to_ubo rebasing the UBOs such that UBO 0
684 * is the uniforms: */
685 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
686 unsigned ubo
= regid(const_state
->offsets
.ubo
, 0) - 2;
687 const unsigned ptrsz
= ir3_pointer_size(ctx
->compiler
);
691 /* First src is ubo index, which could either be an immed or not: */
692 src0
= ir3_get_src(ctx
, &intr
->src
[0])[0];
693 if (is_same_type_mov(src0
) &&
694 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
695 base_lo
= create_uniform(b
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
));
696 base_hi
= create_uniform(b
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
) + 1);
698 base_lo
= create_uniform_indirect(b
, ubo
, ir3_get_addr(ctx
, src0
, ptrsz
));
699 base_hi
= create_uniform_indirect(b
, ubo
+ 1, ir3_get_addr(ctx
, src0
, ptrsz
));
701 /* NOTE: since relative addressing is used, make sure constlen is
702 * at least big enough to cover all the UBO addresses, since the
703 * assembler won't know what the max address reg is.
705 ctx
->so
->constlen
= MAX2(ctx
->so
->constlen
,
706 const_state
->offsets
.ubo
+ (ctx
->s
->info
.num_ubos
* ptrsz
));
709 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
712 if (nir_src_is_const(intr
->src
[1])) {
713 off
+= nir_src_as_uint(intr
->src
[1]);
715 /* For load_ubo_indirect, second src is indirect offset: */
716 src1
= ir3_get_src(ctx
, &intr
->src
[1])[0];
718 /* and add offset to addr: */
719 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
722 /* if offset is to large to encode in the ldg, split it out: */
723 if ((off
+ (intr
->num_components
* 4)) > 1024) {
724 /* split out the minimal amount to improve the odds that
725 * cp can fit the immediate in the add.s instruction:
727 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
728 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
733 struct ir3_instruction
*carry
;
735 /* handle 32b rollover, ie:
736 * if (addr < base_lo)
739 carry
= ir3_CMPS_U(b
, addr
, 0, base_lo
, 0);
740 carry
->cat2
.condition
= IR3_COND_LT
;
741 base_hi
= ir3_ADD_S(b
, base_hi
, 0, carry
, 0);
743 addr
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){ addr
, base_hi
}, 2);
746 for (int i
= 0; i
< intr
->num_components
; i
++) {
747 struct ir3_instruction
*load
=
748 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0);
749 load
->cat6
.type
= TYPE_U32
;
750 load
->cat6
.src_offset
= off
+ i
* 4; /* byte offset */
755 /* src[] = { block_index } */
757 emit_intrinsic_ssbo_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
758 struct ir3_instruction
**dst
)
760 /* SSBO size stored as a const starting at ssbo_sizes: */
761 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
762 unsigned blk_idx
= nir_src_as_uint(intr
->src
[0]);
763 unsigned idx
= regid(const_state
->offsets
.ssbo_sizes
, 0) +
764 const_state
->ssbo_size
.off
[blk_idx
];
766 debug_assert(const_state
->ssbo_size
.mask
& (1 << blk_idx
));
768 dst
[0] = create_uniform(ctx
->block
, idx
);
771 /* src[] = { offset }. const_index[] = { base } */
773 emit_intrinsic_load_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
774 struct ir3_instruction
**dst
)
776 struct ir3_block
*b
= ctx
->block
;
777 struct ir3_instruction
*ldl
, *offset
;
780 offset
= ir3_get_src(ctx
, &intr
->src
[0])[0];
781 base
= nir_intrinsic_base(intr
);
783 ldl
= ir3_LDL(b
, offset
, 0, create_immed(b
, intr
->num_components
), 0);
784 ldl
->cat6
.src_offset
= base
;
785 ldl
->cat6
.type
= utype_dst(intr
->dest
);
786 ldl
->regs
[0]->wrmask
= MASK(intr
->num_components
);
788 ldl
->barrier_class
= IR3_BARRIER_SHARED_R
;
789 ldl
->barrier_conflict
= IR3_BARRIER_SHARED_W
;
791 ir3_split_dest(b
, dst
, ldl
, 0, intr
->num_components
);
794 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
796 emit_intrinsic_store_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
798 struct ir3_block
*b
= ctx
->block
;
799 struct ir3_instruction
*stl
, *offset
;
800 struct ir3_instruction
* const *value
;
801 unsigned base
, wrmask
;
803 value
= ir3_get_src(ctx
, &intr
->src
[0]);
804 offset
= ir3_get_src(ctx
, &intr
->src
[1])[0];
806 base
= nir_intrinsic_base(intr
);
807 wrmask
= nir_intrinsic_write_mask(intr
);
809 /* Combine groups of consecutive enabled channels in one write
810 * message. We use ffs to find the first enabled channel and then ffs on
811 * the bit-inverse, down-shifted writemask to determine the length of
812 * the block of enabled bits.
814 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
817 unsigned first_component
= ffs(wrmask
) - 1;
818 unsigned length
= ffs(~(wrmask
>> first_component
)) - 1;
820 stl
= ir3_STL(b
, offset
, 0,
821 ir3_create_collect(ctx
, &value
[first_component
], length
), 0,
822 create_immed(b
, length
), 0);
823 stl
->cat6
.dst_offset
= first_component
+ base
;
824 stl
->cat6
.type
= utype_src(intr
->src
[0]);
825 stl
->barrier_class
= IR3_BARRIER_SHARED_W
;
826 stl
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
828 array_insert(b
, b
->keeps
, stl
);
830 /* Clear the bits in the writemask that we just wrote, then try
831 * again to see if more channels are left.
833 wrmask
&= (15 << (first_component
+ length
));
838 * CS shared variable atomic intrinsics
840 * All of the shared variable atomic memory operations read a value from
841 * memory, compute a new value using one of the operations below, write the
842 * new value to memory, and return the original value read.
844 * All operations take 2 sources except CompSwap that takes 3. These
847 * 0: The offset into the shared variable storage region that the atomic
848 * operation will operate on.
849 * 1: The data parameter to the atomic function (i.e. the value to add
850 * in shared_atomic_add, etc).
851 * 2: For CompSwap only: the second data parameter.
853 static struct ir3_instruction
*
854 emit_intrinsic_atomic_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
856 struct ir3_block
*b
= ctx
->block
;
857 struct ir3_instruction
*atomic
, *src0
, *src1
;
858 type_t type
= TYPE_U32
;
860 src0
= ir3_get_src(ctx
, &intr
->src
[0])[0]; /* offset */
861 src1
= ir3_get_src(ctx
, &intr
->src
[1])[0]; /* value */
863 switch (intr
->intrinsic
) {
864 case nir_intrinsic_shared_atomic_add
:
865 atomic
= ir3_ATOMIC_ADD(b
, src0
, 0, src1
, 0);
867 case nir_intrinsic_shared_atomic_imin
:
868 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
871 case nir_intrinsic_shared_atomic_umin
:
872 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
874 case nir_intrinsic_shared_atomic_imax
:
875 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
878 case nir_intrinsic_shared_atomic_umax
:
879 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
881 case nir_intrinsic_shared_atomic_and
:
882 atomic
= ir3_ATOMIC_AND(b
, src0
, 0, src1
, 0);
884 case nir_intrinsic_shared_atomic_or
:
885 atomic
= ir3_ATOMIC_OR(b
, src0
, 0, src1
, 0);
887 case nir_intrinsic_shared_atomic_xor
:
888 atomic
= ir3_ATOMIC_XOR(b
, src0
, 0, src1
, 0);
890 case nir_intrinsic_shared_atomic_exchange
:
891 atomic
= ir3_ATOMIC_XCHG(b
, src0
, 0, src1
, 0);
893 case nir_intrinsic_shared_atomic_comp_swap
:
894 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
895 src1
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
896 ir3_get_src(ctx
, &intr
->src
[2])[0],
899 atomic
= ir3_ATOMIC_CMPXCHG(b
, src0
, 0, src1
, 0);
905 atomic
->cat6
.iim_val
= 1;
907 atomic
->cat6
.type
= type
;
908 atomic
->barrier_class
= IR3_BARRIER_SHARED_W
;
909 atomic
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
911 /* even if nothing consume the result, we can't DCE the instruction: */
912 array_insert(b
, b
->keeps
, atomic
);
917 /* TODO handle actual indirect/dynamic case.. which is going to be weird
918 * to handle with the image_mapping table..
920 static struct ir3_instruction
*
921 get_image_samp_tex_src(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
923 unsigned slot
= ir3_get_image_slot(nir_src_as_deref(intr
->src
[0]));
924 unsigned tex_idx
= ir3_image_to_tex(&ctx
->so
->image_mapping
, slot
);
925 struct ir3_instruction
*texture
, *sampler
;
927 texture
= create_immed_typed(ctx
->block
, tex_idx
, TYPE_U16
);
928 sampler
= create_immed_typed(ctx
->block
, tex_idx
, TYPE_U16
);
930 return ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
936 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
938 emit_intrinsic_load_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
939 struct ir3_instruction
**dst
)
941 struct ir3_block
*b
= ctx
->block
;
942 const nir_variable
*var
= nir_intrinsic_get_var(intr
, 0);
943 struct ir3_instruction
*samp_tex
= get_image_samp_tex_src(ctx
, intr
);
944 struct ir3_instruction
*sam
;
945 struct ir3_instruction
* const *src0
= ir3_get_src(ctx
, &intr
->src
[1]);
946 struct ir3_instruction
*coords
[4];
947 unsigned flags
, ncoords
= ir3_get_image_coords(var
, &flags
);
948 type_t type
= ir3_get_image_type(var
);
950 /* hmm, this seems a bit odd, but it is what blob does and (at least
951 * a5xx) just faults on bogus addresses otherwise:
953 if (flags
& IR3_INSTR_3D
) {
954 flags
&= ~IR3_INSTR_3D
;
955 flags
|= IR3_INSTR_A
;
958 for (unsigned i
= 0; i
< ncoords
; i
++)
962 coords
[ncoords
++] = create_immed(b
, 0);
964 sam
= ir3_SAM(b
, OPC_ISAM
, type
, 0b1111, flags
,
965 samp_tex
, ir3_create_collect(ctx
, coords
, ncoords
), NULL
);
967 sam
->barrier_class
= IR3_BARRIER_IMAGE_R
;
968 sam
->barrier_conflict
= IR3_BARRIER_IMAGE_W
;
970 ir3_split_dest(b
, dst
, sam
, 0, 4);
974 emit_intrinsic_image_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
975 struct ir3_instruction
**dst
)
977 struct ir3_block
*b
= ctx
->block
;
978 const nir_variable
*var
= nir_intrinsic_get_var(intr
, 0);
979 struct ir3_instruction
*samp_tex
= get_image_samp_tex_src(ctx
, intr
);
980 struct ir3_instruction
*sam
, *lod
;
981 unsigned flags
, ncoords
= ir3_get_image_coords(var
, &flags
);
983 lod
= create_immed(b
, 0);
984 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, 0b1111, flags
,
985 samp_tex
, lod
, NULL
);
987 /* Array size actually ends up in .w rather than .z. This doesn't
988 * matter for miplevel 0, but for higher mips the value in z is
989 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
990 * returned, which means that we have to add 1 to it for arrays for
993 * Note use a temporary dst and then copy, since the size of the dst
994 * array that is passed in is based on nir's understanding of the
995 * result size, not the hardware's
997 struct ir3_instruction
*tmp
[4];
999 ir3_split_dest(b
, tmp
, sam
, 0, 4);
1001 /* get_size instruction returns size in bytes instead of texels
1002 * for imageBuffer, so we need to divide it by the pixel size
1003 * of the image format.
1005 * TODO: This is at least true on a5xx. Check other gens.
1007 enum glsl_sampler_dim dim
=
1008 glsl_get_sampler_dim(glsl_without_array(var
->type
));
1009 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
1010 /* Since all the possible values the divisor can take are
1011 * power-of-two (4, 8, or 16), the division is implemented
1013 * During shader setup, the log2 of the image format's
1014 * bytes-per-pixel should have been emitted in 2nd slot of
1015 * image_dims. See ir3_shader::emit_image_dims().
1017 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
1018 unsigned cb
= regid(const_state
->offsets
.image_dims
, 0) +
1019 const_state
->image_dims
.off
[var
->data
.driver_location
];
1020 struct ir3_instruction
*aux
= create_uniform(b
, cb
+ 1);
1022 tmp
[0] = ir3_SHR_B(b
, tmp
[0], 0, aux
, 0);
1025 for (unsigned i
= 0; i
< ncoords
; i
++)
1028 if (flags
& IR3_INSTR_A
) {
1029 if (ctx
->compiler
->levels_add_one
) {
1030 dst
[ncoords
-1] = ir3_ADD_U(b
, tmp
[3], 0, create_immed(b
, 1), 0);
1032 dst
[ncoords
-1] = ir3_MOV(b
, tmp
[3], TYPE_U32
);
1038 emit_intrinsic_barrier(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1040 struct ir3_block
*b
= ctx
->block
;
1041 struct ir3_instruction
*barrier
;
1043 switch (intr
->intrinsic
) {
1044 case nir_intrinsic_barrier
:
1045 barrier
= ir3_BAR(b
);
1046 barrier
->cat7
.g
= true;
1047 barrier
->cat7
.l
= true;
1048 barrier
->flags
= IR3_INSTR_SS
| IR3_INSTR_SY
;
1049 barrier
->barrier_class
= IR3_BARRIER_EVERYTHING
;
1051 case nir_intrinsic_memory_barrier
:
1052 barrier
= ir3_FENCE(b
);
1053 barrier
->cat7
.g
= true;
1054 barrier
->cat7
.r
= true;
1055 barrier
->cat7
.w
= true;
1056 barrier
->cat7
.l
= true;
1057 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
|
1058 IR3_BARRIER_BUFFER_W
;
1059 barrier
->barrier_conflict
=
1060 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
1061 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1063 case nir_intrinsic_memory_barrier_atomic_counter
:
1064 case nir_intrinsic_memory_barrier_buffer
:
1065 barrier
= ir3_FENCE(b
);
1066 barrier
->cat7
.g
= true;
1067 barrier
->cat7
.r
= true;
1068 barrier
->cat7
.w
= true;
1069 barrier
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1070 barrier
->barrier_conflict
= IR3_BARRIER_BUFFER_R
|
1071 IR3_BARRIER_BUFFER_W
;
1073 case nir_intrinsic_memory_barrier_image
:
1074 // TODO double check if this should have .g set
1075 barrier
= ir3_FENCE(b
);
1076 barrier
->cat7
.g
= true;
1077 barrier
->cat7
.r
= true;
1078 barrier
->cat7
.w
= true;
1079 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
;
1080 barrier
->barrier_conflict
= IR3_BARRIER_IMAGE_R
|
1081 IR3_BARRIER_IMAGE_W
;
1083 case nir_intrinsic_memory_barrier_shared
:
1084 barrier
= ir3_FENCE(b
);
1085 barrier
->cat7
.g
= true;
1086 barrier
->cat7
.l
= true;
1087 barrier
->cat7
.r
= true;
1088 barrier
->cat7
.w
= true;
1089 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
;
1090 barrier
->barrier_conflict
= IR3_BARRIER_SHARED_R
|
1091 IR3_BARRIER_SHARED_W
;
1093 case nir_intrinsic_group_memory_barrier
:
1094 barrier
= ir3_FENCE(b
);
1095 barrier
->cat7
.g
= true;
1096 barrier
->cat7
.l
= true;
1097 barrier
->cat7
.r
= true;
1098 barrier
->cat7
.w
= true;
1099 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
|
1100 IR3_BARRIER_IMAGE_W
|
1101 IR3_BARRIER_BUFFER_W
;
1102 barrier
->barrier_conflict
=
1103 IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
|
1104 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
1105 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1111 /* make sure barrier doesn't get DCE'd */
1112 array_insert(b
, b
->keeps
, barrier
);
1115 static void add_sysval_input_compmask(struct ir3_context
*ctx
,
1116 gl_system_value slot
, unsigned compmask
,
1117 struct ir3_instruction
*instr
)
1119 struct ir3_shader_variant
*so
= ctx
->so
;
1120 unsigned r
= regid(so
->inputs_count
, 0);
1121 unsigned n
= so
->inputs_count
++;
1123 so
->inputs
[n
].sysval
= true;
1124 so
->inputs
[n
].slot
= slot
;
1125 so
->inputs
[n
].compmask
= compmask
;
1126 so
->inputs
[n
].regid
= r
;
1127 so
->inputs
[n
].interpolate
= INTERP_MODE_FLAT
;
1130 ctx
->ir
->ninputs
= MAX2(ctx
->ir
->ninputs
, r
+ 1);
1131 ctx
->ir
->inputs
[r
] = instr
;
1134 static void add_sysval_input(struct ir3_context
*ctx
, gl_system_value slot
,
1135 struct ir3_instruction
*instr
)
1137 add_sysval_input_compmask(ctx
, slot
, 0x1, instr
);
1140 static struct ir3_instruction
*
1141 get_barycentric_centroid(struct ir3_context
*ctx
)
1143 if (!ctx
->ij_centroid
) {
1144 struct ir3_instruction
*xy
[2];
1145 struct ir3_instruction
*ij
;
1147 ij
= create_input_compmask(ctx
, 0, 0x3);
1148 ir3_split_dest(ctx
->block
, xy
, ij
, 0, 2);
1150 ctx
->ij_centroid
= ir3_create_collect(ctx
, xy
, 2);
1152 add_sysval_input_compmask(ctx
,
1153 SYSTEM_VALUE_BARYCENTRIC_CENTROID
,
1157 return ctx
->ij_centroid
;
1160 static struct ir3_instruction
*
1161 get_barycentric_sample(struct ir3_context
*ctx
)
1163 if (!ctx
->ij_sample
) {
1164 struct ir3_instruction
*xy
[2];
1165 struct ir3_instruction
*ij
;
1167 ij
= create_input_compmask(ctx
, 0, 0x3);
1168 ir3_split_dest(ctx
->block
, xy
, ij
, 0, 2);
1170 ctx
->ij_sample
= ir3_create_collect(ctx
, xy
, 2);
1172 add_sysval_input_compmask(ctx
,
1173 SYSTEM_VALUE_BARYCENTRIC_SAMPLE
,
1177 return ctx
->ij_sample
;
1180 static struct ir3_instruction
*
1181 get_barycentric_pixel(struct ir3_context
*ctx
)
1183 /* TODO when tgsi_to_nir supports "new-style" FS inputs switch
1184 * this to create ij_pixel only on demand:
1186 return ctx
->ij_pixel
;
1189 static struct ir3_instruction
*
1190 get_frag_coord(struct ir3_context
*ctx
)
1192 if (!ctx
->frag_coord
) {
1193 struct ir3_block
*b
= ctx
->block
;
1194 struct ir3_instruction
*xyzw
[4];
1195 struct ir3_instruction
*hw_frag_coord
;
1197 hw_frag_coord
= create_input_compmask(ctx
, 0, 0xf);
1198 ir3_split_dest(ctx
->block
, xyzw
, hw_frag_coord
, 0, 4);
1200 /* for frag_coord.xy, we get unsigned values.. we need
1201 * to subtract (integer) 8 and divide by 16 (right-
1202 * shift by 4) then convert to float:
1206 * mov.u32f32 dst, tmp
1209 for (int i
= 0; i
< 2; i
++) {
1210 xyzw
[i
] = ir3_SUB_S(b
, xyzw
[i
], 0,
1211 create_immed(b
, 8), 0);
1212 xyzw
[i
] = ir3_SHR_B(b
, xyzw
[i
], 0,
1213 create_immed(b
, 4), 0);
1214 xyzw
[i
] = ir3_COV(b
, xyzw
[i
], TYPE_U32
, TYPE_F32
);
1217 ctx
->frag_coord
= ir3_create_collect(ctx
, xyzw
, 4);
1219 add_sysval_input_compmask(ctx
,
1220 SYSTEM_VALUE_FRAG_COORD
,
1221 0xf, hw_frag_coord
);
1223 ctx
->so
->frag_coord
= true;
1226 return ctx
->frag_coord
;
1230 emit_intrinsic(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1232 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
1233 struct ir3_instruction
**dst
;
1234 struct ir3_instruction
* const *src
;
1235 struct ir3_block
*b
= ctx
->block
;
1238 if (info
->has_dest
) {
1239 unsigned n
= nir_intrinsic_dest_components(intr
);
1240 dst
= ir3_get_dst(ctx
, &intr
->dest
, n
);
1245 switch (intr
->intrinsic
) {
1246 case nir_intrinsic_load_uniform
:
1247 idx
= nir_intrinsic_base(intr
);
1248 if (nir_src_is_const(intr
->src
[0])) {
1249 idx
+= nir_src_as_uint(intr
->src
[0]);
1250 for (int i
= 0; i
< intr
->num_components
; i
++) {
1251 dst
[i
] = create_uniform_typed(b
, idx
+ i
,
1252 nir_dest_bit_size(intr
->dest
) < 32 ? TYPE_F16
: TYPE_F32
);
1255 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1256 for (int i
= 0; i
< intr
->num_components
; i
++) {
1257 dst
[i
] = create_uniform_indirect(b
, idx
+ i
,
1258 ir3_get_addr(ctx
, src
[0], 1));
1260 /* NOTE: if relative addressing is used, we set
1261 * constlen in the compiler (to worst-case value)
1262 * since we don't know in the assembler what the max
1263 * addr reg value can be:
1265 ctx
->so
->constlen
= MAX2(ctx
->so
->constlen
,
1266 ctx
->so
->shader
->ubo_state
.size
/ 16);
1269 case nir_intrinsic_load_ubo
:
1270 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
1272 case nir_intrinsic_load_frag_coord
:
1273 ir3_split_dest(b
, dst
, get_frag_coord(ctx
), 0, 4);
1275 case nir_intrinsic_load_sample_pos_from_id
: {
1276 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
1277 * but that doesn't seem necessary.
1279 struct ir3_instruction
*offset
=
1280 ir3_RGETPOS(b
, ir3_get_src(ctx
, &intr
->src
[0])[0], 0);
1281 offset
->regs
[0]->wrmask
= 0x3;
1282 offset
->cat5
.type
= TYPE_F32
;
1284 ir3_split_dest(b
, dst
, offset
, 0, 2);
1288 case nir_intrinsic_load_size_ir3
:
1289 if (!ctx
->ij_size
) {
1290 ctx
->ij_size
= create_input(ctx
, 0);
1292 add_sysval_input(ctx
, SYSTEM_VALUE_BARYCENTRIC_SIZE
,
1295 dst
[0] = ctx
->ij_size
;
1297 case nir_intrinsic_load_barycentric_centroid
:
1298 ir3_split_dest(b
, dst
, get_barycentric_centroid(ctx
), 0, 2);
1300 case nir_intrinsic_load_barycentric_sample
:
1301 if (ctx
->so
->key
.msaa
) {
1302 ir3_split_dest(b
, dst
, get_barycentric_sample(ctx
), 0, 2);
1304 ir3_split_dest(b
, dst
, get_barycentric_pixel(ctx
), 0, 2);
1307 case nir_intrinsic_load_barycentric_pixel
:
1308 ir3_split_dest(b
, dst
, get_barycentric_pixel(ctx
), 0, 2);
1310 case nir_intrinsic_load_interpolated_input
:
1311 idx
= nir_intrinsic_base(intr
);
1312 comp
= nir_intrinsic_component(intr
);
1313 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1314 if (nir_src_is_const(intr
->src
[1])) {
1315 struct ir3_instruction
*coord
= ir3_create_collect(ctx
, src
, 2);
1316 idx
+= nir_src_as_uint(intr
->src
[1]);
1317 for (int i
= 0; i
< intr
->num_components
; i
++) {
1318 unsigned inloc
= idx
* 4 + i
+ comp
;
1319 if (ctx
->so
->inputs
[idx
].bary
&&
1320 !ctx
->so
->inputs
[idx
].use_ldlv
) {
1321 dst
[i
] = ir3_BARY_F(b
, create_immed(b
, inloc
), 0, coord
, 0);
1323 /* for non-varyings use the pre-setup input, since
1324 * that is easier than mapping things back to a
1325 * nir_variable to figure out what it is.
1327 dst
[i
] = ctx
->ir
->inputs
[inloc
];
1331 ir3_context_error(ctx
, "unhandled");
1334 case nir_intrinsic_load_input
:
1335 idx
= nir_intrinsic_base(intr
);
1336 comp
= nir_intrinsic_component(intr
);
1337 if (nir_src_is_const(intr
->src
[0])) {
1338 idx
+= nir_src_as_uint(intr
->src
[0]);
1339 for (int i
= 0; i
< intr
->num_components
; i
++) {
1340 unsigned n
= idx
* 4 + i
+ comp
;
1341 dst
[i
] = ctx
->ir
->inputs
[n
];
1342 compile_assert(ctx
, ctx
->ir
->inputs
[n
]);
1345 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1346 struct ir3_instruction
*collect
=
1347 ir3_create_collect(ctx
, ctx
->ir
->inputs
, ctx
->ir
->ninputs
);
1348 struct ir3_instruction
*addr
= ir3_get_addr(ctx
, src
[0], 4);
1349 for (int i
= 0; i
< intr
->num_components
; i
++) {
1350 unsigned n
= idx
* 4 + i
+ comp
;
1351 dst
[i
] = create_indirect_load(ctx
, ctx
->ir
->ninputs
,
1356 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1357 * pass and replaced by an ir3-specifc version that adds the
1358 * dword-offset in the last source.
1360 case nir_intrinsic_load_ssbo_ir3
:
1361 ctx
->funcs
->emit_intrinsic_load_ssbo(ctx
, intr
, dst
);
1363 case nir_intrinsic_store_ssbo_ir3
:
1364 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1365 !ctx
->s
->info
.fs
.early_fragment_tests
)
1366 ctx
->so
->no_earlyz
= true;
1367 ctx
->funcs
->emit_intrinsic_store_ssbo(ctx
, intr
);
1369 case nir_intrinsic_get_buffer_size
:
1370 emit_intrinsic_ssbo_size(ctx
, intr
, dst
);
1372 case nir_intrinsic_ssbo_atomic_add_ir3
:
1373 case nir_intrinsic_ssbo_atomic_imin_ir3
:
1374 case nir_intrinsic_ssbo_atomic_umin_ir3
:
1375 case nir_intrinsic_ssbo_atomic_imax_ir3
:
1376 case nir_intrinsic_ssbo_atomic_umax_ir3
:
1377 case nir_intrinsic_ssbo_atomic_and_ir3
:
1378 case nir_intrinsic_ssbo_atomic_or_ir3
:
1379 case nir_intrinsic_ssbo_atomic_xor_ir3
:
1380 case nir_intrinsic_ssbo_atomic_exchange_ir3
:
1381 case nir_intrinsic_ssbo_atomic_comp_swap_ir3
:
1382 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1383 !ctx
->s
->info
.fs
.early_fragment_tests
)
1384 ctx
->so
->no_earlyz
= true;
1385 dst
[0] = ctx
->funcs
->emit_intrinsic_atomic_ssbo(ctx
, intr
);
1387 case nir_intrinsic_load_shared
:
1388 emit_intrinsic_load_shared(ctx
, intr
, dst
);
1390 case nir_intrinsic_store_shared
:
1391 emit_intrinsic_store_shared(ctx
, intr
);
1393 case nir_intrinsic_shared_atomic_add
:
1394 case nir_intrinsic_shared_atomic_imin
:
1395 case nir_intrinsic_shared_atomic_umin
:
1396 case nir_intrinsic_shared_atomic_imax
:
1397 case nir_intrinsic_shared_atomic_umax
:
1398 case nir_intrinsic_shared_atomic_and
:
1399 case nir_intrinsic_shared_atomic_or
:
1400 case nir_intrinsic_shared_atomic_xor
:
1401 case nir_intrinsic_shared_atomic_exchange
:
1402 case nir_intrinsic_shared_atomic_comp_swap
:
1403 dst
[0] = emit_intrinsic_atomic_shared(ctx
, intr
);
1405 case nir_intrinsic_image_deref_load
:
1406 emit_intrinsic_load_image(ctx
, intr
, dst
);
1408 case nir_intrinsic_image_deref_store
:
1409 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1410 !ctx
->s
->info
.fs
.early_fragment_tests
)
1411 ctx
->so
->no_earlyz
= true;
1412 ctx
->funcs
->emit_intrinsic_store_image(ctx
, intr
);
1414 case nir_intrinsic_image_deref_size
:
1415 emit_intrinsic_image_size(ctx
, intr
, dst
);
1417 case nir_intrinsic_image_deref_atomic_add
:
1418 case nir_intrinsic_image_deref_atomic_min
:
1419 case nir_intrinsic_image_deref_atomic_max
:
1420 case nir_intrinsic_image_deref_atomic_and
:
1421 case nir_intrinsic_image_deref_atomic_or
:
1422 case nir_intrinsic_image_deref_atomic_xor
:
1423 case nir_intrinsic_image_deref_atomic_exchange
:
1424 case nir_intrinsic_image_deref_atomic_comp_swap
:
1425 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1426 !ctx
->s
->info
.fs
.early_fragment_tests
)
1427 ctx
->so
->no_earlyz
= true;
1428 dst
[0] = ctx
->funcs
->emit_intrinsic_atomic_image(ctx
, intr
);
1430 case nir_intrinsic_barrier
:
1431 case nir_intrinsic_memory_barrier
:
1432 case nir_intrinsic_group_memory_barrier
:
1433 case nir_intrinsic_memory_barrier_atomic_counter
:
1434 case nir_intrinsic_memory_barrier_buffer
:
1435 case nir_intrinsic_memory_barrier_image
:
1436 case nir_intrinsic_memory_barrier_shared
:
1437 emit_intrinsic_barrier(ctx
, intr
);
1438 /* note that blk ptr no longer valid, make that obvious: */
1441 case nir_intrinsic_store_output
:
1442 idx
= nir_intrinsic_base(intr
);
1443 comp
= nir_intrinsic_component(intr
);
1444 compile_assert(ctx
, nir_src_is_const(intr
->src
[1]));
1445 idx
+= nir_src_as_uint(intr
->src
[1]);
1447 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1448 for (int i
= 0; i
< intr
->num_components
; i
++) {
1449 unsigned n
= idx
* 4 + i
+ comp
;
1450 ctx
->ir
->outputs
[n
] = src
[i
];
1453 case nir_intrinsic_load_base_vertex
:
1454 case nir_intrinsic_load_first_vertex
:
1455 if (!ctx
->basevertex
) {
1456 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
1457 add_sysval_input(ctx
, SYSTEM_VALUE_FIRST_VERTEX
, ctx
->basevertex
);
1459 dst
[0] = ctx
->basevertex
;
1461 case nir_intrinsic_load_vertex_id_zero_base
:
1462 case nir_intrinsic_load_vertex_id
:
1463 if (!ctx
->vertex_id
) {
1464 gl_system_value sv
= (intr
->intrinsic
== nir_intrinsic_load_vertex_id
) ?
1465 SYSTEM_VALUE_VERTEX_ID
: SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
;
1466 ctx
->vertex_id
= create_input(ctx
, 0);
1467 add_sysval_input(ctx
, sv
, ctx
->vertex_id
);
1469 dst
[0] = ctx
->vertex_id
;
1471 case nir_intrinsic_load_instance_id
:
1472 if (!ctx
->instance_id
) {
1473 ctx
->instance_id
= create_input(ctx
, 0);
1474 add_sysval_input(ctx
, SYSTEM_VALUE_INSTANCE_ID
,
1477 dst
[0] = ctx
->instance_id
;
1479 case nir_intrinsic_load_sample_id
:
1480 ctx
->so
->per_samp
= true;
1482 case nir_intrinsic_load_sample_id_no_per_sample
:
1483 if (!ctx
->samp_id
) {
1484 ctx
->samp_id
= create_input(ctx
, 0);
1485 ctx
->samp_id
->regs
[0]->flags
|= IR3_REG_HALF
;
1486 add_sysval_input(ctx
, SYSTEM_VALUE_SAMPLE_ID
,
1489 dst
[0] = ir3_COV(b
, ctx
->samp_id
, TYPE_U16
, TYPE_U32
);
1491 case nir_intrinsic_load_sample_mask_in
:
1492 if (!ctx
->samp_mask_in
) {
1493 ctx
->samp_mask_in
= create_input(ctx
, 0);
1494 add_sysval_input(ctx
, SYSTEM_VALUE_SAMPLE_MASK_IN
,
1497 dst
[0] = ctx
->samp_mask_in
;
1499 case nir_intrinsic_load_user_clip_plane
:
1500 idx
= nir_intrinsic_ucp_id(intr
);
1501 for (int i
= 0; i
< intr
->num_components
; i
++) {
1502 unsigned n
= idx
* 4 + i
;
1503 dst
[i
] = create_driver_param(ctx
, IR3_DP_UCP0_X
+ n
);
1506 case nir_intrinsic_load_front_face
:
1507 if (!ctx
->frag_face
) {
1508 ctx
->so
->frag_face
= true;
1509 ctx
->frag_face
= create_input(ctx
, 0);
1510 add_sysval_input(ctx
, SYSTEM_VALUE_FRONT_FACE
, ctx
->frag_face
);
1511 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
1513 /* for fragface, we get -1 for back and 0 for front. However this is
1514 * the inverse of what nir expects (where ~0 is true).
1516 dst
[0] = ir3_COV(b
, ctx
->frag_face
, TYPE_S16
, TYPE_S32
);
1517 dst
[0] = ir3_NOT_B(b
, dst
[0], 0);
1519 case nir_intrinsic_load_local_invocation_id
:
1520 if (!ctx
->local_invocation_id
) {
1521 ctx
->local_invocation_id
= create_input_compmask(ctx
, 0, 0x7);
1522 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
,
1523 0x7, ctx
->local_invocation_id
);
1525 ir3_split_dest(b
, dst
, ctx
->local_invocation_id
, 0, 3);
1527 case nir_intrinsic_load_work_group_id
:
1528 if (!ctx
->work_group_id
) {
1529 ctx
->work_group_id
= create_input_compmask(ctx
, 0, 0x7);
1530 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_WORK_GROUP_ID
,
1531 0x7, ctx
->work_group_id
);
1532 ctx
->work_group_id
->regs
[0]->flags
|= IR3_REG_HIGH
;
1534 ir3_split_dest(b
, dst
, ctx
->work_group_id
, 0, 3);
1536 case nir_intrinsic_load_num_work_groups
:
1537 for (int i
= 0; i
< intr
->num_components
; i
++) {
1538 dst
[i
] = create_driver_param(ctx
, IR3_DP_NUM_WORK_GROUPS_X
+ i
);
1541 case nir_intrinsic_load_local_group_size
:
1542 for (int i
= 0; i
< intr
->num_components
; i
++) {
1543 dst
[i
] = create_driver_param(ctx
, IR3_DP_LOCAL_GROUP_SIZE_X
+ i
);
1546 case nir_intrinsic_discard_if
:
1547 case nir_intrinsic_discard
: {
1548 struct ir3_instruction
*cond
, *kill
;
1550 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
1551 /* conditional discard: */
1552 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1553 cond
= ir3_b2n(b
, src
[0]);
1555 /* unconditional discard: */
1556 cond
= create_immed(b
, 1);
1559 /* NOTE: only cmps.*.* can write p0.x: */
1560 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
1561 cond
->cat2
.condition
= IR3_COND_NE
;
1563 /* condition always goes in predicate register: */
1564 cond
->regs
[0]->num
= regid(REG_P0
, 0);
1566 kill
= ir3_KILL(b
, cond
, 0);
1567 array_insert(ctx
->ir
, ctx
->ir
->predicates
, kill
);
1569 array_insert(b
, b
->keeps
, kill
);
1570 ctx
->so
->no_earlyz
= true;
1575 ir3_context_error(ctx
, "Unhandled intrinsic type: %s\n",
1576 nir_intrinsic_infos
[intr
->intrinsic
].name
);
1581 ir3_put_dst(ctx
, &intr
->dest
);
1585 emit_load_const(struct ir3_context
*ctx
, nir_load_const_instr
*instr
)
1587 struct ir3_instruction
**dst
= ir3_get_dst_ssa(ctx
, &instr
->def
,
1588 instr
->def
.num_components
);
1590 if (instr
->def
.bit_size
< 32) {
1591 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1592 dst
[i
] = create_immed_typed(ctx
->block
,
1593 instr
->value
[i
].u16
,
1596 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1597 dst
[i
] = create_immed_typed(ctx
->block
,
1598 instr
->value
[i
].u32
,
1605 emit_undef(struct ir3_context
*ctx
, nir_ssa_undef_instr
*undef
)
1607 struct ir3_instruction
**dst
= ir3_get_dst_ssa(ctx
, &undef
->def
,
1608 undef
->def
.num_components
);
1609 type_t type
= (undef
->def
.bit_size
< 32) ? TYPE_U16
: TYPE_U32
;
1611 /* backend doesn't want undefined instructions, so just plug
1614 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
1615 dst
[i
] = create_immed_typed(ctx
->block
, fui(0.0), type
);
1619 * texture fetch/sample instructions:
1623 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
1625 unsigned coords
, flags
= 0;
1627 /* note: would use tex->coord_components.. except txs.. also,
1628 * since array index goes after shadow ref, we don't want to
1631 switch (tex
->sampler_dim
) {
1632 case GLSL_SAMPLER_DIM_1D
:
1633 case GLSL_SAMPLER_DIM_BUF
:
1636 case GLSL_SAMPLER_DIM_2D
:
1637 case GLSL_SAMPLER_DIM_RECT
:
1638 case GLSL_SAMPLER_DIM_EXTERNAL
:
1639 case GLSL_SAMPLER_DIM_MS
:
1642 case GLSL_SAMPLER_DIM_3D
:
1643 case GLSL_SAMPLER_DIM_CUBE
:
1645 flags
|= IR3_INSTR_3D
;
1648 unreachable("bad sampler_dim");
1651 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
1652 flags
|= IR3_INSTR_S
;
1654 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
1655 flags
|= IR3_INSTR_A
;
1661 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
1662 * or immediate (in which case it will get lowered later to a non .s2en
1663 * version of the tex instruction which encode tex/samp as immediates:
1665 static struct ir3_instruction
*
1666 get_tex_samp_tex_src(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
1668 int texture_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_texture_offset
);
1669 int sampler_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_sampler_offset
);
1670 struct ir3_instruction
*texture
, *sampler
;
1672 if (texture_idx
>= 0) {
1673 texture
= ir3_get_src(ctx
, &tex
->src
[texture_idx
].src
)[0];
1674 texture
= ir3_COV(ctx
->block
, texture
, TYPE_U32
, TYPE_U16
);
1676 /* TODO what to do for dynamic case? I guess we only need the
1677 * max index for astc srgb workaround so maybe not a problem
1678 * to worry about if we don't enable indirect samplers for
1681 ctx
->max_texture_index
= MAX2(ctx
->max_texture_index
, tex
->texture_index
);
1682 texture
= create_immed_typed(ctx
->block
, tex
->texture_index
, TYPE_U16
);
1685 if (sampler_idx
>= 0) {
1686 sampler
= ir3_get_src(ctx
, &tex
->src
[sampler_idx
].src
)[0];
1687 sampler
= ir3_COV(ctx
->block
, sampler
, TYPE_U32
, TYPE_U16
);
1689 sampler
= create_immed_typed(ctx
->block
, tex
->sampler_index
, TYPE_U16
);
1692 return ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1699 emit_tex(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
1701 struct ir3_block
*b
= ctx
->block
;
1702 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
1703 struct ir3_instruction
* const *coord
, * const *off
, * const *ddx
, * const *ddy
;
1704 struct ir3_instruction
*lod
, *compare
, *proj
, *sample_index
;
1705 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
1706 unsigned i
, coords
, flags
, ncomp
;
1707 unsigned nsrc0
= 0, nsrc1
= 0;
1711 ncomp
= nir_dest_num_components(tex
->dest
);
1713 coord
= off
= ddx
= ddy
= NULL
;
1714 lod
= proj
= compare
= sample_index
= NULL
;
1716 dst
= ir3_get_dst(ctx
, &tex
->dest
, ncomp
);
1718 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
1719 switch (tex
->src
[i
].src_type
) {
1720 case nir_tex_src_coord
:
1721 coord
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
1723 case nir_tex_src_bias
:
1724 lod
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
1727 case nir_tex_src_lod
:
1728 lod
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
1731 case nir_tex_src_comparator
: /* shadow comparator */
1732 compare
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
1734 case nir_tex_src_projector
:
1735 proj
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
1738 case nir_tex_src_offset
:
1739 off
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
1742 case nir_tex_src_ddx
:
1743 ddx
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
1745 case nir_tex_src_ddy
:
1746 ddy
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
1748 case nir_tex_src_ms_index
:
1749 sample_index
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
1751 case nir_tex_src_texture_offset
:
1752 case nir_tex_src_sampler_offset
:
1753 /* handled in get_tex_samp_src() */
1756 ir3_context_error(ctx
, "Unhandled NIR tex src type: %d\n",
1757 tex
->src
[i
].src_type
);
1763 case nir_texop_tex
: opc
= has_lod
? OPC_SAML
: OPC_SAM
; break;
1764 case nir_texop_txb
: opc
= OPC_SAMB
; break;
1765 case nir_texop_txl
: opc
= OPC_SAML
; break;
1766 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
1767 case nir_texop_txf
: opc
= OPC_ISAML
; break;
1768 case nir_texop_lod
: opc
= OPC_GETLOD
; break;
1770 /* NOTE: a4xx might need to emulate gather w/ txf (this is
1771 * what blob does, seems gather is broken?), and a3xx did
1772 * not support it (but probably could also emulate).
1774 switch (tex
->component
) {
1775 case 0: opc
= OPC_GATHER4R
; break;
1776 case 1: opc
= OPC_GATHER4G
; break;
1777 case 2: opc
= OPC_GATHER4B
; break;
1778 case 3: opc
= OPC_GATHER4A
; break;
1781 case nir_texop_txf_ms_fb
:
1782 case nir_texop_txf_ms
: opc
= OPC_ISAMM
; break;
1784 ir3_context_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
1788 tex_info(tex
, &flags
, &coords
);
1791 * lay out the first argument in the proper order:
1792 * - actual coordinates first
1793 * - shadow reference
1796 * - starting at offset 4, dpdx.xy, dpdy.xy
1798 * bias/lod go into the second arg
1801 /* insert tex coords: */
1802 for (i
= 0; i
< coords
; i
++)
1807 /* scale up integer coords for TXF based on the LOD */
1808 if (ctx
->compiler
->unminify_coords
&& (opc
== OPC_ISAML
)) {
1810 for (i
= 0; i
< coords
; i
++)
1811 src0
[i
] = ir3_SHL_B(b
, src0
[i
], 0, lod
, 0);
1815 /* hw doesn't do 1d, so we treat it as 2d with
1816 * height of 1, and patch up the y coord.
1819 src0
[nsrc0
++] = create_immed(b
, 0);
1821 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
1825 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
1826 src0
[nsrc0
++] = compare
;
1828 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
) {
1829 struct ir3_instruction
*idx
= coord
[coords
];
1831 /* the array coord for cube arrays needs 0.5 added to it */
1832 if (ctx
->compiler
->array_index_add_half
&& !is_isam(opc
))
1833 idx
= ir3_ADD_F(b
, idx
, 0, create_immed(b
, fui(0.5)), 0);
1835 src0
[nsrc0
++] = idx
;
1839 src0
[nsrc0
++] = proj
;
1840 flags
|= IR3_INSTR_P
;
1843 /* pad to 4, then ddx/ddy: */
1844 if (tex
->op
== nir_texop_txd
) {
1846 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1847 for (i
= 0; i
< coords
; i
++)
1848 src0
[nsrc0
++] = ddx
[i
];
1850 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1851 for (i
= 0; i
< coords
; i
++)
1852 src0
[nsrc0
++] = ddy
[i
];
1854 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1857 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
1858 * with scaled x coord according to requested sample:
1860 if (opc
== OPC_ISAMM
) {
1861 if (ctx
->compiler
->txf_ms_with_isaml
) {
1862 /* the samples are laid out in x dimension as
1864 * x_ms = (x << ms) + sample_index;
1866 struct ir3_instruction
*ms
;
1867 ms
= create_immed(b
, (ctx
->samples
>> (2 * tex
->texture_index
)) & 3);
1869 src0
[0] = ir3_SHL_B(b
, src0
[0], 0, ms
, 0);
1870 src0
[0] = ir3_ADD_U(b
, src0
[0], 0, sample_index
, 0);
1874 src0
[nsrc0
++] = sample_index
;
1879 * second argument (if applicable):
1884 if (has_off
| has_lod
| has_bias
) {
1886 unsigned off_coords
= coords
;
1887 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
1889 for (i
= 0; i
< off_coords
; i
++)
1890 src1
[nsrc1
++] = off
[i
];
1892 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
1893 flags
|= IR3_INSTR_O
;
1896 if (has_lod
| has_bias
)
1897 src1
[nsrc1
++] = lod
;
1900 switch (tex
->dest_type
) {
1901 case nir_type_invalid
:
1902 case nir_type_float
:
1913 unreachable("bad dest_type");
1916 if (opc
== OPC_GETLOD
)
1919 struct ir3_instruction
*samp_tex
;
1921 if (tex
->op
== nir_texop_txf_ms_fb
) {
1922 /* only expect a single txf_ms_fb per shader: */
1923 compile_assert(ctx
, !ctx
->so
->fb_read
);
1924 compile_assert(ctx
, ctx
->so
->type
== MESA_SHADER_FRAGMENT
);
1926 ctx
->so
->fb_read
= true;
1927 samp_tex
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1928 create_immed_typed(ctx
->block
, ctx
->so
->num_samp
, TYPE_U16
),
1929 create_immed_typed(ctx
->block
, ctx
->so
->num_samp
, TYPE_U16
),
1932 ctx
->so
->num_samp
++;
1934 samp_tex
= get_tex_samp_tex_src(ctx
, tex
);
1937 struct ir3_instruction
*col0
= ir3_create_collect(ctx
, src0
, nsrc0
);
1938 struct ir3_instruction
*col1
= ir3_create_collect(ctx
, src1
, nsrc1
);
1940 sam
= ir3_SAM(b
, opc
, type
, MASK(ncomp
), flags
,
1941 samp_tex
, col0
, col1
);
1943 if ((ctx
->astc_srgb
& (1 << tex
->texture_index
)) && !nir_tex_instr_is_query(tex
)) {
1944 /* only need first 3 components: */
1945 sam
->regs
[0]->wrmask
= 0x7;
1946 ir3_split_dest(b
, dst
, sam
, 0, 3);
1948 /* we need to sample the alpha separately with a non-ASTC
1951 sam
= ir3_SAM(b
, opc
, type
, 0b1000, flags
,
1952 samp_tex
, col0
, col1
);
1954 array_insert(ctx
->ir
, ctx
->ir
->astc_srgb
, sam
);
1956 /* fixup .w component: */
1957 ir3_split_dest(b
, &dst
[3], sam
, 3, 1);
1959 /* normal (non-workaround) case: */
1960 ir3_split_dest(b
, dst
, sam
, 0, ncomp
);
1963 /* GETLOD returns results in 4.8 fixed point */
1964 if (opc
== OPC_GETLOD
) {
1965 struct ir3_instruction
*factor
= create_immed(b
, fui(1.0 / 256));
1967 compile_assert(ctx
, tex
->dest_type
== nir_type_float
);
1968 for (i
= 0; i
< 2; i
++) {
1969 dst
[i
] = ir3_MUL_F(b
, ir3_COV(b
, dst
[i
], TYPE_U32
, TYPE_F32
), 0,
1974 ir3_put_dst(ctx
, &tex
->dest
);
1978 emit_tex_query_levels(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
1980 struct ir3_block
*b
= ctx
->block
;
1981 struct ir3_instruction
**dst
, *sam
;
1983 dst
= ir3_get_dst(ctx
, &tex
->dest
, 1);
1985 sam
= ir3_SAM(b
, OPC_GETINFO
, TYPE_U32
, 0b0100, 0,
1986 get_tex_samp_tex_src(ctx
, tex
), NULL
, NULL
);
1988 /* even though there is only one component, since it ends
1989 * up in .z rather than .x, we need a split_dest()
1991 ir3_split_dest(b
, dst
, sam
, 0, 3);
1993 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
1994 * the value in TEX_CONST_0 is zero-based.
1996 if (ctx
->compiler
->levels_add_one
)
1997 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
1999 ir3_put_dst(ctx
, &tex
->dest
);
2003 emit_tex_txs(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2005 struct ir3_block
*b
= ctx
->block
;
2006 struct ir3_instruction
**dst
, *sam
;
2007 struct ir3_instruction
*lod
;
2008 unsigned flags
, coords
;
2010 tex_info(tex
, &flags
, &coords
);
2012 /* Actually we want the number of dimensions, not coordinates. This
2013 * distinction only matters for cubes.
2015 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2018 dst
= ir3_get_dst(ctx
, &tex
->dest
, 4);
2020 compile_assert(ctx
, tex
->num_srcs
== 1);
2021 compile_assert(ctx
, tex
->src
[0].src_type
== nir_tex_src_lod
);
2023 lod
= ir3_get_src(ctx
, &tex
->src
[0].src
)[0];
2025 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, 0b1111, flags
,
2026 get_tex_samp_tex_src(ctx
, tex
), lod
, NULL
);
2028 ir3_split_dest(b
, dst
, sam
, 0, 4);
2030 /* Array size actually ends up in .w rather than .z. This doesn't
2031 * matter for miplevel 0, but for higher mips the value in z is
2032 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2033 * returned, which means that we have to add 1 to it for arrays.
2035 if (tex
->is_array
) {
2036 if (ctx
->compiler
->levels_add_one
) {
2037 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
2039 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
2043 ir3_put_dst(ctx
, &tex
->dest
);
2047 emit_jump(struct ir3_context
*ctx
, nir_jump_instr
*jump
)
2049 switch (jump
->type
) {
2050 case nir_jump_break
:
2051 case nir_jump_continue
:
2052 case nir_jump_return
:
2053 /* I *think* we can simply just ignore this, and use the
2054 * successor block link to figure out where we need to
2055 * jump to for break/continue
2059 ir3_context_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
2065 emit_instr(struct ir3_context
*ctx
, nir_instr
*instr
)
2067 switch (instr
->type
) {
2068 case nir_instr_type_alu
:
2069 emit_alu(ctx
, nir_instr_as_alu(instr
));
2071 case nir_instr_type_deref
:
2072 /* ignored, handled as part of the intrinsic they are src to */
2074 case nir_instr_type_intrinsic
:
2075 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
2077 case nir_instr_type_load_const
:
2078 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
2080 case nir_instr_type_ssa_undef
:
2081 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
2083 case nir_instr_type_tex
: {
2084 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
2085 /* couple tex instructions get special-cased:
2089 emit_tex_txs(ctx
, tex
);
2091 case nir_texop_query_levels
:
2092 emit_tex_query_levels(ctx
, tex
);
2100 case nir_instr_type_jump
:
2101 emit_jump(ctx
, nir_instr_as_jump(instr
));
2103 case nir_instr_type_phi
:
2104 /* we have converted phi webs to regs in NIR by now */
2105 ir3_context_error(ctx
, "Unexpected NIR instruction type: %d\n", instr
->type
);
2107 case nir_instr_type_call
:
2108 case nir_instr_type_parallel_copy
:
2109 ir3_context_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
2114 static struct ir3_block
*
2115 get_block(struct ir3_context
*ctx
, const nir_block
*nblock
)
2117 struct ir3_block
*block
;
2118 struct hash_entry
*hentry
;
2121 hentry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
2123 return hentry
->data
;
2125 block
= ir3_block_create(ctx
->ir
);
2126 block
->nblock
= nblock
;
2127 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
2129 block
->predecessors_count
= nblock
->predecessors
->entries
;
2130 block
->predecessors
= ralloc_array_size(block
,
2131 sizeof(block
->predecessors
[0]), block
->predecessors_count
);
2133 set_foreach(nblock
->predecessors
, sentry
) {
2134 block
->predecessors
[i
++] = get_block(ctx
, sentry
->key
);
2141 emit_block(struct ir3_context
*ctx
, nir_block
*nblock
)
2143 struct ir3_block
*block
= get_block(ctx
, nblock
);
2145 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
2146 if (nblock
->successors
[i
]) {
2147 block
->successors
[i
] =
2148 get_block(ctx
, nblock
->successors
[i
]);
2153 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
2155 /* re-emit addr register in each block if needed: */
2156 for (int i
= 0; i
< ARRAY_SIZE(ctx
->addr_ht
); i
++) {
2157 _mesa_hash_table_destroy(ctx
->addr_ht
[i
], NULL
);
2158 ctx
->addr_ht
[i
] = NULL
;
2161 nir_foreach_instr(instr
, nblock
) {
2162 ctx
->cur_instr
= instr
;
2163 emit_instr(ctx
, instr
);
2164 ctx
->cur_instr
= NULL
;
2170 static void emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
);
2173 emit_if(struct ir3_context
*ctx
, nir_if
*nif
)
2175 struct ir3_instruction
*condition
= ir3_get_src(ctx
, &nif
->condition
)[0];
2177 ctx
->block
->condition
=
2178 ir3_get_predicate(ctx
, ir3_b2n(condition
->block
, condition
));
2180 emit_cf_list(ctx
, &nif
->then_list
);
2181 emit_cf_list(ctx
, &nif
->else_list
);
2185 emit_loop(struct ir3_context
*ctx
, nir_loop
*nloop
)
2187 emit_cf_list(ctx
, &nloop
->body
);
2192 stack_push(struct ir3_context
*ctx
)
2195 ctx
->max_stack
= MAX2(ctx
->max_stack
, ctx
->stack
);
2199 stack_pop(struct ir3_context
*ctx
)
2201 compile_assert(ctx
, ctx
->stack
> 0);
2206 emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
)
2208 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2209 switch (node
->type
) {
2210 case nir_cf_node_block
:
2211 emit_block(ctx
, nir_cf_node_as_block(node
));
2213 case nir_cf_node_if
:
2215 emit_if(ctx
, nir_cf_node_as_if(node
));
2218 case nir_cf_node_loop
:
2220 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2223 case nir_cf_node_function
:
2224 ir3_context_error(ctx
, "TODO\n");
2230 /* emit stream-out code. At this point, the current block is the original
2231 * (nir) end block, and nir ensures that all flow control paths terminate
2232 * into the end block. We re-purpose the original end block to generate
2233 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2234 * block holding stream-out write instructions, followed by the new end
2238 * p0.x = (vtxcnt < maxvtxcnt)
2239 * // succs: blockStreamOut, blockNewEnd
2242 * ... stream-out instructions ...
2243 * // succs: blockNewEnd
2249 emit_stream_out(struct ir3_context
*ctx
)
2251 struct ir3
*ir
= ctx
->ir
;
2252 struct ir3_stream_output_info
*strmout
=
2253 &ctx
->so
->shader
->stream_output
;
2254 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
2255 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
2256 struct ir3_instruction
*bases
[IR3_MAX_SO_BUFFERS
];
2258 /* create vtxcnt input in input block at top of shader,
2259 * so that it is seen as live over the entire duration
2262 vtxcnt
= create_input(ctx
, 0);
2263 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_CNT
, vtxcnt
);
2265 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
2267 /* at this point, we are at the original 'end' block,
2268 * re-purpose this block to stream-out condition, then
2269 * append stream-out block and new-end block
2271 orig_end_block
= ctx
->block
;
2273 // TODO these blocks need to update predecessors..
2274 // maybe w/ store_global intrinsic, we could do this
2275 // stuff in nir->nir pass
2277 stream_out_block
= ir3_block_create(ir
);
2278 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
2280 new_end_block
= ir3_block_create(ir
);
2281 list_addtail(&new_end_block
->node
, &ir
->block_list
);
2283 orig_end_block
->successors
[0] = stream_out_block
;
2284 orig_end_block
->successors
[1] = new_end_block
;
2285 stream_out_block
->successors
[0] = new_end_block
;
2287 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2288 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
2289 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2290 cond
->cat2
.condition
= IR3_COND_LT
;
2292 /* condition goes on previous block to the conditional,
2293 * since it is used to pick which of the two successor
2296 orig_end_block
->condition
= cond
;
2298 /* switch to stream_out_block to generate the stream-out
2301 ctx
->block
= stream_out_block
;
2303 /* Calculate base addresses based on vtxcnt. Instructions
2304 * generated for bases not used in following loop will be
2305 * stripped out in the backend.
2307 for (unsigned i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++) {
2308 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
2309 unsigned stride
= strmout
->stride
[i
];
2310 struct ir3_instruction
*base
, *off
;
2312 base
= create_uniform(ctx
->block
, regid(const_state
->offsets
.tfbo
, i
));
2314 /* 24-bit should be enough: */
2315 off
= ir3_MUL_U(ctx
->block
, vtxcnt
, 0,
2316 create_immed(ctx
->block
, stride
* 4), 0);
2318 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
2321 /* Generate the per-output store instructions: */
2322 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
2323 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
2324 unsigned c
= j
+ strmout
->output
[i
].start_component
;
2325 struct ir3_instruction
*base
, *out
, *stg
;
2327 base
= bases
[strmout
->output
[i
].output_buffer
];
2328 out
= ctx
->ir
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
2330 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
2331 create_immed(ctx
->block
, 1), 0);
2332 stg
->cat6
.type
= TYPE_U32
;
2333 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
2335 array_insert(ctx
->block
, ctx
->block
->keeps
, stg
);
2339 /* and finally switch to the new_end_block: */
2340 ctx
->block
= new_end_block
;
2344 emit_function(struct ir3_context
*ctx
, nir_function_impl
*impl
)
2346 nir_metadata_require(impl
, nir_metadata_block_index
);
2348 compile_assert(ctx
, ctx
->stack
== 0);
2350 emit_cf_list(ctx
, &impl
->body
);
2351 emit_block(ctx
, impl
->end_block
);
2353 compile_assert(ctx
, ctx
->stack
== 0);
2355 /* at this point, we should have a single empty block,
2356 * into which we emit the 'end' instruction.
2358 compile_assert(ctx
, list_empty(&ctx
->block
->instr_list
));
2360 /* If stream-out (aka transform-feedback) enabled, emit the
2361 * stream-out instructions, followed by a new empty block (into
2362 * which the 'end' instruction lands).
2364 * NOTE: it is done in this order, rather than inserting before
2365 * we emit end_block, because NIR guarantees that all blocks
2366 * flow into end_block, and that end_block has no successors.
2367 * So by re-purposing end_block as the first block of stream-
2368 * out, we guarantee that all exit paths flow into the stream-
2371 if ((ctx
->compiler
->gpu_id
< 500) &&
2372 (ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
2373 !ctx
->so
->binning_pass
) {
2374 debug_assert(ctx
->so
->type
== MESA_SHADER_VERTEX
);
2375 emit_stream_out(ctx
);
2378 ir3_END(ctx
->block
);
2382 setup_input(struct ir3_context
*ctx
, nir_variable
*in
)
2384 struct ir3_shader_variant
*so
= ctx
->so
;
2385 unsigned ncomp
= glsl_get_components(in
->type
);
2386 unsigned n
= in
->data
.driver_location
;
2387 unsigned frac
= in
->data
.location_frac
;
2388 unsigned slot
= in
->data
.location
;
2390 /* skip unread inputs, we could end up with (for example), unsplit
2391 * matrix/etc inputs in the case they are not read, so just silently
2397 so
->inputs
[n
].slot
= slot
;
2398 so
->inputs
[n
].compmask
= (1 << (ncomp
+ frac
)) - 1;
2399 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
2400 so
->inputs
[n
].interpolate
= in
->data
.interpolation
;
2401 so
->inputs
[n
].ncomp
= ncomp
;
2403 if (ctx
->so
->type
== MESA_SHADER_FRAGMENT
) {
2405 /* if any varyings have 'sample' qualifer, that triggers us
2406 * to run in per-sample mode:
2408 so
->per_samp
|= in
->data
.sample
;
2410 for (int i
= 0; i
< ncomp
; i
++) {
2411 struct ir3_instruction
*instr
= NULL
;
2412 unsigned idx
= (n
* 4) + i
+ frac
;
2414 if (slot
== VARYING_SLOT_POS
) {
2415 ir3_context_error(ctx
, "fragcoord should be a sysval!\n");
2416 } else if (slot
== VARYING_SLOT_PNTC
) {
2417 /* see for example st_nir_fixup_varying_slots().. this is
2418 * maybe a bit mesa/st specific. But we need things to line
2419 * up for this in fdN_program:
2420 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2421 * if (emit->sprite_coord_enable & texmask) {
2425 so
->inputs
[n
].slot
= VARYING_SLOT_VAR8
;
2426 so
->inputs
[n
].bary
= true;
2427 instr
= create_frag_input(ctx
, false, idx
);
2429 /* detect the special case for front/back colors where
2430 * we need to do flat vs smooth shading depending on
2433 if (in
->data
.interpolation
== INTERP_MODE_NONE
) {
2435 case VARYING_SLOT_COL0
:
2436 case VARYING_SLOT_COL1
:
2437 case VARYING_SLOT_BFC0
:
2438 case VARYING_SLOT_BFC1
:
2439 so
->inputs
[n
].rasterflat
= true;
2446 if (ctx
->compiler
->flat_bypass
) {
2447 if ((so
->inputs
[n
].interpolate
== INTERP_MODE_FLAT
) ||
2448 (so
->inputs
[n
].rasterflat
&& ctx
->so
->key
.rasterflat
))
2449 so
->inputs
[n
].use_ldlv
= true;
2452 so
->inputs
[n
].bary
= true;
2454 instr
= create_frag_input(ctx
, so
->inputs
[n
].use_ldlv
, idx
);
2457 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
2459 ctx
->ir
->inputs
[idx
] = instr
;
2461 } else if (ctx
->so
->type
== MESA_SHADER_VERTEX
) {
2462 for (int i
= 0; i
< ncomp
; i
++) {
2463 unsigned idx
= (n
* 4) + i
+ frac
;
2464 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
2465 ctx
->ir
->inputs
[idx
] = create_input(ctx
, idx
);
2468 ir3_context_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2471 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== MESA_SHADER_VERTEX
)) {
2472 so
->total_in
+= ncomp
;
2476 /* Initially we assign non-packed inloc's for varyings, as we don't really
2477 * know up-front which components will be unused. After all the compilation
2478 * stages we scan the shader to see which components are actually used, and
2479 * re-pack the inlocs to eliminate unneeded varyings.
2482 pack_inlocs(struct ir3_context
*ctx
)
2484 struct ir3_shader_variant
*so
= ctx
->so
;
2485 uint8_t used_components
[so
->inputs_count
];
2487 memset(used_components
, 0, sizeof(used_components
));
2490 * First Step: scan shader to find which bary.f/ldlv remain:
2493 list_for_each_entry (struct ir3_block
, block
, &ctx
->ir
->block_list
, node
) {
2494 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
2495 if (is_input(instr
)) {
2496 unsigned inloc
= instr
->regs
[1]->iim_val
;
2497 unsigned i
= inloc
/ 4;
2498 unsigned j
= inloc
% 4;
2500 compile_assert(ctx
, instr
->regs
[1]->flags
& IR3_REG_IMMED
);
2501 compile_assert(ctx
, i
< so
->inputs_count
);
2503 used_components
[i
] |= 1 << j
;
2509 * Second Step: reassign varying inloc/slots:
2512 unsigned actual_in
= 0;
2515 for (unsigned i
= 0; i
< so
->inputs_count
; i
++) {
2516 unsigned compmask
= 0, maxcomp
= 0;
2518 so
->inputs
[i
].ncomp
= 0;
2519 so
->inputs
[i
].inloc
= inloc
;
2520 so
->inputs
[i
].bary
= false;
2522 for (unsigned j
= 0; j
< 4; j
++) {
2523 if (!(used_components
[i
] & (1 << j
)))
2526 compmask
|= (1 << j
);
2528 so
->inputs
[i
].ncomp
++;
2531 /* at this point, since used_components[i] mask is only
2532 * considering varyings (ie. not sysvals) we know this
2535 so
->inputs
[i
].bary
= true;
2538 if (so
->inputs
[i
].bary
) {
2540 so
->inputs
[i
].compmask
= (1 << maxcomp
) - 1;
2546 * Third Step: reassign packed inloc's:
2549 list_for_each_entry (struct ir3_block
, block
, &ctx
->ir
->block_list
, node
) {
2550 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
2551 if (is_input(instr
)) {
2552 unsigned inloc
= instr
->regs
[1]->iim_val
;
2553 unsigned i
= inloc
/ 4;
2554 unsigned j
= inloc
% 4;
2556 instr
->regs
[1]->iim_val
= so
->inputs
[i
].inloc
+ j
;
2563 setup_output(struct ir3_context
*ctx
, nir_variable
*out
)
2565 struct ir3_shader_variant
*so
= ctx
->so
;
2566 unsigned ncomp
= glsl_get_components(out
->type
);
2567 unsigned n
= out
->data
.driver_location
;
2568 unsigned frac
= out
->data
.location_frac
;
2569 unsigned slot
= out
->data
.location
;
2572 if (ctx
->so
->type
== MESA_SHADER_FRAGMENT
) {
2574 case FRAG_RESULT_DEPTH
:
2575 comp
= 2; /* tgsi will write to .z component */
2576 so
->writes_pos
= true;
2578 case FRAG_RESULT_COLOR
:
2581 case FRAG_RESULT_SAMPLE_MASK
:
2582 so
->writes_smask
= true;
2585 if (slot
>= FRAG_RESULT_DATA0
)
2587 ir3_context_error(ctx
, "unknown FS output name: %s\n",
2588 gl_frag_result_name(slot
));
2590 } else if (ctx
->so
->type
== MESA_SHADER_VERTEX
) {
2592 case VARYING_SLOT_POS
:
2593 so
->writes_pos
= true;
2595 case VARYING_SLOT_PSIZ
:
2596 so
->writes_psize
= true;
2598 case VARYING_SLOT_COL0
:
2599 case VARYING_SLOT_COL1
:
2600 case VARYING_SLOT_BFC0
:
2601 case VARYING_SLOT_BFC1
:
2602 case VARYING_SLOT_FOGC
:
2603 case VARYING_SLOT_CLIP_DIST0
:
2604 case VARYING_SLOT_CLIP_DIST1
:
2605 case VARYING_SLOT_CLIP_VERTEX
:
2608 if (slot
>= VARYING_SLOT_VAR0
)
2610 if ((VARYING_SLOT_TEX0
<= slot
) && (slot
<= VARYING_SLOT_TEX7
))
2612 ir3_context_error(ctx
, "unknown VS output name: %s\n",
2613 gl_varying_slot_name(slot
));
2616 ir3_context_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2619 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
2621 so
->outputs
[n
].slot
= slot
;
2622 so
->outputs
[n
].regid
= regid(n
, comp
);
2623 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
2625 for (int i
= 0; i
< ncomp
; i
++) {
2626 unsigned idx
= (n
* 4) + i
+ frac
;
2627 compile_assert(ctx
, idx
< ctx
->ir
->noutputs
);
2628 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
2631 /* if varying packing doesn't happen, we could end up in a situation
2632 * with "holes" in the output, and since the per-generation code that
2633 * sets up varying linkage registers doesn't expect to have more than
2634 * one varying per vec4 slot, pad the holes.
2636 * Note that this should probably generate a performance warning of
2639 for (int i
= 0; i
< frac
; i
++) {
2640 unsigned idx
= (n
* 4) + i
;
2641 if (!ctx
->ir
->outputs
[idx
]) {
2642 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
2648 max_drvloc(struct exec_list
*vars
)
2651 nir_foreach_variable(var
, vars
) {
2652 drvloc
= MAX2(drvloc
, (int)var
->data
.driver_location
);
2657 static const unsigned max_sysvals
[] = {
2658 [MESA_SHADER_FRAGMENT
] = 24, // TODO
2659 [MESA_SHADER_VERTEX
] = 16,
2660 [MESA_SHADER_COMPUTE
] = 16, // TODO how many do we actually need?
2661 [MESA_SHADER_KERNEL
] = 16, // TODO how many do we actually need?
2665 emit_instructions(struct ir3_context
*ctx
)
2667 unsigned ninputs
, noutputs
;
2668 nir_function_impl
*fxn
= nir_shader_get_entrypoint(ctx
->s
);
2670 ninputs
= (max_drvloc(&ctx
->s
->inputs
) + 1) * 4;
2671 noutputs
= (max_drvloc(&ctx
->s
->outputs
) + 1) * 4;
2673 /* we need to leave room for sysvals:
2675 ninputs
+= max_sysvals
[ctx
->so
->type
];
2677 ctx
->ir
= ir3_create(ctx
->compiler
, ctx
->so
->type
, ninputs
, noutputs
);
2679 /* Create inputs in first block: */
2680 ctx
->block
= get_block(ctx
, nir_start_block(fxn
));
2681 ctx
->in_block
= ctx
->block
;
2682 list_addtail(&ctx
->block
->node
, &ctx
->ir
->block_list
);
2684 ninputs
-= max_sysvals
[ctx
->so
->type
];
2686 /* for fragment shader, the vcoord input register is used as the
2687 * base for bary.f varying fetch instrs:
2689 * TODO defer creating ctx->ij_pixel and corresponding sysvals
2690 * until emit_intrinsic when we know they are actually needed.
2691 * For now, we defer creating ctx->ij_centroid, etc, since we
2692 * only need ij_pixel for "old style" varying inputs (ie.
2695 struct ir3_instruction
*vcoord
= NULL
;
2696 if (ctx
->so
->type
== MESA_SHADER_FRAGMENT
) {
2697 struct ir3_instruction
*xy
[2];
2699 vcoord
= create_input_compmask(ctx
, 0, 0x3);
2700 ir3_split_dest(ctx
->block
, xy
, vcoord
, 0, 2);
2702 ctx
->ij_pixel
= ir3_create_collect(ctx
, xy
, 2);
2706 nir_foreach_variable(var
, &ctx
->s
->inputs
) {
2707 setup_input(ctx
, var
);
2710 /* Defer add_sysval_input() stuff until after setup_inputs(),
2711 * because sysvals need to be appended after varyings:
2714 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_BARYCENTRIC_PIXEL
,
2718 /* Setup outputs: */
2719 nir_foreach_variable(var
, &ctx
->s
->outputs
) {
2720 setup_output(ctx
, var
);
2723 /* Find # of samplers: */
2724 nir_foreach_variable(var
, &ctx
->s
->uniforms
) {
2725 ctx
->so
->num_samp
+= glsl_type_get_sampler_count(var
->type
);
2726 /* just assume that we'll be reading from images.. if it
2727 * is write-only we don't have to count it, but not sure
2728 * if there is a good way to know?
2730 ctx
->so
->num_samp
+= glsl_type_get_image_count(var
->type
);
2733 /* NOTE: need to do something more clever when we support >1 fxn */
2734 nir_foreach_register(reg
, &fxn
->registers
) {
2735 ir3_declare_array(ctx
, reg
);
2737 /* And emit the body: */
2739 emit_function(ctx
, fxn
);
2742 /* from NIR perspective, we actually have varying inputs. But the varying
2743 * inputs, from an IR standpoint, are just bary.f/ldlv instructions. The
2744 * only actual inputs are the sysvals.
2747 fixup_frag_inputs(struct ir3_context
*ctx
)
2749 struct ir3_shader_variant
*so
= ctx
->so
;
2750 struct ir3
*ir
= ctx
->ir
;
2753 /* sysvals should appear at the end of the inputs, drop everything else: */
2754 while ((i
< so
->inputs_count
) && !so
->inputs
[i
].sysval
)
2757 /* at IR level, inputs are always blocks of 4 scalars: */
2760 ir
->inputs
= &ir
->inputs
[i
];
2764 /* Fixup tex sampler state for astc/srgb workaround instructions. We
2765 * need to assign the tex state indexes for these after we know the
2769 fixup_astc_srgb(struct ir3_context
*ctx
)
2771 struct ir3_shader_variant
*so
= ctx
->so
;
2772 /* indexed by original tex idx, value is newly assigned alpha sampler
2773 * state tex idx. Zero is invalid since there is at least one sampler
2776 unsigned alt_tex_state
[16] = {0};
2777 unsigned tex_idx
= ctx
->max_texture_index
+ 1;
2780 so
->astc_srgb
.base
= tex_idx
;
2782 for (unsigned i
= 0; i
< ctx
->ir
->astc_srgb_count
; i
++) {
2783 struct ir3_instruction
*sam
= ctx
->ir
->astc_srgb
[i
];
2785 compile_assert(ctx
, sam
->cat5
.tex
< ARRAY_SIZE(alt_tex_state
));
2787 if (alt_tex_state
[sam
->cat5
.tex
] == 0) {
2788 /* assign new alternate/alpha tex state slot: */
2789 alt_tex_state
[sam
->cat5
.tex
] = tex_idx
++;
2790 so
->astc_srgb
.orig_idx
[idx
++] = sam
->cat5
.tex
;
2791 so
->astc_srgb
.count
++;
2794 sam
->cat5
.tex
= alt_tex_state
[sam
->cat5
.tex
];
2799 fixup_binning_pass(struct ir3_context
*ctx
)
2801 struct ir3_shader_variant
*so
= ctx
->so
;
2802 struct ir3
*ir
= ctx
->ir
;
2805 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
2806 unsigned slot
= so
->outputs
[i
].slot
;
2808 /* throw away everything but first position/psize */
2809 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
2811 so
->outputs
[j
] = so
->outputs
[i
];
2812 ir
->outputs
[(j
*4)+0] = ir
->outputs
[(i
*4)+0];
2813 ir
->outputs
[(j
*4)+1] = ir
->outputs
[(i
*4)+1];
2814 ir
->outputs
[(j
*4)+2] = ir
->outputs
[(i
*4)+2];
2815 ir
->outputs
[(j
*4)+3] = ir
->outputs
[(i
*4)+3];
2820 so
->outputs_count
= j
;
2821 ir
->noutputs
= j
* 4;
2825 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
2826 struct ir3_shader_variant
*so
)
2828 struct ir3_context
*ctx
;
2830 struct ir3_instruction
**inputs
;
2832 int ret
= 0, max_bary
;
2836 ctx
= ir3_context_init(compiler
, so
);
2838 DBG("INIT failed!");
2843 emit_instructions(ctx
);
2846 DBG("EMIT failed!");
2851 ir
= so
->ir
= ctx
->ir
;
2853 /* keep track of the inputs from TGSI perspective.. */
2854 inputs
= ir
->inputs
;
2856 /* but fixup actual inputs for frag shader: */
2857 if (so
->type
== MESA_SHADER_FRAGMENT
)
2858 fixup_frag_inputs(ctx
);
2860 /* at this point, for binning pass, throw away unneeded outputs: */
2861 if (so
->binning_pass
&& (ctx
->compiler
->gpu_id
< 600))
2862 fixup_binning_pass(ctx
);
2864 /* if we want half-precision outputs, mark the output registers
2867 if (so
->key
.half_precision
) {
2868 for (i
= 0; i
< ir
->noutputs
; i
++) {
2869 struct ir3_instruction
*out
= ir
->outputs
[i
];
2874 /* if frag shader writes z, that needs to be full precision: */
2875 if (so
->outputs
[i
/4].slot
== FRAG_RESULT_DEPTH
)
2878 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2879 /* output could be a fanout (ie. texture fetch output)
2880 * in which case we need to propagate the half-reg flag
2881 * up to the definer so that RA sees it:
2883 if (out
->opc
== OPC_META_FO
) {
2884 out
= out
->regs
[1]->instr
;
2885 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2888 if (out
->opc
== OPC_MOV
) {
2889 out
->cat1
.dst_type
= half_type(out
->cat1
.dst_type
);
2894 if (ir3_shader_debug
& IR3_DBG_OPTMSGS
) {
2895 printf("BEFORE CP:\n");
2901 /* at this point, for binning pass, throw away unneeded outputs:
2902 * Note that for a6xx and later, we do this after ir3_cp to ensure
2903 * that the uniform/constant layout for BS and VS matches, so that
2904 * we can re-use same VS_CONST state group.
2906 if (so
->binning_pass
&& (ctx
->compiler
->gpu_id
>= 600))
2907 fixup_binning_pass(ctx
);
2909 /* for a6xx+, binning and draw pass VS use same VBO state, so we
2910 * need to make sure not to remove any inputs that are used by
2911 * the nonbinning VS.
2913 if (ctx
->compiler
->gpu_id
>= 600 && so
->binning_pass
) {
2914 debug_assert(so
->type
== MESA_SHADER_VERTEX
);
2915 for (int i
= 0; i
< ir
->ninputs
; i
++) {
2916 struct ir3_instruction
*in
= ir
->inputs
[i
];
2924 debug_assert(n
< so
->nonbinning
->inputs_count
);
2926 if (so
->nonbinning
->inputs
[n
].sysval
)
2929 /* be sure to keep inputs, even if only used in VS */
2930 if (so
->nonbinning
->inputs
[n
].compmask
& (1 << c
))
2931 array_insert(in
->block
, in
->block
->keeps
, in
);
2935 /* Insert mov if there's same instruction for each output.
2936 * eg. dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.const_expression.vertex.sampler2dshadow
2938 for (int i
= ir
->noutputs
- 1; i
>= 0; i
--) {
2939 if (!ir
->outputs
[i
])
2941 for (unsigned j
= 0; j
< i
; j
++) {
2942 if (ir
->outputs
[i
] == ir
->outputs
[j
]) {
2944 ir3_MOV(ir
->outputs
[i
]->block
, ir
->outputs
[i
], TYPE_F32
);
2949 if (ir3_shader_debug
& IR3_DBG_OPTMSGS
) {
2950 printf("BEFORE GROUPING:\n");
2954 ir3_sched_add_deps(ir
);
2956 /* Group left/right neighbors, inserting mov's where needed to
2961 if (ir3_shader_debug
& IR3_DBG_OPTMSGS
) {
2962 printf("AFTER GROUPING:\n");
2968 if (ir3_shader_debug
& IR3_DBG_OPTMSGS
) {
2969 printf("AFTER DEPTH:\n");
2973 /* do Sethi–Ullman numbering before scheduling: */
2976 ret
= ir3_sched(ir
);
2978 DBG("SCHED failed!");
2982 if (compiler
->gpu_id
>= 600) {
2983 ir3_a6xx_fixup_atomic_dests(ir
, so
);
2986 if (ir3_shader_debug
& IR3_DBG_OPTMSGS
) {
2987 printf("AFTER SCHED:\n");
2997 if (ir3_shader_debug
& IR3_DBG_OPTMSGS
) {
2998 printf("AFTER RA:\n");
3002 if (so
->type
== MESA_SHADER_FRAGMENT
)
3005 /* fixup input/outputs: */
3006 for (i
= 0; i
< so
->outputs_count
; i
++) {
3007 /* sometimes we get outputs that don't write the .x coord, like:
3009 * decl_var shader_out INTERP_MODE_NONE float Color (VARYING_SLOT_VAR9.z, 1, 0)
3011 * Presumably the result of varying packing and then eliminating
3012 * some unneeded varyings? Just skip head to the first valid
3013 * component of the output.
3015 for (unsigned j
= 0; j
< 4; j
++) {
3016 struct ir3_instruction
*instr
= ir
->outputs
[(i
*4) + j
];
3018 so
->outputs
[i
].regid
= instr
->regs
[0]->num
;
3019 so
->outputs
[i
].half
= !!(instr
->regs
[0]->flags
& IR3_REG_HALF
);
3025 /* Note that some or all channels of an input may be unused: */
3026 for (i
= 0; i
< so
->inputs_count
; i
++) {
3027 unsigned j
, reg
= regid(63,0);
3029 for (j
= 0; j
< 4; j
++) {
3030 struct ir3_instruction
*in
= inputs
[(i
*4) + j
];
3035 if (in
->flags
& IR3_INSTR_UNUSED
)
3038 reg
= in
->regs
[0]->num
- j
;
3040 compile_assert(ctx
, in
->regs
[0]->flags
& IR3_REG_HALF
);
3042 half
= !!(in
->regs
[0]->flags
& IR3_REG_HALF
);
3045 so
->inputs
[i
].regid
= reg
;
3046 so
->inputs
[i
].half
= half
;
3050 fixup_astc_srgb(ctx
);
3052 /* We need to do legalize after (for frag shader's) the "bary.f"
3053 * offsets (inloc) have been assigned.
3055 ir3_legalize(ir
, &so
->has_ssbo
, &so
->need_pixlod
, &max_bary
);
3057 if (ir3_shader_debug
& IR3_DBG_OPTMSGS
) {
3058 printf("AFTER LEGALIZE:\n");
3062 so
->branchstack
= ctx
->max_stack
;
3064 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3065 if (so
->type
== MESA_SHADER_FRAGMENT
)
3066 so
->total_in
= max_bary
+ 1;
3068 so
->max_sun
= ir
->max_sun
;
3073 ir3_destroy(so
->ir
);
3076 ir3_context_free(ctx
);